| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 95.44 | 98.11 | 95.91 | 97.44 | 87.30 | 98.22 | 98.17 | 92.94 |
| T3566 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/440.usbdev_tx_rx_disruption.1200872115 | Feb 08 06:20:11 PM UTC 25 | Feb 08 06:20:14 PM UTC 25 | 501311025 ps | ||
| T3567 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/427.usbdev_tx_rx_disruption.2718707148 | Feb 08 06:20:11 PM UTC 25 | Feb 08 06:20:14 PM UTC 25 | 641772789 ps | ||
| T3568 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/470.usbdev_tx_rx_disruption.1594888006 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:18 PM UTC 25 | 577950473 ps | ||
| T3569 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/472.usbdev_tx_rx_disruption.4265473936 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:19 PM UTC 25 | 450924323 ps | ||
| T3570 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/475.usbdev_tx_rx_disruption.2098914831 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:19 PM UTC 25 | 468075608 ps | ||
| T3571 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/471.usbdev_tx_rx_disruption.1987411362 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:19 PM UTC 25 | 575890649 ps | ||
| T3572 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/477.usbdev_tx_rx_disruption.4191102003 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:19 PM UTC 25 | 465881986 ps | ||
| T3573 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/473.usbdev_tx_rx_disruption.2159889255 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:19 PM UTC 25 | 528432404 ps | ||
| T117 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/474.usbdev_tx_rx_disruption.3920673074 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:19 PM UTC 25 | 639726064 ps | ||
| T3574 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/476.usbdev_tx_rx_disruption.1989802088 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:19 PM UTC 25 | 527175548 ps | ||
| T3575 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/480.usbdev_tx_rx_disruption.1433634275 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:19 PM UTC 25 | 448814098 ps | ||
| T3576 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/479.usbdev_tx_rx_disruption.2482097908 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:19 PM UTC 25 | 577117175 ps | ||
| T3577 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/478.usbdev_tx_rx_disruption.753883775 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:19 PM UTC 25 | 637941409 ps | ||
| T3578 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/485.usbdev_tx_rx_disruption.896911453 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:19 PM UTC 25 | 506196005 ps | ||
| T3579 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/481.usbdev_tx_rx_disruption.3558677516 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:19 PM UTC 25 | 505356897 ps | ||
| T3580 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/482.usbdev_tx_rx_disruption.519068642 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:19 PM UTC 25 | 560218480 ps | ||
| T3581 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/483.usbdev_tx_rx_disruption.3792741372 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:19 PM UTC 25 | 535936133 ps | ||
| T3582 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/461.usbdev_tx_rx_disruption.2631335243 | Feb 08 06:20:14 PM UTC 25 | Feb 08 06:20:23 PM UTC 25 | 447528698 ps | ||
| T3583 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/462.usbdev_tx_rx_disruption.417908007 | Feb 08 06:20:14 PM UTC 25 | Feb 08 06:20:23 PM UTC 25 | 567821103 ps | ||
| T3584 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/464.usbdev_tx_rx_disruption.2454688115 | Feb 08 06:20:14 PM UTC 25 | Feb 08 06:20:24 PM UTC 25 | 520276905 ps | ||
| T3585 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/467.usbdev_tx_rx_disruption.4061708287 | Feb 08 06:20:14 PM UTC 25 | Feb 08 06:20:24 PM UTC 25 | 616995169 ps | ||
| T3586 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/465.usbdev_tx_rx_disruption.2320293966 | Feb 08 06:20:14 PM UTC 25 | Feb 08 06:20:24 PM UTC 25 | 635708243 ps | ||
| T3587 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/466.usbdev_tx_rx_disruption.878873315 | Feb 08 06:20:14 PM UTC 25 | Feb 08 06:20:24 PM UTC 25 | 711278591 ps | ||
| T3588 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/463.usbdev_tx_rx_disruption.1702431368 | Feb 08 06:20:14 PM UTC 25 | Feb 08 06:20:24 PM UTC 25 | 659601499 ps | ||
| T3589 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/468.usbdev_tx_rx_disruption.3355001116 | Feb 08 06:20:14 PM UTC 25 | Feb 08 06:20:24 PM UTC 25 | 638078854 ps | ||
| T3590 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/469.usbdev_tx_rx_disruption.784611835 | Feb 08 06:20:14 PM UTC 25 | Feb 08 06:20:24 PM UTC 25 | 441389368 ps | ||
| T3591 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/499.usbdev_tx_rx_disruption.16070811 | Feb 08 06:20:20 PM UTC 25 | Feb 08 06:20:24 PM UTC 25 | 568795434 ps | ||
| T3592 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/498.usbdev_tx_rx_disruption.390572364 | Feb 08 06:20:20 PM UTC 25 | Feb 08 06:20:24 PM UTC 25 | 621387259 ps | ||
| T3593 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/444.usbdev_tx_rx_disruption.4211782252 | Feb 08 06:20:11 PM UTC 25 | Feb 08 06:20:24 PM UTC 25 | 567306204 ps | ||
| T3594 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/490.usbdev_tx_rx_disruption.973960396 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:26 PM UTC 25 | 479381194 ps | ||
| T3595 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/484.usbdev_tx_rx_disruption.4110114862 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:26 PM UTC 25 | 487861478 ps | ||
| T3596 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/487.usbdev_tx_rx_disruption.2950696928 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:26 PM UTC 25 | 561718444 ps | ||
| T3597 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/488.usbdev_tx_rx_disruption.879372813 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:26 PM UTC 25 | 578110850 ps | ||
| T3598 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/493.usbdev_tx_rx_disruption.3739790204 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:26 PM UTC 25 | 557706421 ps | ||
| T3599 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/494.usbdev_tx_rx_disruption.4190007180 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:26 PM UTC 25 | 498505627 ps | ||
| T3600 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/448.usbdev_tx_rx_disruption.2356305139 | Feb 08 06:20:13 PM UTC 25 | Feb 08 06:20:26 PM UTC 25 | 471859301 ps | ||
| T3601 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/489.usbdev_tx_rx_disruption.1879921369 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:26 PM UTC 25 | 569639175 ps | ||
| T3602 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/486.usbdev_tx_rx_disruption.79725688 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:26 PM UTC 25 | 610799480 ps | ||
| T3603 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/491.usbdev_tx_rx_disruption.2141383656 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:26 PM UTC 25 | 572921216 ps | ||
| T3604 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/496.usbdev_tx_rx_disruption.355555123 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:29 PM UTC 25 | 491165455 ps | ||
| T3605 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/492.usbdev_tx_rx_disruption.3902888256 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:29 PM UTC 25 | 513422025 ps | ||
| T3606 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/495.usbdev_tx_rx_disruption.3777534634 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:30 PM UTC 25 | 658517110 ps | ||
| T3607 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/449.usbdev_tx_rx_disruption.2603202676 | Feb 08 06:20:13 PM UTC 25 | Feb 08 06:20:30 PM UTC 25 | 467694057 ps | ||
| T3608 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/446.usbdev_tx_rx_disruption.3607714160 | Feb 08 06:20:13 PM UTC 25 | Feb 08 06:20:30 PM UTC 25 | 722352845 ps | ||
| T3609 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/452.usbdev_tx_rx_disruption.4137368833 | Feb 08 06:20:13 PM UTC 25 | Feb 08 06:20:30 PM UTC 25 | 519815734 ps | ||
| T3610 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/455.usbdev_tx_rx_disruption.2044901092 | Feb 08 06:20:13 PM UTC 25 | Feb 08 06:20:30 PM UTC 25 | 454134520 ps | ||
| T3611 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/497.usbdev_tx_rx_disruption.243305819 | Feb 08 06:20:16 PM UTC 25 | Feb 08 06:20:30 PM UTC 25 | 613788231 ps | ||
| T3612 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/454.usbdev_tx_rx_disruption.363186607 | Feb 08 06:20:13 PM UTC 25 | Feb 08 06:20:30 PM UTC 25 | 460908337 ps | ||
| T3613 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/447.usbdev_tx_rx_disruption.667300481 | Feb 08 06:20:13 PM UTC 25 | Feb 08 06:20:30 PM UTC 25 | 485888740 ps | ||
| T3614 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/453.usbdev_tx_rx_disruption.2818549278 | Feb 08 06:20:13 PM UTC 25 | Feb 08 06:20:30 PM UTC 25 | 507232757 ps | ||
| T3615 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/459.usbdev_tx_rx_disruption.1176861146 | Feb 08 06:20:14 PM UTC 25 | Feb 08 06:20:30 PM UTC 25 | 472076297 ps | ||
| T3616 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/451.usbdev_tx_rx_disruption.106236553 | Feb 08 06:20:13 PM UTC 25 | Feb 08 06:20:30 PM UTC 25 | 551854606 ps | ||
| T3617 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/457.usbdev_tx_rx_disruption.2068978931 | Feb 08 06:20:13 PM UTC 25 | Feb 08 06:20:30 PM UTC 25 | 564520079 ps | ||
| T3618 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/456.usbdev_tx_rx_disruption.4129134056 | Feb 08 06:20:13 PM UTC 25 | Feb 08 06:20:30 PM UTC 25 | 668775784 ps | ||
| T3619 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/460.usbdev_tx_rx_disruption.3561822535 | Feb 08 06:20:14 PM UTC 25 | Feb 08 06:20:30 PM UTC 25 | 585770396 ps | ||
| T3620 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/450.usbdev_tx_rx_disruption.2460153153 | Feb 08 06:20:13 PM UTC 25 | Feb 08 06:20:30 PM UTC 25 | 567784786 ps | ||
| T3621 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/458.usbdev_tx_rx_disruption.1221724075 | Feb 08 06:20:13 PM UTC 25 | Feb 08 06:20:31 PM UTC 25 | 651752616 ps | ||
| T228 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_intr_test.3497340366 | Feb 08 06:20:20 PM UTC 25 | Feb 08 06:20:23 PM UTC 25 | 32941587 ps | ||
| T250 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_rw.1019805777 | Feb 08 06:20:20 PM UTC 25 | Feb 08 06:20:23 PM UTC 25 | 37557580 ps | ||
| T225 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2218618900 | Feb 08 06:20:20 PM UTC 25 | Feb 08 06:20:23 PM UTC 25 | 118312700 ps | ||
| T242 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1787144167 | Feb 08 06:20:20 PM UTC 25 | Feb 08 06:20:24 PM UTC 25 | 125016690 ps | ||
| T219 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2124771712 | Feb 08 06:20:20 PM UTC 25 | Feb 08 06:20:24 PM UTC 25 | 59869955 ps | ||
| T220 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_errors.1121628745 | Feb 08 06:20:20 PM UTC 25 | Feb 08 06:20:24 PM UTC 25 | 72046800 ps | ||
| T243 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_aliasing.2056509400 | Feb 08 06:20:20 PM UTC 25 | Feb 08 06:20:25 PM UTC 25 | 219795228 ps | ||
| T275 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_partial_access.4042355459 | Feb 08 06:20:20 PM UTC 25 | Feb 08 06:20:25 PM UTC 25 | 164206853 ps | ||
| T226 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_intr_test.2661976910 | Feb 08 06:20:23 PM UTC 25 | Feb 08 06:20:25 PM UTC 25 | 103061552 ps | ||
| T221 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_errors.3726641202 | Feb 08 06:20:20 PM UTC 25 | Feb 08 06:20:26 PM UTC 25 | 308505857 ps | ||
| T241 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_intg_err.344103972 | Feb 08 06:20:20 PM UTC 25 | Feb 08 06:20:27 PM UTC 25 | 744201592 ps | ||
| T3622 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_walk.1131587440 | Feb 08 06:20:20 PM UTC 25 | Feb 08 06:20:27 PM UTC 25 | 719091806 ps | ||
| T248 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_intg_err.3840308925 | Feb 08 06:20:20 PM UTC 25 | Feb 08 06:20:27 PM UTC 25 | 710047758 ps | ||
| T3623 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_walk.1992555542 | Feb 08 06:20:23 PM UTC 25 | Feb 08 06:20:27 PM UTC 25 | 396215876 ps | ||
| T289 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_csr_rw.892487208 | Feb 08 06:20:32 PM UTC 25 | Feb 08 06:20:38 PM UTC 25 | 58149107 ps | ||
| T227 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_intr_test.1533349840 | Feb 08 06:20:25 PM UTC 25 | Feb 08 06:20:28 PM UTC 25 | 72771132 ps | ||
| T276 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_rw.2703456733 | Feb 08 06:20:25 PM UTC 25 | Feb 08 06:20:28 PM UTC 25 | 55726801 ps | ||
| T229 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1822887638 | Feb 08 06:20:25 PM UTC 25 | Feb 08 06:20:28 PM UTC 25 | 128065689 ps | ||
| T230 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3706376629 | Feb 08 06:20:25 PM UTC 25 | Feb 08 06:20:29 PM UTC 25 | 52177527 ps | ||
| T277 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_partial_access.2625283659 | Feb 08 06:20:25 PM UTC 25 | Feb 08 06:20:29 PM UTC 25 | 61317404 ps | ||
| T278 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_rw.1662065941 | Feb 08 06:20:25 PM UTC 25 | Feb 08 06:20:29 PM UTC 25 | 43684075 ps | ||
| T251 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1026027944 | Feb 08 06:20:25 PM UTC 25 | Feb 08 06:20:29 PM UTC 25 | 94526002 ps | ||
| T321 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_intr_test.3185197149 | Feb 08 06:20:27 PM UTC 25 | Feb 08 06:20:29 PM UTC 25 | 37949865 ps | ||
| T279 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_partial_access.2830295904 | Feb 08 06:20:25 PM UTC 25 | Feb 08 06:20:29 PM UTC 25 | 121407585 ps | ||
| T290 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4041775834 | Feb 08 06:20:25 PM UTC 25 | Feb 08 06:20:29 PM UTC 25 | 335882849 ps | ||
| T253 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_errors.3899724412 | Feb 08 06:20:25 PM UTC 25 | Feb 08 06:20:29 PM UTC 25 | 66986932 ps | ||
| T3624 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_aliasing.3667783884 | Feb 08 06:20:25 PM UTC 25 | Feb 08 06:20:29 PM UTC 25 | 216782435 ps | ||
| T280 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2275093178 | Feb 08 06:20:20 PM UTC 25 | Feb 08 06:20:30 PM UTC 25 | 1335329502 ps | ||
| T291 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2889127510 | Feb 08 06:20:26 PM UTC 25 | Feb 08 06:20:30 PM UTC 25 | 195857155 ps | ||
| T252 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_errors.2387471836 | Feb 08 06:20:26 PM UTC 25 | Feb 08 06:20:30 PM UTC 25 | 147148623 ps | ||
| T3625 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_aliasing.2281541931 | Feb 08 06:20:25 PM UTC 25 | Feb 08 06:20:30 PM UTC 25 | 170600652 ps | ||
| T263 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.994830022 | Feb 08 06:20:26 PM UTC 25 | Feb 08 06:20:30 PM UTC 25 | 164654796 ps | ||
| T3626 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_walk.3174369371 | Feb 08 06:20:25 PM UTC 25 | Feb 08 06:20:31 PM UTC 25 | 169197717 ps | ||
| T249 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_intg_err.1575047992 | Feb 08 06:20:25 PM UTC 25 | Feb 08 06:20:32 PM UTC 25 | 1095852616 ps | ||
| T281 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_rw.1549611599 | Feb 08 06:20:30 PM UTC 25 | Feb 08 06:20:33 PM UTC 25 | 72364447 ps | ||
| T296 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_hw_reset.466316906 | Feb 08 06:20:30 PM UTC 25 | Feb 08 06:20:33 PM UTC 25 | 118162800 ps | ||
| T322 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_intr_test.3267916841 | Feb 08 06:20:30 PM UTC 25 | Feb 08 06:20:33 PM UTC 25 | 49293811 ps | ||
| T282 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_rw.1717802503 | Feb 08 06:20:30 PM UTC 25 | Feb 08 06:20:33 PM UTC 25 | 68332729 ps | ||
| T292 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.907317246 | Feb 08 06:20:30 PM UTC 25 | Feb 08 06:20:33 PM UTC 25 | 123081152 ps | ||
| T259 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2958904973 | Feb 08 06:20:30 PM UTC 25 | Feb 08 06:20:34 PM UTC 25 | 119576527 ps | ||
| T3627 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_rw.1264123399 | Feb 08 06:20:28 PM UTC 25 | Feb 08 06:20:34 PM UTC 25 | 84047586 ps | ||
| T325 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_intr_test.1000328304 | Feb 08 06:20:28 PM UTC 25 | Feb 08 06:20:34 PM UTC 25 | 44628666 ps | ||
| T3628 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1340211673 | Feb 08 06:20:30 PM UTC 25 | Feb 08 06:20:34 PM UTC 25 | 159130177 ps | ||
| T283 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1540295165 | Feb 08 06:20:28 PM UTC 25 | Feb 08 06:20:34 PM UTC 25 | 123375597 ps | ||
| T261 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_intg_err.2693364540 | Feb 08 06:20:26 PM UTC 25 | Feb 08 06:20:34 PM UTC 25 | 1730136409 ps | ||
| T3629 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3515699547 | Feb 08 06:20:28 PM UTC 25 | Feb 08 06:20:34 PM UTC 25 | 115764421 ps | ||
| T284 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_partial_access.1162813708 | Feb 08 06:20:28 PM UTC 25 | Feb 08 06:20:34 PM UTC 25 | 59853116 ps | ||
| T264 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.141210625 | Feb 08 06:20:28 PM UTC 25 | Feb 08 06:20:34 PM UTC 25 | 100102254 ps | ||
| T285 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2192536528 | Feb 08 06:20:25 PM UTC 25 | Feb 08 06:20:34 PM UTC 25 | 1126897638 ps | ||
| T286 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_partial_access.363410613 | Feb 08 06:20:28 PM UTC 25 | Feb 08 06:20:35 PM UTC 25 | 211797927 ps | ||
| T3630 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_aliasing.3974496888 | Feb 08 06:20:28 PM UTC 25 | Feb 08 06:20:35 PM UTC 25 | 82514693 ps | ||
| T287 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_aliasing.573630203 | Feb 08 06:20:30 PM UTC 25 | Feb 08 06:20:35 PM UTC 25 | 129075079 ps | ||
| T3631 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_walk.2746906006 | Feb 08 06:20:28 PM UTC 25 | Feb 08 06:20:35 PM UTC 25 | 100451581 ps | ||
| T254 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_errors.2209260754 | Feb 08 06:20:30 PM UTC 25 | Feb 08 06:20:35 PM UTC 25 | 274614861 ps | ||
| T255 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_errors.3828265118 | Feb 08 06:20:28 PM UTC 25 | Feb 08 06:20:35 PM UTC 25 | 209495661 ps | ||
| T331 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_intg_err.3241549316 | Feb 08 06:20:28 PM UTC 25 | Feb 08 06:20:35 PM UTC 25 | 377324247 ps | ||
| T3632 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_bit_bash.788314571 | Feb 08 06:20:25 PM UTC 25 | Feb 08 06:20:35 PM UTC 25 | 1832855126 ps | ||
| T257 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_tl_errors.1930130661 | Feb 08 06:20:32 PM UTC 25 | Feb 08 06:20:36 PM UTC 25 | 170712233 ps | ||
| T3633 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1064627940 | Feb 08 06:20:32 PM UTC 25 | Feb 08 06:20:36 PM UTC 25 | 117553649 ps | ||
| T332 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_intg_err.3056637024 | Feb 08 06:20:30 PM UTC 25 | Feb 08 06:20:36 PM UTC 25 | 811616157 ps | ||
| T3634 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_walk.2933015856 | Feb 08 06:20:28 PM UTC 25 | Feb 08 06:20:36 PM UTC 25 | 178360660 ps | ||
| T326 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_intr_test.3591818359 | Feb 08 06:20:32 PM UTC 25 | Feb 08 06:20:37 PM UTC 25 | 35231327 ps | ||
| T288 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_csr_rw.1436207576 | Feb 08 06:20:32 PM UTC 25 | Feb 08 06:20:38 PM UTC 25 | 44268566 ps | ||
| T324 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_intr_test.871951356 | Feb 08 06:20:32 PM UTC 25 | Feb 08 06:20:38 PM UTC 25 | 43396453 ps | ||
| T3635 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1459943152 | Feb 08 06:20:32 PM UTC 25 | Feb 08 06:20:38 PM UTC 25 | 80989423 ps | ||
| T3636 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2292071303 | Feb 08 06:20:32 PM UTC 25 | Feb 08 06:20:38 PM UTC 25 | 52064245 ps | ||
| T3637 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_csr_rw.2992082320 | Feb 08 06:20:32 PM UTC 25 | Feb 08 06:20:38 PM UTC 25 | 51071657 ps | ||
| T3638 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2938941379 | Feb 08 06:20:32 PM UTC 25 | Feb 08 06:20:38 PM UTC 25 | 90896465 ps | ||
| T327 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_intr_test.920284174 | Feb 08 06:20:33 PM UTC 25 | Feb 08 06:20:38 PM UTC 25 | 55667120 ps | ||
| T323 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_intr_test.1518704056 | Feb 08 06:20:32 PM UTC 25 | Feb 08 06:20:38 PM UTC 25 | 51950592 ps | ||
| T3639 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_csr_rw.2999342749 | Feb 08 06:20:33 PM UTC 25 | Feb 08 06:20:38 PM UTC 25 | 61980062 ps | ||
| T3640 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3399360225 | Feb 08 06:20:33 PM UTC 25 | Feb 08 06:20:38 PM UTC 25 | 103692119 ps | ||
| T3641 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4072075314 | Feb 08 06:20:32 PM UTC 25 | Feb 08 06:20:38 PM UTC 25 | 183662003 ps | ||
| T3642 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3737960783 | Feb 08 06:20:33 PM UTC 25 | Feb 08 06:20:38 PM UTC 25 | 91967629 ps | ||
| T328 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_intr_test.1532395286 | Feb 08 06:20:37 PM UTC 25 | Feb 08 06:20:39 PM UTC 25 | 54700427 ps | ||
| T3643 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_intr_test.2464085301 | Feb 08 06:20:36 PM UTC 25 | Feb 08 06:20:39 PM UTC 25 | 41497636 ps | ||
| T3644 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.98416965 | Feb 08 06:20:33 PM UTC 25 | Feb 08 06:20:39 PM UTC 25 | 137583639 ps | ||
| T3645 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.251430545 | Feb 08 06:20:33 PM UTC 25 | Feb 08 06:20:39 PM UTC 25 | 126528800 ps | ||
| T333 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_tl_intg_err.1250019445 | Feb 08 06:20:32 PM UTC 25 | Feb 08 06:20:39 PM UTC 25 | 1207393644 ps | ||
| T3646 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_rw.3620492484 | Feb 08 06:20:36 PM UTC 25 | Feb 08 06:20:39 PM UTC 25 | 51667899 ps | ||
| T329 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_intr_test.1505800200 | Feb 08 06:20:36 PM UTC 25 | Feb 08 06:20:39 PM UTC 25 | 46904466 ps | ||
| T3647 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_rw.3149545353 | Feb 08 06:20:37 PM UTC 25 | Feb 08 06:20:39 PM UTC 25 | 50497356 ps | ||
| T330 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/35.usbdev_intr_test.3881425266 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 56352439 ps | ||
| T3648 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1010733527 | Feb 08 06:20:37 PM UTC 25 | Feb 08 06:20:39 PM UTC 25 | 68435514 ps | ||
| T256 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_tl_errors.937976960 | Feb 08 06:20:32 PM UTC 25 | Feb 08 06:20:39 PM UTC 25 | 157364607 ps | ||
| T3649 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2870216142 | Feb 08 06:20:30 PM UTC 25 | Feb 08 06:20:39 PM UTC 25 | 1936038110 ps | ||
| T3650 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_tl_errors.3096401556 | Feb 08 06:20:32 PM UTC 25 | Feb 08 06:20:39 PM UTC 25 | 182142315 ps | ||
| T3651 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3149174973 | Feb 08 06:20:36 PM UTC 25 | Feb 08 06:20:39 PM UTC 25 | 87380668 ps | ||
| T3652 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_rw.2566860261 | Feb 08 06:20:37 PM UTC 25 | Feb 08 06:20:39 PM UTC 25 | 154742604 ps | ||
| T3653 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.4020956269 | Feb 08 06:20:36 PM UTC 25 | Feb 08 06:20:40 PM UTC 25 | 102376886 ps | ||
| T3654 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_rw.751894663 | Feb 08 06:20:34 PM UTC 25 | Feb 08 06:20:40 PM UTC 25 | 40564062 ps | ||
| T3655 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.4048948182 | Feb 08 06:20:37 PM UTC 25 | Feb 08 06:20:40 PM UTC 25 | 124794767 ps | ||
| T3656 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2545369570 | Feb 08 06:20:37 PM UTC 25 | Feb 08 06:20:40 PM UTC 25 | 95966339 ps | ||
| T3657 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_intr_test.875076897 | Feb 08 06:20:34 PM UTC 25 | Feb 08 06:20:40 PM UTC 25 | 112099969 ps | ||
| T258 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_errors.695855183 | Feb 08 06:20:36 PM UTC 25 | Feb 08 06:20:40 PM UTC 25 | 73641868 ps | ||
| T495 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_tl_intg_err.2590914938 | Feb 08 06:20:33 PM UTC 25 | Feb 08 06:20:40 PM UTC 25 | 366430411 ps | ||
| T3658 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_tl_intg_err.2930343046 | Feb 08 06:20:32 PM UTC 25 | Feb 08 06:20:40 PM UTC 25 | 382347287 ps | ||
| T3659 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.188686593 | Feb 08 06:20:37 PM UTC 25 | Feb 08 06:20:40 PM UTC 25 | 172067024 ps | ||
| T3660 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_intg_err.1718799479 | Feb 08 06:20:36 PM UTC 25 | Feb 08 06:20:40 PM UTC 25 | 259806446 ps | ||
| T334 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_intg_err.1152692224 | Feb 08 06:20:37 PM UTC 25 | Feb 08 06:20:40 PM UTC 25 | 266796916 ps | ||
| T3661 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_errors.2925025455 | Feb 08 06:20:34 PM UTC 25 | Feb 08 06:20:40 PM UTC 25 | 114688770 ps | ||
| T3662 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2134257277 | Feb 08 06:20:28 PM UTC 25 | Feb 08 06:20:40 PM UTC 25 | 728848936 ps | ||
| T3663 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3408388194 | Feb 08 06:20:34 PM UTC 25 | Feb 08 06:20:41 PM UTC 25 | 352820963 ps | ||
| T3664 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_tl_errors.1394494681 | Feb 08 06:20:33 PM UTC 25 | Feb 08 06:20:41 PM UTC 25 | 305145915 ps | ||
| T3665 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.860360541 | Feb 08 06:20:34 PM UTC 25 | Feb 08 06:20:41 PM UTC 25 | 119993898 ps | ||
| T3666 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_errors.2278609583 | Feb 08 06:20:37 PM UTC 25 | Feb 08 06:20:41 PM UTC 25 | 224827269 ps | ||
| T336 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_tl_intg_err.2941224298 | Feb 08 06:20:32 PM UTC 25 | Feb 08 06:20:41 PM UTC 25 | 1214726333 ps | ||
| T3667 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_errors.3988819149 | Feb 08 06:20:34 PM UTC 25 | Feb 08 06:20:41 PM UTC 25 | 212381737 ps | ||
| T3668 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_errors.3068169381 | Feb 08 06:20:37 PM UTC 25 | Feb 08 06:20:41 PM UTC 25 | 123216705 ps | ||
| T3669 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_intg_err.904073344 | Feb 08 06:20:34 PM UTC 25 | Feb 08 06:20:43 PM UTC 25 | 667081008 ps | ||
| T335 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_intg_err.2018562786 | Feb 08 06:20:34 PM UTC 25 | Feb 08 06:20:43 PM UTC 25 | 477738525 ps | ||
| T3670 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3559459149 | Feb 08 06:21:00 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 133833319 ps | ||
| T3671 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_intr_test.2166532681 | Feb 08 06:20:41 PM UTC 25 | Feb 08 06:20:43 PM UTC 25 | 43725072 ps | ||
| T3672 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_intr_test.489770692 | Feb 08 06:20:41 PM UTC 25 | Feb 08 06:20:44 PM UTC 25 | 43598982 ps | ||
| T3673 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/33.usbdev_intr_test.3815433597 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 49750165 ps | ||
| T3674 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_rw.4051279188 | Feb 08 06:20:41 PM UTC 25 | Feb 08 06:20:44 PM UTC 25 | 90040701 ps | ||
| T3675 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4079848909 | Feb 08 06:20:41 PM UTC 25 | Feb 08 06:20:44 PM UTC 25 | 131035595 ps | ||
| T3676 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_rw.2238133419 | Feb 08 06:20:41 PM UTC 25 | Feb 08 06:20:44 PM UTC 25 | 96928706 ps | ||
| T3677 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_intr_test.231822984 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:44 PM UTC 25 | 63249084 ps | ||
| T3678 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_rw.4019841386 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:44 PM UTC 25 | 67962724 ps | ||
| T3679 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3253554892 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:44 PM UTC 25 | 129238503 ps | ||
| T3680 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_intr_test.905392133 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:44 PM UTC 25 | 39006209 ps | ||
| T3681 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_intr_test.2463720682 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:44 PM UTC 25 | 83564009 ps | ||
| T3682 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_rw.2737538608 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:44 PM UTC 25 | 76341370 ps | ||
| T3683 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3488367244 | Feb 08 06:20:41 PM UTC 25 | Feb 08 06:20:44 PM UTC 25 | 132187855 ps | ||
| T3684 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.100849588 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:44 PM UTC 25 | 159368871 ps | ||
| T3685 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_errors.2784763915 | Feb 08 06:20:41 PM UTC 25 | Feb 08 06:20:44 PM UTC 25 | 132302590 ps | ||
| T3686 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_rw.640007259 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:44 PM UTC 25 | 78987905 ps | ||
| T3687 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_intg_err.3567856603 | Feb 08 06:20:41 PM UTC 25 | Feb 08 06:20:45 PM UTC 25 | 334800016 ps | ||
| T3688 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.628037688 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:45 PM UTC 25 | 183749063 ps | ||
| T3689 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.345178609 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:45 PM UTC 25 | 116088441 ps | ||
| T3690 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2304372399 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:45 PM UTC 25 | 138875810 ps | ||
| T3691 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_errors.1991110521 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:45 PM UTC 25 | 72390786 ps | ||
| T3692 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_errors.2895177464 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:45 PM UTC 25 | 147389008 ps | ||
| T3693 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.33024914 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:45 PM UTC 25 | 159871280 ps | ||
| T3694 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1433347743 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:45 PM UTC 25 | 213726456 ps | ||
| T3695 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_intg_err.676851639 | Feb 08 06:20:41 PM UTC 25 | Feb 08 06:20:45 PM UTC 25 | 300257375 ps | ||
| T3696 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3171954098 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:45 PM UTC 25 | 152295569 ps | ||
| T3697 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_intg_err.3696251375 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:46 PM UTC 25 | 656885654 ps | ||
| T3698 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_intg_err.1410635424 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:46 PM UTC 25 | 410435264 ps | ||
| T3699 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_errors.3969680301 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:46 PM UTC 25 | 94338122 ps | ||
| T3700 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_errors.211923746 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:46 PM UTC 25 | 294885414 ps | ||
| T3701 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_intg_err.751669490 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:47 PM UTC 25 | 790159827 ps | ||
| T494 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_intg_err.3743693800 | Feb 08 06:20:42 PM UTC 25 | Feb 08 06:20:48 PM UTC 25 | 811803683 ps | ||
| T3702 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_intr_test.3062702157 | Feb 08 06:21:00 PM UTC 25 | Feb 08 06:21:02 PM UTC 25 | 34374334 ps | ||
| T3703 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/21.usbdev_intr_test.2431941540 | Feb 08 06:21:00 PM UTC 25 | Feb 08 06:21:02 PM UTC 25 | 49003473 ps | ||
| T3704 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/22.usbdev_intr_test.891428682 | Feb 08 06:21:00 PM UTC 25 | Feb 08 06:21:02 PM UTC 25 | 34341732 ps | ||
| T3705 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/26.usbdev_intr_test.2655127681 | Feb 08 06:21:00 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 35737846 ps | ||
| T3706 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/32.usbdev_intr_test.3263147080 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 34475274 ps | ||
| T3707 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/31.usbdev_intr_test.3335466813 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 53101140 ps | ||
| T3708 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/37.usbdev_intr_test.3595291007 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 41907044 ps | ||
| T3709 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_rw.1006219596 | Feb 08 06:21:00 PM UTC 25 | Feb 08 06:21:02 PM UTC 25 | 58053051 ps | ||
| T3710 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/20.usbdev_intr_test.2040126666 | Feb 08 06:21:00 PM UTC 25 | Feb 08 06:21:02 PM UTC 25 | 102764641 ps | ||
| T3711 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/23.usbdev_intr_test.4118729327 | Feb 08 06:21:00 PM UTC 25 | Feb 08 06:21:02 PM UTC 25 | 69222616 ps | ||
| T3712 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/24.usbdev_intr_test.1534185154 | Feb 08 06:21:00 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 123388025 ps | ||
| T3713 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/28.usbdev_intr_test.728360555 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 42973699 ps | ||
| T3714 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/30.usbdev_intr_test.1650896024 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 41592867 ps | ||
| T3715 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/25.usbdev_intr_test.1582710835 | Feb 08 06:21:00 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 53157694 ps | ||
| T3716 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/29.usbdev_intr_test.3953646150 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 36181723 ps | ||
| T3717 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/27.usbdev_intr_test.541034510 | Feb 08 06:21:00 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 112883020 ps | ||
| T3718 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/34.usbdev_intr_test.1798625651 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 37497119 ps | ||
| T3719 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/36.usbdev_intr_test.2234178873 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 67010774 ps | ||
| T3720 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/44.usbdev_intr_test.779744020 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 33303202 ps | ||
| T3721 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/41.usbdev_intr_test.2092854682 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 60582205 ps | ||
| T3722 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/38.usbdev_intr_test.2433650590 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 81903251 ps | ||
| T3723 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/39.usbdev_intr_test.2809335892 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 81990835 ps | ||
| T3724 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/40.usbdev_intr_test.3483672659 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 79881549 ps | ||
| T3725 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/42.usbdev_intr_test.2201306867 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 42067464 ps | ||
| T3726 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2741172499 | Feb 08 06:21:00 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 133471490 ps | ||
| T3727 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/43.usbdev_intr_test.2249505342 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 44524458 ps | ||
| T3728 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/45.usbdev_intr_test.1978038763 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 36606201 ps | ||
| T3729 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/47.usbdev_intr_test.3211625906 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:03 PM UTC 25 | 66354614 ps | ||
| T3730 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/46.usbdev_intr_test.2082211066 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:04 PM UTC 25 | 48409003 ps | ||
| T3731 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/48.usbdev_intr_test.2494900276 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:04 PM UTC 25 | 95722946 ps | ||
| T3732 | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/49.usbdev_intr_test.3107083056 | Feb 08 06:21:01 PM UTC 25 | Feb 08 06:21:04 PM UTC 25 | 32829204 ps |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_restore.2818809002 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1164454536 ps |
| CPU time | 5.89 seconds |
| Started | Feb 08 05:51:39 PM UTC 25 |
| Finished | Feb 08 05:51:46 PM UTC 25 |
| Peak memory | 217392 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818809002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2818809002 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_device_address.257630083 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 30318728653 ps |
| CPU time | 85.15 seconds |
| Started | Feb 08 05:51:40 PM UTC 25 |
| Finished | Feb 08 05:53:07 PM UTC 25 |
| Peak memory | 217676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=257630083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.us bdev_device_address.257630083 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_reset.2758131656 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 13808703688 ps |
| CPU time | 37.25 seconds |
| Started | Feb 08 05:51:34 PM UTC 25 |
| Finished | Feb 08 05:52:13 PM UTC 25 |
| Peak memory | 227592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758131656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.2758131656 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_intr_test.3185197149 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 37949865 ps |
| CPU time | 0.63 seconds |
| Started | Feb 08 06:20:27 PM UTC 25 |
| Finished | Feb 08 06:20:29 PM UTC 25 |
| Peak memory | 216768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185197149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.usbdev_intr_test.3185197149 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_resume.1947079809 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 31060478583 ps |
| CPU time | 65.61 seconds |
| Started | Feb 08 05:51:34 PM UTC 25 |
| Finished | Feb 08 05:52:42 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947079809 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.1947079809 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_max_usb_traffic.3749661985 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 2597946332 ps |
| CPU time | 73.99 seconds |
| Started | Feb 08 05:52:40 PM UTC 25 |
| Finished | Feb 08 05:53:56 PM UTC 25 |
| Peak memory | 234356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749661985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_ traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 0.usbdev_max_usb_traffic.3749661985 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_intg_err.1575047992 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 1095852616 ps |
| CPU time | 4.55 seconds |
| Started | Feb 08 06:20:25 PM UTC 25 |
| Finished | Feb 08 06:20:32 PM UTC 25 |
| Peak memory | 217892 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575047992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1575047992 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_bitstuff_err.1174051453 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 149799444 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 05:51:39 PM UTC 25 |
| Finished | Feb 08 05:51:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1174051453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usb dev_bitstuff_err.1174051453 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_sec_cm.2802779323 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 482177699 ps |
| CPU time | 2.58 seconds |
| Started | Feb 08 05:54:07 PM UTC 25 |
| Finished | Feb 08 05:54:11 PM UTC 25 |
| Peak memory | 251740 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802779323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 0.usbdev_sec_cm.2802779323 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_disconnect.3125583547 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 6335968635 ps |
| CPU time | 11.61 seconds |
| Started | Feb 08 05:57:28 PM UTC 25 |
| Finished | Feb 08 05:57:41 PM UTC 25 |
| Peak memory | 227660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125583547 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.3125583547 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.2359966731 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 301865343 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 05:53:09 PM UTC 25 |
| Finished | Feb 08 05:53:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2359966731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.2359966731 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_phy_config_tx_osc_test_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_buffer.1837131019 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 19226866210 ps |
| CPU time | 76.49 seconds |
| Started | Feb 08 05:53:13 PM UTC 25 |
| Finished | Feb 08 05:54:31 PM UTC 25 |
| Peak memory | 227808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1837131019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbde v_pkt_buffer.1837131019 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_errors.3726641202 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 308505857 ps |
| CPU time | 3.24 seconds |
| Started | Feb 08 06:20:20 PM UTC 25 |
| Finished | Feb 08 06:20:26 PM UTC 25 |
| Peak memory | 232344 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726641202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.usbdev_tl_errors.3726641202 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_phy_pins_sense.259743068 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 40135708 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 05:55:39 PM UTC 25 |
| Finished | Feb 08 05:55:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=259743068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.us bdev_phy_pins_sense.259743068 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_intr_test.2661976910 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 103061552 ps |
| CPU time | 0.73 seconds |
| Started | Feb 08 06:20:23 PM UTC 25 |
| Finished | Feb 08 06:20:25 PM UTC 25 |
| Peak memory | 216544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661976910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.usbdev_intr_test.2661976910 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_link_resume.2044287354 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 13580325259 ps |
| CPU time | 33.26 seconds |
| Started | Feb 08 05:54:57 PM UTC 25 |
| Finished | Feb 08 05:55:32 PM UTC 25 |
| Peak memory | 217384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2044287354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbd ev_link_resume.2044287354 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_device_timeout.2923822212 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1300089413 ps |
| CPU time | 35.12 seconds |
| Started | Feb 08 05:51:42 PM UTC 25 |
| Finished | Feb 08 05:52:19 PM UTC 25 |
| Peak memory | 217544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923822212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.2923822212 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_device_address.2692520497 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 36877399394 ps |
| CPU time | 92.42 seconds |
| Started | Feb 08 05:54:25 PM UTC 25 |
| Finished | Feb 08 05:56:00 PM UTC 25 |
| Peak memory | 217580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2692520497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.u sbdev_device_address.2692520497 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_link_suspend.608841137 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 8990387892 ps |
| CPU time | 16.16 seconds |
| Started | Feb 08 05:56:41 PM UTC 25 |
| Finished | Feb 08 05:56:58 PM UTC 25 |
| Peak memory | 217388 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=608841137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbd ev_link_suspend.608841137 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_rw.1019805777 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 37557580 ps |
| CPU time | 0.69 seconds |
| Started | Feb 08 06:20:20 PM UTC 25 |
| Finished | Feb 08 06:20:23 PM UTC 25 |
| Peak memory | 216956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019805777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1019805777 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_resume_link_active.1083752022 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 20164616681 ps |
| CPU time | 47.71 seconds |
| Started | Feb 08 05:53:28 PM UTC 25 |
| Finished | Feb 08 05:54:18 PM UTC 25 |
| Peak memory | 217276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1083752022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.1083752022 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_resume_link_active/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_tx_rx_disruption.1296782864 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 593520211 ps |
| CPU time | 2.59 seconds |
| Started | Feb 08 06:08:51 PM UTC 25 |
| Finished | Feb 08 06:08:55 PM UTC 25 |
| Peak memory | 217116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 296782864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_tx_rx_disruption.1296782864 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_link_resume.3114899975 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 9109547685 ps |
| CPU time | 15.61 seconds |
| Started | Feb 08 06:05:07 PM UTC 25 |
| Finished | Feb 08 06:05:24 PM UTC 25 |
| Peak memory | 227784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3114899975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usb dev_link_resume.3114899975 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_tx_rx_disruption.2294398374 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 578518971 ps |
| CPU time | 2.46 seconds |
| Started | Feb 08 06:05:52 PM UTC 25 |
| Finished | Feb 08 06:05:55 PM UTC 25 |
| Peak memory | 217308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 294398374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_tx_rx_disruption.2294398374 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/345.usbdev_tx_rx_disruption.3649423302 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 532803221 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:19:41 PM UTC 25 |
| Finished | Feb 08 06:19:44 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 649423302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 345.usbdev_tx_rx_disruption.3649423302 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/345.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_endpoint_types.3746978887 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 575310821 ps |
| CPU time | 2.67 seconds |
| Started | Feb 08 05:57:50 PM UTC 25 |
| Finished | Feb 08 05:57:54 PM UTC 25 |
| Peak memory | 217144 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746978887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 3.usbdev_endpoint_types.3746978887 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_rx_full.3585104044 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 259818147 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 05:58:26 PM UTC 25 |
| Finished | Feb 08 05:58:28 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3585104044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_r x_full.3585104044 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_intr_test.875076897 |
| Short name | T3657 |
| Test name | |
| Test status | |
| Simulation time | 112099969 ps |
| CPU time | 0.76 seconds |
| Started | Feb 08 06:20:34 PM UTC 25 |
| Finished | Feb 08 06:20:40 PM UTC 25 |
| Peak memory | 216544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875076897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 10.usbdev_intr_test.875076897 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_stress_usb_traffic.1490272924 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 11058913795 ps |
| CPU time | 240.6 seconds |
| Started | Feb 08 05:54:04 PM UTC 25 |
| Finished | Feb 08 05:58:08 PM UTC 25 |
| Peak memory | 229688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490272924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM _TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.1490272924 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_stress_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_endpoint_types.3862307008 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 668040039 ps |
| CPU time | 1.99 seconds |
| Started | Feb 08 06:08:36 PM UTC 25 |
| Finished | Feb 08 06:08:40 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862307008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 21.usbdev_endpoint_types.3862307008 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/68.usbdev_endpoint_types.1818795189 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 567151902 ps |
| CPU time | 1.72 seconds |
| Started | Feb 08 06:18:09 PM UTC 25 |
| Finished | Feb 08 06:18:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818795189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 68.usbdev_endpoint_types.1818795189 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/68.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_disconnected.3297285492 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 140080983 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:01:45 PM UTC 25 |
| Finished | Feb 08 06:01:48 PM UTC 25 |
| Peak memory | 216768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3297285492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usb dev_disconnected.3297285492 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_low_speed_traffic.93927464 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 3343746172 ps |
| CPU time | 32.95 seconds |
| Started | Feb 08 05:56:42 PM UTC 25 |
| Finished | Feb 08 05:57:16 PM UTC 25 |
| Peak memory | 234628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93927464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_ traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 2.usbdev_low_speed_traffic.93927464 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_device_address.1444281508 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 19191493899 ps |
| CPU time | 60.84 seconds |
| Started | Feb 08 06:00:49 PM UTC 25 |
| Finished | Feb 08 06:01:52 PM UTC 25 |
| Peak memory | 217496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1444281508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.u sbdev_device_address.1444281508 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_received.1798186594 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 170527757 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 05:53:13 PM UTC 25 |
| Finished | Feb 08 05:53:15 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1798186594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usb dev_pkt_received.1798186594 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_endpoint_types.905300507 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 670174648 ps |
| CPU time | 2.28 seconds |
| Started | Feb 08 06:05:03 PM UTC 25 |
| Finished | Feb 08 06:05:06 PM UTC 25 |
| Peak memory | 217080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905300507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 13.usbdev_endpoint_types.905300507 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_rx_crc_err.3166368807 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 148369055 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 05:53:42 PM UTC 25 |
| Finished | Feb 08 05:53:45 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3166368807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbde v_rx_crc_err.3166368807 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_endpoint_types.2272145578 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 719130912 ps |
| CPU time | 2.49 seconds |
| Started | Feb 08 06:17:27 PM UTC 25 |
| Finished | Feb 08 06:17:31 PM UTC 25 |
| Peak memory | 217084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272145578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 48.usbdev_endpoint_types.2272145578 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/97.usbdev_endpoint_types.1693215736 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 705215460 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 06:18:19 PM UTC 25 |
| Finished | Feb 08 06:18:22 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693215736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 97.usbdev_endpoint_types.1693215736 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/97.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/157.usbdev_endpoint_types.4047072840 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 521014154 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:18:34 PM UTC 25 |
| Finished | Feb 08 06:18:38 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047072840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 157.usbdev_endpoint_types.4047072840 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/157.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/179.usbdev_endpoint_types.1233156379 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 809498976 ps |
| CPU time | 1.67 seconds |
| Started | Feb 08 06:18:38 PM UTC 25 |
| Finished | Feb 08 06:19:45 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233156379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 179.usbdev_endpoint_types.1233156379 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/179.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_endpoint_types.3143196142 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 512925380 ps |
| CPU time | 2.33 seconds |
| Started | Feb 08 06:00:20 PM UTC 25 |
| Finished | Feb 08 06:00:24 PM UTC 25 |
| Peak memory | 217080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143196142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 5.usbdev_endpoint_types.3143196142 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority.304852660 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 404312323 ps |
| CPU time | 2.56 seconds |
| Started | Feb 08 05:53:50 PM UTC 25 |
| Finished | Feb 08 05:53:53 PM UTC 25 |
| Peak memory | 217288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=304852660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.us bdev_setup_priority.304852660 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_setup_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_intg_err.3056637024 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 811616157 ps |
| CPU time | 3.78 seconds |
| Started | Feb 08 06:20:30 PM UTC 25 |
| Finished | Feb 08 06:20:36 PM UTC 25 |
| Peak memory | 217960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056637024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3056637024 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/60.usbdev_endpoint_types.1317879409 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 560274429 ps |
| CPU time | 2 seconds |
| Started | Feb 08 06:18:06 PM UTC 25 |
| Finished | Feb 08 06:18:09 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317879409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 60.usbdev_endpoint_types.1317879409 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/60.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_endpoint_types.1376990434 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 313659832 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 05:54:33 PM UTC 25 |
| Finished | Feb 08 05:54:36 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376990434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 1.usbdev_endpoint_types.1376990434 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_endpoint_types.3534642946 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 505392577 ps |
| CPU time | 2.52 seconds |
| Started | Feb 08 06:03:55 PM UTC 25 |
| Finished | Feb 08 06:03:59 PM UTC 25 |
| Peak memory | 217148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534642946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 11.usbdev_endpoint_types.3534642946 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_endpoint_types.2984705854 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 378226058 ps |
| CPU time | 1.85 seconds |
| Started | Feb 08 06:04:26 PM UTC 25 |
| Finished | Feb 08 06:04:29 PM UTC 25 |
| Peak memory | 215072 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984705854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 12.usbdev_endpoint_types.2984705854 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_data_toggle_restore.3381703723 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 989036880 ps |
| CPU time | 2.82 seconds |
| Started | Feb 08 06:07:19 PM UTC 25 |
| Finished | Feb 08 06:07:24 PM UTC 25 |
| Peak memory | 217316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381703723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.3381703723 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/189.usbdev_endpoint_types.657696821 |
| Short name | T3323 |
| Test name | |
| Test status | |
| Simulation time | 441948994 ps |
| CPU time | 1.21 seconds |
| Started | Feb 08 06:18:41 PM UTC 25 |
| Finished | Feb 08 06:19:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657696821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 189.usbdev_endpoint_types.657696821 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/189.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_endpoint_types.1407398724 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 424414168 ps |
| CPU time | 1.72 seconds |
| Started | Feb 08 06:11:15 PM UTC 25 |
| Finished | Feb 08 06:11:18 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407398724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 28.usbdev_endpoint_types.1407398724 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/65.usbdev_endpoint_types.2847067904 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 454845423 ps |
| CPU time | 2.12 seconds |
| Started | Feb 08 06:18:09 PM UTC 25 |
| Finished | Feb 08 06:18:12 PM UTC 25 |
| Peak memory | 217296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847067904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 65.usbdev_endpoint_types.2847067904 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/65.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/98.usbdev_endpoint_types.1701945614 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 714668924 ps |
| CPU time | 1.72 seconds |
| Started | Feb 08 06:18:19 PM UTC 25 |
| Finished | Feb 08 06:18:22 PM UTC 25 |
| Peak memory | 215052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701945614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 98.usbdev_endpoint_types.1701945614 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/98.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_alert_test.3239744532 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 33483517 ps |
| CPU time | 0.92 seconds |
| Started | Feb 08 05:54:07 PM UTC 25 |
| Finished | Feb 08 05:54:09 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239744532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.usbdev_alert_test.3239744532 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.2764134435 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 528700341 ps |
| CPU time | 2.33 seconds |
| Started | Feb 08 05:52:06 PM UTC 25 |
| Finished | Feb 08 05:52:09 PM UTC 25 |
| Peak memory | 217244 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2764134435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usb dev_invalid_data1_data0_toggle_test.2764134435 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_invalid_data1_data0_toggle_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_tx_rx_disruption.3937544595 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 645890128 ps |
| CPU time | 2.88 seconds |
| Started | Feb 08 06:00:40 PM UTC 25 |
| Finished | Feb 08 06:00:45 PM UTC 25 |
| Peak memory | 217116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 937544595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_tx_rx_disruption.3937544595 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_disconnects.722614925 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 6217815438 ps |
| CPU time | 30.52 seconds |
| Started | Feb 08 05:53:17 PM UTC 25 |
| Finished | Feb 08 05:53:49 PM UTC 25 |
| Peak memory | 234452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722614925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.722614925 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_rand_bus_disconnects/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/113.usbdev_endpoint_types.2274331545 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 669112389 ps |
| CPU time | 1.86 seconds |
| Started | Feb 08 06:18:24 PM UTC 25 |
| Finished | Feb 08 06:18:27 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274331545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 113.usbdev_endpoint_types.2274331545 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/113.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/167.usbdev_endpoint_types.3752402826 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 438460607 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:37 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752402826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 167.usbdev_endpoint_types.3752402826 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/167.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_pkt_buffer.566678156 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 18640347104 ps |
| CPU time | 51.47 seconds |
| Started | Feb 08 06:07:32 PM UTC 25 |
| Finished | Feb 08 06:08:25 PM UTC 25 |
| Peak memory | 231904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=566678156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbde v_pkt_buffer.566678156 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/196.usbdev_endpoint_types.409292186 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 600633501 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 06:18:45 PM UTC 25 |
| Finished | Feb 08 06:18:54 PM UTC 25 |
| Peak memory | 214616 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409292186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 196.usbdev_endpoint_types.409292186 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/196.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_data_toggle_restore.1420142218 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 937987972 ps |
| CPU time | 4.82 seconds |
| Started | Feb 08 06:08:54 PM UTC 25 |
| Finished | Feb 08 06:09:00 PM UTC 25 |
| Peak memory | 217452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420142218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.1420142218 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_endpoint_types.3883149342 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 375421507 ps |
| CPU time | 2.27 seconds |
| Started | Feb 08 06:10:14 PM UTC 25 |
| Finished | Feb 08 06:10:18 PM UTC 25 |
| Peak memory | 217084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883149342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 25.usbdev_endpoint_types.3883149342 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_endpoint_types.4057021407 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 637266702 ps |
| CPU time | 1.77 seconds |
| Started | Feb 08 06:12:45 PM UTC 25 |
| Finished | Feb 08 06:12:48 PM UTC 25 |
| Peak memory | 215060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057021407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 33.usbdev_endpoint_types.4057021407 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/82.usbdev_endpoint_types.1718578091 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 407684928 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:18:14 PM UTC 25 |
| Finished | Feb 08 06:18:17 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718578091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 82.usbdev_endpoint_types.1718578091 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/82.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_rand_bus_resets.1733772172 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 3139021583 ps |
| CPU time | 65.74 seconds |
| Started | Feb 08 06:00:35 PM UTC 25 |
| Finished | Feb 08 06:01:43 PM UTC 25 |
| Peak memory | 234288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733772172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 5.usbdev_rand_bus_resets.1733772172 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_rand_bus_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2275093178 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1335329502 ps |
| CPU time | 6.96 seconds |
| Started | Feb 08 06:20:20 PM UTC 25 |
| Finished | Feb 08 06:20:30 PM UTC 25 |
| Peak memory | 217952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275093178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2275093178 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_av_overflow.4234507602 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 138801730 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 05:51:36 PM UTC 25 |
| Finished | Feb 08 05:51:38 PM UTC 25 |
| Peak memory | 216564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4234507602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbd ev_av_overflow.4234507602 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_intr_test.1532395286 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 54700427 ps |
| CPU time | 0.63 seconds |
| Started | Feb 08 06:20:37 PM UTC 25 |
| Finished | Feb 08 06:20:39 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532395286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 13.usbdev_intr_test.1532395286 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_dpi_config_host.2159980619 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 5105828203 ps |
| CPU time | 169.55 seconds |
| Started | Feb 08 05:51:50 PM UTC 25 |
| Finished | Feb 08 05:54:42 PM UTC 25 |
| Peak memory | 227848 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2159980619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0. usbdev_dpi_config_host.2159980619 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_dpi_config_host/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/137.usbdev_endpoint_types.214660862 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 290252057 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:18:28 PM UTC 25 |
| Finished | Feb 08 06:18:31 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214660862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 137.usbdev_endpoint_types.214660862 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/137.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_endpoint_types.20883019 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 435393446 ps |
| CPU time | 1.71 seconds |
| Started | Feb 08 06:12:13 PM UTC 25 |
| Finished | Feb 08 06:12:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20883019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_t ypes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_types.20883019 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_endpoint_types.3174582278 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 458830782 ps |
| CPU time | 2.2 seconds |
| Started | Feb 08 06:13:55 PM UTC 25 |
| Finished | Feb 08 06:13:59 PM UTC 25 |
| Peak memory | 217276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174582278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 37.usbdev_endpoint_types.3174582278 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/85.usbdev_endpoint_types.244875350 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 400805739 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:18:16 PM UTC 25 |
| Finished | Feb 08 06:18:19 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244875350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 85.usbdev_endpoint_types.244875350 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/85.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/92.usbdev_endpoint_types.3831092124 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 593915229 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:18:17 PM UTC 25 |
| Finished | Feb 08 06:18:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831092124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 92.usbdev_endpoint_types.3831092124 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/92.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_nak_trans.433511458 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 215570219 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 05:52:55 PM UTC 25 |
| Finished | Feb 08 05:52:57 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=433511458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ nak_trans.433511458 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_invalid_sync.2959798979 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 2668344982 ps |
| CPU time | 91.96 seconds |
| Started | Feb 08 05:54:45 PM UTC 25 |
| Finished | Feb 08 05:56:19 PM UTC 25 |
| Peak memory | 234496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959798979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.2959798979 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_phy_pins_sense.1678142228 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 57578927 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 06:04:45 PM UTC 25 |
| Finished | Feb 08 06:04:47 PM UTC 25 |
| Peak memory | 214792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1678142228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12. usbdev_phy_pins_sense.1678142228 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_intg_err.344103972 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 744201592 ps |
| CPU time | 4 seconds |
| Started | Feb 08 06:20:20 PM UTC 25 |
| Finished | Feb 08 06:20:27 PM UTC 25 |
| Peak memory | 217796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344103972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.344103972 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_types.3047041438 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 216516851 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 05:51:54 PM UTC 25 |
| Finished | Feb 08 05:51:57 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047041438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 0.usbdev_endpoint_types.3047041438 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_freq_hiclk.1155929631 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 83180622463 ps |
| CPU time | 214.1 seconds |
| Started | Feb 08 05:51:57 PM UTC 25 |
| Finished | Feb 08 05:55:34 PM UTC 25 |
| Peak memory | 217408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155929631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phas e_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 0.usbdev_freq_hiclk.1155929631 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_freq_hiclk/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_rx_full.1015086371 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 364294831 ps |
| CPU time | 2.3 seconds |
| Started | Feb 08 05:55:50 PM UTC 25 |
| Finished | Feb 08 05:55:53 PM UTC 25 |
| Peak memory | 217364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1015086371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_r x_full.1015086371 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_endpoint_types.704060587 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 352410721 ps |
| CPU time | 2.08 seconds |
| Started | Feb 08 06:03:24 PM UTC 25 |
| Finished | Feb 08 06:03:27 PM UTC 25 |
| Peak memory | 217080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704060587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 10.usbdev_endpoint_types.704060587 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_low_speed_traffic.1800412989 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 2716165722 ps |
| CPU time | 24.92 seconds |
| Started | Feb 08 06:04:33 PM UTC 25 |
| Finished | Feb 08 06:05:00 PM UTC 25 |
| Peak memory | 234364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800412989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 12.usbdev_low_speed_traffic.1800412989 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/124.usbdev_endpoint_types.503277157 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 234178923 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 06:18:26 PM UTC 25 |
| Finished | Feb 08 06:18:29 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503277157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 124.usbdev_endpoint_types.503277157 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/124.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/139.usbdev_endpoint_types.2290781487 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 453173165 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 06:18:28 PM UTC 25 |
| Finished | Feb 08 06:18:31 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290781487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 139.usbdev_endpoint_types.2290781487 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/139.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/142.usbdev_endpoint_types.2495602769 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 613493582 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:18:30 PM UTC 25 |
| Finished | Feb 08 06:18:33 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495602769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 142.usbdev_endpoint_types.2495602769 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/142.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/147.usbdev_endpoint_types.2859565368 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 284294039 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 06:18:30 PM UTC 25 |
| Finished | Feb 08 06:18:33 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859565368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 147.usbdev_endpoint_types.2859565368 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/147.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_rx_full.549363513 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 249317256 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:06:18 PM UTC 25 |
| Finished | Feb 08 06:06:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=549363513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_r x_full.549363513 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/154.usbdev_endpoint_types.1179672307 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 677550748 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:18:32 PM UTC 25 |
| Finished | Feb 08 06:18:35 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179672307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 154.usbdev_endpoint_types.1179672307 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/154.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/163.usbdev_endpoint_types.2380863494 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 652310464 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380863494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 163.usbdev_endpoint_types.2380863494 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/163.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/197.usbdev_endpoint_types.2436335196 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 186998174 ps |
| CPU time | 0.85 seconds |
| Started | Feb 08 06:18:45 PM UTC 25 |
| Finished | Feb 08 06:19:23 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436335196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 197.usbdev_endpoint_types.2436335196 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/197.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/198.usbdev_endpoint_types.1170488565 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 299047757 ps |
| CPU time | 1 seconds |
| Started | Feb 08 06:18:45 PM UTC 25 |
| Finished | Feb 08 06:19:08 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170488565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 198.usbdev_endpoint_types.1170488565 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/198.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_rx_full.3790290356 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 245879690 ps |
| CPU time | 1.84 seconds |
| Started | Feb 08 06:08:48 PM UTC 25 |
| Finished | Feb 08 06:08:51 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3790290356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_ rx_full.3790290356 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_rx_full.824470732 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 277793948 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:11:07 PM UTC 25 |
| Finished | Feb 08 06:11:09 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=824470732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_r x_full.824470732 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_low_speed_traffic.3286229645 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 4971606973 ps |
| CPU time | 48.77 seconds |
| Started | Feb 08 06:11:37 PM UTC 25 |
| Finished | Feb 08 06:12:27 PM UTC 25 |
| Peak memory | 234456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286229645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 29.usbdev_low_speed_traffic.3286229645 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_data_toggle_restore.295802165 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 801402030 ps |
| CPU time | 3.79 seconds |
| Started | Feb 08 05:57:36 PM UTC 25 |
| Finished | Feb 08 05:57:41 PM UTC 25 |
| Peak memory | 217424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295802165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_t oggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.295802165 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_endpoint_types.1431669329 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 345349895 ps |
| CPU time | 1.86 seconds |
| Started | Feb 08 06:12:59 PM UTC 25 |
| Finished | Feb 08 06:13:02 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431669329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 34.usbdev_endpoint_types.1431669329 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_endpoint_types.3482240939 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 770961337 ps |
| CPU time | 3.1 seconds |
| Started | Feb 08 06:14:51 PM UTC 25 |
| Finished | Feb 08 06:14:55 PM UTC 25 |
| Peak memory | 217084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482240939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 40.usbdev_endpoint_types.3482240939 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_endpoint_types.2646409715 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 306086519 ps |
| CPU time | 1.96 seconds |
| Started | Feb 08 06:16:47 PM UTC 25 |
| Finished | Feb 08 06:16:50 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646409715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 46.usbdev_endpoint_types.2646409715 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_usb_ref_disable.2114824253 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 139681651 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 05:53:09 PM UTC 25 |
| Finished | Feb 08 05:53:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2114824253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.2114824253 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_link_suspend.3633626190 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 6236930407 ps |
| CPU time | 15.64 seconds |
| Started | Feb 08 06:03:30 PM UTC 25 |
| Finished | Feb 08 06:03:47 PM UTC 25 |
| Peak memory | 227784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3633626190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.us bdev_link_suspend.3633626190 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_errors.3988819149 |
| Short name | T3667 |
| Test name | |
| Test status | |
| Simulation time | 212381737 ps |
| CPU time | 2.21 seconds |
| Started | Feb 08 06:20:34 PM UTC 25 |
| Finished | Feb 08 06:20:41 PM UTC 25 |
| Peak memory | 234908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988819149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 11.usbdev_tl_errors.3988819149 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_av_overflow.385633198 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 207502970 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 05:56:13 PM UTC 25 |
| Finished | Feb 08 05:56:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=385633198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbde v_av_overflow.385633198 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_av_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_av_empty.3142873407 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 219067270 ps |
| CPU time | 1.67 seconds |
| Started | Feb 08 05:51:36 PM UTC 25 |
| Finished | Feb 08 05:51:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3142873407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ av_empty.3142873407 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_host_lost.3514672021 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4179899514 ps |
| CPU time | 16.64 seconds |
| Started | Feb 08 05:52:03 PM UTC 25 |
| Finished | Feb 08 05:52:21 PM UTC 25 |
| Peak memory | 217444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3514672021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev _host_lost.3514672021 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_host_lost/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_link_reset.3877437147 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 168200129 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 05:52:18 PM UTC 25 |
| Finished | Feb 08 05:52:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3877437147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbde v_link_reset.3877437147 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_link_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_use_d_se0.2907121763 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 221563672 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 05:53:09 PM UTC 25 |
| Finished | Feb 08 05:53:12 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907121763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.usbdev_phy_config_tx_use_d_se0.2907121763 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_phy_config_tx_use_d_se0/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_rx_pid_err.1506379278 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 153040048 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 05:53:50 PM UTC 25 |
| Finished | Feb 08 05:53:52 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1506379278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbde v_rx_pid_err.1506379278 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_rx_pid_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2218618900 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 118312700 ps |
| CPU time | 0.86 seconds |
| Started | Feb 08 06:20:20 PM UTC 25 |
| Finished | Feb 08 06:20:23 PM UTC 25 |
| Peak memory | 216964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218618900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2218618900 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_intg_err.2693364540 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1730136409 ps |
| CPU time | 5.72 seconds |
| Started | Feb 08 06:20:26 PM UTC 25 |
| Finished | Feb 08 06:20:34 PM UTC 25 |
| Peak memory | 217960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693364540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2693364540 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_rst.2327249029 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 249094355 ps |
| CPU time | 3.15 seconds |
| Started | Feb 08 05:51:55 PM UTC 25 |
| Finished | Feb 08 05:51:59 PM UTC 25 |
| Peak memory | 217536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2327249029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ fifo_rst.2327249029 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_iso_retraction.2658072664 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 8603748304 ps |
| CPU time | 119.32 seconds |
| Started | Feb 08 05:52:13 PM UTC 25 |
| Finished | Feb 08 05:54:15 PM UTC 25 |
| Peak memory | 217416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658072664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 0.usbdev_iso_retraction.2658072664 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_nak_trans.3218028088 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 222433915 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 05:55:32 PM UTC 25 |
| Finished | Feb 08 05:55:35 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3218028088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev _nak_trans.3218028088 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_stress_usb_traffic.3515621379 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 8086585703 ps |
| CPU time | 121.41 seconds |
| Started | Feb 08 05:56:06 PM UTC 25 |
| Finished | Feb 08 05:58:10 PM UTC 25 |
| Peak memory | 231860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515621379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM _TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.3515621379 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_stress_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/103.usbdev_tx_rx_disruption.870671293 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 561266355 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:18:20 PM UTC 25 |
| Finished | Feb 08 06:18:23 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 70671293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.usbdev_tx_rx_disruption.870671293 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/103.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_nak_trans.1988143299 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 222371313 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:04:05 PM UTC 25 |
| Finished | Feb 08 06:04:08 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1988143299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbde v_nak_trans.1988143299 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_pending_in_trans.2430799071 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 222697605 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:04:09 PM UTC 25 |
| Finished | Feb 08 06:04:11 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2430799071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.usbdev_pending_in_trans.2430799071 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/113.usbdev_tx_rx_disruption.510507496 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 571954647 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:18:24 PM UTC 25 |
| Finished | Feb 08 06:18:26 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 10507496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.usbdev_tx_rx_disruption.510507496 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/113.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/118.usbdev_tx_rx_disruption.3736832467 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 623725488 ps |
| CPU time | 1.72 seconds |
| Started | Feb 08 06:18:24 PM UTC 25 |
| Finished | Feb 08 06:18:27 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 736832467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.usbdev_tx_rx_disruption.3736832467 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/118.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_nak_trans.2379499925 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 203700188 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:04:39 PM UTC 25 |
| Finished | Feb 08 06:04:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2379499925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbde v_nak_trans.2379499925 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_nak_trans.3117458108 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 175959900 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:05:13 PM UTC 25 |
| Finished | Feb 08 06:05:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3117458108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbde v_nak_trans.3117458108 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_nak_trans.3225930888 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 215472593 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:07:02 PM UTC 25 |
| Finished | Feb 08 06:07:05 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3225930888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbde v_nak_trans.3225930888 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_nak_trans.3669703657 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 241363243 ps |
| CPU time | 1.9 seconds |
| Started | Feb 08 06:07:28 PM UTC 25 |
| Finished | Feb 08 06:07:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3669703657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbde v_nak_trans.3669703657 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_nak_trans.4289458759 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 190732359 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:07:54 PM UTC 25 |
| Finished | Feb 08 06:07:57 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4289458759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbde v_nak_trans.4289458759 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_nak_trans.104291121 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 207858939 ps |
| CPU time | 1.67 seconds |
| Started | Feb 08 06:09:07 PM UTC 25 |
| Finished | Feb 08 06:09:10 PM UTC 25 |
| Peak memory | 214936 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=104291121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev _nak_trans.104291121 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_nak_trans.369545325 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 207428507 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:14:36 PM UTC 25 |
| Finished | Feb 08 06:14:39 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=369545325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev _nak_trans.369545325 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_nak_trans.327215339 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 170163469 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 06:16:34 PM UTC 25 |
| Finished | Feb 08 06:16:36 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=327215339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev _nak_trans.327215339 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/474.usbdev_tx_rx_disruption.3920673074 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 639726064 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:19 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 920673074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 474.usbdev_tx_rx_disruption.3920673074 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/474.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_aliasing.2056509400 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 219795228 ps |
| CPU time | 1.8 seconds |
| Started | Feb 08 06:20:20 PM UTC 25 |
| Finished | Feb 08 06:20:25 PM UTC 25 |
| Peak memory | 216908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056509400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.usbdev_csr_aliasing.2056509400 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2124771712 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 59869955 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:20:20 PM UTC 25 |
| Finished | Feb 08 06:20:24 PM UTC 25 |
| Peak memory | 227204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124771712 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.2124771712 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_intr_test.3497340366 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 32941587 ps |
| CPU time | 0.62 seconds |
| Started | Feb 08 06:20:20 PM UTC 25 |
| Finished | Feb 08 06:20:23 PM UTC 25 |
| Peak memory | 217164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497340366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.usbdev_intr_test.3497340366 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_partial_access.4042355459 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 164206853 ps |
| CPU time | 2.03 seconds |
| Started | Feb 08 06:20:20 PM UTC 25 |
| Finished | Feb 08 06:20:25 PM UTC 25 |
| Peak memory | 218072 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042355459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.4042355459 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_walk.1131587440 |
| Short name | T3622 |
| Test name | |
| Test status | |
| Simulation time | 719091806 ps |
| CPU time | 4.15 seconds |
| Started | Feb 08 06:20:20 PM UTC 25 |
| Finished | Feb 08 06:20:27 PM UTC 25 |
| Peak memory | 217748 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131587440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.usbdev_mem_walk.1131587440 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1787144167 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 125016690 ps |
| CPU time | 0.93 seconds |
| Started | Feb 08 06:20:20 PM UTC 25 |
| Finished | Feb 08 06:20:24 PM UTC 25 |
| Peak memory | 216900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787144167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_re g_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.1787144167 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_aliasing.3667783884 |
| Short name | T3624 |
| Test name | |
| Test status | |
| Simulation time | 216782435 ps |
| CPU time | 2.07 seconds |
| Started | Feb 08 06:20:25 PM UTC 25 |
| Finished | Feb 08 06:20:29 PM UTC 25 |
| Peak memory | 217940 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667783884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 1.usbdev_csr_aliasing.3667783884 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_bit_bash.788314571 |
| Short name | T3632 |
| Test name | |
| Test status | |
| Simulation time | 1832855126 ps |
| CPU time | 7.99 seconds |
| Started | Feb 08 06:20:25 PM UTC 25 |
| Finished | Feb 08 06:20:35 PM UTC 25 |
| Peak memory | 217888 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788314571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.usbdev_csr_bit_bash.788314571 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1822887638 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 128065689 ps |
| CPU time | 0.94 seconds |
| Started | Feb 08 06:20:25 PM UTC 25 |
| Finished | Feb 08 06:20:28 PM UTC 25 |
| Peak memory | 216872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822887638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1822887638 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1026027944 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 94526002 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 06:20:25 PM UTC 25 |
| Finished | Feb 08 06:20:29 PM UTC 25 |
| Peak memory | 226976 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026027944 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.1026027944 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_rw.2703456733 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 55726801 ps |
| CPU time | 0.82 seconds |
| Started | Feb 08 06:20:25 PM UTC 25 |
| Finished | Feb 08 06:20:28 PM UTC 25 |
| Peak memory | 216956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703456733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2703456733 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_partial_access.2625283659 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 61317404 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 06:20:25 PM UTC 25 |
| Finished | Feb 08 06:20:29 PM UTC 25 |
| Peak memory | 216968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625283659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2625283659 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_walk.1992555542 |
| Short name | T3623 |
| Test name | |
| Test status | |
| Simulation time | 396215876 ps |
| CPU time | 2.42 seconds |
| Started | Feb 08 06:20:23 PM UTC 25 |
| Finished | Feb 08 06:20:27 PM UTC 25 |
| Peak memory | 217800 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992555542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 1.usbdev_mem_walk.1992555542 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4041775834 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 335882849 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:20:25 PM UTC 25 |
| Finished | Feb 08 06:20:29 PM UTC 25 |
| Peak memory | 217016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041775834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_re g_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.4041775834 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_errors.1121628745 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 72046800 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:20:20 PM UTC 25 |
| Finished | Feb 08 06:20:24 PM UTC 25 |
| Peak memory | 216964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121628745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.usbdev_tl_errors.1121628745 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_intg_err.3840308925 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 710047758 ps |
| CPU time | 4.26 seconds |
| Started | Feb 08 06:20:20 PM UTC 25 |
| Finished | Feb 08 06:20:27 PM UTC 25 |
| Peak memory | 218004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840308925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3840308925 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.860360541 |
| Short name | T3665 |
| Test name | |
| Test status | |
| Simulation time | 119993898 ps |
| CPU time | 1.99 seconds |
| Started | Feb 08 06:20:34 PM UTC 25 |
| Finished | Feb 08 06:20:41 PM UTC 25 |
| Peak memory | 227148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860360541 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.860360541 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_rw.751894663 |
| Short name | T3654 |
| Test name | |
| Test status | |
| Simulation time | 40564062 ps |
| CPU time | 0.65 seconds |
| Started | Feb 08 06:20:34 PM UTC 25 |
| Finished | Feb 08 06:20:40 PM UTC 25 |
| Peak memory | 216956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751894663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 10.usbdev_csr_rw.751894663 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3408388194 |
| Short name | T3663 |
| Test name | |
| Test status | |
| Simulation time | 352820963 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:20:34 PM UTC 25 |
| Finished | Feb 08 06:20:41 PM UTC 25 |
| Peak memory | 216972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408388194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_re g_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.3408388194 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_errors.2925025455 |
| Short name | T3661 |
| Test name | |
| Test status | |
| Simulation time | 114688770 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:20:34 PM UTC 25 |
| Finished | Feb 08 06:20:40 PM UTC 25 |
| Peak memory | 216764 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925025455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 10.usbdev_tl_errors.2925025455 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_intg_err.904073344 |
| Short name | T3669 |
| Test name | |
| Test status | |
| Simulation time | 667081008 ps |
| CPU time | 3.73 seconds |
| Started | Feb 08 06:20:34 PM UTC 25 |
| Finished | Feb 08 06:20:43 PM UTC 25 |
| Peak memory | 218040 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904073344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.904073344 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.4020956269 |
| Short name | T3653 |
| Test name | |
| Test status | |
| Simulation time | 102376886 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:20:36 PM UTC 25 |
| Finished | Feb 08 06:20:40 PM UTC 25 |
| Peak memory | 227140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020956269 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.4020956269 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_rw.3620492484 |
| Short name | T3646 |
| Test name | |
| Test status | |
| Simulation time | 51667899 ps |
| CPU time | 0.82 seconds |
| Started | Feb 08 06:20:36 PM UTC 25 |
| Finished | Feb 08 06:20:39 PM UTC 25 |
| Peak memory | 216828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620492484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3620492484 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_intr_test.2464085301 |
| Short name | T3643 |
| Test name | |
| Test status | |
| Simulation time | 41497636 ps |
| CPU time | 0.68 seconds |
| Started | Feb 08 06:20:36 PM UTC 25 |
| Finished | Feb 08 06:20:39 PM UTC 25 |
| Peak memory | 216776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464085301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 11.usbdev_intr_test.2464085301 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3149174973 |
| Short name | T3651 |
| Test name | |
| Test status | |
| Simulation time | 87380668 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:20:36 PM UTC 25 |
| Finished | Feb 08 06:20:39 PM UTC 25 |
| Peak memory | 216904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149174973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_re g_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3149174973 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_intg_err.2018562786 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 477738525 ps |
| CPU time | 3.6 seconds |
| Started | Feb 08 06:20:34 PM UTC 25 |
| Finished | Feb 08 06:20:43 PM UTC 25 |
| Peak memory | 218068 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018562786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.2018562786 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.188686593 |
| Short name | T3659 |
| Test name | |
| Test status | |
| Simulation time | 172067024 ps |
| CPU time | 1.71 seconds |
| Started | Feb 08 06:20:37 PM UTC 25 |
| Finished | Feb 08 06:20:40 PM UTC 25 |
| Peak memory | 227148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188686593 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.188686593 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_rw.3149545353 |
| Short name | T3647 |
| Test name | |
| Test status | |
| Simulation time | 50497356 ps |
| CPU time | 0.77 seconds |
| Started | Feb 08 06:20:37 PM UTC 25 |
| Finished | Feb 08 06:20:39 PM UTC 25 |
| Peak memory | 216960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149545353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3149545353 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_intr_test.1505800200 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 46904466 ps |
| CPU time | 0.68 seconds |
| Started | Feb 08 06:20:36 PM UTC 25 |
| Finished | Feb 08 06:20:39 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505800200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 12.usbdev_intr_test.1505800200 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1010733527 |
| Short name | T3648 |
| Test name | |
| Test status | |
| Simulation time | 68435514 ps |
| CPU time | 0.93 seconds |
| Started | Feb 08 06:20:37 PM UTC 25 |
| Finished | Feb 08 06:20:39 PM UTC 25 |
| Peak memory | 216964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010733527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_re g_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.1010733527 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_errors.695855183 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 73641868 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:20:36 PM UTC 25 |
| Finished | Feb 08 06:20:40 PM UTC 25 |
| Peak memory | 216912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695855183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 12.usbdev_tl_errors.695855183 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_intg_err.1718799479 |
| Short name | T3660 |
| Test name | |
| Test status | |
| Simulation time | 259806446 ps |
| CPU time | 2.05 seconds |
| Started | Feb 08 06:20:36 PM UTC 25 |
| Finished | Feb 08 06:20:40 PM UTC 25 |
| Peak memory | 217824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718799479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1718799479 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2545369570 |
| Short name | T3656 |
| Test name | |
| Test status | |
| Simulation time | 95966339 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 06:20:37 PM UTC 25 |
| Finished | Feb 08 06:20:40 PM UTC 25 |
| Peak memory | 229188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545369570 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.2545369570 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_rw.2566860261 |
| Short name | T3652 |
| Test name | |
| Test status | |
| Simulation time | 154742604 ps |
| CPU time | 0.91 seconds |
| Started | Feb 08 06:20:37 PM UTC 25 |
| Finished | Feb 08 06:20:39 PM UTC 25 |
| Peak memory | 216960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566860261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2566860261 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.4048948182 |
| Short name | T3655 |
| Test name | |
| Test status | |
| Simulation time | 124794767 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 06:20:37 PM UTC 25 |
| Finished | Feb 08 06:20:40 PM UTC 25 |
| Peak memory | 216968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048948182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_re g_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.4048948182 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_errors.3068169381 |
| Short name | T3668 |
| Test name | |
| Test status | |
| Simulation time | 123216705 ps |
| CPU time | 2.91 seconds |
| Started | Feb 08 06:20:37 PM UTC 25 |
| Finished | Feb 08 06:20:41 PM UTC 25 |
| Peak memory | 228256 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068169381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 13.usbdev_tl_errors.3068169381 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_intg_err.1152692224 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 266796916 ps |
| CPU time | 1.95 seconds |
| Started | Feb 08 06:20:37 PM UTC 25 |
| Finished | Feb 08 06:20:40 PM UTC 25 |
| Peak memory | 216964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152692224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1152692224 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3488367244 |
| Short name | T3683 |
| Test name | |
| Test status | |
| Simulation time | 132187855 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:20:41 PM UTC 25 |
| Finished | Feb 08 06:20:44 PM UTC 25 |
| Peak memory | 231236 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488367244 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.3488367244 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_rw.4051279188 |
| Short name | T3674 |
| Test name | |
| Test status | |
| Simulation time | 90040701 ps |
| CPU time | 0.88 seconds |
| Started | Feb 08 06:20:41 PM UTC 25 |
| Finished | Feb 08 06:20:44 PM UTC 25 |
| Peak memory | 216960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051279188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.4051279188 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_intr_test.2166532681 |
| Short name | T3671 |
| Test name | |
| Test status | |
| Simulation time | 43725072 ps |
| CPU time | 0.61 seconds |
| Started | Feb 08 06:20:41 PM UTC 25 |
| Finished | Feb 08 06:20:43 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166532681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 14.usbdev_intr_test.2166532681 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4079848909 |
| Short name | T3675 |
| Test name | |
| Test status | |
| Simulation time | 131035595 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 06:20:41 PM UTC 25 |
| Finished | Feb 08 06:20:44 PM UTC 25 |
| Peak memory | 216984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079848909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_re g_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.4079848909 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_errors.2278609583 |
| Short name | T3666 |
| Test name | |
| Test status | |
| Simulation time | 224827269 ps |
| CPU time | 2.5 seconds |
| Started | Feb 08 06:20:37 PM UTC 25 |
| Finished | Feb 08 06:20:41 PM UTC 25 |
| Peak memory | 235324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278609583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 14.usbdev_tl_errors.2278609583 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_intg_err.3567856603 |
| Short name | T3687 |
| Test name | |
| Test status | |
| Simulation time | 334800016 ps |
| CPU time | 1.97 seconds |
| Started | Feb 08 06:20:41 PM UTC 25 |
| Finished | Feb 08 06:20:45 PM UTC 25 |
| Peak memory | 216964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567856603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3567856603 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.100849588 |
| Short name | T3684 |
| Test name | |
| Test status | |
| Simulation time | 159368871 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:44 PM UTC 25 |
| Peak memory | 227140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100849588 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.100849588 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_rw.2238133419 |
| Short name | T3676 |
| Test name | |
| Test status | |
| Simulation time | 96928706 ps |
| CPU time | 0.91 seconds |
| Started | Feb 08 06:20:41 PM UTC 25 |
| Finished | Feb 08 06:20:44 PM UTC 25 |
| Peak memory | 216960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238133419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2238133419 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_intr_test.489770692 |
| Short name | T3672 |
| Test name | |
| Test status | |
| Simulation time | 43598982 ps |
| CPU time | 0.65 seconds |
| Started | Feb 08 06:20:41 PM UTC 25 |
| Finished | Feb 08 06:20:44 PM UTC 25 |
| Peak memory | 216772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489770692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 15.usbdev_intr_test.489770692 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3253554892 |
| Short name | T3679 |
| Test name | |
| Test status | |
| Simulation time | 129238503 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:44 PM UTC 25 |
| Peak memory | 217028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253554892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_re g_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3253554892 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_errors.2784763915 |
| Short name | T3685 |
| Test name | |
| Test status | |
| Simulation time | 132302590 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:20:41 PM UTC 25 |
| Finished | Feb 08 06:20:44 PM UTC 25 |
| Peak memory | 233644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784763915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 15.usbdev_tl_errors.2784763915 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_intg_err.676851639 |
| Short name | T3695 |
| Test name | |
| Test status | |
| Simulation time | 300257375 ps |
| CPU time | 2.15 seconds |
| Started | Feb 08 06:20:41 PM UTC 25 |
| Finished | Feb 08 06:20:45 PM UTC 25 |
| Peak memory | 217956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676851639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.676851639 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1433347743 |
| Short name | T3694 |
| Test name | |
| Test status | |
| Simulation time | 213726456 ps |
| CPU time | 1.67 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:45 PM UTC 25 |
| Peak memory | 227084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433347743 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.1433347743 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_rw.4019841386 |
| Short name | T3678 |
| Test name | |
| Test status | |
| Simulation time | 67962724 ps |
| CPU time | 0.73 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:44 PM UTC 25 |
| Peak memory | 216952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019841386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.4019841386 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_intr_test.231822984 |
| Short name | T3677 |
| Test name | |
| Test status | |
| Simulation time | 63249084 ps |
| CPU time | 0.68 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:44 PM UTC 25 |
| Peak memory | 216772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231822984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 16.usbdev_intr_test.231822984 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.628037688 |
| Short name | T3688 |
| Test name | |
| Test status | |
| Simulation time | 183749063 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:45 PM UTC 25 |
| Peak memory | 216964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628037688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg _top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.628037688 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_errors.2895177464 |
| Short name | T3692 |
| Test name | |
| Test status | |
| Simulation time | 147389008 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:45 PM UTC 25 |
| Peak memory | 217028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895177464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 16.usbdev_tl_errors.2895177464 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_intg_err.751669490 |
| Short name | T3701 |
| Test name | |
| Test status | |
| Simulation time | 790159827 ps |
| CPU time | 3.58 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:47 PM UTC 25 |
| Peak memory | 218000 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751669490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.751669490 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.33024914 |
| Short name | T3693 |
| Test name | |
| Test status | |
| Simulation time | 159871280 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:45 PM UTC 25 |
| Peak memory | 227132 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33024914 -assert nopostproc +UVM_TESTN AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.33024914 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_rw.2737538608 |
| Short name | T3682 |
| Test name | |
| Test status | |
| Simulation time | 76341370 ps |
| CPU time | 0.9 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:44 PM UTC 25 |
| Peak memory | 216960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737538608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2737538608 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_intr_test.905392133 |
| Short name | T3680 |
| Test name | |
| Test status | |
| Simulation time | 39006209 ps |
| CPU time | 0.64 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:44 PM UTC 25 |
| Peak memory | 216720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905392133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 17.usbdev_intr_test.905392133 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2304372399 |
| Short name | T3690 |
| Test name | |
| Test status | |
| Simulation time | 138875810 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:45 PM UTC 25 |
| Peak memory | 217028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304372399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_re g_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2304372399 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_errors.211923746 |
| Short name | T3700 |
| Test name | |
| Test status | |
| Simulation time | 294885414 ps |
| CPU time | 2.79 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:46 PM UTC 25 |
| Peak memory | 218020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211923746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 17.usbdev_tl_errors.211923746 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_intg_err.3696251375 |
| Short name | T3697 |
| Test name | |
| Test status | |
| Simulation time | 656885654 ps |
| CPU time | 2.42 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:46 PM UTC 25 |
| Peak memory | 217872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696251375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3696251375 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3171954098 |
| Short name | T3696 |
| Test name | |
| Test status | |
| Simulation time | 152295569 ps |
| CPU time | 1.72 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:45 PM UTC 25 |
| Peak memory | 227140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171954098 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.3171954098 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_rw.640007259 |
| Short name | T3686 |
| Test name | |
| Test status | |
| Simulation time | 78987905 ps |
| CPU time | 0.9 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:44 PM UTC 25 |
| Peak memory | 216956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640007259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 18.usbdev_csr_rw.640007259 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_intr_test.2463720682 |
| Short name | T3681 |
| Test name | |
| Test status | |
| Simulation time | 83564009 ps |
| CPU time | 0.68 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:44 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463720682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 18.usbdev_intr_test.2463720682 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.345178609 |
| Short name | T3689 |
| Test name | |
| Test status | |
| Simulation time | 116088441 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:45 PM UTC 25 |
| Peak memory | 216972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345178609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg _top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.345178609 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_errors.1991110521 |
| Short name | T3691 |
| Test name | |
| Test status | |
| Simulation time | 72390786 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:45 PM UTC 25 |
| Peak memory | 217028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991110521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 18.usbdev_tl_errors.1991110521 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_intg_err.1410635424 |
| Short name | T3698 |
| Test name | |
| Test status | |
| Simulation time | 410435264 ps |
| CPU time | 2.31 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:46 PM UTC 25 |
| Peak memory | 217880 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410635424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1410635424 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2741172499 |
| Short name | T3726 |
| Test name | |
| Test status | |
| Simulation time | 133471490 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:21:00 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 227140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741172499 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.2741172499 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_rw.1006219596 |
| Short name | T3709 |
| Test name | |
| Test status | |
| Simulation time | 58053051 ps |
| CPU time | 0.78 seconds |
| Started | Feb 08 06:21:00 PM UTC 25 |
| Finished | Feb 08 06:21:02 PM UTC 25 |
| Peak memory | 216960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006219596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1006219596 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_intr_test.3062702157 |
| Short name | T3702 |
| Test name | |
| Test status | |
| Simulation time | 34374334 ps |
| CPU time | 0.65 seconds |
| Started | Feb 08 06:21:00 PM UTC 25 |
| Finished | Feb 08 06:21:02 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062702157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 19.usbdev_intr_test.3062702157 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3559459149 |
| Short name | T3670 |
| Test name | |
| Test status | |
| Simulation time | 133833319 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 06:21:00 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559459149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_re g_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.3559459149 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_errors.3969680301 |
| Short name | T3699 |
| Test name | |
| Test status | |
| Simulation time | 94338122 ps |
| CPU time | 2.33 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:46 PM UTC 25 |
| Peak memory | 234968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969680301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 19.usbdev_tl_errors.3969680301 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_intg_err.3743693800 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 811803683 ps |
| CPU time | 4.16 seconds |
| Started | Feb 08 06:20:42 PM UTC 25 |
| Finished | Feb 08 06:20:48 PM UTC 25 |
| Peak memory | 217944 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743693800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.3743693800 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_aliasing.2281541931 |
| Short name | T3625 |
| Test name | |
| Test status | |
| Simulation time | 170600652 ps |
| CPU time | 1.91 seconds |
| Started | Feb 08 06:20:25 PM UTC 25 |
| Finished | Feb 08 06:20:30 PM UTC 25 |
| Peak memory | 216888 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281541931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.usbdev_csr_aliasing.2281541931 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2192536528 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 1126897638 ps |
| CPU time | 6.61 seconds |
| Started | Feb 08 06:20:25 PM UTC 25 |
| Finished | Feb 08 06:20:34 PM UTC 25 |
| Peak memory | 217944 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192536528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.usbdev_csr_bit_bash.2192536528 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3706376629 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 52177527 ps |
| CPU time | 0.79 seconds |
| Started | Feb 08 06:20:25 PM UTC 25 |
| Finished | Feb 08 06:20:29 PM UTC 25 |
| Peak memory | 216964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706376629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3706376629 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.994830022 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 164654796 ps |
| CPU time | 1.8 seconds |
| Started | Feb 08 06:20:26 PM UTC 25 |
| Finished | Feb 08 06:20:30 PM UTC 25 |
| Peak memory | 227140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994830022 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.994830022 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_rw.1662065941 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 43684075 ps |
| CPU time | 0.84 seconds |
| Started | Feb 08 06:20:25 PM UTC 25 |
| Finished | Feb 08 06:20:29 PM UTC 25 |
| Peak memory | 216948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662065941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1662065941 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_intr_test.1533349840 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 72771132 ps |
| CPU time | 0.67 seconds |
| Started | Feb 08 06:20:25 PM UTC 25 |
| Finished | Feb 08 06:20:28 PM UTC 25 |
| Peak memory | 216704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533349840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.usbdev_intr_test.1533349840 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_partial_access.2830295904 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 121407585 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:20:25 PM UTC 25 |
| Finished | Feb 08 06:20:29 PM UTC 25 |
| Peak memory | 227204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830295904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2830295904 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_walk.3174369371 |
| Short name | T3626 |
| Test name | |
| Test status | |
| Simulation time | 169197717 ps |
| CPU time | 3.47 seconds |
| Started | Feb 08 06:20:25 PM UTC 25 |
| Finished | Feb 08 06:20:31 PM UTC 25 |
| Peak memory | 217972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174369371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.usbdev_mem_walk.3174369371 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2889127510 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 195857155 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:20:26 PM UTC 25 |
| Finished | Feb 08 06:20:30 PM UTC 25 |
| Peak memory | 216900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889127510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_re g_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2889127510 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_errors.3899724412 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 66986932 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:20:25 PM UTC 25 |
| Finished | Feb 08 06:20:29 PM UTC 25 |
| Peak memory | 233956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899724412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.usbdev_tl_errors.3899724412 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/20.usbdev_intr_test.2040126666 |
| Short name | T3710 |
| Test name | |
| Test status | |
| Simulation time | 102764641 ps |
| CPU time | 0.76 seconds |
| Started | Feb 08 06:21:00 PM UTC 25 |
| Finished | Feb 08 06:21:02 PM UTC 25 |
| Peak memory | 216776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040126666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 20.usbdev_intr_test.2040126666 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/21.usbdev_intr_test.2431941540 |
| Short name | T3703 |
| Test name | |
| Test status | |
| Simulation time | 49003473 ps |
| CPU time | 0.63 seconds |
| Started | Feb 08 06:21:00 PM UTC 25 |
| Finished | Feb 08 06:21:02 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431941540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 21.usbdev_intr_test.2431941540 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/22.usbdev_intr_test.891428682 |
| Short name | T3704 |
| Test name | |
| Test status | |
| Simulation time | 34341732 ps |
| CPU time | 0.63 seconds |
| Started | Feb 08 06:21:00 PM UTC 25 |
| Finished | Feb 08 06:21:02 PM UTC 25 |
| Peak memory | 216712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891428682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 22.usbdev_intr_test.891428682 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/23.usbdev_intr_test.4118729327 |
| Short name | T3711 |
| Test name | |
| Test status | |
| Simulation time | 69222616 ps |
| CPU time | 0.72 seconds |
| Started | Feb 08 06:21:00 PM UTC 25 |
| Finished | Feb 08 06:21:02 PM UTC 25 |
| Peak memory | 216776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118729327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 23.usbdev_intr_test.4118729327 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/24.usbdev_intr_test.1534185154 |
| Short name | T3712 |
| Test name | |
| Test status | |
| Simulation time | 123388025 ps |
| CPU time | 0.71 seconds |
| Started | Feb 08 06:21:00 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534185154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 24.usbdev_intr_test.1534185154 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/25.usbdev_intr_test.1582710835 |
| Short name | T3715 |
| Test name | |
| Test status | |
| Simulation time | 53157694 ps |
| CPU time | 0.71 seconds |
| Started | Feb 08 06:21:00 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582710835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 25.usbdev_intr_test.1582710835 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/26.usbdev_intr_test.2655127681 |
| Short name | T3705 |
| Test name | |
| Test status | |
| Simulation time | 35737846 ps |
| CPU time | 0.65 seconds |
| Started | Feb 08 06:21:00 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655127681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 26.usbdev_intr_test.2655127681 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/27.usbdev_intr_test.541034510 |
| Short name | T3717 |
| Test name | |
| Test status | |
| Simulation time | 112883020 ps |
| CPU time | 0.83 seconds |
| Started | Feb 08 06:21:00 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541034510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 27.usbdev_intr_test.541034510 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/28.usbdev_intr_test.728360555 |
| Short name | T3713 |
| Test name | |
| Test status | |
| Simulation time | 42973699 ps |
| CPU time | 0.66 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728360555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 28.usbdev_intr_test.728360555 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/29.usbdev_intr_test.3953646150 |
| Short name | T3716 |
| Test name | |
| Test status | |
| Simulation time | 36181723 ps |
| CPU time | 0.67 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953646150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 29.usbdev_intr_test.3953646150 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_aliasing.3974496888 |
| Short name | T3630 |
| Test name | |
| Test status | |
| Simulation time | 82514693 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:20:28 PM UTC 25 |
| Finished | Feb 08 06:20:35 PM UTC 25 |
| Peak memory | 216908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974496888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 3.usbdev_csr_aliasing.3974496888 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2134257277 |
| Short name | T3662 |
| Test name | |
| Test status | |
| Simulation time | 728848936 ps |
| CPU time | 7.3 seconds |
| Started | Feb 08 06:20:28 PM UTC 25 |
| Finished | Feb 08 06:20:40 PM UTC 25 |
| Peak memory | 217828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134257277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2134257277 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1540295165 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 123375597 ps |
| CPU time | 0.94 seconds |
| Started | Feb 08 06:20:28 PM UTC 25 |
| Finished | Feb 08 06:20:34 PM UTC 25 |
| Peak memory | 216908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540295165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1540295165 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.141210625 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 100102254 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 06:20:28 PM UTC 25 |
| Finished | Feb 08 06:20:34 PM UTC 25 |
| Peak memory | 227140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141210625 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.141210625 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_rw.1264123399 |
| Short name | T3627 |
| Test name | |
| Test status | |
| Simulation time | 84047586 ps |
| CPU time | 0.81 seconds |
| Started | Feb 08 06:20:28 PM UTC 25 |
| Finished | Feb 08 06:20:34 PM UTC 25 |
| Peak memory | 216956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264123399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1264123399 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_partial_access.363410613 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 211797927 ps |
| CPU time | 2.03 seconds |
| Started | Feb 08 06:20:28 PM UTC 25 |
| Finished | Feb 08 06:20:35 PM UTC 25 |
| Peak memory | 228196 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363410613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.363410613 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_walk.2933015856 |
| Short name | T3634 |
| Test name | |
| Test status | |
| Simulation time | 178360660 ps |
| CPU time | 3.54 seconds |
| Started | Feb 08 06:20:28 PM UTC 25 |
| Finished | Feb 08 06:20:36 PM UTC 25 |
| Peak memory | 217972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933015856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 3.usbdev_mem_walk.2933015856 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3515699547 |
| Short name | T3629 |
| Test name | |
| Test status | |
| Simulation time | 115764421 ps |
| CPU time | 0.99 seconds |
| Started | Feb 08 06:20:28 PM UTC 25 |
| Finished | Feb 08 06:20:34 PM UTC 25 |
| Peak memory | 216960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515699547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_re g_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3515699547 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_errors.2387471836 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 147148623 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:20:26 PM UTC 25 |
| Finished | Feb 08 06:20:30 PM UTC 25 |
| Peak memory | 216964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387471836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.usbdev_tl_errors.2387471836 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/30.usbdev_intr_test.1650896024 |
| Short name | T3714 |
| Test name | |
| Test status | |
| Simulation time | 41592867 ps |
| CPU time | 0.68 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650896024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 30.usbdev_intr_test.1650896024 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/31.usbdev_intr_test.3335466813 |
| Short name | T3707 |
| Test name | |
| Test status | |
| Simulation time | 53101140 ps |
| CPU time | 0.66 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335466813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 31.usbdev_intr_test.3335466813 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/32.usbdev_intr_test.3263147080 |
| Short name | T3706 |
| Test name | |
| Test status | |
| Simulation time | 34475274 ps |
| CPU time | 0.61 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263147080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 32.usbdev_intr_test.3263147080 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/33.usbdev_intr_test.3815433597 |
| Short name | T3673 |
| Test name | |
| Test status | |
| Simulation time | 49750165 ps |
| CPU time | 0.64 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815433597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 33.usbdev_intr_test.3815433597 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/34.usbdev_intr_test.1798625651 |
| Short name | T3718 |
| Test name | |
| Test status | |
| Simulation time | 37497119 ps |
| CPU time | 0.67 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798625651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 34.usbdev_intr_test.1798625651 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/35.usbdev_intr_test.3881425266 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 56352439 ps |
| CPU time | 0.65 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881425266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 35.usbdev_intr_test.3881425266 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/36.usbdev_intr_test.2234178873 |
| Short name | T3719 |
| Test name | |
| Test status | |
| Simulation time | 67010774 ps |
| CPU time | 0.68 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234178873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 36.usbdev_intr_test.2234178873 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/37.usbdev_intr_test.3595291007 |
| Short name | T3708 |
| Test name | |
| Test status | |
| Simulation time | 41907044 ps |
| CPU time | 0.66 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595291007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 37.usbdev_intr_test.3595291007 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/38.usbdev_intr_test.2433650590 |
| Short name | T3722 |
| Test name | |
| Test status | |
| Simulation time | 81903251 ps |
| CPU time | 0.71 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433650590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 38.usbdev_intr_test.2433650590 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/39.usbdev_intr_test.2809335892 |
| Short name | T3723 |
| Test name | |
| Test status | |
| Simulation time | 81990835 ps |
| CPU time | 0.73 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809335892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 39.usbdev_intr_test.2809335892 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_aliasing.573630203 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 129075079 ps |
| CPU time | 2.84 seconds |
| Started | Feb 08 06:20:30 PM UTC 25 |
| Finished | Feb 08 06:20:35 PM UTC 25 |
| Peak memory | 218016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573630203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.usbdev_csr_aliasing.573630203 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2870216142 |
| Short name | T3649 |
| Test name | |
| Test status | |
| Simulation time | 1936038110 ps |
| CPU time | 6.91 seconds |
| Started | Feb 08 06:20:30 PM UTC 25 |
| Finished | Feb 08 06:20:39 PM UTC 25 |
| Peak memory | 218036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870216142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2870216142 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_hw_reset.466316906 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 118162800 ps |
| CPU time | 0.91 seconds |
| Started | Feb 08 06:20:30 PM UTC 25 |
| Finished | Feb 08 06:20:33 PM UTC 25 |
| Peak memory | 216964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466316906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.usbdev_csr_hw_reset.466316906 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2958904973 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 119576527 ps |
| CPU time | 1.23 seconds |
| Started | Feb 08 06:20:30 PM UTC 25 |
| Finished | Feb 08 06:20:34 PM UTC 25 |
| Peak memory | 227188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958904973 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.2958904973 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_rw.1549611599 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 72364447 ps |
| CPU time | 0.72 seconds |
| Started | Feb 08 06:20:30 PM UTC 25 |
| Finished | Feb 08 06:20:33 PM UTC 25 |
| Peak memory | 216956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549611599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1549611599 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_intr_test.1000328304 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 44628666 ps |
| CPU time | 0.66 seconds |
| Started | Feb 08 06:20:28 PM UTC 25 |
| Finished | Feb 08 06:20:34 PM UTC 25 |
| Peak memory | 216708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000328304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.usbdev_intr_test.1000328304 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_partial_access.1162813708 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 59853116 ps |
| CPU time | 1.21 seconds |
| Started | Feb 08 06:20:28 PM UTC 25 |
| Finished | Feb 08 06:20:34 PM UTC 25 |
| Peak memory | 216968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162813708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1162813708 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_walk.2746906006 |
| Short name | T3631 |
| Test name | |
| Test status | |
| Simulation time | 100451581 ps |
| CPU time | 2.08 seconds |
| Started | Feb 08 06:20:28 PM UTC 25 |
| Finished | Feb 08 06:20:35 PM UTC 25 |
| Peak memory | 217972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746906006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.usbdev_mem_walk.2746906006 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.907317246 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 123081152 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 06:20:30 PM UTC 25 |
| Finished | Feb 08 06:20:33 PM UTC 25 |
| Peak memory | 217036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907317246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg _top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.907317246 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_errors.3828265118 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 209495661 ps |
| CPU time | 2.31 seconds |
| Started | Feb 08 06:20:28 PM UTC 25 |
| Finished | Feb 08 06:20:35 PM UTC 25 |
| Peak memory | 218140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828265118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.usbdev_tl_errors.3828265118 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_intg_err.3241549316 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 377324247 ps |
| CPU time | 2.31 seconds |
| Started | Feb 08 06:20:28 PM UTC 25 |
| Finished | Feb 08 06:20:35 PM UTC 25 |
| Peak memory | 218136 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241549316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3241549316 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/40.usbdev_intr_test.3483672659 |
| Short name | T3724 |
| Test name | |
| Test status | |
| Simulation time | 79881549 ps |
| CPU time | 0.72 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483672659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 40.usbdev_intr_test.3483672659 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/41.usbdev_intr_test.2092854682 |
| Short name | T3721 |
| Test name | |
| Test status | |
| Simulation time | 60582205 ps |
| CPU time | 0.7 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092854682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 41.usbdev_intr_test.2092854682 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/42.usbdev_intr_test.2201306867 |
| Short name | T3725 |
| Test name | |
| Test status | |
| Simulation time | 42067464 ps |
| CPU time | 0.63 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201306867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 42.usbdev_intr_test.2201306867 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/43.usbdev_intr_test.2249505342 |
| Short name | T3727 |
| Test name | |
| Test status | |
| Simulation time | 44524458 ps |
| CPU time | 0.67 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249505342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 43.usbdev_intr_test.2249505342 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/44.usbdev_intr_test.779744020 |
| Short name | T3720 |
| Test name | |
| Test status | |
| Simulation time | 33303202 ps |
| CPU time | 0.68 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779744020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 44.usbdev_intr_test.779744020 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/45.usbdev_intr_test.1978038763 |
| Short name | T3728 |
| Test name | |
| Test status | |
| Simulation time | 36606201 ps |
| CPU time | 0.64 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978038763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 45.usbdev_intr_test.1978038763 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/46.usbdev_intr_test.2082211066 |
| Short name | T3730 |
| Test name | |
| Test status | |
| Simulation time | 48409003 ps |
| CPU time | 0.68 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:04 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082211066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 46.usbdev_intr_test.2082211066 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/47.usbdev_intr_test.3211625906 |
| Short name | T3729 |
| Test name | |
| Test status | |
| Simulation time | 66354614 ps |
| CPU time | 0.64 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:03 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211625906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 47.usbdev_intr_test.3211625906 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/48.usbdev_intr_test.2494900276 |
| Short name | T3731 |
| Test name | |
| Test status | |
| Simulation time | 95722946 ps |
| CPU time | 0.73 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:04 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494900276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 48.usbdev_intr_test.2494900276 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/49.usbdev_intr_test.3107083056 |
| Short name | T3732 |
| Test name | |
| Test status | |
| Simulation time | 32829204 ps |
| CPU time | 0.64 seconds |
| Started | Feb 08 06:21:01 PM UTC 25 |
| Finished | Feb 08 06:21:04 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107083056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 49.usbdev_intr_test.3107083056 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1064627940 |
| Short name | T3633 |
| Test name | |
| Test status | |
| Simulation time | 117553649 ps |
| CPU time | 1.74 seconds |
| Started | Feb 08 06:20:32 PM UTC 25 |
| Finished | Feb 08 06:20:36 PM UTC 25 |
| Peak memory | 231236 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064627940 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.1064627940 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_rw.1717802503 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 68332729 ps |
| CPU time | 0.81 seconds |
| Started | Feb 08 06:20:30 PM UTC 25 |
| Finished | Feb 08 06:20:33 PM UTC 25 |
| Peak memory | 216956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717802503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1717802503 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_intr_test.3267916841 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 49293811 ps |
| CPU time | 0.61 seconds |
| Started | Feb 08 06:20:30 PM UTC 25 |
| Finished | Feb 08 06:20:33 PM UTC 25 |
| Peak memory | 216768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267916841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.usbdev_intr_test.3267916841 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1340211673 |
| Short name | T3628 |
| Test name | |
| Test status | |
| Simulation time | 159130177 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:20:30 PM UTC 25 |
| Finished | Feb 08 06:20:34 PM UTC 25 |
| Peak memory | 216900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340211673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_re g_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1340211673 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_errors.2209260754 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 274614861 ps |
| CPU time | 2.63 seconds |
| Started | Feb 08 06:20:30 PM UTC 25 |
| Finished | Feb 08 06:20:35 PM UTC 25 |
| Peak memory | 228244 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209260754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.usbdev_tl_errors.2209260754 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2938941379 |
| Short name | T3638 |
| Test name | |
| Test status | |
| Simulation time | 90896465 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 06:20:32 PM UTC 25 |
| Finished | Feb 08 06:20:38 PM UTC 25 |
| Peak memory | 227140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938941379 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.2938941379 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_csr_rw.1436207576 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 44268566 ps |
| CPU time | 0.68 seconds |
| Started | Feb 08 06:20:32 PM UTC 25 |
| Finished | Feb 08 06:20:38 PM UTC 25 |
| Peak memory | 216816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436207576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1436207576 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_intr_test.3591818359 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 35231327 ps |
| CPU time | 0.62 seconds |
| Started | Feb 08 06:20:32 PM UTC 25 |
| Finished | Feb 08 06:20:37 PM UTC 25 |
| Peak memory | 216708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591818359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.usbdev_intr_test.3591818359 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4072075314 |
| Short name | T3641 |
| Test name | |
| Test status | |
| Simulation time | 183662003 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:20:32 PM UTC 25 |
| Finished | Feb 08 06:20:38 PM UTC 25 |
| Peak memory | 216972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072075314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_re g_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.4072075314 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_tl_errors.1930130661 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 170712233 ps |
| CPU time | 1.71 seconds |
| Started | Feb 08 06:20:32 PM UTC 25 |
| Finished | Feb 08 06:20:36 PM UTC 25 |
| Peak memory | 234164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930130661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.usbdev_tl_errors.1930130661 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_tl_intg_err.1250019445 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1207393644 ps |
| CPU time | 4.89 seconds |
| Started | Feb 08 06:20:32 PM UTC 25 |
| Finished | Feb 08 06:20:39 PM UTC 25 |
| Peak memory | 217940 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250019445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.1250019445 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2292071303 |
| Short name | T3636 |
| Test name | |
| Test status | |
| Simulation time | 52064245 ps |
| CPU time | 1 seconds |
| Started | Feb 08 06:20:32 PM UTC 25 |
| Finished | Feb 08 06:20:38 PM UTC 25 |
| Peak memory | 227140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292071303 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.2292071303 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_csr_rw.2992082320 |
| Short name | T3637 |
| Test name | |
| Test status | |
| Simulation time | 51071657 ps |
| CPU time | 0.7 seconds |
| Started | Feb 08 06:20:32 PM UTC 25 |
| Finished | Feb 08 06:20:38 PM UTC 25 |
| Peak memory | 216956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992082320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2992082320 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_intr_test.871951356 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 43396453 ps |
| CPU time | 0.67 seconds |
| Started | Feb 08 06:20:32 PM UTC 25 |
| Finished | Feb 08 06:20:38 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871951356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 7.usbdev_intr_test.871951356 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1459943152 |
| Short name | T3635 |
| Test name | |
| Test status | |
| Simulation time | 80989423 ps |
| CPU time | 0.99 seconds |
| Started | Feb 08 06:20:32 PM UTC 25 |
| Finished | Feb 08 06:20:38 PM UTC 25 |
| Peak memory | 216916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459943152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_re g_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1459943152 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_tl_errors.3096401556 |
| Short name | T3650 |
| Test name | |
| Test status | |
| Simulation time | 182142315 ps |
| CPU time | 2.22 seconds |
| Started | Feb 08 06:20:32 PM UTC 25 |
| Finished | Feb 08 06:20:39 PM UTC 25 |
| Peak memory | 218080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096401556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.usbdev_tl_errors.3096401556 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_tl_intg_err.2941224298 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1214726333 ps |
| CPU time | 4.16 seconds |
| Started | Feb 08 06:20:32 PM UTC 25 |
| Finished | Feb 08 06:20:41 PM UTC 25 |
| Peak memory | 217732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941224298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.2941224298 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3737960783 |
| Short name | T3642 |
| Test name | |
| Test status | |
| Simulation time | 91967629 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:20:33 PM UTC 25 |
| Finished | Feb 08 06:20:38 PM UTC 25 |
| Peak memory | 227204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737960783 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.3737960783 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_csr_rw.892487208 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 58149107 ps |
| CPU time | 0.75 seconds |
| Started | Feb 08 06:20:32 PM UTC 25 |
| Finished | Feb 08 06:20:38 PM UTC 25 |
| Peak memory | 216956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892487208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.usbdev_csr_rw.892487208 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_intr_test.1518704056 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 51950592 ps |
| CPU time | 0.69 seconds |
| Started | Feb 08 06:20:32 PM UTC 25 |
| Finished | Feb 08 06:20:38 PM UTC 25 |
| Peak memory | 216708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518704056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.usbdev_intr_test.1518704056 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3399360225 |
| Short name | T3640 |
| Test name | |
| Test status | |
| Simulation time | 103692119 ps |
| CPU time | 1.02 seconds |
| Started | Feb 08 06:20:33 PM UTC 25 |
| Finished | Feb 08 06:20:38 PM UTC 25 |
| Peak memory | 216960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399360225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SE Q=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_re g_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3399360225 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_tl_errors.937976960 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 157364607 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:20:32 PM UTC 25 |
| Finished | Feb 08 06:20:39 PM UTC 25 |
| Peak memory | 216972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937976960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 8.usbdev_tl_errors.937976960 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_tl_intg_err.2930343046 |
| Short name | T3658 |
| Test name | |
| Test status | |
| Simulation time | 382347287 ps |
| CPU time | 2.36 seconds |
| Started | Feb 08 06:20:32 PM UTC 25 |
| Finished | Feb 08 06:20:40 PM UTC 25 |
| Peak memory | 218096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930343046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.2930343046 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.251430545 |
| Short name | T3645 |
| Test name | |
| Test status | |
| Simulation time | 126528800 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 06:20:33 PM UTC 25 |
| Finished | Feb 08 06:20:39 PM UTC 25 |
| Peak memory | 235080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251430545 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.251430545 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_csr_rw.2999342749 |
| Short name | T3639 |
| Test name | |
| Test status | |
| Simulation time | 61980062 ps |
| CPU time | 0.76 seconds |
| Started | Feb 08 06:20:33 PM UTC 25 |
| Finished | Feb 08 06:20:38 PM UTC 25 |
| Peak memory | 216956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999342749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2999342749 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_intr_test.920284174 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 55667120 ps |
| CPU time | 0.64 seconds |
| Started | Feb 08 06:20:33 PM UTC 25 |
| Finished | Feb 08 06:20:38 PM UTC 25 |
| Peak memory | 216716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920284174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 9.usbdev_intr_test.920284174 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.98416965 |
| Short name | T3644 |
| Test name | |
| Test status | |
| Simulation time | 137583639 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 06:20:33 PM UTC 25 |
| Finished | Feb 08 06:20:39 PM UTC 25 |
| Peak memory | 216976 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98416965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.98416965 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_tl_errors.1394494681 |
| Short name | T3664 |
| Test name | |
| Test status | |
| Simulation time | 305145915 ps |
| CPU time | 3.33 seconds |
| Started | Feb 08 06:20:33 PM UTC 25 |
| Finished | Feb 08 06:20:41 PM UTC 25 |
| Peak memory | 228316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394494681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.usbdev_tl_errors.1394494681 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_tl_intg_err.2590914938 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 366430411 ps |
| CPU time | 2.25 seconds |
| Started | Feb 08 06:20:33 PM UTC 25 |
| Finished | Feb 08 06:20:40 PM UTC 25 |
| Peak memory | 218012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590914938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2590914938 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_disconnect.3515888105 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 6165788413 ps |
| CPU time | 18.71 seconds |
| Started | Feb 08 05:51:34 PM UTC 25 |
| Finished | Feb 08 05:51:54 PM UTC 25 |
| Peak memory | 227776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515888105 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.3515888105 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_av_buffer.4067640243 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 152494249 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 05:51:36 PM UTC 25 |
| Finished | Feb 08 05:51:38 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4067640243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev _av_buffer.4067640243 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_clear.3557771990 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 277449255 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 05:51:39 PM UTC 25 |
| Finished | Feb 08 05:51:42 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3557771990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.3557771990 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_disable_endpoint.1179161427 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 714557254 ps |
| CPU time | 3.47 seconds |
| Started | Feb 08 05:51:45 PM UTC 25 |
| Finished | Feb 08 05:51:50 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1179161427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0 .usbdev_disable_endpoint.1179161427 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_disconnected.1792538558 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 182554296 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 05:51:47 PM UTC 25 |
| Finished | Feb 08 05:51:50 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1792538558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usb dev_disconnected.1792538558 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_enable.2015895142 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 44065157 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 05:51:51 PM UTC 25 |
| Finished | Feb 08 05:51:53 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2015895142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_en able.2015895142 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_access.546927163 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 841157579 ps |
| CPU time | 4.28 seconds |
| Started | Feb 08 05:51:51 PM UTC 25 |
| Finished | Feb 08 05:51:56 PM UTC 25 |
| Peak memory | 217320 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=546927163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.u sbdev_endpoint_access.546927163 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_freq_hiclk_max.1898169471 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 115206148126 ps |
| CPU time | 254.11 seconds |
| Started | Feb 08 05:51:57 PM UTC 25 |
| Finished | Feb 08 05:56:15 PM UTC 25 |
| Peak memory | 217468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_track ing=1 +reset_recovery=1 +usb_freq_delta=+120000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1898169471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hi clk_max.1898169471 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_freq_hiclk_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_freq_loclk.3693462455 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 99116697239 ps |
| CPU time | 274.75 seconds |
| Started | Feb 08 05:51:58 PM UTC 25 |
| Finished | Feb 08 05:56:37 PM UTC 25 |
| Peak memory | 217424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693462455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phas e_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 0.usbdev_freq_loclk.3693462455 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_freq_loclk/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_freq_loclk_max.3519258581 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 99171377616 ps |
| CPU time | 231.08 seconds |
| Started | Feb 08 05:52:00 PM UTC 25 |
| Finished | Feb 08 05:55:55 PM UTC 25 |
| Peak memory | 217616 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+1 20000 +reset_recovery=1 +usb_freq_delta=-120000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3519258581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_lo clk_max.3519258581 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_freq_loclk_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_freq_phase.1857719907 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 112152490092 ps |
| CPU time | 297.51 seconds |
| Started | Feb 08 05:52:03 PM UTC 25 |
| Finished | Feb 08 05:57:05 PM UTC 25 |
| Peak memory | 217544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1857719907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0 .usbdev_freq_phase.1857719907 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_freq_phase/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_in_iso.2168246772 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 235864726 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 05:52:09 PM UTC 25 |
| Finished | Feb 08 05:52:12 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168246772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 0.usbdev_in_iso.2168246772 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_in_stall.1162325195 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 134887142 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 05:52:10 PM UTC 25 |
| Finished | Feb 08 05:52:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1162325195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ in_stall.1162325195 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_in_trans.783393976 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 224972221 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 05:52:13 PM UTC 25 |
| Finished | Feb 08 05:52:16 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=783393976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_i n_trans.783393976 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_sync.2551039935 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 4961787999 ps |
| CPU time | 143.93 seconds |
| Started | Feb 08 05:52:08 PM UTC 25 |
| Finished | Feb 08 05:54:34 PM UTC 25 |
| Peak memory | 227720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551039935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.2551039935 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_link_in_err.3145137132 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 249825435 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 05:52:14 PM UTC 25 |
| Finished | Feb 08 05:52:17 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3145137132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbd ev_link_in_err.3145137132 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_link_out_err.2782209781 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 537374664 ps |
| CPU time | 2.38 seconds |
| Started | Feb 08 05:52:16 PM UTC 25 |
| Finished | Feb 08 05:52:20 PM UTC 25 |
| Peak memory | 217116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2782209781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usb dev_link_out_err.2782209781 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_link_out_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_link_resume.150049393 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 24939934482 ps |
| CPU time | 65.35 seconds |
| Started | Feb 08 05:52:20 PM UTC 25 |
| Finished | Feb 08 05:53:27 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=150049393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbde v_link_resume.150049393 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_link_suspend.2357751056 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 8431375223 ps |
| CPU time | 17.57 seconds |
| Started | Feb 08 05:52:21 PM UTC 25 |
| Finished | Feb 08 05:52:40 PM UTC 25 |
| Peak memory | 217452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2357751056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usb dev_link_suspend.2357751056 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_low_speed_traffic.1970259934 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 2216269618 ps |
| CPU time | 21.84 seconds |
| Started | Feb 08 05:52:21 PM UTC 25 |
| Finished | Feb 08 05:52:44 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970259934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.usbdev_low_speed_traffic.1970259934 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_max_inter_pkt_delay.871008777 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 2212620821 ps |
| CPU time | 77.03 seconds |
| Started | Feb 08 05:52:22 PM UTC 25 |
| Finished | Feb 08 05:53:41 PM UTC 25 |
| Peak memory | 227892 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871008777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.871008777 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_max_length_in_transaction.3751833417 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 244081824 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 05:52:22 PM UTC 25 |
| Finished | Feb 08 05:52:25 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751833417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.usbdev_max_length_in_transaction.3751833417 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_max_length_out_transaction.4177159403 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 195597302 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 05:52:26 PM UTC 25 |
| Finished | Feb 08 05:52:29 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4177159403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.4177159403 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_max_non_iso_usb_traffic.2940746596 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 2001145425 ps |
| CPU time | 28.58 seconds |
| Started | Feb 08 05:52:29 PM UTC 25 |
| Finished | Feb 08 05:52:59 PM UTC 25 |
| Peak memory | 229888 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2940746596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.usbdev_max_non_iso_usb_traffic.2940746596 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_min_inter_pkt_delay.1730168360 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 3795952463 ps |
| CPU time | 149.63 seconds |
| Started | Feb 08 05:52:42 PM UTC 25 |
| Finished | Feb 08 05:55:15 PM UTC 25 |
| Peak memory | 229644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730168360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.1730168360 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_min_length_in_transaction.2862617799 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 236812609 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 05:52:45 PM UTC 25 |
| Finished | Feb 08 05:52:47 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862617799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.usbdev_min_length_in_transaction.2862617799 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_min_length_out_transaction.896589692 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 145885223 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 05:52:48 PM UTC 25 |
| Finished | Feb 08 05:52:50 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=896589692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 0.usbdev_min_length_out_transaction.896589692 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2127657786 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 503662302 ps |
| CPU time | 2.15 seconds |
| Started | Feb 08 05:52:51 PM UTC 25 |
| Finished | Feb 08 05:52:54 PM UTC 25 |
| Peak memory | 217112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2127657786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usb dev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2127657786 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_out_iso.3437933996 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 184207924 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 05:52:58 PM UTC 25 |
| Finished | Feb 08 05:53:00 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3437933996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_o ut_iso.3437933996 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_out_stall.4206423946 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 199636800 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 05:53:00 PM UTC 25 |
| Finished | Feb 08 05:53:03 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4206423946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev _out_stall.4206423946 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_out_trans_nak.1496977591 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 150764662 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 05:53:01 PM UTC 25 |
| Finished | Feb 08 05:53:04 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1496977591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.us bdev_out_trans_nak.1496977591 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_pending_in_trans.1399323827 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 160291379 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 05:53:01 PM UTC 25 |
| Finished | Feb 08 05:53:04 PM UTC 25 |
| Peak memory | 215088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1399323827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0 .usbdev_pending_in_trans.1399323827 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2762168836 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 217138472 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 05:53:03 PM UTC 25 |
| Finished | Feb 08 05:53:06 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2762168836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handlin g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.2762168836 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_phy_config_eop_single_bit_handling/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_pinflip.2226818826 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 291196669 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 05:53:05 PM UTC 25 |
| Finished | Feb 08 05:53:08 PM UTC 25 |
| Peak memory | 215076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226818826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.usbdev_phy_config_pinflip.2226818826 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_rand_bus_type.1786937245 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 205397518 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 05:53:05 PM UTC 25 |
| Finished | Feb 08 05:53:08 PM UTC 25 |
| Peak memory | 215092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1786937245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.usbdev_phy_config_rand_bus_type.1786937245 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_phy_config_rand_bus_type/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_rx_dp_dn.3515108387 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 237397323 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 05:53:08 PM UTC 25 |
| Finished | Feb 08 05:53:10 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515108387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.usbdev_phy_config_rx_dp_dn.3515108387 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_phy_config_rx_dp_dn/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_phy_pins_sense.210652851 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 39014757 ps |
| CPU time | 1.05 seconds |
| Started | Feb 08 05:53:11 PM UTC 25 |
| Finished | Feb 08 05:53:14 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=210652851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.us bdev_phy_pins_sense.210652851 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_sent.36926015 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 237460248 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 05:53:13 PM UTC 25 |
| Finished | Feb 08 05:53:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=36926015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pk t_sent.36926015 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_resets.1939982358 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 7580582812 ps |
| CPU time | 197.05 seconds |
| Started | Feb 08 05:53:18 PM UTC 25 |
| Finished | Feb 08 05:56:38 PM UTC 25 |
| Peak memory | 229776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939982358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.usbdev_rand_bus_resets.1939982358 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_rand_bus_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_rand_suspends.4083423932 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 7416605473 ps |
| CPU time | 111.98 seconds |
| Started | Feb 08 05:53:19 PM UTC 25 |
| Finished | Feb 08 05:55:13 PM UTC 25 |
| Peak memory | 227856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083423932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_ TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.4083423932 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_rand_suspends/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_random_length_in_transaction.331857581 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 194082182 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 05:53:15 PM UTC 25 |
| Finished | Feb 08 05:53:18 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=331857581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usb dev_random_length_in_transaction.331857581 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_random_length_out_transaction.845633136 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 173935131 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 05:53:16 PM UTC 25 |
| Finished | Feb 08 05:53:18 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=845633136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.usbdev_random_length_out_transaction.845633136 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_rx_full.2355392614 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 351505853 ps |
| CPU time | 1.89 seconds |
| Started | Feb 08 05:53:45 PM UTC 25 |
| Finished | Feb 08 05:53:48 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2355392614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_r x_full.2355392614 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority_over_stall_response.2726560370 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 321928988 ps |
| CPU time | 1.99 seconds |
| Started | Feb 08 05:53:53 PM UTC 25 |
| Finished | Feb 08 05:53:56 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2726560370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_respons e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.usbdev_setup_priority_over_stall_response.2726560370 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_setup_priority_over_stall_response/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_setup_stage.550247134 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 149292404 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 05:53:54 PM UTC 25 |
| Finished | Feb 08 05:53:56 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=550247134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbde v_setup_stage.550247134 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_setup_trans_ignored.801724924 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 172337164 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 05:53:57 PM UTC 25 |
| Finished | Feb 08 05:53:59 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=801724924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.801724924 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_smoke.419593955 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 266238569 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 05:53:57 PM UTC 25 |
| Finished | Feb 08 05:54:00 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=419593955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smok e.419593955 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_spurious_pids_ignored.1117395836 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 3098010320 ps |
| CPU time | 22.45 seconds |
| Started | Feb 08 05:53:57 PM UTC 25 |
| Finished | Feb 08 05:54:21 PM UTC 25 |
| Peak memory | 234300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117395836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 0.usbdev_spurious_pids_ignored.1117395836 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_stall_priority_over_nak.564226457 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 165544663 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 05:54:01 PM UTC 25 |
| Finished | Feb 08 05:54:03 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=564226457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 0.usbdev_stall_priority_over_nak.564226457 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_stall_trans.660899876 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 207596779 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 05:54:01 PM UTC 25 |
| Finished | Feb 08 05:54:04 PM UTC 25 |
| Peak memory | 215064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=660899876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbde v_stall_trans.660899876 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_stream_len_max.3362724133 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 980263373 ps |
| CPU time | 4.25 seconds |
| Started | Feb 08 05:54:01 PM UTC 25 |
| Finished | Feb 08 05:54:06 PM UTC 25 |
| Peak memory | 217328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3362724133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.u sbdev_stream_len_max.3362724133 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_streaming_out.1555843061 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 3588536179 ps |
| CPU time | 42.3 seconds |
| Started | Feb 08 05:54:01 PM UTC 25 |
| Finished | Feb 08 05:54:45 PM UTC 25 |
| Peak memory | 227728 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1555843061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev _streaming_out.1555843061 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_timeout_missing_host_handshake.3247550875 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 141591561 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 05:51:42 PM UTC 25 |
| Finished | Feb 08 05:51:45 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247550875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_host_handshake.3247550875 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/0.usbdev_tx_rx_disruption.3724437841 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 568419036 ps |
| CPU time | 3.03 seconds |
| Started | Feb 08 05:54:04 PM UTC 25 |
| Finished | Feb 08 05:54:08 PM UTC 25 |
| Peak memory | 217180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 724437841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_tx_rx_disruption.3724437841 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/0.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_alert_test.175842026 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 40763905 ps |
| CPU time | 0.93 seconds |
| Started | Feb 08 05:56:10 PM UTC 25 |
| Finished | Feb 08 05:56:12 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175842026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 1.usbdev_alert_test.175842026 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_disconnect.2779186426 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4850280764 ps |
| CPU time | 16.11 seconds |
| Started | Feb 08 05:54:09 PM UTC 25 |
| Finished | Feb 08 05:54:27 PM UTC 25 |
| Peak memory | 227596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779186426 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.2779186426 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_reset.3053429191 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 20365001940 ps |
| CPU time | 32.05 seconds |
| Started | Feb 08 05:54:10 PM UTC 25 |
| Finished | Feb 08 05:54:44 PM UTC 25 |
| Peak memory | 217384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053429191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.3053429191 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_resume.1067118286 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 30722815571 ps |
| CPU time | 63.87 seconds |
| Started | Feb 08 05:54:11 PM UTC 25 |
| Finished | Feb 08 05:55:17 PM UTC 25 |
| Peak memory | 217376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067118286 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.1067118286 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_av_buffer.4013263825 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 166945846 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 05:54:16 PM UTC 25 |
| Finished | Feb 08 05:54:19 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4013263825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev _av_buffer.4013263825 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_av_empty.4162493219 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 170733530 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 05:54:19 PM UTC 25 |
| Finished | Feb 08 05:54:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4162493219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ av_empty.4162493219 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_av_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_av_overflow.975873373 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 192823142 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 05:54:20 PM UTC 25 |
| Finished | Feb 08 05:54:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=975873373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbde v_av_overflow.975873373 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_av_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_bitstuff_err.2044311366 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 145488617 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 05:54:22 PM UTC 25 |
| Finished | Feb 08 05:54:25 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2044311366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usb dev_bitstuff_err.2044311366 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_data_toggle_clear.3195664445 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 241186700 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 05:54:22 PM UTC 25 |
| Finished | Feb 08 05:54:25 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3195664445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.3195664445 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_data_toggle_restore.2131118520 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 759724449 ps |
| CPU time | 3.77 seconds |
| Started | Feb 08 05:54:23 PM UTC 25 |
| Finished | Feb 08 05:54:28 PM UTC 25 |
| Peak memory | 217628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131118520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.2131118520 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_device_timeout.1446195274 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 1125258765 ps |
| CPU time | 35.56 seconds |
| Started | Feb 08 05:54:26 PM UTC 25 |
| Finished | Feb 08 05:55:03 PM UTC 25 |
| Peak memory | 217328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446195274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.1446195274 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_disable_endpoint.3182963467 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 640421733 ps |
| CPU time | 3.15 seconds |
| Started | Feb 08 05:54:28 PM UTC 25 |
| Finished | Feb 08 05:54:32 PM UTC 25 |
| Peak memory | 217088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3182963467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 .usbdev_disable_endpoint.3182963467 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_disconnected.2458765736 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 141625797 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 05:54:29 PM UTC 25 |
| Finished | Feb 08 05:54:31 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2458765736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usb dev_disconnected.2458765736 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_enable.4151062235 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 47925515 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 05:54:32 PM UTC 25 |
| Finished | Feb 08 05:54:34 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4151062235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_en able.4151062235 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_endpoint_access.680864159 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1073683993 ps |
| CPU time | 4.81 seconds |
| Started | Feb 08 05:54:32 PM UTC 25 |
| Finished | Feb 08 05:54:38 PM UTC 25 |
| Peak memory | 217376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=680864159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.u sbdev_endpoint_access.680864159 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_fifo_rst.2067424792 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 198115183 ps |
| CPU time | 3.81 seconds |
| Started | Feb 08 05:54:36 PM UTC 25 |
| Finished | Feb 08 05:54:41 PM UTC 25 |
| Peak memory | 217480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2067424792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ fifo_rst.2067424792 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_freq_hiclk.4068223738 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 99209057382 ps |
| CPU time | 197.94 seconds |
| Started | Feb 08 05:54:36 PM UTC 25 |
| Finished | Feb 08 05:57:57 PM UTC 25 |
| Peak memory | 217468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068223738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phas e_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 1.usbdev_freq_hiclk.4068223738 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_freq_hiclk/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_freq_hiclk_max.4063358718 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 89260812195 ps |
| CPU time | 249.12 seconds |
| Started | Feb 08 05:54:37 PM UTC 25 |
| Finished | Feb 08 05:58:50 PM UTC 25 |
| Peak memory | 217472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_track ing=1 +reset_recovery=1 +usb_freq_delta=+120000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=4063358718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hi clk_max.4063358718 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_freq_hiclk_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_freq_loclk.1089524817 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 110099931696 ps |
| CPU time | 285.02 seconds |
| Started | Feb 08 05:54:39 PM UTC 25 |
| Finished | Feb 08 05:59:28 PM UTC 25 |
| Peak memory | 217480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089524817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phas e_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 1.usbdev_freq_loclk.1089524817 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_freq_loclk/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_freq_loclk_max.2277984903 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 114209722648 ps |
| CPU time | 220.2 seconds |
| Started | Feb 08 05:54:42 PM UTC 25 |
| Finished | Feb 08 05:58:25 PM UTC 25 |
| Peak memory | 217552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+1 20000 +reset_recovery=1 +usb_freq_delta=-120000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2277984903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_lo clk_max.2277984903 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_freq_loclk_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_freq_phase.564063745 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 96168748616 ps |
| CPU time | 217.38 seconds |
| Started | Feb 08 05:54:43 PM UTC 25 |
| Finished | Feb 08 05:58:24 PM UTC 25 |
| Peak memory | 217356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=564063745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1. usbdev_freq_phase.564063745 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_freq_phase/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_in_iso.269111963 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 162907960 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 05:54:46 PM UTC 25 |
| Finished | Feb 08 05:54:49 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269111963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.usbdev_in_iso.269111963 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_in_stall.3815642244 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 148430418 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 05:54:48 PM UTC 25 |
| Finished | Feb 08 05:54:51 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3815642244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ in_stall.3815642244 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_in_trans.1878321726 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 219025262 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 05:54:49 PM UTC 25 |
| Finished | Feb 08 05:54:52 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1878321726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ in_trans.1878321726 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_iso_retraction.2805030219 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 13259348693 ps |
| CPU time | 113.65 seconds |
| Started | Feb 08 05:54:51 PM UTC 25 |
| Finished | Feb 08 05:56:47 PM UTC 25 |
| Peak memory | 217608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805030219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 1.usbdev_iso_retraction.2805030219 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_link_in_err.4189258213 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 216760444 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 05:54:53 PM UTC 25 |
| Finished | Feb 08 05:54:55 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4189258213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbd ev_link_in_err.4189258213 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_link_suspend.448780656 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 9777317175 ps |
| CPU time | 26.64 seconds |
| Started | Feb 08 05:54:57 PM UTC 25 |
| Finished | Feb 08 05:55:25 PM UTC 25 |
| Peak memory | 217580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=448780656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbd ev_link_suspend.448780656 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_low_speed_traffic.1268474412 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 5692327112 ps |
| CPU time | 65.19 seconds |
| Started | Feb 08 05:55:03 PM UTC 25 |
| Finished | Feb 08 05:56:10 PM UTC 25 |
| Peak memory | 229760 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268474412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.usbdev_low_speed_traffic.1268474412 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_max_inter_pkt_delay.3310052249 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 2531049864 ps |
| CPU time | 27.77 seconds |
| Started | Feb 08 05:55:14 PM UTC 25 |
| Finished | Feb 08 05:55:43 PM UTC 25 |
| Peak memory | 227776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310052249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.3310052249 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_max_length_in_transaction.519598863 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 252995704 ps |
| CPU time | 1.76 seconds |
| Started | Feb 08 05:55:16 PM UTC 25 |
| Finished | Feb 08 05:55:19 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519598863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.usbdev_max_length_in_transaction.519598863 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_max_length_out_transaction.3921006528 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 243007313 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 05:55:17 PM UTC 25 |
| Finished | Feb 08 05:55:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3921006528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.3921006528 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_max_non_iso_usb_traffic.1304260178 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 4280285531 ps |
| CPU time | 43.86 seconds |
| Started | Feb 08 05:55:21 PM UTC 25 |
| Finished | Feb 08 05:56:06 PM UTC 25 |
| Peak memory | 227660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1304260178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.usbdev_max_non_iso_usb_traffic.1304260178 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_max_usb_traffic.3429815762 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 3353724459 ps |
| CPU time | 42.45 seconds |
| Started | Feb 08 05:55:21 PM UTC 25 |
| Finished | Feb 08 05:56:05 PM UTC 25 |
| Peak memory | 229780 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429815762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_ traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 1.usbdev_max_usb_traffic.3429815762 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_min_inter_pkt_delay.3451467727 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 2334536008 ps |
| CPU time | 26.14 seconds |
| Started | Feb 08 05:55:26 PM UTC 25 |
| Finished | Feb 08 05:55:53 PM UTC 25 |
| Peak memory | 227624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451467727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.3451467727 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_min_length_in_transaction.3262831090 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 172005373 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 05:55:27 PM UTC 25 |
| Finished | Feb 08 05:55:30 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262831090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.usbdev_min_length_in_transaction.3262831090 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_min_length_out_transaction.3432312171 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 156809438 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 05:55:30 PM UTC 25 |
| Finished | Feb 08 05:55:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3432312171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.3432312171 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_out_iso.4248306842 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 196243083 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 05:55:34 PM UTC 25 |
| Finished | Feb 08 05:55:36 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4248306842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_o ut_iso.4248306842 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_out_stall.283100471 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 158635685 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 05:55:34 PM UTC 25 |
| Finished | Feb 08 05:55:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=283100471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ out_stall.283100471 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_out_trans_nak.1326974051 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 178729973 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 05:55:36 PM UTC 25 |
| Finished | Feb 08 05:55:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1326974051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.us bdev_out_trans_nak.1326974051 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_pending_in_trans.3966930982 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 153561968 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 05:55:36 PM UTC 25 |
| Finished | Feb 08 05:55:39 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3966930982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 .usbdev_pending_in_trans.3966930982 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_pinflip.1688958147 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 260427148 ps |
| CPU time | 1.76 seconds |
| Started | Feb 08 05:55:37 PM UTC 25 |
| Finished | Feb 08 05:55:40 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688958147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.usbdev_phy_config_pinflip.1688958147 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_rand_bus_type.894186899 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 253876288 ps |
| CPU time | 1.81 seconds |
| Started | Feb 08 05:55:37 PM UTC 25 |
| Finished | Feb 08 05:55:40 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=894186899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.usbdev_phy_config_rand_bus_type.894186899 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_phy_config_rand_bus_type/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_usb_ref_disable.4189306791 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 145907901 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 05:55:39 PM UTC 25 |
| Finished | Feb 08 05:55:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4189306791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.4189306791 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_buffer.691637941 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 11060499429 ps |
| CPU time | 38.34 seconds |
| Started | Feb 08 05:55:40 PM UTC 25 |
| Finished | Feb 08 05:56:20 PM UTC 25 |
| Peak memory | 227864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=691637941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev _pkt_buffer.691637941 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_received.2311073575 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 171384509 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 05:55:42 PM UTC 25 |
| Finished | Feb 08 05:55:44 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2311073575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usb dev_pkt_received.2311073575 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_sent.810754296 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 212101549 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 05:55:43 PM UTC 25 |
| Finished | Feb 08 05:55:46 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=810754296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_p kt_sent.810754296 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_rand_bus_disconnects.865369763 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 13329140661 ps |
| CPU time | 83.56 seconds |
| Started | Feb 08 05:55:44 PM UTC 25 |
| Finished | Feb 08 05:57:10 PM UTC 25 |
| Peak memory | 229768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865369763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.865369763 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_rand_bus_disconnects/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_rand_bus_resets.2974750128 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 5323611196 ps |
| CPU time | 24.04 seconds |
| Started | Feb 08 05:55:45 PM UTC 25 |
| Finished | Feb 08 05:56:11 PM UTC 25 |
| Peak memory | 227736 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974750128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.usbdev_rand_bus_resets.2974750128 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_rand_bus_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_rand_suspends.1424779478 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 10803928550 ps |
| CPU time | 92.92 seconds |
| Started | Feb 08 05:55:46 PM UTC 25 |
| Finished | Feb 08 05:57:21 PM UTC 25 |
| Peak memory | 227856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424779478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_ TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.1424779478 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_rand_suspends/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_random_length_in_transaction.4165775198 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 165815716 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 05:55:43 PM UTC 25 |
| Finished | Feb 08 05:55:45 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4165775198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.us bdev_random_length_in_transaction.4165775198 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_random_length_out_transaction.2021048008 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 217349690 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 05:55:43 PM UTC 25 |
| Finished | Feb 08 05:55:46 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2021048008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.usbdev_random_length_out_transaction.2021048008 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_resume_link_active.3328748335 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 20176953694 ps |
| CPU time | 38.12 seconds |
| Started | Feb 08 05:55:46 PM UTC 25 |
| Finished | Feb 08 05:56:26 PM UTC 25 |
| Peak memory | 217212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3328748335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_resume_link_active.3328748335 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_resume_link_active/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_rx_crc_err.656624707 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 184673620 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 05:55:47 PM UTC 25 |
| Finished | Feb 08 05:55:49 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=656624707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev _rx_crc_err.656624707 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_rx_pid_err.2296063071 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 220884132 ps |
| CPU time | 1.79 seconds |
| Started | Feb 08 05:55:54 PM UTC 25 |
| Finished | Feb 08 05:55:57 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2296063071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbde v_rx_pid_err.2296063071 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_rx_pid_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_sec_cm.1739075876 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 686291281 ps |
| CPU time | 1.99 seconds |
| Started | Feb 08 05:56:08 PM UTC 25 |
| Finished | Feb 08 05:56:11 PM UTC 25 |
| Peak memory | 249516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739075876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 1.usbdev_sec_cm.1739075876 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_setup_priority.3014505314 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 388406981 ps |
| CPU time | 2.31 seconds |
| Started | Feb 08 05:55:54 PM UTC 25 |
| Finished | Feb 08 05:55:57 PM UTC 25 |
| Peak memory | 217116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3014505314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.u sbdev_setup_priority.3014505314 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_setup_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_setup_priority_over_stall_response.3110789719 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 328250505 ps |
| CPU time | 2.13 seconds |
| Started | Feb 08 05:55:56 PM UTC 25 |
| Finished | Feb 08 05:56:00 PM UTC 25 |
| Peak memory | 217180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3110789719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_respons e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 1.usbdev_setup_priority_over_stall_response.3110789719 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_setup_priority_over_stall_response/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_setup_stage.3120116476 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 184596556 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 05:55:58 PM UTC 25 |
| Finished | Feb 08 05:56:00 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3120116476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbd ev_setup_stage.3120116476 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_setup_trans_ignored.2624698222 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 153327699 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 05:55:59 PM UTC 25 |
| Finished | Feb 08 05:56:01 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2624698222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.usbdev_setup_trans_ignored.2624698222 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_smoke.1562778810 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 232671446 ps |
| CPU time | 1.78 seconds |
| Started | Feb 08 05:56:01 PM UTC 25 |
| Finished | Feb 08 05:56:04 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1562778810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smo ke.1562778810 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_spurious_pids_ignored.153739989 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 2859480304 ps |
| CPU time | 120.33 seconds |
| Started | Feb 08 05:56:01 PM UTC 25 |
| Finished | Feb 08 05:58:04 PM UTC 25 |
| Peak memory | 229772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153739989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.usbdev_spurious_pids_ignored.153739989 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_stall_priority_over_nak.234420323 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 167395452 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 05:56:01 PM UTC 25 |
| Finished | Feb 08 05:56:04 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=234420323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 1.usbdev_stall_priority_over_nak.234420323 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_stall_trans.2391004105 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 231694611 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 05:56:01 PM UTC 25 |
| Finished | Feb 08 05:56:04 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2391004105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbd ev_stall_trans.2391004105 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_stream_len_max.1254491237 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 1055664062 ps |
| CPU time | 4.32 seconds |
| Started | Feb 08 05:56:05 PM UTC 25 |
| Finished | Feb 08 05:56:10 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1254491237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.u sbdev_stream_len_max.1254491237 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_streaming_out.1347460866 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1991767264 ps |
| CPU time | 16.43 seconds |
| Started | Feb 08 05:56:05 PM UTC 25 |
| Finished | Feb 08 05:56:22 PM UTC 25 |
| Peak memory | 234368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1347460866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev _streaming_out.1347460866 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_timeout_missing_host_handshake.1647268525 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 881793381 ps |
| CPU time | 20.28 seconds |
| Started | Feb 08 05:54:26 PM UTC 25 |
| Finished | Feb 08 05:54:47 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647268525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_host_handshake.1647268525 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/1.usbdev_tx_rx_disruption.3491957669 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 607336365 ps |
| CPU time | 3.07 seconds |
| Started | Feb 08 05:56:06 PM UTC 25 |
| Finished | Feb 08 05:56:10 PM UTC 25 |
| Peak memory | 217116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 491957669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_tx_rx_disruption.3491957669 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/1.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_alert_test.2674808064 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 43190932 ps |
| CPU time | 1.02 seconds |
| Started | Feb 08 06:03:47 PM UTC 25 |
| Finished | Feb 08 06:03:50 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674808064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 10.usbdev_alert_test.2674808064 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_aon_wake_disconnect.2963853295 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 8956181458 ps |
| CPU time | 19.22 seconds |
| Started | Feb 08 06:03:17 PM UTC 25 |
| Finished | Feb 08 06:03:38 PM UTC 25 |
| Peak memory | 217336 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963853295 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.2963853295 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_aon_wake_reset.899345507 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 20799303024 ps |
| CPU time | 32.13 seconds |
| Started | Feb 08 06:03:17 PM UTC 25 |
| Finished | Feb 08 06:03:51 PM UTC 25 |
| Peak memory | 217384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899345507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TE ST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.899345507 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_aon_wake_resume.1381292096 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 31354669618 ps |
| CPU time | 48.17 seconds |
| Started | Feb 08 06:03:17 PM UTC 25 |
| Finished | Feb 08 06:04:07 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381292096 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.1381292096 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_av_buffer.2432510077 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 213934173 ps |
| CPU time | 1.67 seconds |
| Started | Feb 08 06:03:19 PM UTC 25 |
| Finished | Feb 08 06:03:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2432510077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbde v_av_buffer.2432510077 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_bitstuff_err.2876323678 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 165276312 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:03:19 PM UTC 25 |
| Finished | Feb 08 06:03:21 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2876323678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.us bdev_bitstuff_err.2876323678 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_data_toggle_clear.1082191969 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 362958367 ps |
| CPU time | 1.85 seconds |
| Started | Feb 08 06:03:20 PM UTC 25 |
| Finished | Feb 08 06:03:23 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1082191969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.1082191969 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_data_toggle_restore.1189492634 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 306483132 ps |
| CPU time | 1.94 seconds |
| Started | Feb 08 06:03:20 PM UTC 25 |
| Finished | Feb 08 06:03:23 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189492634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.1189492634 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_device_address.1486826887 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 17745075090 ps |
| CPU time | 33.16 seconds |
| Started | Feb 08 06:03:21 PM UTC 25 |
| Finished | Feb 08 06:03:56 PM UTC 25 |
| Peak memory | 217608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1486826887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10. usbdev_device_address.1486826887 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_device_timeout.501207886 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 1314052033 ps |
| CPU time | 28.5 seconds |
| Started | Feb 08 06:03:22 PM UTC 25 |
| Finished | Feb 08 06:03:52 PM UTC 25 |
| Peak memory | 217472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501207886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.501207886 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_disable_endpoint.3720709854 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 578959854 ps |
| CPU time | 3.04 seconds |
| Started | Feb 08 06:03:22 PM UTC 25 |
| Finished | Feb 08 06:03:27 PM UTC 25 |
| Peak memory | 217344 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3720709854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.usbdev_disable_endpoint.3720709854 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_disconnected.267326647 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 141935259 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:03:23 PM UTC 25 |
| Finished | Feb 08 06:03:25 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=267326647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usb dev_disconnected.267326647 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_enable.3074914260 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 49366752 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 06:03:23 PM UTC 25 |
| Finished | Feb 08 06:03:25 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3074914260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_e nable.3074914260 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_endpoint_access.2690190203 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 992360862 ps |
| CPU time | 4.86 seconds |
| Started | Feb 08 06:03:24 PM UTC 25 |
| Finished | Feb 08 06:03:30 PM UTC 25 |
| Peak memory | 217436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2690190203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10 .usbdev_endpoint_access.2690190203 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_fifo_rst.3110383419 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 177454739 ps |
| CPU time | 2.68 seconds |
| Started | Feb 08 06:03:26 PM UTC 25 |
| Finished | Feb 08 06:03:30 PM UTC 25 |
| Peak memory | 217596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3110383419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev _fifo_rst.3110383419 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_in_iso.1964503304 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 259061548 ps |
| CPU time | 1.82 seconds |
| Started | Feb 08 06:03:26 PM UTC 25 |
| Finished | Feb 08 06:03:29 PM UTC 25 |
| Peak memory | 227756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964503304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 10.usbdev_in_iso.1964503304 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_in_stall.7459454 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 141442114 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:03:28 PM UTC 25 |
| Finished | Feb 08 06:03:30 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=7459454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in _stall.7459454 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_in_trans.2319281804 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 234864459 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:03:28 PM UTC 25 |
| Finished | Feb 08 06:03:30 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2319281804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev _in_trans.2319281804 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_invalid_sync.3718894492 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 3698444603 ps |
| CPU time | 109.55 seconds |
| Started | Feb 08 06:03:26 PM UTC 25 |
| Finished | Feb 08 06:05:18 PM UTC 25 |
| Peak memory | 229652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718894492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.3718894492 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_iso_retraction.1821769785 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 6032178909 ps |
| CPU time | 55.6 seconds |
| Started | Feb 08 06:03:28 PM UTC 25 |
| Finished | Feb 08 06:04:25 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821769785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 10.usbdev_iso_retraction.1821769785 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_link_in_err.2507159484 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 269310731 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:03:29 PM UTC 25 |
| Finished | Feb 08 06:03:32 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2507159484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usb dev_link_in_err.2507159484 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_link_resume.165066998 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 27287929506 ps |
| CPU time | 57.91 seconds |
| Started | Feb 08 06:03:30 PM UTC 25 |
| Finished | Feb 08 06:04:30 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=165066998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbd ev_link_resume.165066998 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_low_speed_traffic.1647550487 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 2438800710 ps |
| CPU time | 25.58 seconds |
| Started | Feb 08 06:03:30 PM UTC 25 |
| Finished | Feb 08 06:03:57 PM UTC 25 |
| Peak memory | 227752 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647550487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 10.usbdev_low_speed_traffic.1647550487 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_max_inter_pkt_delay.1386532644 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 2275533040 ps |
| CPU time | 60.95 seconds |
| Started | Feb 08 06:03:30 PM UTC 25 |
| Finished | Feb 08 06:04:33 PM UTC 25 |
| Peak memory | 227720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386532644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.1386532644 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_max_length_in_transaction.409869329 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 242592900 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 06:03:30 PM UTC 25 |
| Finished | Feb 08 06:03:33 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409869329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.usbdev_max_length_in_transaction.409869329 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_max_length_out_transaction.3062548478 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 202816361 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:03:32 PM UTC 25 |
| Finished | Feb 08 06:03:35 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3062548478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3062548478 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_max_non_iso_usb_traffic.2386608506 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 2337012674 ps |
| CPU time | 69.25 seconds |
| Started | Feb 08 06:03:32 PM UTC 25 |
| Finished | Feb 08 06:04:43 PM UTC 25 |
| Peak memory | 229840 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2386608506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 10.usbdev_max_non_iso_usb_traffic.2386608506 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_max_usb_traffic.1691745289 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 1844188627 ps |
| CPU time | 50.28 seconds |
| Started | Feb 08 06:03:32 PM UTC 25 |
| Finished | Feb 08 06:04:24 PM UTC 25 |
| Peak memory | 229652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691745289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_ traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 10.usbdev_max_usb_traffic.1691745289 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_min_inter_pkt_delay.3071114094 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 3895125581 ps |
| CPU time | 129.04 seconds |
| Started | Feb 08 06:03:32 PM UTC 25 |
| Finished | Feb 08 06:05:44 PM UTC 25 |
| Peak memory | 227664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071114094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.3071114094 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_min_length_in_transaction.1858716515 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 161687967 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:03:32 PM UTC 25 |
| Finished | Feb 08 06:03:35 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858716515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.usbdev_min_length_in_transaction.1858716515 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_min_length_out_transaction.2642054363 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 145750372 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:03:32 PM UTC 25 |
| Finished | Feb 08 06:03:35 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2642054363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2642054363 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_nak_trans.2238072992 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 228019396 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:03:34 PM UTC 25 |
| Finished | Feb 08 06:03:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2238072992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbde v_nak_trans.2238072992 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_out_iso.399902765 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 153290685 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:03:34 PM UTC 25 |
| Finished | Feb 08 06:03:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=399902765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_o ut_iso.399902765 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_out_stall.2672261746 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 181041814 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:03:34 PM UTC 25 |
| Finished | Feb 08 06:03:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2672261746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbde v_out_stall.2672261746 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_out_trans_nak.1429285655 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 212788094 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:03:36 PM UTC 25 |
| Finished | Feb 08 06:03:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1429285655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.u sbdev_out_trans_nak.1429285655 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_pending_in_trans.210476011 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 186001574 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:03:36 PM UTC 25 |
| Finished | Feb 08 06:03:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=210476011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10 .usbdev_pending_in_trans.210476011 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_phy_config_pinflip.1381176928 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 210917404 ps |
| CPU time | 1.74 seconds |
| Started | Feb 08 06:03:36 PM UTC 25 |
| Finished | Feb 08 06:03:39 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381176928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 10.usbdev_phy_config_pinflip.1381176928 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_phy_config_usb_ref_disable.3231214796 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 140437555 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:03:37 PM UTC 25 |
| Finished | Feb 08 06:03:40 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3231214796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3231214796 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_phy_pins_sense.3100911079 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 50206931 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 06:03:37 PM UTC 25 |
| Finished | Feb 08 06:03:40 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3100911079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10. usbdev_phy_pins_sense.3100911079 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_pkt_buffer.2325805331 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 7591483842 ps |
| CPU time | 19.23 seconds |
| Started | Feb 08 06:03:37 PM UTC 25 |
| Finished | Feb 08 06:03:58 PM UTC 25 |
| Peak memory | 227676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2325805331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbd ev_pkt_buffer.2325805331 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_pkt_received.3655312020 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 154608377 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:03:39 PM UTC 25 |
| Finished | Feb 08 06:03:41 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3655312020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.us bdev_pkt_received.3655312020 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_pkt_sent.1010602875 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 240104970 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:03:39 PM UTC 25 |
| Finished | Feb 08 06:03:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1010602875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev _pkt_sent.1010602875 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_random_length_in_transaction.3849054773 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 195608585 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:03:40 PM UTC 25 |
| Finished | Feb 08 06:03:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3849054773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.u sbdev_random_length_in_transaction.3849054773 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_random_length_out_transaction.2326632152 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 163582479 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:03:40 PM UTC 25 |
| Finished | Feb 08 06:03:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2326632152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.usbdev_random_length_out_transaction.2326632152 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_resume_link_active.3020046985 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 20216624116 ps |
| CPU time | 29.35 seconds |
| Started | Feb 08 06:03:40 PM UTC 25 |
| Finished | Feb 08 06:04:11 PM UTC 25 |
| Peak memory | 217344 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3020046985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_resume_link_active.3020046985 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_resume_link_active/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_rx_crc_err.2480677503 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 135128091 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:03:41 PM UTC 25 |
| Finished | Feb 08 06:03:44 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2480677503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbd ev_rx_crc_err.2480677503 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_rx_full.2454435121 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 400580722 ps |
| CPU time | 2.05 seconds |
| Started | Feb 08 06:03:41 PM UTC 25 |
| Finished | Feb 08 06:03:45 PM UTC 25 |
| Peak memory | 217112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2454435121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_ rx_full.2454435121 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_setup_stage.1052515178 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 148324242 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 06:03:41 PM UTC 25 |
| Finished | Feb 08 06:03:44 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1052515178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usb dev_setup_stage.1052515178 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_setup_trans_ignored.2252068037 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 147832880 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:03:42 PM UTC 25 |
| Finished | Feb 08 06:03:45 PM UTC 25 |
| Peak memory | 215060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2252068037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.usbdev_setup_trans_ignored.2252068037 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_smoke.266982461 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 228171584 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:03:43 PM UTC 25 |
| Finished | Feb 08 06:03:46 PM UTC 25 |
| Peak memory | 215076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=266982461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smo ke.266982461 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_spurious_pids_ignored.4025469271 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 2620279501 ps |
| CPU time | 75.1 seconds |
| Started | Feb 08 06:03:44 PM UTC 25 |
| Finished | Feb 08 06:05:01 PM UTC 25 |
| Peak memory | 229948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025469271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 10.usbdev_spurious_pids_ignored.4025469271 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_stall_priority_over_nak.1327006742 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 186719933 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:03:44 PM UTC 25 |
| Finished | Feb 08 06:03:47 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1327006742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 10.usbdev_stall_priority_over_nak.1327006742 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_stall_trans.1873686267 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 196563502 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:03:45 PM UTC 25 |
| Finished | Feb 08 06:03:48 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1873686267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usb dev_stall_trans.1873686267 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_stream_len_max.2731161575 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 1022021347 ps |
| CPU time | 4.38 seconds |
| Started | Feb 08 06:03:45 PM UTC 25 |
| Finished | Feb 08 06:03:51 PM UTC 25 |
| Peak memory | 217344 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2731161575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10. usbdev_stream_len_max.2731161575 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_streaming_out.860813196 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 2848500627 ps |
| CPU time | 30.88 seconds |
| Started | Feb 08 06:03:45 PM UTC 25 |
| Finished | Feb 08 06:04:17 PM UTC 25 |
| Peak memory | 229704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=860813196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev _streaming_out.860813196 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_timeout_missing_host_handshake.3383094153 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 3848125897 ps |
| CPU time | 37.56 seconds |
| Started | Feb 08 06:03:22 PM UTC 25 |
| Finished | Feb 08 06:04:02 PM UTC 25 |
| Peak memory | 217612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383094153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing_host_handshake.3383094153 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/10.usbdev_tx_rx_disruption.2693664424 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 453715054 ps |
| CPU time | 2.5 seconds |
| Started | Feb 08 06:03:46 PM UTC 25 |
| Finished | Feb 08 06:03:50 PM UTC 25 |
| Peak memory | 217308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 693664424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_tx_rx_disruption.2693664424 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/10.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/100.usbdev_endpoint_types.791923361 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 325730801 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:18:20 PM UTC 25 |
| Finished | Feb 08 06:18:22 PM UTC 25 |
| Peak memory | 215028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791923361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 100.usbdev_endpoint_types.791923361 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/100.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/100.usbdev_tx_rx_disruption.3898816801 |
| Short name | T3175 |
| Test name | |
| Test status | |
| Simulation time | 538822040 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:18:20 PM UTC 25 |
| Finished | Feb 08 06:18:23 PM UTC 25 |
| Peak memory | 215004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 898816801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.usbdev_tx_rx_disruption.3898816801 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/100.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/101.usbdev_endpoint_types.1032956768 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 815257370 ps |
| CPU time | 1.77 seconds |
| Started | Feb 08 06:18:20 PM UTC 25 |
| Finished | Feb 08 06:18:23 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032956768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 101.usbdev_endpoint_types.1032956768 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/101.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/101.usbdev_tx_rx_disruption.4065672000 |
| Short name | T3180 |
| Test name | |
| Test status | |
| Simulation time | 557538550 ps |
| CPU time | 2.14 seconds |
| Started | Feb 08 06:18:20 PM UTC 25 |
| Finished | Feb 08 06:18:23 PM UTC 25 |
| Peak memory | 217124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 065672000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.usbdev_tx_rx_disruption.4065672000 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/101.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/102.usbdev_endpoint_types.97691928 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 439017757 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:18:20 PM UTC 25 |
| Finished | Feb 08 06:18:23 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97691928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_t ypes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.usbdev_endpoint_types.97691928 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/102.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/102.usbdev_tx_rx_disruption.9404795 |
| Short name | T3177 |
| Test name | |
| Test status | |
| Simulation time | 542206870 ps |
| CPU time | 1.74 seconds |
| Started | Feb 08 06:18:20 PM UTC 25 |
| Finished | Feb 08 06:18:23 PM UTC 25 |
| Peak memory | 215116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 404795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.usbdev_tx_rx_disruption.9404795 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/102.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/103.usbdev_endpoint_types.509251937 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 459298378 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:18:20 PM UTC 25 |
| Finished | Feb 08 06:18:23 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509251937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 103.usbdev_endpoint_types.509251937 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/103.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/104.usbdev_endpoint_types.2752507509 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 583688175 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:18:20 PM UTC 25 |
| Finished | Feb 08 06:18:23 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752507509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 104.usbdev_endpoint_types.2752507509 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/104.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/104.usbdev_tx_rx_disruption.1037904310 |
| Short name | T3179 |
| Test name | |
| Test status | |
| Simulation time | 549720531 ps |
| CPU time | 1.78 seconds |
| Started | Feb 08 06:18:20 PM UTC 25 |
| Finished | Feb 08 06:18:23 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 037904310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.usbdev_tx_rx_disruption.1037904310 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/104.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/105.usbdev_endpoint_types.339019940 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 275687805 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:18:21 PM UTC 25 |
| Finished | Feb 08 06:18:24 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339019940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 105.usbdev_endpoint_types.339019940 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/105.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/105.usbdev_tx_rx_disruption.3776021801 |
| Short name | T3187 |
| Test name | |
| Test status | |
| Simulation time | 606726125 ps |
| CPU time | 1.74 seconds |
| Started | Feb 08 06:18:21 PM UTC 25 |
| Finished | Feb 08 06:18:25 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 776021801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.usbdev_tx_rx_disruption.3776021801 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/105.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/106.usbdev_endpoint_types.4039862442 |
| Short name | T3182 |
| Test name | |
| Test status | |
| Simulation time | 276443346 ps |
| CPU time | 1.12 seconds |
| Started | Feb 08 06:18:22 PM UTC 25 |
| Finished | Feb 08 06:18:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039862442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 106.usbdev_endpoint_types.4039862442 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/106.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/106.usbdev_tx_rx_disruption.465676224 |
| Short name | T3184 |
| Test name | |
| Test status | |
| Simulation time | 485381228 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:18:22 PM UTC 25 |
| Finished | Feb 08 06:18:24 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 65676224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.usbdev_tx_rx_disruption.465676224 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/106.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/107.usbdev_endpoint_types.3187412456 |
| Short name | T3183 |
| Test name | |
| Test status | |
| Simulation time | 266357020 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:18:22 PM UTC 25 |
| Finished | Feb 08 06:18:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187412456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 107.usbdev_endpoint_types.3187412456 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/107.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/107.usbdev_tx_rx_disruption.3222136319 |
| Short name | T3186 |
| Test name | |
| Test status | |
| Simulation time | 507499164 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:18:22 PM UTC 25 |
| Finished | Feb 08 06:18:25 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 222136319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.usbdev_tx_rx_disruption.3222136319 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/107.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/108.usbdev_endpoint_types.560686619 |
| Short name | T3189 |
| Test name | |
| Test status | |
| Simulation time | 642253122 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:18:22 PM UTC 25 |
| Finished | Feb 08 06:18:25 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560686619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 108.usbdev_endpoint_types.560686619 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/108.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/108.usbdev_tx_rx_disruption.3343138211 |
| Short name | T3188 |
| Test name | |
| Test status | |
| Simulation time | 501581240 ps |
| CPU time | 1.74 seconds |
| Started | Feb 08 06:18:22 PM UTC 25 |
| Finished | Feb 08 06:18:25 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 343138211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.usbdev_tx_rx_disruption.3343138211 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/108.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/109.usbdev_endpoint_types.2767677622 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 343167208 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:18:22 PM UTC 25 |
| Finished | Feb 08 06:18:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767677622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 109.usbdev_endpoint_types.2767677622 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/109.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/109.usbdev_tx_rx_disruption.3663332755 |
| Short name | T3191 |
| Test name | |
| Test status | |
| Simulation time | 647088467 ps |
| CPU time | 1.74 seconds |
| Started | Feb 08 06:18:22 PM UTC 25 |
| Finished | Feb 08 06:18:25 PM UTC 25 |
| Peak memory | 214984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 663332755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.usbdev_tx_rx_disruption.3663332755 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/109.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_alert_test.1378339617 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 89971062 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 06:04:21 PM UTC 25 |
| Finished | Feb 08 06:04:23 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378339617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 11.usbdev_alert_test.1378339617 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_aon_wake_disconnect.3160462789 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 11992157836 ps |
| CPU time | 26.13 seconds |
| Started | Feb 08 06:03:49 PM UTC 25 |
| Finished | Feb 08 06:04:16 PM UTC 25 |
| Peak memory | 217636 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160462789 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.3160462789 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_aon_wake_reset.1432380261 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 18329606424 ps |
| CPU time | 27.56 seconds |
| Started | Feb 08 06:03:49 PM UTC 25 |
| Finished | Feb 08 06:04:18 PM UTC 25 |
| Peak memory | 217576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432380261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.1432380261 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_aon_wake_resume.1857857866 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 29983131415 ps |
| CPU time | 49.52 seconds |
| Started | Feb 08 06:03:49 PM UTC 25 |
| Finished | Feb 08 06:04:40 PM UTC 25 |
| Peak memory | 217576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857857866 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.1857857866 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_av_buffer.1559825399 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 163608816 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:03:50 PM UTC 25 |
| Finished | Feb 08 06:03:52 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1559825399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbde v_av_buffer.1559825399 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_bitstuff_err.1722817191 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 163420868 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:03:51 PM UTC 25 |
| Finished | Feb 08 06:03:54 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1722817191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.us bdev_bitstuff_err.1722817191 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_data_toggle_clear.2363519464 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 302057224 ps |
| CPU time | 2.16 seconds |
| Started | Feb 08 06:03:51 PM UTC 25 |
| Finished | Feb 08 06:03:55 PM UTC 25 |
| Peak memory | 217308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2363519464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.2363519464 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_data_toggle_restore.464466218 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 707357351 ps |
| CPU time | 3 seconds |
| Started | Feb 08 06:03:51 PM UTC 25 |
| Finished | Feb 08 06:03:56 PM UTC 25 |
| Peak memory | 217172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464466218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_t oggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.464466218 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_device_address.965072102 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 25525525245 ps |
| CPU time | 48.8 seconds |
| Started | Feb 08 06:03:51 PM UTC 25 |
| Finished | Feb 08 06:04:42 PM UTC 25 |
| Peak memory | 217484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=965072102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.u sbdev_device_address.965072102 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_device_timeout.3602393254 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 6753972260 ps |
| CPU time | 52.99 seconds |
| Started | Feb 08 06:03:53 PM UTC 25 |
| Finished | Feb 08 06:04:47 PM UTC 25 |
| Peak memory | 217340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602393254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.3602393254 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_disable_endpoint.2572895667 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 900110499 ps |
| CPU time | 3.4 seconds |
| Started | Feb 08 06:03:54 PM UTC 25 |
| Finished | Feb 08 06:03:59 PM UTC 25 |
| Peak memory | 216920 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2572895667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.usbdev_disable_endpoint.2572895667 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_disconnected.3700177492 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 135200317 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 06:03:54 PM UTC 25 |
| Finished | Feb 08 06:03:56 PM UTC 25 |
| Peak memory | 214900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3700177492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.us bdev_disconnected.3700177492 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_enable.2821835329 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 49912467 ps |
| CPU time | 1.05 seconds |
| Started | Feb 08 06:03:55 PM UTC 25 |
| Finished | Feb 08 06:03:57 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2821835329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_e nable.2821835329 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_endpoint_access.1100792332 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 886497164 ps |
| CPU time | 3.86 seconds |
| Started | Feb 08 06:03:55 PM UTC 25 |
| Finished | Feb 08 06:04:00 PM UTC 25 |
| Peak memory | 217588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1100792332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11 .usbdev_endpoint_access.1100792332 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_fifo_rst.431520255 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 232051536 ps |
| CPU time | 2.5 seconds |
| Started | Feb 08 06:03:57 PM UTC 25 |
| Finished | Feb 08 06:04:01 PM UTC 25 |
| Peak memory | 217600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=431520255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_ fifo_rst.431520255 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_in_iso.466302388 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 181574915 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:03:57 PM UTC 25 |
| Finished | Feb 08 06:04:00 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466302388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 11.usbdev_in_iso.466302388 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_in_stall.740467112 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 184722599 ps |
| CPU time | 0.99 seconds |
| Started | Feb 08 06:03:57 PM UTC 25 |
| Finished | Feb 08 06:04:00 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=740467112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_ in_stall.740467112 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_in_trans.579493015 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 218682948 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:03:59 PM UTC 25 |
| Finished | Feb 08 06:04:02 PM UTC 25 |
| Peak memory | 214932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=579493015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_ in_trans.579493015 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_invalid_sync.344004138 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 2557963878 ps |
| CPU time | 21.5 seconds |
| Started | Feb 08 06:03:57 PM UTC 25 |
| Finished | Feb 08 06:04:20 PM UTC 25 |
| Peak memory | 229696 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344004138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.344004138 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_iso_retraction.3887811419 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 8973371595 ps |
| CPU time | 102.95 seconds |
| Started | Feb 08 06:03:59 PM UTC 25 |
| Finished | Feb 08 06:05:44 PM UTC 25 |
| Peak memory | 217212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887811419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 11.usbdev_iso_retraction.3887811419 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_link_in_err.4000813846 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 161331259 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:03:59 PM UTC 25 |
| Finished | Feb 08 06:04:01 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4000813846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usb dev_link_in_err.4000813846 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_link_resume.2132410762 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 9909758834 ps |
| CPU time | 14.88 seconds |
| Started | Feb 08 06:04:00 PM UTC 25 |
| Finished | Feb 08 06:04:16 PM UTC 25 |
| Peak memory | 227792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2132410762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usb dev_link_resume.2132410762 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_link_suspend.2278727594 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 4598832993 ps |
| CPU time | 13.81 seconds |
| Started | Feb 08 06:04:00 PM UTC 25 |
| Finished | Feb 08 06:04:15 PM UTC 25 |
| Peak memory | 217544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2278727594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.us bdev_link_suspend.2278727594 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_low_speed_traffic.3873171109 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 3407561756 ps |
| CPU time | 106 seconds |
| Started | Feb 08 06:04:00 PM UTC 25 |
| Finished | Feb 08 06:05:49 PM UTC 25 |
| Peak memory | 229764 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873171109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 11.usbdev_low_speed_traffic.3873171109 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_max_inter_pkt_delay.1462792517 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 2780414614 ps |
| CPU time | 74.28 seconds |
| Started | Feb 08 06:04:02 PM UTC 25 |
| Finished | Feb 08 06:05:18 PM UTC 25 |
| Peak memory | 234308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462792517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.1462792517 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_max_length_in_transaction.2579414914 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 252760128 ps |
| CPU time | 1.71 seconds |
| Started | Feb 08 06:04:02 PM UTC 25 |
| Finished | Feb 08 06:04:04 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579414914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 11.usbdev_max_length_in_transaction.2579414914 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_max_length_out_transaction.544088226 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 211286598 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:04:02 PM UTC 25 |
| Finished | Feb 08 06:04:04 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=544088226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 11.usbdev_max_length_out_transaction.544088226 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_max_non_iso_usb_traffic.534488557 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 2536700416 ps |
| CPU time | 34.05 seconds |
| Started | Feb 08 06:04:03 PM UTC 25 |
| Finished | Feb 08 06:04:38 PM UTC 25 |
| Peak memory | 227752 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=534488557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 11.usbdev_max_non_iso_usb_traffic.534488557 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_max_usb_traffic.3192270116 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 2076415407 ps |
| CPU time | 70.93 seconds |
| Started | Feb 08 06:04:03 PM UTC 25 |
| Finished | Feb 08 06:05:16 PM UTC 25 |
| Peak memory | 229900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192270116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_ traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 11.usbdev_max_usb_traffic.3192270116 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_min_inter_pkt_delay.3762939107 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 3145084265 ps |
| CPU time | 91.15 seconds |
| Started | Feb 08 06:04:03 PM UTC 25 |
| Finished | Feb 08 06:05:36 PM UTC 25 |
| Peak memory | 227600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762939107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.3762939107 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_min_length_in_transaction.1302994506 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 151567462 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:04:04 PM UTC 25 |
| Finished | Feb 08 06:04:07 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302994506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 11.usbdev_min_length_in_transaction.1302994506 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_min_length_out_transaction.1280398683 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 148438627 ps |
| CPU time | 0.99 seconds |
| Started | Feb 08 06:04:04 PM UTC 25 |
| Finished | Feb 08 06:04:06 PM UTC 25 |
| Peak memory | 215092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1280398683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.1280398683 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_out_iso.1124763590 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 170883855 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:04:07 PM UTC 25 |
| Finished | Feb 08 06:04:10 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1124763590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_ out_iso.1124763590 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_out_stall.2638034895 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 174387069 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:04:08 PM UTC 25 |
| Finished | Feb 08 06:04:10 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2638034895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbde v_out_stall.2638034895 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_out_trans_nak.880951893 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 173541867 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:04:09 PM UTC 25 |
| Finished | Feb 08 06:04:11 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=880951893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.us bdev_out_trans_nak.880951893 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_phy_config_pinflip.3045911969 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 222435715 ps |
| CPU time | 1.79 seconds |
| Started | Feb 08 06:04:10 PM UTC 25 |
| Finished | Feb 08 06:04:13 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045911969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 11.usbdev_phy_config_pinflip.3045911969 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_phy_config_usb_ref_disable.4086395897 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 182722282 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:04:11 PM UTC 25 |
| Finished | Feb 08 06:04:14 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4086395897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.4086395897 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_phy_pins_sense.588483954 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 35097871 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 06:04:11 PM UTC 25 |
| Finished | Feb 08 06:04:13 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=588483954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.u sbdev_phy_pins_sense.588483954 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_pkt_buffer.1030058019 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 14025394603 ps |
| CPU time | 48.5 seconds |
| Started | Feb 08 06:04:12 PM UTC 25 |
| Finished | Feb 08 06:05:03 PM UTC 25 |
| Peak memory | 227876 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1030058019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbd ev_pkt_buffer.1030058019 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_pkt_received.18148174 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 167244260 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:04:12 PM UTC 25 |
| Finished | Feb 08 06:04:16 PM UTC 25 |
| Peak memory | 216816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=18148174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbd ev_pkt_received.18148174 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_pkt_sent.2581422159 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 267149844 ps |
| CPU time | 1.71 seconds |
| Started | Feb 08 06:04:12 PM UTC 25 |
| Finished | Feb 08 06:04:16 PM UTC 25 |
| Peak memory | 214356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2581422159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev _pkt_sent.2581422159 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_random_length_in_transaction.616003695 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 189664766 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:04:14 PM UTC 25 |
| Finished | Feb 08 06:04:17 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=616003695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.us bdev_random_length_in_transaction.616003695 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_random_length_out_transaction.991345279 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 155370028 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:04:15 PM UTC 25 |
| Finished | Feb 08 06:04:18 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=991345279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 11.usbdev_random_length_out_transaction.991345279 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_resume_link_active.1192526871 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 20232917223 ps |
| CPU time | 38.82 seconds |
| Started | Feb 08 06:04:15 PM UTC 25 |
| Finished | Feb 08 06:04:56 PM UTC 25 |
| Peak memory | 217216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1192526871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_resume_link_active.1192526871 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_resume_link_active/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_rx_crc_err.1476129764 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 141106919 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:04:15 PM UTC 25 |
| Finished | Feb 08 06:04:18 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1476129764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbd ev_rx_crc_err.1476129764 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_rx_full.1923363056 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 252604682 ps |
| CPU time | 1.87 seconds |
| Started | Feb 08 06:04:16 PM UTC 25 |
| Finished | Feb 08 06:04:19 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1923363056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_ rx_full.1923363056 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_setup_stage.1918031485 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 147213326 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 06:04:18 PM UTC 25 |
| Finished | Feb 08 06:04:20 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1918031485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usb dev_setup_stage.1918031485 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_setup_trans_ignored.1274434767 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 156164958 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:04:18 PM UTC 25 |
| Finished | Feb 08 06:04:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1274434767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.usbdev_setup_trans_ignored.1274434767 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_smoke.1911682957 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 226609828 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:04:18 PM UTC 25 |
| Finished | Feb 08 06:04:21 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1911682957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_sm oke.1911682957 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_spurious_pids_ignored.2825092791 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 3986853772 ps |
| CPU time | 132.06 seconds |
| Started | Feb 08 06:04:18 PM UTC 25 |
| Finished | Feb 08 06:06:32 PM UTC 25 |
| Peak memory | 229764 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825092791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 11.usbdev_spurious_pids_ignored.2825092791 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_stall_priority_over_nak.926687090 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 160120660 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:04:18 PM UTC 25 |
| Finished | Feb 08 06:04:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=926687090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 11.usbdev_stall_priority_over_nak.926687090 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_stall_trans.796967419 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 156126184 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:04:18 PM UTC 25 |
| Finished | Feb 08 06:04:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=796967419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbd ev_stall_trans.796967419 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_stream_len_max.2317743401 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 930206384 ps |
| CPU time | 3.08 seconds |
| Started | Feb 08 06:04:19 PM UTC 25 |
| Finished | Feb 08 06:04:24 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2317743401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11. usbdev_stream_len_max.2317743401 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_streaming_out.85470225 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 1876340763 ps |
| CPU time | 51.11 seconds |
| Started | Feb 08 06:04:19 PM UTC 25 |
| Finished | Feb 08 06:05:12 PM UTC 25 |
| Peak memory | 227600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=85470225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_ streaming_out.85470225 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_timeout_missing_host_handshake.2242085449 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 2996042997 ps |
| CPU time | 30.8 seconds |
| Started | Feb 08 06:03:53 PM UTC 25 |
| Finished | Feb 08 06:04:25 PM UTC 25 |
| Peak memory | 217528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242085449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_host_handshake.2242085449 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_tx_rx_disruption.3032273156 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 565226422 ps |
| CPU time | 2.12 seconds |
| Started | Feb 08 06:04:19 PM UTC 25 |
| Finished | Feb 08 06:04:23 PM UTC 25 |
| Peak memory | 217116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 032273156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_tx_rx_disruption.3032273156 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/11.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/110.usbdev_endpoint_types.4113554411 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 173785408 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 06:18:22 PM UTC 25 |
| Finished | Feb 08 06:18:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113554411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 110.usbdev_endpoint_types.4113554411 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/110.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/110.usbdev_tx_rx_disruption.1498882061 |
| Short name | T3192 |
| Test name | |
| Test status | |
| Simulation time | 520767729 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:18:22 PM UTC 25 |
| Finished | Feb 08 06:18:25 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 498882061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.usbdev_tx_rx_disruption.1498882061 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/110.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/111.usbdev_endpoint_types.184779712 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 357330502 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:18:22 PM UTC 25 |
| Finished | Feb 08 06:18:25 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184779712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 111.usbdev_endpoint_types.184779712 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/111.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/111.usbdev_tx_rx_disruption.1406709175 |
| Short name | T3190 |
| Test name | |
| Test status | |
| Simulation time | 460938688 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:18:22 PM UTC 25 |
| Finished | Feb 08 06:18:25 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 406709175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.usbdev_tx_rx_disruption.1406709175 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/111.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/112.usbdev_endpoint_types.2018592460 |
| Short name | T3185 |
| Test name | |
| Test status | |
| Simulation time | 237987182 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 06:18:22 PM UTC 25 |
| Finished | Feb 08 06:18:25 PM UTC 25 |
| Peak memory | 215088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018592460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 112.usbdev_endpoint_types.2018592460 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/112.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/112.usbdev_tx_rx_disruption.561582487 |
| Short name | T3197 |
| Test name | |
| Test status | |
| Simulation time | 644514533 ps |
| CPU time | 1.71 seconds |
| Started | Feb 08 06:18:23 PM UTC 25 |
| Finished | Feb 08 06:18:27 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 61582487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.usbdev_tx_rx_disruption.561582487 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/112.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/114.usbdev_endpoint_types.3893590913 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 287699461 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:18:24 PM UTC 25 |
| Finished | Feb 08 06:18:26 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893590913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 114.usbdev_endpoint_types.3893590913 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/114.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/114.usbdev_tx_rx_disruption.662613884 |
| Short name | T3196 |
| Test name | |
| Test status | |
| Simulation time | 448319538 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:18:24 PM UTC 25 |
| Finished | Feb 08 06:18:27 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6 62613884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.usbdev_tx_rx_disruption.662613884 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/114.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/115.usbdev_endpoint_types.1411782666 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 197901299 ps |
| CPU time | 0.93 seconds |
| Started | Feb 08 06:18:24 PM UTC 25 |
| Finished | Feb 08 06:18:26 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411782666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 115.usbdev_endpoint_types.1411782666 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/115.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/115.usbdev_tx_rx_disruption.189843560 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 603392109 ps |
| CPU time | 1.74 seconds |
| Started | Feb 08 06:18:24 PM UTC 25 |
| Finished | Feb 08 06:18:27 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 89843560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.usbdev_tx_rx_disruption.189843560 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/115.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/116.usbdev_endpoint_types.1702809320 |
| Short name | T3194 |
| Test name | |
| Test status | |
| Simulation time | 161051784 ps |
| CPU time | 0.86 seconds |
| Started | Feb 08 06:18:24 PM UTC 25 |
| Finished | Feb 08 06:18:26 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702809320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 116.usbdev_endpoint_types.1702809320 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/116.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/116.usbdev_tx_rx_disruption.502741319 |
| Short name | T3199 |
| Test name | |
| Test status | |
| Simulation time | 590159294 ps |
| CPU time | 1.76 seconds |
| Started | Feb 08 06:18:24 PM UTC 25 |
| Finished | Feb 08 06:18:27 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 02741319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.usbdev_tx_rx_disruption.502741319 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/116.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/117.usbdev_endpoint_types.1145600284 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 373222310 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:18:24 PM UTC 25 |
| Finished | Feb 08 06:18:27 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145600284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 117.usbdev_endpoint_types.1145600284 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/117.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/117.usbdev_tx_rx_disruption.2271143338 |
| Short name | T3201 |
| Test name | |
| Test status | |
| Simulation time | 517128128 ps |
| CPU time | 1.95 seconds |
| Started | Feb 08 06:18:24 PM UTC 25 |
| Finished | Feb 08 06:18:27 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 271143338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.usbdev_tx_rx_disruption.2271143338 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/117.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/118.usbdev_endpoint_types.382695197 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 368832892 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 06:18:24 PM UTC 25 |
| Finished | Feb 08 06:18:27 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382695197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 118.usbdev_endpoint_types.382695197 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/118.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/119.usbdev_endpoint_types.4022685212 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 222244707 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:18:24 PM UTC 25 |
| Finished | Feb 08 06:18:27 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022685212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 119.usbdev_endpoint_types.4022685212 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/119.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/119.usbdev_tx_rx_disruption.2035520039 |
| Short name | T3202 |
| Test name | |
| Test status | |
| Simulation time | 558534211 ps |
| CPU time | 1.94 seconds |
| Started | Feb 08 06:18:24 PM UTC 25 |
| Finished | Feb 08 06:18:27 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 035520039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.usbdev_tx_rx_disruption.2035520039 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/119.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_alert_test.1202421653 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 44798621 ps |
| CPU time | 0.93 seconds |
| Started | Feb 08 06:04:55 PM UTC 25 |
| Finished | Feb 08 06:04:57 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202421653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 12.usbdev_alert_test.1202421653 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_aon_wake_disconnect.4169603064 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 10022320294 ps |
| CPU time | 29.58 seconds |
| Started | Feb 08 06:04:21 PM UTC 25 |
| Finished | Feb 08 06:04:52 PM UTC 25 |
| Peak memory | 217444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169603064 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.4169603064 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_aon_wake_reset.1097119266 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 15344465329 ps |
| CPU time | 23.7 seconds |
| Started | Feb 08 06:04:22 PM UTC 25 |
| Finished | Feb 08 06:04:47 PM UTC 25 |
| Peak memory | 227784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097119266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.1097119266 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_aon_wake_resume.943565324 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 31340844587 ps |
| CPU time | 44.33 seconds |
| Started | Feb 08 06:04:22 PM UTC 25 |
| Finished | Feb 08 06:05:08 PM UTC 25 |
| Peak memory | 217336 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943565324 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.943565324 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_av_buffer.3603649141 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 184880522 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:04:22 PM UTC 25 |
| Finished | Feb 08 06:04:25 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3603649141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbde v_av_buffer.3603649141 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_bitstuff_err.2302781299 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 190517492 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:04:22 PM UTC 25 |
| Finished | Feb 08 06:04:24 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2302781299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.us bdev_bitstuff_err.2302781299 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_data_toggle_clear.276033949 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 366107020 ps |
| CPU time | 2.29 seconds |
| Started | Feb 08 06:04:22 PM UTC 25 |
| Finished | Feb 08 06:04:25 PM UTC 25 |
| Peak memory | 217268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=276033949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.usbdev_data_toggle_clear.276033949 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_data_toggle_restore.2299349621 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 951574611 ps |
| CPU time | 4.16 seconds |
| Started | Feb 08 06:04:23 PM UTC 25 |
| Finished | Feb 08 06:04:28 PM UTC 25 |
| Peak memory | 217304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299349621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.2299349621 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_device_address.1301106320 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 43345673542 ps |
| CPU time | 102.87 seconds |
| Started | Feb 08 06:04:23 PM UTC 25 |
| Finished | Feb 08 06:06:08 PM UTC 25 |
| Peak memory | 217424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1301106320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12. usbdev_device_address.1301106320 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_device_timeout.1929082334 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 3611045722 ps |
| CPU time | 25.04 seconds |
| Started | Feb 08 06:04:24 PM UTC 25 |
| Finished | Feb 08 06:04:51 PM UTC 25 |
| Peak memory | 217228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929082334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.1929082334 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_disable_endpoint.160127254 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 877173971 ps |
| CPU time | 3.76 seconds |
| Started | Feb 08 06:04:26 PM UTC 25 |
| Finished | Feb 08 06:04:31 PM UTC 25 |
| Peak memory | 216940 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=160127254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12 .usbdev_disable_endpoint.160127254 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_disconnected.2527982571 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 180814914 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:04:26 PM UTC 25 |
| Finished | Feb 08 06:04:29 PM UTC 25 |
| Peak memory | 215060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2527982571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.us bdev_disconnected.2527982571 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_enable.1508380427 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 47911485 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:04:26 PM UTC 25 |
| Finished | Feb 08 06:04:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1508380427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_e nable.1508380427 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_endpoint_access.3663248891 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 916201827 ps |
| CPU time | 4.32 seconds |
| Started | Feb 08 06:04:26 PM UTC 25 |
| Finished | Feb 08 06:04:32 PM UTC 25 |
| Peak memory | 217320 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3663248891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12 .usbdev_endpoint_access.3663248891 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_fifo_rst.313515598 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 186021892 ps |
| CPU time | 3.38 seconds |
| Started | Feb 08 06:04:26 PM UTC 25 |
| Finished | Feb 08 06:04:31 PM UTC 25 |
| Peak memory | 217548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=313515598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_ fifo_rst.313515598 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_in_iso.109759057 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 235148904 ps |
| CPU time | 2.07 seconds |
| Started | Feb 08 06:04:29 PM UTC 25 |
| Finished | Feb 08 06:04:33 PM UTC 25 |
| Peak memory | 227560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109759057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 12.usbdev_in_iso.109759057 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_in_stall.3932819398 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 148681386 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:04:30 PM UTC 25 |
| Finished | Feb 08 06:04:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3932819398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev _in_stall.3932819398 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_in_trans.4010454058 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 176860568 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:04:30 PM UTC 25 |
| Finished | Feb 08 06:04:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4010454058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev _in_trans.4010454058 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_invalid_sync.2696947529 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 2687268129 ps |
| CPU time | 77.2 seconds |
| Started | Feb 08 06:04:29 PM UTC 25 |
| Finished | Feb 08 06:05:49 PM UTC 25 |
| Peak memory | 229900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696947529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.2696947529 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_iso_retraction.1852887120 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 6369961505 ps |
| CPU time | 60.03 seconds |
| Started | Feb 08 06:04:31 PM UTC 25 |
| Finished | Feb 08 06:05:32 PM UTC 25 |
| Peak memory | 217356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852887120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 12.usbdev_iso_retraction.1852887120 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_link_in_err.2145476889 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 270255498 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:04:32 PM UTC 25 |
| Finished | Feb 08 06:04:35 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2145476889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usb dev_link_in_err.2145476889 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_link_resume.1313198364 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 24880245526 ps |
| CPU time | 52.34 seconds |
| Started | Feb 08 06:04:32 PM UTC 25 |
| Finished | Feb 08 06:05:26 PM UTC 25 |
| Peak memory | 227664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1313198364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usb dev_link_resume.1313198364 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_link_suspend.25476186 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 9806070121 ps |
| CPU time | 28.77 seconds |
| Started | Feb 08 06:04:33 PM UTC 25 |
| Finished | Feb 08 06:05:04 PM UTC 25 |
| Peak memory | 217432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=25476186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbd ev_link_suspend.25476186 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_max_inter_pkt_delay.3335205134 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 3640467900 ps |
| CPU time | 104.88 seconds |
| Started | Feb 08 06:04:33 PM UTC 25 |
| Finished | Feb 08 06:06:21 PM UTC 25 |
| Peak memory | 229728 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335205134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.3335205134 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_max_length_in_transaction.1601409167 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 241011111 ps |
| CPU time | 1.71 seconds |
| Started | Feb 08 06:04:33 PM UTC 25 |
| Finished | Feb 08 06:04:36 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601409167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 12.usbdev_max_length_in_transaction.1601409167 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_max_length_out_transaction.1311351882 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 245494405 ps |
| CPU time | 1.72 seconds |
| Started | Feb 08 06:04:33 PM UTC 25 |
| Finished | Feb 08 06:04:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1311351882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1311351882 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_max_non_iso_usb_traffic.2091320751 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 3127638308 ps |
| CPU time | 30.01 seconds |
| Started | Feb 08 06:04:35 PM UTC 25 |
| Finished | Feb 08 06:05:06 PM UTC 25 |
| Peak memory | 229912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2091320751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 12.usbdev_max_non_iso_usb_traffic.2091320751 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_max_usb_traffic.737469402 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 2871300719 ps |
| CPU time | 98.15 seconds |
| Started | Feb 08 06:04:36 PM UTC 25 |
| Finished | Feb 08 06:06:16 PM UTC 25 |
| Peak memory | 229768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737469402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_t raffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 12.usbdev_max_usb_traffic.737469402 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_min_inter_pkt_delay.922975494 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 2413366513 ps |
| CPU time | 23.85 seconds |
| Started | Feb 08 06:04:36 PM UTC 25 |
| Finished | Feb 08 06:05:01 PM UTC 25 |
| Peak memory | 229824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922975494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usb dev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.922975494 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_min_length_in_transaction.3962606975 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 150726820 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:04:37 PM UTC 25 |
| Finished | Feb 08 06:04:40 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962606975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.usbdev_min_length_in_transaction.3962606975 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_min_length_out_transaction.2527082010 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 143045802 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:04:37 PM UTC 25 |
| Finished | Feb 08 06:04:40 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2527082010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2527082010 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_out_iso.2148002112 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 168050538 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:04:41 PM UTC 25 |
| Finished | Feb 08 06:04:44 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2148002112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_ out_iso.2148002112 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_out_stall.3898920108 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 164905493 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:04:41 PM UTC 25 |
| Finished | Feb 08 06:04:43 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3898920108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbde v_out_stall.3898920108 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_out_trans_nak.2535837233 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 175519890 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:04:41 PM UTC 25 |
| Finished | Feb 08 06:04:43 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2535837233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.u sbdev_out_trans_nak.2535837233 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_pending_in_trans.3183644113 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 152157149 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:04:43 PM UTC 25 |
| Finished | Feb 08 06:04:46 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3183644113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.usbdev_pending_in_trans.3183644113 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_phy_config_pinflip.2839281303 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 234939700 ps |
| CPU time | 1.89 seconds |
| Started | Feb 08 06:04:43 PM UTC 25 |
| Finished | Feb 08 06:04:46 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839281303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 12.usbdev_phy_config_pinflip.2839281303 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_phy_config_usb_ref_disable.2301110447 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 139717467 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:04:45 PM UTC 25 |
| Finished | Feb 08 06:04:47 PM UTC 25 |
| Peak memory | 214668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2301110447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.2301110447 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_pkt_buffer.3009659428 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 18810867104 ps |
| CPU time | 47.62 seconds |
| Started | Feb 08 06:04:45 PM UTC 25 |
| Finished | Feb 08 06:05:34 PM UTC 25 |
| Peak memory | 227828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3009659428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbd ev_pkt_buffer.3009659428 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_pkt_received.1244374136 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 161723668 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:04:45 PM UTC 25 |
| Finished | Feb 08 06:04:48 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1244374136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.us bdev_pkt_received.1244374136 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_pkt_sent.245774235 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 193554229 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:04:47 PM UTC 25 |
| Finished | Feb 08 06:04:50 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=245774235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_ pkt_sent.245774235 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_random_length_in_transaction.1230713822 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 230600706 ps |
| CPU time | 1.78 seconds |
| Started | Feb 08 06:04:47 PM UTC 25 |
| Finished | Feb 08 06:04:50 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1230713822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.u sbdev_random_length_in_transaction.1230713822 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_random_length_out_transaction.3911913211 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 158701488 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:04:48 PM UTC 25 |
| Finished | Feb 08 06:04:51 PM UTC 25 |
| Peak memory | 214816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3911913211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.usbdev_random_length_out_transaction.3911913211 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_resume_link_active.105002159 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 20153922963 ps |
| CPU time | 35.67 seconds |
| Started | Feb 08 06:04:48 PM UTC 25 |
| Finished | Feb 08 06:05:26 PM UTC 25 |
| Peak memory | 216888 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=105002159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_resume_link_active.105002159 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_resume_link_active/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_rx_crc_err.3944976250 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 168500825 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:04:48 PM UTC 25 |
| Finished | Feb 08 06:04:51 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3944976250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbd ev_rx_crc_err.3944976250 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_rx_full.3217404838 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 245908358 ps |
| CPU time | 1.92 seconds |
| Started | Feb 08 06:04:49 PM UTC 25 |
| Finished | Feb 08 06:04:52 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3217404838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_ rx_full.3217404838 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_setup_stage.600273117 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 161585066 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:04:49 PM UTC 25 |
| Finished | Feb 08 06:04:51 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=600273117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbd ev_setup_stage.600273117 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_setup_trans_ignored.2596314821 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 160128868 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:04:51 PM UTC 25 |
| Finished | Feb 08 06:04:53 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2596314821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.usbdev_setup_trans_ignored.2596314821 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_smoke.3877467138 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 203418170 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:04:51 PM UTC 25 |
| Finished | Feb 08 06:04:54 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3877467138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_sm oke.3877467138 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_spurious_pids_ignored.3379374733 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 2087016241 ps |
| CPU time | 22 seconds |
| Started | Feb 08 06:04:52 PM UTC 25 |
| Finished | Feb 08 06:05:16 PM UTC 25 |
| Peak memory | 234352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379374733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 12.usbdev_spurious_pids_ignored.3379374733 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_stall_priority_over_nak.3304778037 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 201636336 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:04:52 PM UTC 25 |
| Finished | Feb 08 06:04:55 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3304778037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 12.usbdev_stall_priority_over_nak.3304778037 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_stall_trans.2941861515 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 185925752 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:04:52 PM UTC 25 |
| Finished | Feb 08 06:04:55 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2941861515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usb dev_stall_trans.2941861515 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_stream_len_max.976328791 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 991779139 ps |
| CPU time | 2.63 seconds |
| Started | Feb 08 06:04:53 PM UTC 25 |
| Finished | Feb 08 06:04:57 PM UTC 25 |
| Peak memory | 217428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=976328791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.u sbdev_stream_len_max.976328791 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_streaming_out.115637034 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 2289090031 ps |
| CPU time | 74.09 seconds |
| Started | Feb 08 06:04:52 PM UTC 25 |
| Finished | Feb 08 06:06:08 PM UTC 25 |
| Peak memory | 227728 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=115637034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev _streaming_out.115637034 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_timeout_missing_host_handshake.2314034562 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 1399362776 ps |
| CPU time | 38.56 seconds |
| Started | Feb 08 06:04:24 PM UTC 25 |
| Finished | Feb 08 06:05:05 PM UTC 25 |
| Peak memory | 217248 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314034562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing_host_handshake.2314034562 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_tx_rx_disruption.192405258 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 488449783 ps |
| CPU time | 2.62 seconds |
| Started | Feb 08 06:04:53 PM UTC 25 |
| Finished | Feb 08 06:04:57 PM UTC 25 |
| Peak memory | 217316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 92405258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_tx_rx_disruption.192405258 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/12.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/120.usbdev_endpoint_types.1334412016 |
| Short name | T3198 |
| Test name | |
| Test status | |
| Simulation time | 264765751 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:18:24 PM UTC 25 |
| Finished | Feb 08 06:18:27 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334412016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 120.usbdev_endpoint_types.1334412016 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/120.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/120.usbdev_tx_rx_disruption.423576872 |
| Short name | T3200 |
| Test name | |
| Test status | |
| Simulation time | 635280761 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:18:24 PM UTC 25 |
| Finished | Feb 08 06:18:27 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 23576872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.usbdev_tx_rx_disruption.423576872 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/120.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/121.usbdev_endpoint_types.498936476 |
| Short name | T3203 |
| Test name | |
| Test status | |
| Simulation time | 161171039 ps |
| CPU time | 0.9 seconds |
| Started | Feb 08 06:18:26 PM UTC 25 |
| Finished | Feb 08 06:18:28 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498936476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 121.usbdev_endpoint_types.498936476 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/121.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/121.usbdev_tx_rx_disruption.583625194 |
| Short name | T3205 |
| Test name | |
| Test status | |
| Simulation time | 557125313 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:18:26 PM UTC 25 |
| Finished | Feb 08 06:18:29 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 83625194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.usbdev_tx_rx_disruption.583625194 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/121.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/122.usbdev_endpoint_types.2469038544 |
| Short name | T3204 |
| Test name | |
| Test status | |
| Simulation time | 295156810 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 06:18:26 PM UTC 25 |
| Finished | Feb 08 06:18:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469038544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 122.usbdev_endpoint_types.2469038544 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/122.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/122.usbdev_tx_rx_disruption.3028659580 |
| Short name | T3208 |
| Test name | |
| Test status | |
| Simulation time | 587384273 ps |
| CPU time | 1.79 seconds |
| Started | Feb 08 06:18:26 PM UTC 25 |
| Finished | Feb 08 06:18:29 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 028659580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.usbdev_tx_rx_disruption.3028659580 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/122.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/123.usbdev_endpoint_types.3745841538 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 462821478 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:18:26 PM UTC 25 |
| Finished | Feb 08 06:18:29 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745841538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 123.usbdev_endpoint_types.3745841538 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/123.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/123.usbdev_tx_rx_disruption.4043664940 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 489161530 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 06:18:26 PM UTC 25 |
| Finished | Feb 08 06:18:29 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 043664940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.usbdev_tx_rx_disruption.4043664940 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/123.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/124.usbdev_tx_rx_disruption.1137935001 |
| Short name | T3211 |
| Test name | |
| Test status | |
| Simulation time | 617092126 ps |
| CPU time | 1.9 seconds |
| Started | Feb 08 06:18:26 PM UTC 25 |
| Finished | Feb 08 06:18:29 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 137935001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.usbdev_tx_rx_disruption.1137935001 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/124.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/125.usbdev_endpoint_types.2818034951 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 308921862 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:18:26 PM UTC 25 |
| Finished | Feb 08 06:18:29 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818034951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 125.usbdev_endpoint_types.2818034951 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/125.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/125.usbdev_tx_rx_disruption.1424007172 |
| Short name | T3212 |
| Test name | |
| Test status | |
| Simulation time | 527596830 ps |
| CPU time | 1.83 seconds |
| Started | Feb 08 06:18:26 PM UTC 25 |
| Finished | Feb 08 06:18:29 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 424007172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.usbdev_tx_rx_disruption.1424007172 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/125.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/126.usbdev_endpoint_types.2838424959 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 366066368 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:18:26 PM UTC 25 |
| Finished | Feb 08 06:18:29 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838424959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 126.usbdev_endpoint_types.2838424959 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/126.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/126.usbdev_tx_rx_disruption.680331880 |
| Short name | T3210 |
| Test name | |
| Test status | |
| Simulation time | 483954542 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:18:26 PM UTC 25 |
| Finished | Feb 08 06:18:29 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6 80331880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.usbdev_tx_rx_disruption.680331880 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/126.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/127.usbdev_endpoint_types.1944138450 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 723872440 ps |
| CPU time | 1.67 seconds |
| Started | Feb 08 06:18:26 PM UTC 25 |
| Finished | Feb 08 06:18:29 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944138450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 127.usbdev_endpoint_types.1944138450 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/127.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/127.usbdev_tx_rx_disruption.2110024687 |
| Short name | T3214 |
| Test name | |
| Test status | |
| Simulation time | 598209064 ps |
| CPU time | 1.67 seconds |
| Started | Feb 08 06:18:26 PM UTC 25 |
| Finished | Feb 08 06:18:29 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 110024687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.usbdev_tx_rx_disruption.2110024687 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/127.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/128.usbdev_endpoint_types.1957154502 |
| Short name | T3206 |
| Test name | |
| Test status | |
| Simulation time | 170791688 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:18:26 PM UTC 25 |
| Finished | Feb 08 06:18:29 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957154502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 128.usbdev_endpoint_types.1957154502 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/128.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/128.usbdev_tx_rx_disruption.3031059315 |
| Short name | T3215 |
| Test name | |
| Test status | |
| Simulation time | 617732396 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 06:18:26 PM UTC 25 |
| Finished | Feb 08 06:18:29 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 031059315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.usbdev_tx_rx_disruption.3031059315 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/128.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/129.usbdev_endpoint_types.1937233322 |
| Short name | T3209 |
| Test name | |
| Test status | |
| Simulation time | 280175967 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 06:18:26 PM UTC 25 |
| Finished | Feb 08 06:18:29 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937233322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 129.usbdev_endpoint_types.1937233322 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/129.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/129.usbdev_tx_rx_disruption.1141056206 |
| Short name | T3213 |
| Test name | |
| Test status | |
| Simulation time | 475777954 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:18:26 PM UTC 25 |
| Finished | Feb 08 06:18:29 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 141056206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.usbdev_tx_rx_disruption.1141056206 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/129.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_alert_test.3355511901 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 69671238 ps |
| CPU time | 0.96 seconds |
| Started | Feb 08 06:05:23 PM UTC 25 |
| Finished | Feb 08 06:05:25 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355511901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 13.usbdev_alert_test.3355511901 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_aon_wake_disconnect.2011211180 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 11800660236 ps |
| CPU time | 18.76 seconds |
| Started | Feb 08 06:04:55 PM UTC 25 |
| Finished | Feb 08 06:05:15 PM UTC 25 |
| Peak memory | 217572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011211180 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.2011211180 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_aon_wake_reset.1531811805 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 19171983065 ps |
| CPU time | 27.79 seconds |
| Started | Feb 08 06:04:56 PM UTC 25 |
| Finished | Feb 08 06:05:25 PM UTC 25 |
| Peak memory | 217640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531811805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.1531811805 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_aon_wake_resume.1999570586 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 23746462308 ps |
| CPU time | 46.14 seconds |
| Started | Feb 08 06:04:56 PM UTC 25 |
| Finished | Feb 08 06:05:44 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999570586 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.1999570586 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_av_buffer.569239927 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 171069364 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:04:57 PM UTC 25 |
| Finished | Feb 08 06:05:00 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=569239927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev _av_buffer.569239927 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_bitstuff_err.172581140 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 191861372 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:04:57 PM UTC 25 |
| Finished | Feb 08 06:05:00 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=172581140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usb dev_bitstuff_err.172581140 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_data_toggle_clear.3146615522 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 558810133 ps |
| CPU time | 3.1 seconds |
| Started | Feb 08 06:04:57 PM UTC 25 |
| Finished | Feb 08 06:05:02 PM UTC 25 |
| Peak memory | 217180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3146615522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.3146615522 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_data_toggle_restore.1269757907 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 432630963 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:04:59 PM UTC 25 |
| Finished | Feb 08 06:05:01 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269757907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.1269757907 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_device_address.4010326477 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 36367136334 ps |
| CPU time | 101.53 seconds |
| Started | Feb 08 06:04:59 PM UTC 25 |
| Finished | Feb 08 06:06:42 PM UTC 25 |
| Peak memory | 217552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4010326477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13. usbdev_device_address.4010326477 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_device_timeout.429546355 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 1355611677 ps |
| CPU time | 12.53 seconds |
| Started | Feb 08 06:05:01 PM UTC 25 |
| Finished | Feb 08 06:05:15 PM UTC 25 |
| Peak memory | 217280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429546355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.429546355 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_disable_endpoint.3091380603 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 629517681 ps |
| CPU time | 3.27 seconds |
| Started | Feb 08 06:05:01 PM UTC 25 |
| Finished | Feb 08 06:05:06 PM UTC 25 |
| Peak memory | 217040 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3091380603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.usbdev_disable_endpoint.3091380603 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_disconnected.1994243103 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 182457362 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:05:01 PM UTC 25 |
| Finished | Feb 08 06:05:04 PM UTC 25 |
| Peak memory | 215140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1994243103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.us bdev_disconnected.1994243103 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_enable.3510586208 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 46518003 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:05:03 PM UTC 25 |
| Finished | Feb 08 06:05:05 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3510586208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_e nable.3510586208 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_endpoint_access.1813101812 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 1085372367 ps |
| CPU time | 5.38 seconds |
| Started | Feb 08 06:05:03 PM UTC 25 |
| Finished | Feb 08 06:05:09 PM UTC 25 |
| Peak memory | 217444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1813101812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13 .usbdev_endpoint_access.1813101812 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_fifo_rst.1282945452 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 270174027 ps |
| CPU time | 2.73 seconds |
| Started | Feb 08 06:05:03 PM UTC 25 |
| Finished | Feb 08 06:05:07 PM UTC 25 |
| Peak memory | 217544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1282945452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev _fifo_rst.1282945452 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_in_iso.2330617815 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 239152989 ps |
| CPU time | 2.11 seconds |
| Started | Feb 08 06:05:04 PM UTC 25 |
| Finished | Feb 08 06:05:08 PM UTC 25 |
| Peak memory | 227616 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330617815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 13.usbdev_in_iso.2330617815 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_in_stall.2995339843 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 143288293 ps |
| CPU time | 1.12 seconds |
| Started | Feb 08 06:05:04 PM UTC 25 |
| Finished | Feb 08 06:05:07 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2995339843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev _in_stall.2995339843 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_in_trans.3512843723 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 174525030 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:05:06 PM UTC 25 |
| Finished | Feb 08 06:05:08 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3512843723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev _in_trans.3512843723 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_invalid_sync.4243592974 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 3004552168 ps |
| CPU time | 85.37 seconds |
| Started | Feb 08 06:05:04 PM UTC 25 |
| Finished | Feb 08 06:06:32 PM UTC 25 |
| Peak memory | 229740 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243592974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.4243592974 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_iso_retraction.3019642215 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 9599839622 ps |
| CPU time | 137.34 seconds |
| Started | Feb 08 06:05:06 PM UTC 25 |
| Finished | Feb 08 06:07:25 PM UTC 25 |
| Peak memory | 217544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019642215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 13.usbdev_iso_retraction.3019642215 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_link_in_err.2305061827 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 224628060 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 06:05:07 PM UTC 25 |
| Finished | Feb 08 06:05:10 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2305061827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usb dev_link_in_err.2305061827 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_link_suspend.3346055571 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 3963762747 ps |
| CPU time | 7.39 seconds |
| Started | Feb 08 06:05:08 PM UTC 25 |
| Finished | Feb 08 06:05:17 PM UTC 25 |
| Peak memory | 227592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3346055571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.us bdev_link_suspend.3346055571 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_low_speed_traffic.664958571 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 3404733636 ps |
| CPU time | 95.98 seconds |
| Started | Feb 08 06:05:08 PM UTC 25 |
| Finished | Feb 08 06:06:46 PM UTC 25 |
| Peak memory | 229696 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664958571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed _traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 13.usbdev_low_speed_traffic.664958571 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_max_inter_pkt_delay.3330121049 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 4113108431 ps |
| CPU time | 126.95 seconds |
| Started | Feb 08 06:05:08 PM UTC 25 |
| Finished | Feb 08 06:07:17 PM UTC 25 |
| Peak memory | 227720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330121049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.3330121049 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_max_length_in_transaction.4237313201 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 239958590 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:05:08 PM UTC 25 |
| Finished | Feb 08 06:05:11 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237313201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 13.usbdev_max_length_in_transaction.4237313201 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_max_length_out_transaction.3371237050 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 188046284 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:05:09 PM UTC 25 |
| Finished | Feb 08 06:05:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3371237050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3371237050 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_max_non_iso_usb_traffic.2249234653 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 2996032495 ps |
| CPU time | 98.38 seconds |
| Started | Feb 08 06:05:09 PM UTC 25 |
| Finished | Feb 08 06:06:50 PM UTC 25 |
| Peak memory | 234368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2249234653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 13.usbdev_max_non_iso_usb_traffic.2249234653 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_max_usb_traffic.2345986522 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 2849964477 ps |
| CPU time | 81.66 seconds |
| Started | Feb 08 06:05:11 PM UTC 25 |
| Finished | Feb 08 06:06:34 PM UTC 25 |
| Peak memory | 229708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345986522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_ traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 13.usbdev_max_usb_traffic.2345986522 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_min_inter_pkt_delay.2923852982 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 1688920057 ps |
| CPU time | 15.27 seconds |
| Started | Feb 08 06:05:11 PM UTC 25 |
| Finished | Feb 08 06:05:27 PM UTC 25 |
| Peak memory | 227672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923852982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.2923852982 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_min_length_in_transaction.2328197589 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 154255176 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:05:12 PM UTC 25 |
| Finished | Feb 08 06:05:14 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328197589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.usbdev_min_length_in_transaction.2328197589 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_min_length_out_transaction.4105072226 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 150587624 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:05:13 PM UTC 25 |
| Finished | Feb 08 06:05:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4105072226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.4105072226 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_out_iso.2990523471 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 173370391 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:05:15 PM UTC 25 |
| Finished | Feb 08 06:05:18 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2990523471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_ out_iso.2990523471 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_out_stall.3501936586 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 177499922 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:05:15 PM UTC 25 |
| Finished | Feb 08 06:05:18 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3501936586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbde v_out_stall.3501936586 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_out_trans_nak.2916034660 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 203440757 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:05:16 PM UTC 25 |
| Finished | Feb 08 06:05:18 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2916034660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.u sbdev_out_trans_nak.2916034660 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_pending_in_trans.2176552780 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 159421422 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:05:16 PM UTC 25 |
| Finished | Feb 08 06:05:18 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2176552780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.usbdev_pending_in_trans.2176552780 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_phy_config_pinflip.1302958874 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 216452209 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:05:17 PM UTC 25 |
| Finished | Feb 08 06:05:19 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302958874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 13.usbdev_phy_config_pinflip.1302958874 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_phy_config_usb_ref_disable.452097044 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 158260767 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:05:17 PM UTC 25 |
| Finished | Feb 08 06:05:20 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=452097044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 13.usbdev_phy_config_usb_ref_disable.452097044 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_phy_pins_sense.2939040157 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 40479413 ps |
| CPU time | 0.84 seconds |
| Started | Feb 08 06:05:17 PM UTC 25 |
| Finished | Feb 08 06:05:19 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2939040157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13. usbdev_phy_pins_sense.2939040157 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_pkt_buffer.109080563 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 21864021708 ps |
| CPU time | 61.36 seconds |
| Started | Feb 08 06:05:17 PM UTC 25 |
| Finished | Feb 08 06:06:20 PM UTC 25 |
| Peak memory | 227740 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=109080563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbde v_pkt_buffer.109080563 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_pkt_received.1306196445 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 167814604 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:05:18 PM UTC 25 |
| Finished | Feb 08 06:05:21 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1306196445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.us bdev_pkt_received.1306196445 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_pkt_sent.1053260073 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 230808206 ps |
| CPU time | 1.74 seconds |
| Started | Feb 08 06:05:18 PM UTC 25 |
| Finished | Feb 08 06:05:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1053260073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev _pkt_sent.1053260073 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_random_length_in_transaction.3262535974 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 228651385 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 06:05:18 PM UTC 25 |
| Finished | Feb 08 06:05:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3262535974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.u sbdev_random_length_in_transaction.3262535974 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_random_length_out_transaction.3804160232 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 186895588 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 06:05:20 PM UTC 25 |
| Finished | Feb 08 06:05:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3804160232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.usbdev_random_length_out_transaction.3804160232 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_resume_link_active.1812866188 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 20176565456 ps |
| CPU time | 31.88 seconds |
| Started | Feb 08 06:05:20 PM UTC 25 |
| Finished | Feb 08 06:05:53 PM UTC 25 |
| Peak memory | 217216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1812866188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_resume_link_active.1812866188 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_resume_link_active/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_rx_crc_err.3565378717 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 151468777 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 06:05:20 PM UTC 25 |
| Finished | Feb 08 06:05:22 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3565378717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbd ev_rx_crc_err.3565378717 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_rx_full.1956204229 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 338509470 ps |
| CPU time | 2.1 seconds |
| Started | Feb 08 06:05:20 PM UTC 25 |
| Finished | Feb 08 06:05:23 PM UTC 25 |
| Peak memory | 217176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1956204229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_ rx_full.1956204229 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_setup_stage.3289972713 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 148974778 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:05:20 PM UTC 25 |
| Finished | Feb 08 06:05:23 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3289972713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usb dev_setup_stage.3289972713 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_setup_trans_ignored.3637636141 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 149735982 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:05:20 PM UTC 25 |
| Finished | Feb 08 06:05:23 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3637636141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.usbdev_setup_trans_ignored.3637636141 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_smoke.322068631 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 241472303 ps |
| CPU time | 1.83 seconds |
| Started | Feb 08 06:05:22 PM UTC 25 |
| Finished | Feb 08 06:05:25 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=322068631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smo ke.322068631 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_spurious_pids_ignored.3445025065 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 3046412726 ps |
| CPU time | 85 seconds |
| Started | Feb 08 06:05:22 PM UTC 25 |
| Finished | Feb 08 06:06:49 PM UTC 25 |
| Peak memory | 229704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445025065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 13.usbdev_spurious_pids_ignored.3445025065 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_stall_priority_over_nak.784928557 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 164016501 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:05:22 PM UTC 25 |
| Finished | Feb 08 06:05:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=784928557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 13.usbdev_stall_priority_over_nak.784928557 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_stall_trans.2684240499 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 152972509 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:05:22 PM UTC 25 |
| Finished | Feb 08 06:05:24 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2684240499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usb dev_stall_trans.2684240499 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_stream_len_max.1851415029 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 1139804935 ps |
| CPU time | 3.7 seconds |
| Started | Feb 08 06:05:23 PM UTC 25 |
| Finished | Feb 08 06:05:28 PM UTC 25 |
| Peak memory | 217432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1851415029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13. usbdev_stream_len_max.1851415029 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_streaming_out.789137177 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 2154597885 ps |
| CPU time | 19.92 seconds |
| Started | Feb 08 06:05:23 PM UTC 25 |
| Finished | Feb 08 06:05:44 PM UTC 25 |
| Peak memory | 227700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=789137177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev _streaming_out.789137177 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_timeout_missing_host_handshake.3882544645 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 565704017 ps |
| CPU time | 12.27 seconds |
| Started | Feb 08 06:05:01 PM UTC 25 |
| Finished | Feb 08 06:05:15 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882544645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing_host_handshake.3882544645 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_tx_rx_disruption.2991181321 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 582242149 ps |
| CPU time | 2.49 seconds |
| Started | Feb 08 06:05:23 PM UTC 25 |
| Finished | Feb 08 06:05:27 PM UTC 25 |
| Peak memory | 217180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 991181321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_tx_rx_disruption.2991181321 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/13.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/130.usbdev_endpoint_types.411174900 |
| Short name | T3207 |
| Test name | |
| Test status | |
| Simulation time | 248252973 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 06:18:26 PM UTC 25 |
| Finished | Feb 08 06:18:29 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411174900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 130.usbdev_endpoint_types.411174900 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/130.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/130.usbdev_tx_rx_disruption.3650777086 |
| Short name | T3224 |
| Test name | |
| Test status | |
| Simulation time | 600687565 ps |
| CPU time | 1.81 seconds |
| Started | Feb 08 06:18:28 PM UTC 25 |
| Finished | Feb 08 06:18:31 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 650777086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.usbdev_tx_rx_disruption.3650777086 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/130.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/131.usbdev_endpoint_types.2075040712 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 410315941 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:18:28 PM UTC 25 |
| Finished | Feb 08 06:18:31 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075040712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 131.usbdev_endpoint_types.2075040712 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/131.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/131.usbdev_tx_rx_disruption.1245320397 |
| Short name | T3223 |
| Test name | |
| Test status | |
| Simulation time | 578008342 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:18:28 PM UTC 25 |
| Finished | Feb 08 06:18:31 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 245320397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.usbdev_tx_rx_disruption.1245320397 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/131.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/132.usbdev_endpoint_types.1084325262 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 483889996 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:18:28 PM UTC 25 |
| Finished | Feb 08 06:18:31 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084325262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 132.usbdev_endpoint_types.1084325262 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/132.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/132.usbdev_tx_rx_disruption.102540938 |
| Short name | T3221 |
| Test name | |
| Test status | |
| Simulation time | 534416816 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:18:28 PM UTC 25 |
| Finished | Feb 08 06:18:31 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 02540938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.usbdev_tx_rx_disruption.102540938 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/132.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/133.usbdev_endpoint_types.1937660235 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 625993242 ps |
| CPU time | 1.93 seconds |
| Started | Feb 08 06:18:28 PM UTC 25 |
| Finished | Feb 08 06:18:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937660235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 133.usbdev_endpoint_types.1937660235 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/133.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/133.usbdev_tx_rx_disruption.2457776207 |
| Short name | T3219 |
| Test name | |
| Test status | |
| Simulation time | 508303726 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:18:28 PM UTC 25 |
| Finished | Feb 08 06:18:31 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 457776207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.usbdev_tx_rx_disruption.2457776207 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/133.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/134.usbdev_endpoint_types.636397747 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 498560813 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:18:28 PM UTC 25 |
| Finished | Feb 08 06:18:31 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636397747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 134.usbdev_endpoint_types.636397747 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/134.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/134.usbdev_tx_rx_disruption.2974799421 |
| Short name | T3222 |
| Test name | |
| Test status | |
| Simulation time | 466717892 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:18:28 PM UTC 25 |
| Finished | Feb 08 06:18:31 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 974799421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.usbdev_tx_rx_disruption.2974799421 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/134.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/135.usbdev_endpoint_types.3613648580 |
| Short name | T3217 |
| Test name | |
| Test status | |
| Simulation time | 290109631 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 06:18:28 PM UTC 25 |
| Finished | Feb 08 06:18:31 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613648580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 135.usbdev_endpoint_types.3613648580 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/135.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/135.usbdev_tx_rx_disruption.488595858 |
| Short name | T3225 |
| Test name | |
| Test status | |
| Simulation time | 614899589 ps |
| CPU time | 1.81 seconds |
| Started | Feb 08 06:18:28 PM UTC 25 |
| Finished | Feb 08 06:18:32 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 88595858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.usbdev_tx_rx_disruption.488595858 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/135.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/136.usbdev_endpoint_types.1920770854 |
| Short name | T3218 |
| Test name | |
| Test status | |
| Simulation time | 341447832 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:18:28 PM UTC 25 |
| Finished | Feb 08 06:18:31 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920770854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 136.usbdev_endpoint_types.1920770854 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/136.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/136.usbdev_tx_rx_disruption.2658646491 |
| Short name | T3228 |
| Test name | |
| Test status | |
| Simulation time | 527649828 ps |
| CPU time | 1.91 seconds |
| Started | Feb 08 06:18:28 PM UTC 25 |
| Finished | Feb 08 06:18:32 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 658646491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.usbdev_tx_rx_disruption.2658646491 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/136.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/137.usbdev_tx_rx_disruption.2097250980 |
| Short name | T3226 |
| Test name | |
| Test status | |
| Simulation time | 599645585 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:18:28 PM UTC 25 |
| Finished | Feb 08 06:18:32 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 097250980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.usbdev_tx_rx_disruption.2097250980 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/137.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/138.usbdev_endpoint_types.1475274304 |
| Short name | T3220 |
| Test name | |
| Test status | |
| Simulation time | 228536848 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:18:28 PM UTC 25 |
| Finished | Feb 08 06:18:31 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475274304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 138.usbdev_endpoint_types.1475274304 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/138.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/138.usbdev_tx_rx_disruption.523494871 |
| Short name | T3229 |
| Test name | |
| Test status | |
| Simulation time | 645273016 ps |
| CPU time | 2.07 seconds |
| Started | Feb 08 06:18:28 PM UTC 25 |
| Finished | Feb 08 06:18:32 PM UTC 25 |
| Peak memory | 217376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 23494871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.usbdev_tx_rx_disruption.523494871 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/138.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/139.usbdev_tx_rx_disruption.4043597588 |
| Short name | T3240 |
| Test name | |
| Test status | |
| Simulation time | 549217408 ps |
| CPU time | 1.84 seconds |
| Started | Feb 08 06:18:30 PM UTC 25 |
| Finished | Feb 08 06:18:33 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 043597588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.usbdev_tx_rx_disruption.4043597588 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/139.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_alert_test.3816834899 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 39918426 ps |
| CPU time | 1.02 seconds |
| Started | Feb 08 06:05:54 PM UTC 25 |
| Finished | Feb 08 06:05:56 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816834899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 14.usbdev_alert_test.3816834899 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_aon_wake_disconnect.3432361125 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 4170416469 ps |
| CPU time | 7.49 seconds |
| Started | Feb 08 06:05:24 PM UTC 25 |
| Finished | Feb 08 06:05:33 PM UTC 25 |
| Peak memory | 227652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432361125 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.3432361125 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_aon_wake_reset.3652632915 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 20094159806 ps |
| CPU time | 41.35 seconds |
| Started | Feb 08 06:05:25 PM UTC 25 |
| Finished | Feb 08 06:06:07 PM UTC 25 |
| Peak memory | 217436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652632915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.3652632915 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_aon_wake_resume.531676329 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 25951155372 ps |
| CPU time | 38.35 seconds |
| Started | Feb 08 06:05:26 PM UTC 25 |
| Finished | Feb 08 06:06:06 PM UTC 25 |
| Peak memory | 227776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531676329 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.531676329 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_av_buffer.2947119817 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 158117049 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:05:26 PM UTC 25 |
| Finished | Feb 08 06:05:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2947119817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbde v_av_buffer.2947119817 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_bitstuff_err.328055620 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 154033344 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:05:26 PM UTC 25 |
| Finished | Feb 08 06:05:28 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=328055620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usb dev_bitstuff_err.328055620 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_data_toggle_clear.3174008443 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 253674613 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:05:26 PM UTC 25 |
| Finished | Feb 08 06:05:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3174008443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.3174008443 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_data_toggle_restore.3564759308 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 574359026 ps |
| CPU time | 3.08 seconds |
| Started | Feb 08 06:05:26 PM UTC 25 |
| Finished | Feb 08 06:05:30 PM UTC 25 |
| Peak memory | 217172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564759308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.3564759308 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_device_address.609771193 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 32283294386 ps |
| CPU time | 61.82 seconds |
| Started | Feb 08 06:05:27 PM UTC 25 |
| Finished | Feb 08 06:06:31 PM UTC 25 |
| Peak memory | 217484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=609771193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.u sbdev_device_address.609771193 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_device_timeout.535582454 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 202322691 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:05:27 PM UTC 25 |
| Finished | Feb 08 06:05:30 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535582454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.535582454 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_disable_endpoint.311100606 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 1187807516 ps |
| CPU time | 4.63 seconds |
| Started | Feb 08 06:05:27 PM UTC 25 |
| Finished | Feb 08 06:05:33 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=311100606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14 .usbdev_disable_endpoint.311100606 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_disconnected.1306023363 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 156770708 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:05:29 PM UTC 25 |
| Finished | Feb 08 06:05:32 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1306023363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.us bdev_disconnected.1306023363 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_enable.4233942055 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 39422496 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 06:05:29 PM UTC 25 |
| Finished | Feb 08 06:05:31 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4233942055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_e nable.4233942055 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_endpoint_access.4207515116 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 1126024827 ps |
| CPU time | 3.6 seconds |
| Started | Feb 08 06:05:29 PM UTC 25 |
| Finished | Feb 08 06:05:34 PM UTC 25 |
| Peak memory | 217572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4207515116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14 .usbdev_endpoint_access.4207515116 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_endpoint_types.2066719166 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 184473373 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:05:29 PM UTC 25 |
| Finished | Feb 08 06:05:32 PM UTC 25 |
| Peak memory | 215040 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066719166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 14.usbdev_endpoint_types.2066719166 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_fifo_rst.2202246825 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 170373599 ps |
| CPU time | 2.2 seconds |
| Started | Feb 08 06:05:29 PM UTC 25 |
| Finished | Feb 08 06:05:32 PM UTC 25 |
| Peak memory | 217284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2202246825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev _fifo_rst.2202246825 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_in_iso.3142019771 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 229542203 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:05:31 PM UTC 25 |
| Finished | Feb 08 06:05:34 PM UTC 25 |
| Peak memory | 233756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142019771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 14.usbdev_in_iso.3142019771 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_in_stall.1486196150 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 152969336 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:05:32 PM UTC 25 |
| Finished | Feb 08 06:05:35 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1486196150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev _in_stall.1486196150 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_in_trans.4123034053 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 250378238 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:05:32 PM UTC 25 |
| Finished | Feb 08 06:05:35 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4123034053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev _in_trans.4123034053 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_invalid_sync.876501945 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 2926873162 ps |
| CPU time | 27.27 seconds |
| Started | Feb 08 06:05:31 PM UTC 25 |
| Finished | Feb 08 06:06:00 PM UTC 25 |
| Peak memory | 227852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876501945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.876501945 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_iso_retraction.1773552664 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 10933618283 ps |
| CPU time | 79.33 seconds |
| Started | Feb 08 06:05:33 PM UTC 25 |
| Finished | Feb 08 06:06:54 PM UTC 25 |
| Peak memory | 217548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773552664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 14.usbdev_iso_retraction.1773552664 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_link_in_err.179019783 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 188244059 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:05:34 PM UTC 25 |
| Finished | Feb 08 06:05:37 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=179019783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbd ev_link_in_err.179019783 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_link_resume.1865905314 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 13033175045 ps |
| CPU time | 29.38 seconds |
| Started | Feb 08 06:05:34 PM UTC 25 |
| Finished | Feb 08 06:06:05 PM UTC 25 |
| Peak memory | 217456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1865905314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usb dev_link_resume.1865905314 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_link_suspend.525749187 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 10336063392 ps |
| CPU time | 28.05 seconds |
| Started | Feb 08 06:05:34 PM UTC 25 |
| Finished | Feb 08 06:06:03 PM UTC 25 |
| Peak memory | 217456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=525749187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usb dev_link_suspend.525749187 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_low_speed_traffic.3909462140 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 4584628317 ps |
| CPU time | 138.48 seconds |
| Started | Feb 08 06:05:34 PM UTC 25 |
| Finished | Feb 08 06:07:55 PM UTC 25 |
| Peak memory | 234388 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909462140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 14.usbdev_low_speed_traffic.3909462140 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_max_inter_pkt_delay.1399097326 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 2962592324 ps |
| CPU time | 25.4 seconds |
| Started | Feb 08 06:05:36 PM UTC 25 |
| Finished | Feb 08 06:06:03 PM UTC 25 |
| Peak memory | 227468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399097326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.1399097326 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_max_length_in_transaction.187084539 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 241687855 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:05:36 PM UTC 25 |
| Finished | Feb 08 06:05:38 PM UTC 25 |
| Peak memory | 214904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187084539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 14.usbdev_max_length_in_transaction.187084539 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_max_length_out_transaction.1906867796 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 191823891 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:05:36 PM UTC 25 |
| Finished | Feb 08 06:05:38 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1906867796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1906867796 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_max_non_iso_usb_traffic.3308354266 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 3636111302 ps |
| CPU time | 37.07 seconds |
| Started | Feb 08 06:05:36 PM UTC 25 |
| Finished | Feb 08 06:06:15 PM UTC 25 |
| Peak memory | 234372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3308354266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 14.usbdev_max_non_iso_usb_traffic.3308354266 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_max_usb_traffic.3891967121 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 3098961606 ps |
| CPU time | 29.42 seconds |
| Started | Feb 08 06:05:36 PM UTC 25 |
| Finished | Feb 08 06:06:07 PM UTC 25 |
| Peak memory | 234364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891967121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_ traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 14.usbdev_max_usb_traffic.3891967121 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_min_inter_pkt_delay.1689736770 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 2354945910 ps |
| CPU time | 20.42 seconds |
| Started | Feb 08 06:05:37 PM UTC 25 |
| Finished | Feb 08 06:05:59 PM UTC 25 |
| Peak memory | 229712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689736770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.1689736770 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_min_length_in_transaction.2031755459 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 226793173 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:05:37 PM UTC 25 |
| Finished | Feb 08 06:05:40 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031755459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 14.usbdev_min_length_in_transaction.2031755459 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_min_length_out_transaction.709345857 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 160526573 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:05:37 PM UTC 25 |
| Finished | Feb 08 06:05:40 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=709345857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 14.usbdev_min_length_out_transaction.709345857 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_nak_trans.1311948646 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 219543410 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:05:40 PM UTC 25 |
| Finished | Feb 08 06:05:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1311948646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbde v_nak_trans.1311948646 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_out_iso.2341541384 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 227303997 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:05:40 PM UTC 25 |
| Finished | Feb 08 06:05:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2341541384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_ out_iso.2341541384 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_out_stall.2011094133 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 214313280 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:05:41 PM UTC 25 |
| Finished | Feb 08 06:05:44 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2011094133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbde v_out_stall.2011094133 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_out_trans_nak.2079971464 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 161533779 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:05:41 PM UTC 25 |
| Finished | Feb 08 06:05:43 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2079971464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.u sbdev_out_trans_nak.2079971464 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_pending_in_trans.1657199905 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 153030248 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 06:05:43 PM UTC 25 |
| Finished | Feb 08 06:05:46 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1657199905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.usbdev_pending_in_trans.1657199905 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_phy_config_pinflip.3097088323 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 217328352 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 06:05:43 PM UTC 25 |
| Finished | Feb 08 06:05:46 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097088323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 14.usbdev_phy_config_pinflip.3097088323 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_phy_config_usb_ref_disable.3501843400 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 147147506 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:05:44 PM UTC 25 |
| Finished | Feb 08 06:05:47 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3501843400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.3501843400 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_phy_pins_sense.1642072754 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 47692829 ps |
| CPU time | 0.94 seconds |
| Started | Feb 08 06:05:44 PM UTC 25 |
| Finished | Feb 08 06:05:46 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1642072754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14. usbdev_phy_pins_sense.1642072754 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_pkt_buffer.42111455 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 20728804883 ps |
| CPU time | 79.4 seconds |
| Started | Feb 08 06:05:44 PM UTC 25 |
| Finished | Feb 08 06:07:06 PM UTC 25 |
| Peak memory | 227800 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=42111455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev _pkt_buffer.42111455 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_pkt_received.405760423 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 180602840 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:05:46 PM UTC 25 |
| Finished | Feb 08 06:05:49 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=405760423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usb dev_pkt_received.405760423 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_pkt_sent.4155709862 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 186066775 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:05:46 PM UTC 25 |
| Finished | Feb 08 06:05:48 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4155709862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev _pkt_sent.4155709862 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_random_length_in_transaction.72752636 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 257093212 ps |
| CPU time | 1.79 seconds |
| Started | Feb 08 06:05:46 PM UTC 25 |
| Finished | Feb 08 06:05:49 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=72752636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usb dev_random_length_in_transaction.72752636 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_random_length_out_transaction.227443670 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 169603908 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:05:48 PM UTC 25 |
| Finished | Feb 08 06:05:50 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=227443670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 14.usbdev_random_length_out_transaction.227443670 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_resume_link_active.2961384370 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 20144359676 ps |
| CPU time | 30.26 seconds |
| Started | Feb 08 06:05:48 PM UTC 25 |
| Finished | Feb 08 06:06:19 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2961384370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_resume_link_active.2961384370 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_resume_link_active/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_rx_crc_err.323222378 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 144725262 ps |
| CPU time | 1.12 seconds |
| Started | Feb 08 06:05:48 PM UTC 25 |
| Finished | Feb 08 06:05:50 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=323222378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbde v_rx_crc_err.323222378 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_rx_full.2229657534 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 333633010 ps |
| CPU time | 2.07 seconds |
| Started | Feb 08 06:05:48 PM UTC 25 |
| Finished | Feb 08 06:05:51 PM UTC 25 |
| Peak memory | 217176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2229657534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_ rx_full.2229657534 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_setup_stage.4118901608 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 150854184 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:05:48 PM UTC 25 |
| Finished | Feb 08 06:05:50 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4118901608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usb dev_setup_stage.4118901608 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_setup_trans_ignored.2769673361 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 162339082 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:05:50 PM UTC 25 |
| Finished | Feb 08 06:05:53 PM UTC 25 |
| Peak memory | 217260 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2769673361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.usbdev_setup_trans_ignored.2769673361 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_smoke.749005756 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 245371940 ps |
| CPU time | 1.86 seconds |
| Started | Feb 08 06:05:50 PM UTC 25 |
| Finished | Feb 08 06:05:53 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=749005756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smo ke.749005756 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_spurious_pids_ignored.1756280687 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 2255064172 ps |
| CPU time | 72.9 seconds |
| Started | Feb 08 06:05:50 PM UTC 25 |
| Finished | Feb 08 06:07:05 PM UTC 25 |
| Peak memory | 229760 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756280687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 14.usbdev_spurious_pids_ignored.1756280687 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_stall_priority_over_nak.2407870241 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 222150672 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:05:50 PM UTC 25 |
| Finished | Feb 08 06:05:53 PM UTC 25 |
| Peak memory | 214936 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2407870241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 14.usbdev_stall_priority_over_nak.2407870241 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_stall_trans.588918788 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 206649224 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:05:50 PM UTC 25 |
| Finished | Feb 08 06:05:53 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=588918788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbd ev_stall_trans.588918788 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_stream_len_max.2046801787 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 1116544860 ps |
| CPU time | 5.19 seconds |
| Started | Feb 08 06:05:52 PM UTC 25 |
| Finished | Feb 08 06:05:58 PM UTC 25 |
| Peak memory | 217432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2046801787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14. usbdev_stream_len_max.2046801787 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_streaming_out.231642626 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 2701542963 ps |
| CPU time | 23.7 seconds |
| Started | Feb 08 06:05:52 PM UTC 25 |
| Finished | Feb 08 06:06:17 PM UTC 25 |
| Peak memory | 229948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=231642626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev _streaming_out.231642626 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_timeout_missing_host_handshake.2131507451 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 3609464854 ps |
| CPU time | 23.99 seconds |
| Started | Feb 08 06:05:27 PM UTC 25 |
| Finished | Feb 08 06:05:53 PM UTC 25 |
| Peak memory | 217404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131507451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing_host_handshake.2131507451 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/14.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/140.usbdev_endpoint_types.1094972102 |
| Short name | T3195 |
| Test name | |
| Test status | |
| Simulation time | 243978835 ps |
| CPU time | 0.97 seconds |
| Started | Feb 08 06:18:30 PM UTC 25 |
| Finished | Feb 08 06:18:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094972102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 140.usbdev_endpoint_types.1094972102 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/140.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/140.usbdev_tx_rx_disruption.1409773644 |
| Short name | T3237 |
| Test name | |
| Test status | |
| Simulation time | 591001875 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:18:30 PM UTC 25 |
| Finished | Feb 08 06:18:33 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 409773644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.usbdev_tx_rx_disruption.1409773644 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/140.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/141.usbdev_endpoint_types.2514744805 |
| Short name | T3230 |
| Test name | |
| Test status | |
| Simulation time | 222741493 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 06:18:30 PM UTC 25 |
| Finished | Feb 08 06:18:33 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514744805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 141.usbdev_endpoint_types.2514744805 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/141.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/141.usbdev_tx_rx_disruption.4065240160 |
| Short name | T3238 |
| Test name | |
| Test status | |
| Simulation time | 488875247 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:18:30 PM UTC 25 |
| Finished | Feb 08 06:18:33 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 065240160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.usbdev_tx_rx_disruption.4065240160 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/141.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/142.usbdev_tx_rx_disruption.1630907389 |
| Short name | T3245 |
| Test name | |
| Test status | |
| Simulation time | 630685667 ps |
| CPU time | 1.9 seconds |
| Started | Feb 08 06:18:30 PM UTC 25 |
| Finished | Feb 08 06:18:34 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 630907389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.usbdev_tx_rx_disruption.1630907389 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/142.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/143.usbdev_endpoint_types.467278925 |
| Short name | T3239 |
| Test name | |
| Test status | |
| Simulation time | 461944345 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:18:30 PM UTC 25 |
| Finished | Feb 08 06:18:33 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467278925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 143.usbdev_endpoint_types.467278925 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/143.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/143.usbdev_tx_rx_disruption.979141708 |
| Short name | T3242 |
| Test name | |
| Test status | |
| Simulation time | 580911216 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:18:30 PM UTC 25 |
| Finished | Feb 08 06:18:33 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 79141708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.usbdev_tx_rx_disruption.979141708 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/143.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/144.usbdev_endpoint_types.2648751969 |
| Short name | T3235 |
| Test name | |
| Test status | |
| Simulation time | 324754891 ps |
| CPU time | 1.12 seconds |
| Started | Feb 08 06:18:30 PM UTC 25 |
| Finished | Feb 08 06:18:33 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648751969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 144.usbdev_endpoint_types.2648751969 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/144.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/144.usbdev_tx_rx_disruption.1126180146 |
| Short name | T3244 |
| Test name | |
| Test status | |
| Simulation time | 411216721 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:18:30 PM UTC 25 |
| Finished | Feb 08 06:18:33 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 126180146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.usbdev_tx_rx_disruption.1126180146 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/144.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/145.usbdev_endpoint_types.620476965 |
| Short name | T3236 |
| Test name | |
| Test status | |
| Simulation time | 337322168 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 06:18:30 PM UTC 25 |
| Finished | Feb 08 06:18:33 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620476965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 145.usbdev_endpoint_types.620476965 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/145.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/145.usbdev_tx_rx_disruption.1162766028 |
| Short name | T3246 |
| Test name | |
| Test status | |
| Simulation time | 505436907 ps |
| CPU time | 1.67 seconds |
| Started | Feb 08 06:18:30 PM UTC 25 |
| Finished | Feb 08 06:18:34 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 162766028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.usbdev_tx_rx_disruption.1162766028 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/145.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/146.usbdev_endpoint_types.3710125942 |
| Short name | T3233 |
| Test name | |
| Test status | |
| Simulation time | 163075412 ps |
| CPU time | 0.87 seconds |
| Started | Feb 08 06:18:30 PM UTC 25 |
| Finished | Feb 08 06:18:33 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710125942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 146.usbdev_endpoint_types.3710125942 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/146.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/146.usbdev_tx_rx_disruption.558698650 |
| Short name | T3243 |
| Test name | |
| Test status | |
| Simulation time | 519093169 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:18:30 PM UTC 25 |
| Finished | Feb 08 06:18:33 PM UTC 25 |
| Peak memory | 215168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 58698650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.usbdev_tx_rx_disruption.558698650 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/146.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/147.usbdev_tx_rx_disruption.1053146859 |
| Short name | T3247 |
| Test name | |
| Test status | |
| Simulation time | 562158947 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:18:31 PM UTC 25 |
| Finished | Feb 08 06:18:34 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 053146859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.usbdev_tx_rx_disruption.1053146859 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/147.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/148.usbdev_endpoint_types.116252564 |
| Short name | T3241 |
| Test name | |
| Test status | |
| Simulation time | 410803469 ps |
| CPU time | 1.23 seconds |
| Started | Feb 08 06:18:31 PM UTC 25 |
| Finished | Feb 08 06:18:33 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116252564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 148.usbdev_endpoint_types.116252564 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/148.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/148.usbdev_tx_rx_disruption.1029090644 |
| Short name | T3248 |
| Test name | |
| Test status | |
| Simulation time | 516547693 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:18:31 PM UTC 25 |
| Finished | Feb 08 06:18:34 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 029090644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.usbdev_tx_rx_disruption.1029090644 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/148.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/149.usbdev_endpoint_types.4118491298 |
| Short name | T3253 |
| Test name | |
| Test status | |
| Simulation time | 569484444 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:18:32 PM UTC 25 |
| Finished | Feb 08 06:18:35 PM UTC 25 |
| Peak memory | 215080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118491298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 149.usbdev_endpoint_types.4118491298 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/149.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/149.usbdev_tx_rx_disruption.3926937590 |
| Short name | T3254 |
| Test name | |
| Test status | |
| Simulation time | 623110813 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:18:32 PM UTC 25 |
| Finished | Feb 08 06:18:35 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 926937590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.usbdev_tx_rx_disruption.3926937590 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/149.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_alert_test.457335125 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 90663551 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:06:22 PM UTC 25 |
| Finished | Feb 08 06:06:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457335125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 15.usbdev_alert_test.457335125 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_aon_wake_disconnect.1511157049 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 6131544015 ps |
| CPU time | 9.95 seconds |
| Started | Feb 08 06:05:54 PM UTC 25 |
| Finished | Feb 08 06:06:05 PM UTC 25 |
| Peak memory | 227652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511157049 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.1511157049 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_aon_wake_reset.34351728 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 13982928524 ps |
| CPU time | 21.68 seconds |
| Started | Feb 08 06:05:54 PM UTC 25 |
| Finished | Feb 08 06:06:17 PM UTC 25 |
| Peak memory | 227652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34351728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TES T_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.34351728 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_aon_wake_resume.324646096 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 30232974016 ps |
| CPU time | 42 seconds |
| Started | Feb 08 06:05:54 PM UTC 25 |
| Finished | Feb 08 06:06:38 PM UTC 25 |
| Peak memory | 217380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324646096 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.324646096 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_av_buffer.1023572880 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 176676405 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:05:54 PM UTC 25 |
| Finished | Feb 08 06:05:57 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1023572880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbde v_av_buffer.1023572880 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_bitstuff_err.3864046124 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 160560905 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:05:54 PM UTC 25 |
| Finished | Feb 08 06:05:57 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3864046124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.us bdev_bitstuff_err.3864046124 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_data_toggle_clear.2807846914 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 269722453 ps |
| CPU time | 1.88 seconds |
| Started | Feb 08 06:05:54 PM UTC 25 |
| Finished | Feb 08 06:05:57 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2807846914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.2807846914 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_data_toggle_restore.3405042661 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 611078627 ps |
| CPU time | 2.47 seconds |
| Started | Feb 08 06:05:57 PM UTC 25 |
| Finished | Feb 08 06:06:00 PM UTC 25 |
| Peak memory | 217172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405042661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.3405042661 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_device_address.308537940 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 19959057436 ps |
| CPU time | 35.61 seconds |
| Started | Feb 08 06:05:58 PM UTC 25 |
| Finished | Feb 08 06:06:35 PM UTC 25 |
| Peak memory | 217464 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=308537940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.u sbdev_device_address.308537940 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_device_timeout.4206413240 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 1923718750 ps |
| CPU time | 45.68 seconds |
| Started | Feb 08 06:05:58 PM UTC 25 |
| Finished | Feb 08 06:06:45 PM UTC 25 |
| Peak memory | 217404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206413240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.4206413240 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_disable_endpoint.84389948 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 636820560 ps |
| CPU time | 2.3 seconds |
| Started | Feb 08 06:05:58 PM UTC 25 |
| Finished | Feb 08 06:06:01 PM UTC 25 |
| Peak memory | 217148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=84389948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15. usbdev_disable_endpoint.84389948 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_disconnected.1912568816 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 183979522 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:05:59 PM UTC 25 |
| Finished | Feb 08 06:06:01 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1912568816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.us bdev_disconnected.1912568816 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_enable.2522585187 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 54832807 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:06:00 PM UTC 25 |
| Finished | Feb 08 06:06:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2522585187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_e nable.2522585187 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_endpoint_access.1774923085 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 808009556 ps |
| CPU time | 3.67 seconds |
| Started | Feb 08 06:06:01 PM UTC 25 |
| Finished | Feb 08 06:06:05 PM UTC 25 |
| Peak memory | 217324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1774923085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15 .usbdev_endpoint_access.1774923085 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_endpoint_types.801031534 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 189022623 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:06:01 PM UTC 25 |
| Finished | Feb 08 06:06:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801031534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 15.usbdev_endpoint_types.801031534 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_fifo_rst.3382019522 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 195526097 ps |
| CPU time | 3.15 seconds |
| Started | Feb 08 06:06:03 PM UTC 25 |
| Finished | Feb 08 06:06:07 PM UTC 25 |
| Peak memory | 217280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3382019522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev _fifo_rst.3382019522 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_in_iso.693068767 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 270068321 ps |
| CPU time | 1.67 seconds |
| Started | Feb 08 06:06:04 PM UTC 25 |
| Finished | Feb 08 06:06:07 PM UTC 25 |
| Peak memory | 227288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693068767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 15.usbdev_in_iso.693068767 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_in_stall.4126316995 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 147696420 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:06:04 PM UTC 25 |
| Finished | Feb 08 06:06:07 PM UTC 25 |
| Peak memory | 214740 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4126316995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev _in_stall.4126316995 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_in_trans.3155880399 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 217503917 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:06:04 PM UTC 25 |
| Finished | Feb 08 06:06:07 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3155880399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev _in_trans.3155880399 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_invalid_sync.1029519648 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 4462282700 ps |
| CPU time | 123.97 seconds |
| Started | Feb 08 06:06:03 PM UTC 25 |
| Finished | Feb 08 06:08:09 PM UTC 25 |
| Peak memory | 234348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029519648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.1029519648 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_iso_retraction.1684334544 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 6217334734 ps |
| CPU time | 73.74 seconds |
| Started | Feb 08 06:06:04 PM UTC 25 |
| Finished | Feb 08 06:07:20 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684334544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 15.usbdev_iso_retraction.1684334544 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_link_in_err.2324053857 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 176279021 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:06:05 PM UTC 25 |
| Finished | Feb 08 06:06:08 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2324053857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usb dev_link_in_err.2324053857 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_link_resume.3956890290 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 23466376651 ps |
| CPU time | 43.98 seconds |
| Started | Feb 08 06:06:07 PM UTC 25 |
| Finished | Feb 08 06:06:52 PM UTC 25 |
| Peak memory | 217416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3956890290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usb dev_link_resume.3956890290 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_link_suspend.3356817986 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 5930382665 ps |
| CPU time | 12.88 seconds |
| Started | Feb 08 06:06:07 PM UTC 25 |
| Finished | Feb 08 06:06:21 PM UTC 25 |
| Peak memory | 227784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3356817986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.us bdev_link_suspend.3356817986 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_low_speed_traffic.3734314815 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 4903701513 ps |
| CPU time | 40.12 seconds |
| Started | Feb 08 06:06:07 PM UTC 25 |
| Finished | Feb 08 06:06:48 PM UTC 25 |
| Peak memory | 229944 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734314815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 15.usbdev_low_speed_traffic.3734314815 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_max_inter_pkt_delay.102837151 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 1497468598 ps |
| CPU time | 14.48 seconds |
| Started | Feb 08 06:06:08 PM UTC 25 |
| Finished | Feb 08 06:06:24 PM UTC 25 |
| Peak memory | 229876 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102837151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.102837151 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_max_length_in_transaction.1310095357 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 240013578 ps |
| CPU time | 1.96 seconds |
| Started | Feb 08 06:06:08 PM UTC 25 |
| Finished | Feb 08 06:06:11 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310095357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 15.usbdev_max_length_in_transaction.1310095357 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_max_length_out_transaction.46420246 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 195570424 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:06:08 PM UTC 25 |
| Finished | Feb 08 06:06:11 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=46420246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 15.usbdev_max_length_out_transaction.46420246 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_max_non_iso_usb_traffic.2686586087 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 1903529332 ps |
| CPU time | 23.46 seconds |
| Started | Feb 08 06:06:08 PM UTC 25 |
| Finished | Feb 08 06:06:33 PM UTC 25 |
| Peak memory | 227536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2686586087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 15.usbdev_max_non_iso_usb_traffic.2686586087 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_min_inter_pkt_delay.825457467 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 1724518705 ps |
| CPU time | 16.12 seconds |
| Started | Feb 08 06:06:08 PM UTC 25 |
| Finished | Feb 08 06:06:26 PM UTC 25 |
| Peak memory | 234300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825457467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usb dev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.825457467 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_min_length_in_transaction.1500141811 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 158522126 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:06:08 PM UTC 25 |
| Finished | Feb 08 06:06:11 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500141811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.usbdev_min_length_in_transaction.1500141811 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_min_length_out_transaction.1486135943 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 157015739 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:06:08 PM UTC 25 |
| Finished | Feb 08 06:06:11 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1486135943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.1486135943 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_nak_trans.2040672866 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 217530725 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 06:06:10 PM UTC 25 |
| Finished | Feb 08 06:06:13 PM UTC 25 |
| Peak memory | 214856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2040672866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbde v_nak_trans.2040672866 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_out_iso.4063019315 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 153070042 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:06:10 PM UTC 25 |
| Finished | Feb 08 06:06:13 PM UTC 25 |
| Peak memory | 214864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4063019315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_ out_iso.4063019315 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_out_stall.415903902 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 163571797 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:06:12 PM UTC 25 |
| Finished | Feb 08 06:06:14 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=415903902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev _out_stall.415903902 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_out_trans_nak.645344218 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 174110379 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:06:12 PM UTC 25 |
| Finished | Feb 08 06:06:14 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=645344218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.us bdev_out_trans_nak.645344218 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_pending_in_trans.2705694616 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 169991390 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:06:12 PM UTC 25 |
| Finished | Feb 08 06:06:14 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2705694616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.usbdev_pending_in_trans.2705694616 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_phy_config_pinflip.3039387124 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 252794058 ps |
| CPU time | 1.83 seconds |
| Started | Feb 08 06:06:13 PM UTC 25 |
| Finished | Feb 08 06:06:16 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039387124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 15.usbdev_phy_config_pinflip.3039387124 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_phy_config_usb_ref_disable.1341921604 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 146331823 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:06:14 PM UTC 25 |
| Finished | Feb 08 06:06:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1341921604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.1341921604 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_phy_pins_sense.2565377634 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 46311221 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 06:06:14 PM UTC 25 |
| Finished | Feb 08 06:06:16 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2565377634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15. usbdev_phy_pins_sense.2565377634 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_pkt_buffer.520604949 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 23590005229 ps |
| CPU time | 66.99 seconds |
| Started | Feb 08 06:06:16 PM UTC 25 |
| Finished | Feb 08 06:07:24 PM UTC 25 |
| Peak memory | 227404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=520604949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbde v_pkt_buffer.520604949 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_pkt_received.1772315727 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 194317696 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:06:16 PM UTC 25 |
| Finished | Feb 08 06:06:18 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1772315727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.us bdev_pkt_received.1772315727 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_pkt_sent.3146715015 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 214028679 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:06:16 PM UTC 25 |
| Finished | Feb 08 06:06:18 PM UTC 25 |
| Peak memory | 214888 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3146715015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev _pkt_sent.3146715015 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_random_length_in_transaction.55322712 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 185667922 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:06:16 PM UTC 25 |
| Finished | Feb 08 06:06:18 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=55322712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usb dev_random_length_in_transaction.55322712 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_random_length_out_transaction.844983133 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 183534166 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:06:17 PM UTC 25 |
| Finished | Feb 08 06:06:20 PM UTC 25 |
| Peak memory | 214968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=844983133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 15.usbdev_random_length_out_transaction.844983133 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_resume_link_active.3090204189 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 20209582123 ps |
| CPU time | 31.7 seconds |
| Started | Feb 08 06:06:17 PM UTC 25 |
| Finished | Feb 08 06:06:50 PM UTC 25 |
| Peak memory | 216980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3090204189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_resume_link_active.3090204189 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_resume_link_active/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_rx_crc_err.1984333064 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 192543096 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:06:17 PM UTC 25 |
| Finished | Feb 08 06:06:19 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1984333064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbd ev_rx_crc_err.1984333064 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_setup_stage.4168189842 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 231937224 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 06:06:18 PM UTC 25 |
| Finished | Feb 08 06:06:21 PM UTC 25 |
| Peak memory | 215064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4168189842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usb dev_setup_stage.4168189842 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_setup_trans_ignored.169275238 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 156787267 ps |
| CPU time | 1.21 seconds |
| Started | Feb 08 06:06:18 PM UTC 25 |
| Finished | Feb 08 06:06:21 PM UTC 25 |
| Peak memory | 215040 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=169275238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.169275238 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_smoke.887946443 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 200006586 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:06:20 PM UTC 25 |
| Finished | Feb 08 06:06:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=887946443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smo ke.887946443 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_spurious_pids_ignored.4045970461 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 3297200627 ps |
| CPU time | 23.53 seconds |
| Started | Feb 08 06:06:20 PM UTC 25 |
| Finished | Feb 08 06:06:45 PM UTC 25 |
| Peak memory | 234432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045970461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 15.usbdev_spurious_pids_ignored.4045970461 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_stall_priority_over_nak.367667830 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 186587058 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 06:06:20 PM UTC 25 |
| Finished | Feb 08 06:06:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=367667830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 15.usbdev_stall_priority_over_nak.367667830 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_stall_trans.1578528369 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 184173129 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:06:22 PM UTC 25 |
| Finished | Feb 08 06:06:25 PM UTC 25 |
| Peak memory | 214808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1578528369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usb dev_stall_trans.1578528369 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_stream_len_max.1932997811 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 571142205 ps |
| CPU time | 1.98 seconds |
| Started | Feb 08 06:06:22 PM UTC 25 |
| Finished | Feb 08 06:06:25 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1932997811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15. usbdev_stream_len_max.1932997811 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_streaming_out.1550599332 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 2041469730 ps |
| CPU time | 64.17 seconds |
| Started | Feb 08 06:06:22 PM UTC 25 |
| Finished | Feb 08 06:07:28 PM UTC 25 |
| Peak memory | 227376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1550599332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbde v_streaming_out.1550599332 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_timeout_missing_host_handshake.2369104957 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 2107280985 ps |
| CPU time | 20.31 seconds |
| Started | Feb 08 06:05:58 PM UTC 25 |
| Finished | Feb 08 06:06:20 PM UTC 25 |
| Peak memory | 217472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369104957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_host_handshake.2369104957 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_tx_rx_disruption.825893411 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 543680802 ps |
| CPU time | 2.93 seconds |
| Started | Feb 08 06:06:22 PM UTC 25 |
| Finished | Feb 08 06:06:26 PM UTC 25 |
| Peak memory | 217084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 25893411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_tx_rx_disruption.825893411 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/15.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/150.usbdev_endpoint_types.1487403989 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 417283639 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 06:18:32 PM UTC 25 |
| Finished | Feb 08 06:18:35 PM UTC 25 |
| Peak memory | 215080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487403989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 150.usbdev_endpoint_types.1487403989 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/150.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/150.usbdev_tx_rx_disruption.557967948 |
| Short name | T3255 |
| Test name | |
| Test status | |
| Simulation time | 563675717 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:18:32 PM UTC 25 |
| Finished | Feb 08 06:18:35 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 57967948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.usbdev_tx_rx_disruption.557967948 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/150.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/151.usbdev_endpoint_types.3895407573 |
| Short name | T3250 |
| Test name | |
| Test status | |
| Simulation time | 207229028 ps |
| CPU time | 0.92 seconds |
| Started | Feb 08 06:18:32 PM UTC 25 |
| Finished | Feb 08 06:18:34 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895407573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 151.usbdev_endpoint_types.3895407573 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/151.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/151.usbdev_tx_rx_disruption.489936991 |
| Short name | T3252 |
| Test name | |
| Test status | |
| Simulation time | 420836647 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:18:32 PM UTC 25 |
| Finished | Feb 08 06:18:35 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 89936991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.usbdev_tx_rx_disruption.489936991 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/151.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/152.usbdev_endpoint_types.3075096355 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 508332639 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:18:32 PM UTC 25 |
| Finished | Feb 08 06:18:35 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075096355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 152.usbdev_endpoint_types.3075096355 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/152.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/152.usbdev_tx_rx_disruption.973302240 |
| Short name | T3258 |
| Test name | |
| Test status | |
| Simulation time | 520242598 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:18:32 PM UTC 25 |
| Finished | Feb 08 06:18:35 PM UTC 25 |
| Peak memory | 215168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 73302240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.usbdev_tx_rx_disruption.973302240 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/152.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/153.usbdev_endpoint_types.1812630175 |
| Short name | T3251 |
| Test name | |
| Test status | |
| Simulation time | 251888073 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 06:18:32 PM UTC 25 |
| Finished | Feb 08 06:18:35 PM UTC 25 |
| Peak memory | 215092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812630175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 153.usbdev_endpoint_types.1812630175 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/153.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/153.usbdev_tx_rx_disruption.1937423761 |
| Short name | T3256 |
| Test name | |
| Test status | |
| Simulation time | 486565287 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:18:32 PM UTC 25 |
| Finished | Feb 08 06:18:35 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 937423761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.usbdev_tx_rx_disruption.1937423761 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/153.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/154.usbdev_tx_rx_disruption.1767522214 |
| Short name | T3259 |
| Test name | |
| Test status | |
| Simulation time | 602197415 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:18:32 PM UTC 25 |
| Finished | Feb 08 06:18:35 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 767522214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.usbdev_tx_rx_disruption.1767522214 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/154.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/155.usbdev_endpoint_types.4107887661 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 220434343 ps |
| CPU time | 0.95 seconds |
| Started | Feb 08 06:18:34 PM UTC 25 |
| Finished | Feb 08 06:18:38 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107887661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 155.usbdev_endpoint_types.4107887661 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/155.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/155.usbdev_tx_rx_disruption.3855277189 |
| Short name | T3267 |
| Test name | |
| Test status | |
| Simulation time | 613997291 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:18:34 PM UTC 25 |
| Finished | Feb 08 06:18:38 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 855277189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.usbdev_tx_rx_disruption.3855277189 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/155.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/156.usbdev_endpoint_types.2467962233 |
| Short name | T3263 |
| Test name | |
| Test status | |
| Simulation time | 379026616 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:18:34 PM UTC 25 |
| Finished | Feb 08 06:18:38 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467962233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 156.usbdev_endpoint_types.2467962233 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/156.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/156.usbdev_tx_rx_disruption.1280542645 |
| Short name | T3269 |
| Test name | |
| Test status | |
| Simulation time | 537745180 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:18:34 PM UTC 25 |
| Finished | Feb 08 06:18:38 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 280542645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.usbdev_tx_rx_disruption.1280542645 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/156.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/157.usbdev_tx_rx_disruption.1416377989 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 481997965 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:18:34 PM UTC 25 |
| Finished | Feb 08 06:18:38 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 416377989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.usbdev_tx_rx_disruption.1416377989 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/157.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/158.usbdev_endpoint_types.824357393 |
| Short name | T3264 |
| Test name | |
| Test status | |
| Simulation time | 226239615 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 06:18:34 PM UTC 25 |
| Finished | Feb 08 06:18:38 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824357393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 158.usbdev_endpoint_types.824357393 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/158.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/158.usbdev_tx_rx_disruption.556170978 |
| Short name | T3270 |
| Test name | |
| Test status | |
| Simulation time | 456634835 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:39 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 56170978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.usbdev_tx_rx_disruption.556170978 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/158.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/159.usbdev_endpoint_types.649776671 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 351535104 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:38 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649776671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 159.usbdev_endpoint_types.649776671 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/159.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/159.usbdev_tx_rx_disruption.2549310963 |
| Short name | T3273 |
| Test name | |
| Test status | |
| Simulation time | 628662170 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:39 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 549310963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.usbdev_tx_rx_disruption.2549310963 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/159.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_alert_test.2110130669 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 29269851 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 06:06:47 PM UTC 25 |
| Finished | Feb 08 06:06:50 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110130669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 16.usbdev_alert_test.2110130669 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_aon_wake_disconnect.1955189217 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 6364499180 ps |
| CPU time | 10.51 seconds |
| Started | Feb 08 06:06:22 PM UTC 25 |
| Finished | Feb 08 06:06:34 PM UTC 25 |
| Peak memory | 227588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955189217 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.1955189217 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_aon_wake_reset.2442670052 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 20863571038 ps |
| CPU time | 41.52 seconds |
| Started | Feb 08 06:06:22 PM UTC 25 |
| Finished | Feb 08 06:07:05 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442670052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.2442670052 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_aon_wake_resume.2329167428 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 28893533301 ps |
| CPU time | 52.27 seconds |
| Started | Feb 08 06:06:22 PM UTC 25 |
| Finished | Feb 08 06:07:16 PM UTC 25 |
| Peak memory | 217500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329167428 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.2329167428 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_av_buffer.4205877820 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 192911383 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:06:23 PM UTC 25 |
| Finished | Feb 08 06:06:26 PM UTC 25 |
| Peak memory | 214928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4205877820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbde v_av_buffer.4205877820 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_bitstuff_err.4246963013 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 145304122 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:06:23 PM UTC 25 |
| Finished | Feb 08 06:06:26 PM UTC 25 |
| Peak memory | 215064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4246963013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.us bdev_bitstuff_err.4246963013 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_data_toggle_clear.86110644 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 406403104 ps |
| CPU time | 2.17 seconds |
| Started | Feb 08 06:06:23 PM UTC 25 |
| Finished | Feb 08 06:06:27 PM UTC 25 |
| Peak memory | 217368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=86110644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16 .usbdev_data_toggle_clear.86110644 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_data_toggle_restore.1626929643 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 292511363 ps |
| CPU time | 1.83 seconds |
| Started | Feb 08 06:06:25 PM UTC 25 |
| Finished | Feb 08 06:06:28 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626929643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1626929643 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_device_address.3245958851 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 26370323215 ps |
| CPU time | 48.85 seconds |
| Started | Feb 08 06:06:25 PM UTC 25 |
| Finished | Feb 08 06:07:15 PM UTC 25 |
| Peak memory | 217400 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3245958851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16. usbdev_device_address.3245958851 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_device_timeout.287591206 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 1994875884 ps |
| CPU time | 14.23 seconds |
| Started | Feb 08 06:06:25 PM UTC 25 |
| Finished | Feb 08 06:06:40 PM UTC 25 |
| Peak memory | 217640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287591206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.287591206 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_disable_endpoint.1740028100 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 769494953 ps |
| CPU time | 2.78 seconds |
| Started | Feb 08 06:06:26 PM UTC 25 |
| Finished | Feb 08 06:06:30 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1740028100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.usbdev_disable_endpoint.1740028100 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_disconnected.4208131659 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 147282516 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:06:27 PM UTC 25 |
| Finished | Feb 08 06:06:30 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4208131659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.us bdev_disconnected.4208131659 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_enable.1098978047 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 71830319 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 06:06:27 PM UTC 25 |
| Finished | Feb 08 06:06:30 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1098978047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_e nable.1098978047 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_endpoint_access.3283245812 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 965743748 ps |
| CPU time | 3.93 seconds |
| Started | Feb 08 06:06:28 PM UTC 25 |
| Finished | Feb 08 06:06:33 PM UTC 25 |
| Peak memory | 217508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3283245812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16 .usbdev_endpoint_access.3283245812 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_endpoint_types.2695993298 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 566869518 ps |
| CPU time | 1.93 seconds |
| Started | Feb 08 06:06:28 PM UTC 25 |
| Finished | Feb 08 06:06:31 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695993298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 16.usbdev_endpoint_types.2695993298 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_fifo_rst.56562251 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 246047392 ps |
| CPU time | 2.39 seconds |
| Started | Feb 08 06:06:28 PM UTC 25 |
| Finished | Feb 08 06:06:31 PM UTC 25 |
| Peak memory | 217404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=56562251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_f ifo_rst.56562251 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_in_iso.2156316087 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 186800266 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:06:31 PM UTC 25 |
| Finished | Feb 08 06:06:34 PM UTC 25 |
| Peak memory | 227756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156316087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 16.usbdev_in_iso.2156316087 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_in_stall.2229247451 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 145286311 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:06:31 PM UTC 25 |
| Finished | Feb 08 06:06:34 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2229247451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev _in_stall.2229247451 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_in_trans.4236966907 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 201321121 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:06:31 PM UTC 25 |
| Finished | Feb 08 06:06:34 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4236966907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev _in_trans.4236966907 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_invalid_sync.3850710714 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 6084599092 ps |
| CPU time | 173.19 seconds |
| Started | Feb 08 06:06:29 PM UTC 25 |
| Finished | Feb 08 06:09:25 PM UTC 25 |
| Peak memory | 229772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850710714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.3850710714 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_iso_retraction.3522211580 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 9266468280 ps |
| CPU time | 101.25 seconds |
| Started | Feb 08 06:06:31 PM UTC 25 |
| Finished | Feb 08 06:08:15 PM UTC 25 |
| Peak memory | 217356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522211580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 16.usbdev_iso_retraction.3522211580 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_link_in_err.3565915299 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 232248835 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 06:06:33 PM UTC 25 |
| Finished | Feb 08 06:06:35 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3565915299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usb dev_link_in_err.3565915299 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_link_resume.4244644539 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 14221518925 ps |
| CPU time | 18.49 seconds |
| Started | Feb 08 06:06:33 PM UTC 25 |
| Finished | Feb 08 06:06:53 PM UTC 25 |
| Peak memory | 217648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4244644539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usb dev_link_resume.4244644539 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_link_suspend.342864439 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 8698112190 ps |
| CPU time | 12.23 seconds |
| Started | Feb 08 06:06:33 PM UTC 25 |
| Finished | Feb 08 06:06:46 PM UTC 25 |
| Peak memory | 217456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=342864439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usb dev_link_suspend.342864439 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_low_speed_traffic.392792532 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 3099491693 ps |
| CPU time | 28.96 seconds |
| Started | Feb 08 06:06:34 PM UTC 25 |
| Finished | Feb 08 06:07:05 PM UTC 25 |
| Peak memory | 234276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392792532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed _traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 16.usbdev_low_speed_traffic.392792532 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_max_inter_pkt_delay.877805768 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 2258435120 ps |
| CPU time | 66.71 seconds |
| Started | Feb 08 06:06:34 PM UTC 25 |
| Finished | Feb 08 06:07:43 PM UTC 25 |
| Peak memory | 227788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877805768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.877805768 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_max_length_in_transaction.1146173895 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 251631100 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:06:34 PM UTC 25 |
| Finished | Feb 08 06:06:37 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146173895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 16.usbdev_max_length_in_transaction.1146173895 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_max_length_out_transaction.1166205823 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 190952214 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:06:35 PM UTC 25 |
| Finished | Feb 08 06:06:37 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1166205823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1166205823 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_max_non_iso_usb_traffic.2134932067 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 3314932246 ps |
| CPU time | 92.09 seconds |
| Started | Feb 08 06:06:35 PM UTC 25 |
| Finished | Feb 08 06:08:09 PM UTC 25 |
| Peak memory | 229712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2134932067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 16.usbdev_max_non_iso_usb_traffic.2134932067 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_min_inter_pkt_delay.2524097077 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 3289605873 ps |
| CPU time | 32.89 seconds |
| Started | Feb 08 06:06:35 PM UTC 25 |
| Finished | Feb 08 06:07:09 PM UTC 25 |
| Peak memory | 229704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524097077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.2524097077 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_min_length_in_transaction.2454511944 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 165956040 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:06:35 PM UTC 25 |
| Finished | Feb 08 06:06:37 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454511944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 16.usbdev_min_length_in_transaction.2454511944 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_min_length_out_transaction.1574956547 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 151363662 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:06:36 PM UTC 25 |
| Finished | Feb 08 06:06:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1574956547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1574956547 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_nak_trans.1760423856 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 219248633 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:06:36 PM UTC 25 |
| Finished | Feb 08 06:06:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1760423856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbde v_nak_trans.1760423856 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_out_iso.1564149988 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 259651113 ps |
| CPU time | 1.77 seconds |
| Started | Feb 08 06:06:36 PM UTC 25 |
| Finished | Feb 08 06:06:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1564149988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_ out_iso.1564149988 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_out_stall.3557350629 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 176241389 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:06:37 PM UTC 25 |
| Finished | Feb 08 06:06:40 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3557350629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbde v_out_stall.3557350629 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_out_trans_nak.1950515869 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 164845730 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:06:39 PM UTC 25 |
| Finished | Feb 08 06:06:41 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1950515869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.u sbdev_out_trans_nak.1950515869 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_pending_in_trans.265646261 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 151285329 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:06:39 PM UTC 25 |
| Finished | Feb 08 06:06:41 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=265646261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16 .usbdev_pending_in_trans.265646261 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_phy_config_pinflip.2481365814 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 221503513 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:06:39 PM UTC 25 |
| Finished | Feb 08 06:06:41 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481365814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 16.usbdev_phy_config_pinflip.2481365814 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_phy_config_usb_ref_disable.1565152128 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 148880687 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:06:40 PM UTC 25 |
| Finished | Feb 08 06:06:43 PM UTC 25 |
| Peak memory | 215084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1565152128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1565152128 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_phy_pins_sense.541923196 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 34120343 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 06:06:40 PM UTC 25 |
| Finished | Feb 08 06:06:42 PM UTC 25 |
| Peak memory | 216140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=541923196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.u sbdev_phy_pins_sense.541923196 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_pkt_buffer.1966243081 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 7454096063 ps |
| CPU time | 23.85 seconds |
| Started | Feb 08 06:06:40 PM UTC 25 |
| Finished | Feb 08 06:07:05 PM UTC 25 |
| Peak memory | 226800 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1966243081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbd ev_pkt_buffer.1966243081 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_pkt_received.3422035613 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 178305070 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:06:41 PM UTC 25 |
| Finished | Feb 08 06:06:44 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3422035613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.us bdev_pkt_received.3422035613 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_pkt_sent.1013787348 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 199079334 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:06:41 PM UTC 25 |
| Finished | Feb 08 06:06:44 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1013787348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev _pkt_sent.1013787348 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_random_length_in_transaction.1685898788 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 164155943 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:06:43 PM UTC 25 |
| Finished | Feb 08 06:06:45 PM UTC 25 |
| Peak memory | 214988 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1685898788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.u sbdev_random_length_in_transaction.1685898788 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_random_length_out_transaction.3594120050 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 188210931 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 06:06:43 PM UTC 25 |
| Finished | Feb 08 06:06:45 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3594120050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 16.usbdev_random_length_out_transaction.3594120050 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_resume_link_active.2380200703 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 20197318801 ps |
| CPU time | 43.24 seconds |
| Started | Feb 08 06:06:43 PM UTC 25 |
| Finished | Feb 08 06:07:27 PM UTC 25 |
| Peak memory | 217056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2380200703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_resume_link_active.2380200703 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_resume_link_active/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_rx_crc_err.292977570 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 152519850 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:06:44 PM UTC 25 |
| Finished | Feb 08 06:06:47 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=292977570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbde v_rx_crc_err.292977570 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_rx_full.1329486887 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 390486992 ps |
| CPU time | 2.56 seconds |
| Started | Feb 08 06:06:44 PM UTC 25 |
| Finished | Feb 08 06:06:48 PM UTC 25 |
| Peak memory | 217176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1329486887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_ rx_full.1329486887 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_setup_stage.2748536338 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 215278721 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:06:44 PM UTC 25 |
| Finished | Feb 08 06:06:47 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2748536338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usb dev_setup_stage.2748536338 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_setup_trans_ignored.702617982 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 148943966 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:06:46 PM UTC 25 |
| Finished | Feb 08 06:06:49 PM UTC 25 |
| Peak memory | 215092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=702617982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.702617982 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_smoke.913372586 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 234538401 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:06:46 PM UTC 25 |
| Finished | Feb 08 06:06:49 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=913372586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smo ke.913372586 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_spurious_pids_ignored.2103826022 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 2208491289 ps |
| CPU time | 59.04 seconds |
| Started | Feb 08 06:06:46 PM UTC 25 |
| Finished | Feb 08 06:07:47 PM UTC 25 |
| Peak memory | 227688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103826022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 16.usbdev_spurious_pids_ignored.2103826022 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_stall_priority_over_nak.2840783483 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 159373884 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:06:46 PM UTC 25 |
| Finished | Feb 08 06:06:48 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2840783483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 16.usbdev_stall_priority_over_nak.2840783483 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_stall_trans.3644546043 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 249476751 ps |
| CPU time | 1.12 seconds |
| Started | Feb 08 06:06:46 PM UTC 25 |
| Finished | Feb 08 06:06:48 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3644546043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usb dev_stall_trans.3644546043 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_stream_len_max.308545576 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 406633964 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:06:47 PM UTC 25 |
| Finished | Feb 08 06:06:50 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=308545576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.u sbdev_stream_len_max.308545576 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_streaming_out.1118383682 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 4006957617 ps |
| CPU time | 108.83 seconds |
| Started | Feb 08 06:06:47 PM UTC 25 |
| Finished | Feb 08 06:08:38 PM UTC 25 |
| Peak memory | 229708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1118383682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbde v_streaming_out.1118383682 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_timeout_missing_host_handshake.3659322235 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 5585460903 ps |
| CPU time | 43.97 seconds |
| Started | Feb 08 06:06:26 PM UTC 25 |
| Finished | Feb 08 06:07:11 PM UTC 25 |
| Peak memory | 217676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659322235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing_host_handshake.3659322235 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_tx_rx_disruption.1443757020 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 477002976 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:06:47 PM UTC 25 |
| Finished | Feb 08 06:06:50 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 443757020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_tx_rx_disruption.1443757020 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/16.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/160.usbdev_endpoint_types.3722830058 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 704230320 ps |
| CPU time | 1.79 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722830058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 160.usbdev_endpoint_types.3722830058 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/160.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/160.usbdev_tx_rx_disruption.39362791 |
| Short name | T3272 |
| Test name | |
| Test status | |
| Simulation time | 483442560 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:39 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 9362791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.usbdev_tx_rx_disruption.39362791 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/160.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/161.usbdev_endpoint_types.1681407249 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 278460974 ps |
| CPU time | 1.02 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:38 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681407249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 161.usbdev_endpoint_types.1681407249 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/161.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/161.usbdev_tx_rx_disruption.2582747637 |
| Short name | T3275 |
| Test name | |
| Test status | |
| Simulation time | 531709327 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:39 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 582747637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.usbdev_tx_rx_disruption.2582747637 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/161.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/162.usbdev_endpoint_types.304879059 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 309158759 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:38 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304879059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 162.usbdev_endpoint_types.304879059 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/162.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/162.usbdev_tx_rx_disruption.485211780 |
| Short name | T3276 |
| Test name | |
| Test status | |
| Simulation time | 476238296 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:39 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 85211780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.usbdev_tx_rx_disruption.485211780 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/162.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/163.usbdev_tx_rx_disruption.2103337699 |
| Short name | T3278 |
| Test name | |
| Test status | |
| Simulation time | 560916501 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:39 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 103337699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.usbdev_tx_rx_disruption.2103337699 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/163.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/164.usbdev_endpoint_types.323718056 |
| Short name | T3271 |
| Test name | |
| Test status | |
| Simulation time | 269659738 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:39 PM UTC 25 |
| Peak memory | 215092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323718056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 164.usbdev_endpoint_types.323718056 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/164.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/164.usbdev_tx_rx_disruption.2887633208 |
| Short name | T3274 |
| Test name | |
| Test status | |
| Simulation time | 513390454 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:39 PM UTC 25 |
| Peak memory | 214948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 887633208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.usbdev_tx_rx_disruption.2887633208 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/164.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/165.usbdev_endpoint_types.1121398072 |
| Short name | T3266 |
| Test name | |
| Test status | |
| Simulation time | 153452714 ps |
| CPU time | 0.79 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:38 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121398072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 165.usbdev_endpoint_types.1121398072 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/165.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/165.usbdev_tx_rx_disruption.3350607996 |
| Short name | T3262 |
| Test name | |
| Test status | |
| Simulation time | 502373399 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:38 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 350607996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.usbdev_tx_rx_disruption.3350607996 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/165.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/166.usbdev_endpoint_types.3884886807 |
| Short name | T3261 |
| Test name | |
| Test status | |
| Simulation time | 498539623 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:38 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884886807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 166.usbdev_endpoint_types.3884886807 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/166.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/166.usbdev_tx_rx_disruption.2841421189 |
| Short name | T3260 |
| Test name | |
| Test status | |
| Simulation time | 514139095 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:38 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 841421189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.usbdev_tx_rx_disruption.2841421189 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/166.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/167.usbdev_tx_rx_disruption.28052152 |
| Short name | T3265 |
| Test name | |
| Test status | |
| Simulation time | 610964916 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:38 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 8052152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.usbdev_tx_rx_disruption.28052152 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/167.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/168.usbdev_endpoint_types.2123463588 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 639810956 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123463588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 168.usbdev_endpoint_types.2123463588 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/168.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/168.usbdev_tx_rx_disruption.3329509736 |
| Short name | T3277 |
| Test name | |
| Test status | |
| Simulation time | 564342193 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:39 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 329509736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.usbdev_tx_rx_disruption.3329509736 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/168.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/169.usbdev_endpoint_types.1105108888 |
| Short name | T3268 |
| Test name | |
| Test status | |
| Simulation time | 187013498 ps |
| CPU time | 0.86 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:38 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105108888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 169.usbdev_endpoint_types.1105108888 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/169.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/169.usbdev_tx_rx_disruption.1357852915 |
| Short name | T3279 |
| Test name | |
| Test status | |
| Simulation time | 457663698 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:18:35 PM UTC 25 |
| Finished | Feb 08 06:18:39 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 357852915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.usbdev_tx_rx_disruption.1357852915 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/169.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_alert_test.1765576379 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 71053549 ps |
| CPU time | 0.9 seconds |
| Started | Feb 08 06:07:18 PM UTC 25 |
| Finished | Feb 08 06:07:20 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765576379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 17.usbdev_alert_test.1765576379 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_aon_wake_disconnect.1886889296 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 10867529417 ps |
| CPU time | 30.87 seconds |
| Started | Feb 08 06:06:49 PM UTC 25 |
| Finished | Feb 08 06:07:21 PM UTC 25 |
| Peak memory | 217572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886889296 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.1886889296 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_aon_wake_reset.3786185521 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 21093845836 ps |
| CPU time | 27.79 seconds |
| Started | Feb 08 06:06:50 PM UTC 25 |
| Finished | Feb 08 06:07:19 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786185521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.3786185521 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_aon_wake_resume.2801210566 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 29667589951 ps |
| CPU time | 51.31 seconds |
| Started | Feb 08 06:06:50 PM UTC 25 |
| Finished | Feb 08 06:07:43 PM UTC 25 |
| Peak memory | 217384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801210566 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.2801210566 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_av_buffer.4146451049 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 148306182 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:06:50 PM UTC 25 |
| Finished | Feb 08 06:06:53 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4146451049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbde v_av_buffer.4146451049 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_bitstuff_err.2974911278 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 135400432 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:06:50 PM UTC 25 |
| Finished | Feb 08 06:06:53 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2974911278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.us bdev_bitstuff_err.2974911278 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_data_toggle_clear.2765049268 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 477830330 ps |
| CPU time | 1.8 seconds |
| Started | Feb 08 06:06:50 PM UTC 25 |
| Finished | Feb 08 06:06:53 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2765049268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.2765049268 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_data_toggle_restore.1826310902 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 1029018704 ps |
| CPU time | 4.57 seconds |
| Started | Feb 08 06:06:50 PM UTC 25 |
| Finished | Feb 08 06:06:56 PM UTC 25 |
| Peak memory | 217364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826310902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1826310902 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_device_address.3245455472 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 47173877046 ps |
| CPU time | 100.78 seconds |
| Started | Feb 08 06:06:50 PM UTC 25 |
| Finished | Feb 08 06:08:33 PM UTC 25 |
| Peak memory | 217360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3245455472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17. usbdev_device_address.3245455472 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_device_timeout.2479687490 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 7872951560 ps |
| CPU time | 55.6 seconds |
| Started | Feb 08 06:06:50 PM UTC 25 |
| Finished | Feb 08 06:07:48 PM UTC 25 |
| Peak memory | 217604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479687490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.2479687490 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_disable_endpoint.1144310459 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 1058812303 ps |
| CPU time | 4.56 seconds |
| Started | Feb 08 06:06:52 PM UTC 25 |
| Finished | Feb 08 06:06:57 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1144310459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.usbdev_disable_endpoint.1144310459 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_disconnected.3475932511 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 140547992 ps |
| CPU time | 1.02 seconds |
| Started | Feb 08 06:06:52 PM UTC 25 |
| Finished | Feb 08 06:06:54 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3475932511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.us bdev_disconnected.3475932511 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_enable.1711748909 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 58104630 ps |
| CPU time | 0.84 seconds |
| Started | Feb 08 06:06:52 PM UTC 25 |
| Finished | Feb 08 06:06:54 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1711748909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_e nable.1711748909 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_endpoint_access.1253304200 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 767918262 ps |
| CPU time | 3.29 seconds |
| Started | Feb 08 06:06:53 PM UTC 25 |
| Finished | Feb 08 06:06:58 PM UTC 25 |
| Peak memory | 217256 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1253304200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17 .usbdev_endpoint_access.1253304200 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_endpoint_types.2212770765 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 572633934 ps |
| CPU time | 2.67 seconds |
| Started | Feb 08 06:06:53 PM UTC 25 |
| Finished | Feb 08 06:06:57 PM UTC 25 |
| Peak memory | 217016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212770765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 17.usbdev_endpoint_types.2212770765 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_fifo_rst.3750995260 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 353563123 ps |
| CPU time | 3.54 seconds |
| Started | Feb 08 06:06:55 PM UTC 25 |
| Finished | Feb 08 06:06:59 PM UTC 25 |
| Peak memory | 217316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3750995260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev _fifo_rst.3750995260 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_in_iso.2571316673 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 193491037 ps |
| CPU time | 1.89 seconds |
| Started | Feb 08 06:06:55 PM UTC 25 |
| Finished | Feb 08 06:06:58 PM UTC 25 |
| Peak memory | 227756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571316673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 17.usbdev_in_iso.2571316673 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_in_stall.2651609624 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 205273150 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:06:55 PM UTC 25 |
| Finished | Feb 08 06:06:58 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2651609624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev _in_stall.2651609624 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_in_trans.1874167939 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 182031837 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:06:55 PM UTC 25 |
| Finished | Feb 08 06:06:58 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1874167939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev _in_trans.1874167939 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_invalid_sync.1397621376 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 4483273823 ps |
| CPU time | 48.32 seconds |
| Started | Feb 08 06:06:55 PM UTC 25 |
| Finished | Feb 08 06:07:45 PM UTC 25 |
| Peak memory | 234228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397621376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.1397621376 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_iso_retraction.927903895 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 12911875449 ps |
| CPU time | 99.21 seconds |
| Started | Feb 08 06:06:55 PM UTC 25 |
| Finished | Feb 08 06:08:36 PM UTC 25 |
| Peak memory | 217544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927903895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retra ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 17.usbdev_iso_retraction.927903895 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_link_in_err.633500723 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 190395150 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:06:57 PM UTC 25 |
| Finished | Feb 08 06:07:00 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=633500723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbd ev_link_in_err.633500723 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_link_resume.2011689695 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 7426962932 ps |
| CPU time | 15.93 seconds |
| Started | Feb 08 06:06:58 PM UTC 25 |
| Finished | Feb 08 06:07:16 PM UTC 25 |
| Peak memory | 227664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2011689695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usb dev_link_resume.2011689695 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_link_suspend.4273216328 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 9640876148 ps |
| CPU time | 17.24 seconds |
| Started | Feb 08 06:06:58 PM UTC 25 |
| Finished | Feb 08 06:07:17 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4273216328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.us bdev_link_suspend.4273216328 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_low_speed_traffic.4293074243 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 3913096882 ps |
| CPU time | 106.39 seconds |
| Started | Feb 08 06:06:58 PM UTC 25 |
| Finished | Feb 08 06:08:47 PM UTC 25 |
| Peak memory | 234376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293074243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 17.usbdev_low_speed_traffic.4293074243 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_max_inter_pkt_delay.3031888682 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 2296166014 ps |
| CPU time | 23.97 seconds |
| Started | Feb 08 06:06:58 PM UTC 25 |
| Finished | Feb 08 06:07:24 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031888682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.3031888682 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_max_length_in_transaction.3874514846 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 255400578 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:06:58 PM UTC 25 |
| Finished | Feb 08 06:07:01 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874514846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 17.usbdev_max_length_in_transaction.3874514846 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_max_length_out_transaction.3325089052 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 187385665 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:06:58 PM UTC 25 |
| Finished | Feb 08 06:07:01 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3325089052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3325089052 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_max_non_iso_usb_traffic.3777575896 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 2922895364 ps |
| CPU time | 82.46 seconds |
| Started | Feb 08 06:07:01 PM UTC 25 |
| Finished | Feb 08 06:08:25 PM UTC 25 |
| Peak memory | 229904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3777575896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 17.usbdev_max_non_iso_usb_traffic.3777575896 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_min_inter_pkt_delay.1545136274 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 2334232334 ps |
| CPU time | 18.67 seconds |
| Started | Feb 08 06:07:01 PM UTC 25 |
| Finished | Feb 08 06:07:21 PM UTC 25 |
| Peak memory | 227856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545136274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.1545136274 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_min_length_in_transaction.3730612763 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 177715053 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:07:02 PM UTC 25 |
| Finished | Feb 08 06:07:05 PM UTC 25 |
| Peak memory | 215060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730612763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 17.usbdev_min_length_in_transaction.3730612763 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_min_length_out_transaction.4251846027 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 139145066 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:07:02 PM UTC 25 |
| Finished | Feb 08 06:07:05 PM UTC 25 |
| Peak memory | 215064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4251846027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.4251846027 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_out_iso.250410825 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 218478134 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:07:06 PM UTC 25 |
| Finished | Feb 08 06:07:08 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=250410825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_o ut_iso.250410825 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_out_stall.3381043123 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 183011361 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:07:06 PM UTC 25 |
| Finished | Feb 08 06:07:08 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3381043123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbde v_out_stall.3381043123 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_out_trans_nak.2731027668 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 150894089 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:07:06 PM UTC 25 |
| Finished | Feb 08 06:07:08 PM UTC 25 |
| Peak memory | 214892 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2731027668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.u sbdev_out_trans_nak.2731027668 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_pending_in_trans.1006637287 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 173247361 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:07:06 PM UTC 25 |
| Finished | Feb 08 06:07:08 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1006637287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.usbdev_pending_in_trans.1006637287 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_phy_config_pinflip.3542344948 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 270356905 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:07:06 PM UTC 25 |
| Finished | Feb 08 06:07:09 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542344948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 17.usbdev_phy_config_pinflip.3542344948 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_phy_config_usb_ref_disable.1014049281 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 141939180 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:07:08 PM UTC 25 |
| Finished | Feb 08 06:07:10 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1014049281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.1014049281 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_phy_pins_sense.3749826772 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 67906630 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 06:07:08 PM UTC 25 |
| Finished | Feb 08 06:07:10 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3749826772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17. usbdev_phy_pins_sense.3749826772 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_pkt_buffer.1896671204 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 21299597013 ps |
| CPU time | 60.4 seconds |
| Started | Feb 08 06:07:08 PM UTC 25 |
| Finished | Feb 08 06:08:10 PM UTC 25 |
| Peak memory | 227928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1896671204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbd ev_pkt_buffer.1896671204 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_pkt_received.209574882 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 181371889 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 06:07:09 PM UTC 25 |
| Finished | Feb 08 06:07:11 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=209574882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usb dev_pkt_received.209574882 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_pkt_sent.4288315832 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 163653309 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:07:09 PM UTC 25 |
| Finished | Feb 08 06:07:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4288315832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev _pkt_sent.4288315832 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_random_length_in_transaction.3993174803 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 277415459 ps |
| CPU time | 1.76 seconds |
| Started | Feb 08 06:07:09 PM UTC 25 |
| Finished | Feb 08 06:07:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3993174803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.u sbdev_random_length_in_transaction.3993174803 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_random_length_out_transaction.47793166 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 147751355 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 06:07:09 PM UTC 25 |
| Finished | Feb 08 06:07:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=47793166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.47793166 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_resume_link_active.751739403 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 20151929313 ps |
| CPU time | 29.43 seconds |
| Started | Feb 08 06:07:09 PM UTC 25 |
| Finished | Feb 08 06:07:40 PM UTC 25 |
| Peak memory | 217148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=751739403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_resume_link_active.751739403 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_resume_link_active/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_rx_crc_err.3052966545 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 174247422 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:07:11 PM UTC 25 |
| Finished | Feb 08 06:07:14 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3052966545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbd ev_rx_crc_err.3052966545 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_rx_full.970341578 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 251893991 ps |
| CPU time | 1.82 seconds |
| Started | Feb 08 06:07:11 PM UTC 25 |
| Finished | Feb 08 06:07:14 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=970341578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_r x_full.970341578 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_setup_stage.4157766610 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 153977606 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:07:12 PM UTC 25 |
| Finished | Feb 08 06:07:14 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4157766610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usb dev_setup_stage.4157766610 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_setup_trans_ignored.1791965808 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 154146728 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:07:13 PM UTC 25 |
| Finished | Feb 08 06:07:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1791965808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.usbdev_setup_trans_ignored.1791965808 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_smoke.659877061 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 248350984 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:07:13 PM UTC 25 |
| Finished | Feb 08 06:07:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=659877061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smo ke.659877061 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_spurious_pids_ignored.2075905083 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 2677927459 ps |
| CPU time | 25.78 seconds |
| Started | Feb 08 06:07:13 PM UTC 25 |
| Finished | Feb 08 06:07:40 PM UTC 25 |
| Peak memory | 234420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075905083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 17.usbdev_spurious_pids_ignored.2075905083 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_stall_priority_over_nak.370486244 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 167187984 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:07:13 PM UTC 25 |
| Finished | Feb 08 06:07:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=370486244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 17.usbdev_stall_priority_over_nak.370486244 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_stall_trans.1483504901 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 154644575 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:07:13 PM UTC 25 |
| Finished | Feb 08 06:07:16 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1483504901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usb dev_stall_trans.1483504901 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_stream_len_max.2251467935 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 438202331 ps |
| CPU time | 2.8 seconds |
| Started | Feb 08 06:07:14 PM UTC 25 |
| Finished | Feb 08 06:07:19 PM UTC 25 |
| Peak memory | 217344 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2251467935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17. usbdev_stream_len_max.2251467935 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_streaming_out.1944129406 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 3246996174 ps |
| CPU time | 90.04 seconds |
| Started | Feb 08 06:07:14 PM UTC 25 |
| Finished | Feb 08 06:08:47 PM UTC 25 |
| Peak memory | 229708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1944129406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbde v_streaming_out.1944129406 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_timeout_missing_host_handshake.2381358163 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 2939559259 ps |
| CPU time | 25.42 seconds |
| Started | Feb 08 06:06:52 PM UTC 25 |
| Finished | Feb 08 06:07:18 PM UTC 25 |
| Peak memory | 217356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381358163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing_host_handshake.2381358163 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_tx_rx_disruption.3803219145 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 592173933 ps |
| CPU time | 2.15 seconds |
| Started | Feb 08 06:07:16 PM UTC 25 |
| Finished | Feb 08 06:07:19 PM UTC 25 |
| Peak memory | 217180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 803219145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_tx_rx_disruption.3803219145 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/17.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/170.usbdev_endpoint_types.1883533568 |
| Short name | T3280 |
| Test name | |
| Test status | |
| Simulation time | 226945339 ps |
| CPU time | 0.92 seconds |
| Started | Feb 08 06:18:37 PM UTC 25 |
| Finished | Feb 08 06:18:43 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883533568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 170.usbdev_endpoint_types.1883533568 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/170.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/170.usbdev_tx_rx_disruption.2314188565 |
| Short name | T3284 |
| Test name | |
| Test status | |
| Simulation time | 477596900 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:18:37 PM UTC 25 |
| Finished | Feb 08 06:18:43 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 314188565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.usbdev_tx_rx_disruption.2314188565 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/170.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/171.usbdev_endpoint_types.3665344947 |
| Short name | T3281 |
| Test name | |
| Test status | |
| Simulation time | 168640506 ps |
| CPU time | 0.87 seconds |
| Started | Feb 08 06:18:37 PM UTC 25 |
| Finished | Feb 08 06:18:43 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665344947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 171.usbdev_endpoint_types.3665344947 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/171.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/171.usbdev_tx_rx_disruption.3200279632 |
| Short name | T3286 |
| Test name | |
| Test status | |
| Simulation time | 652630040 ps |
| CPU time | 1.78 seconds |
| Started | Feb 08 06:18:37 PM UTC 25 |
| Finished | Feb 08 06:18:43 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 200279632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.usbdev_tx_rx_disruption.3200279632 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/171.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/172.usbdev_endpoint_types.3916062746 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 227574469 ps |
| CPU time | 0.93 seconds |
| Started | Feb 08 06:18:37 PM UTC 25 |
| Finished | Feb 08 06:18:43 PM UTC 25 |
| Peak memory | 215928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916062746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 172.usbdev_endpoint_types.3916062746 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/172.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/172.usbdev_tx_rx_disruption.4089965987 |
| Short name | T3285 |
| Test name | |
| Test status | |
| Simulation time | 461508308 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:18:37 PM UTC 25 |
| Finished | Feb 08 06:18:43 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 089965987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.usbdev_tx_rx_disruption.4089965987 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/172.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/173.usbdev_endpoint_types.1496428441 |
| Short name | T3282 |
| Test name | |
| Test status | |
| Simulation time | 239861977 ps |
| CPU time | 0.89 seconds |
| Started | Feb 08 06:18:37 PM UTC 25 |
| Finished | Feb 08 06:18:43 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496428441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 173.usbdev_endpoint_types.1496428441 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/173.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/173.usbdev_tx_rx_disruption.2224012833 |
| Short name | T3283 |
| Test name | |
| Test status | |
| Simulation time | 483772639 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:18:37 PM UTC 25 |
| Finished | Feb 08 06:18:43 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 224012833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.usbdev_tx_rx_disruption.2224012833 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/173.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/174.usbdev_endpoint_types.1337654407 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 282657770 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 06:18:37 PM UTC 25 |
| Finished | Feb 08 06:18:43 PM UTC 25 |
| Peak memory | 216140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337654407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 174.usbdev_endpoint_types.1337654407 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/174.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/174.usbdev_tx_rx_disruption.2427871300 |
| Short name | T3289 |
| Test name | |
| Test status | |
| Simulation time | 617599137 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:18:37 PM UTC 25 |
| Finished | Feb 08 06:18:43 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 427871300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.usbdev_tx_rx_disruption.2427871300 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/174.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/175.usbdev_endpoint_types.4281151828 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 167472085 ps |
| CPU time | 0.83 seconds |
| Started | Feb 08 06:18:37 PM UTC 25 |
| Finished | Feb 08 06:18:43 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281151828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 175.usbdev_endpoint_types.4281151828 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/175.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/175.usbdev_tx_rx_disruption.4017481311 |
| Short name | T3288 |
| Test name | |
| Test status | |
| Simulation time | 576660994 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:18:37 PM UTC 25 |
| Finished | Feb 08 06:18:43 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 017481311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.usbdev_tx_rx_disruption.4017481311 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/175.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/176.usbdev_endpoint_types.281110513 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 468379592 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:18:37 PM UTC 25 |
| Finished | Feb 08 06:18:54 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281110513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 176.usbdev_endpoint_types.281110513 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/176.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/176.usbdev_tx_rx_disruption.1866486797 |
| Short name | T3287 |
| Test name | |
| Test status | |
| Simulation time | 545627923 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:18:37 PM UTC 25 |
| Finished | Feb 08 06:18:43 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 866486797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.usbdev_tx_rx_disruption.1866486797 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/176.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/177.usbdev_endpoint_types.2547509211 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 294106790 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 06:18:38 PM UTC 25 |
| Finished | Feb 08 06:19:41 PM UTC 25 |
| Peak memory | 216700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547509211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 177.usbdev_endpoint_types.2547509211 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/177.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/177.usbdev_tx_rx_disruption.3994880067 |
| Short name | T3434 |
| Test name | |
| Test status | |
| Simulation time | 548440250 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:18:38 PM UTC 25 |
| Finished | Feb 08 06:19:42 PM UTC 25 |
| Peak memory | 215260 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 994880067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.usbdev_tx_rx_disruption.3994880067 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/177.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/178.usbdev_endpoint_types.2130728009 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 570606020 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:18:38 PM UTC 25 |
| Finished | Feb 08 06:19:41 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130728009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 178.usbdev_endpoint_types.2130728009 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/178.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_alert_test.2562717772 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 65546502 ps |
| CPU time | 0.86 seconds |
| Started | Feb 08 06:07:41 PM UTC 25 |
| Finished | Feb 08 06:07:44 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562717772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 18.usbdev_alert_test.2562717772 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_aon_wake_disconnect.2766236785 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 9986306498 ps |
| CPU time | 22.2 seconds |
| Started | Feb 08 06:07:18 PM UTC 25 |
| Finished | Feb 08 06:07:42 PM UTC 25 |
| Peak memory | 217444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766236785 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.2766236785 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_aon_wake_reset.3481080940 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 14939443295 ps |
| CPU time | 28.4 seconds |
| Started | Feb 08 06:07:18 PM UTC 25 |
| Finished | Feb 08 06:07:48 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481080940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.3481080940 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_aon_wake_resume.2926964228 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 25145681311 ps |
| CPU time | 43.88 seconds |
| Started | Feb 08 06:07:18 PM UTC 25 |
| Finished | Feb 08 06:08:04 PM UTC 25 |
| Peak memory | 227592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926964228 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.2926964228 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_av_buffer.3106304203 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 152606156 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 06:07:18 PM UTC 25 |
| Finished | Feb 08 06:07:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3106304203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbde v_av_buffer.3106304203 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_bitstuff_err.393926019 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 156492034 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:07:18 PM UTC 25 |
| Finished | Feb 08 06:07:21 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=393926019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usb dev_bitstuff_err.393926019 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_data_toggle_clear.3158284186 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 357026150 ps |
| CPU time | 2.39 seconds |
| Started | Feb 08 06:07:18 PM UTC 25 |
| Finished | Feb 08 06:07:22 PM UTC 25 |
| Peak memory | 217372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3158284186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.3158284186 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_device_address.1784909845 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 14264847004 ps |
| CPU time | 23.95 seconds |
| Started | Feb 08 06:07:19 PM UTC 25 |
| Finished | Feb 08 06:07:45 PM UTC 25 |
| Peak memory | 217496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1784909845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18. usbdev_device_address.1784909845 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_device_timeout.1822637149 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 1100536660 ps |
| CPU time | 12.02 seconds |
| Started | Feb 08 06:07:19 PM UTC 25 |
| Finished | Feb 08 06:07:33 PM UTC 25 |
| Peak memory | 217456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822637149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.1822637149 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_disable_endpoint.2783993781 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 744832624 ps |
| CPU time | 3.19 seconds |
| Started | Feb 08 06:07:21 PM UTC 25 |
| Finished | Feb 08 06:07:25 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2783993781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.usbdev_disable_endpoint.2783993781 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_disconnected.1321292635 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 146868340 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 06:07:21 PM UTC 25 |
| Finished | Feb 08 06:07:23 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1321292635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.us bdev_disconnected.1321292635 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_enable.3061524866 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 39762340 ps |
| CPU time | 0.97 seconds |
| Started | Feb 08 06:07:21 PM UTC 25 |
| Finished | Feb 08 06:07:23 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3061524866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_e nable.3061524866 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_endpoint_access.3855426796 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 740051620 ps |
| CPU time | 3.39 seconds |
| Started | Feb 08 06:07:22 PM UTC 25 |
| Finished | Feb 08 06:07:27 PM UTC 25 |
| Peak memory | 217500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3855426796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18 .usbdev_endpoint_access.3855426796 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_endpoint_types.4057409191 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 520603646 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:07:22 PM UTC 25 |
| Finished | Feb 08 06:07:25 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057409191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 18.usbdev_endpoint_types.4057409191 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_fifo_rst.1353831710 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 218864455 ps |
| CPU time | 2.38 seconds |
| Started | Feb 08 06:07:22 PM UTC 25 |
| Finished | Feb 08 06:07:26 PM UTC 25 |
| Peak memory | 217472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1353831710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev _fifo_rst.1353831710 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_in_iso.1488652772 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 271954945 ps |
| CPU time | 2.23 seconds |
| Started | Feb 08 06:07:22 PM UTC 25 |
| Finished | Feb 08 06:07:26 PM UTC 25 |
| Peak memory | 227628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488652772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 18.usbdev_in_iso.1488652772 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_in_stall.1046695753 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 142340998 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:07:24 PM UTC 25 |
| Finished | Feb 08 06:07:26 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1046695753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev _in_stall.1046695753 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_in_trans.2653670345 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 249723299 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:07:24 PM UTC 25 |
| Finished | Feb 08 06:07:26 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2653670345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev _in_trans.2653670345 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_invalid_sync.2716279381 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 3326167527 ps |
| CPU time | 26.23 seconds |
| Started | Feb 08 06:07:22 PM UTC 25 |
| Finished | Feb 08 06:07:50 PM UTC 25 |
| Peak memory | 229628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716279381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.2716279381 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_iso_retraction.881007329 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 13618098632 ps |
| CPU time | 96.14 seconds |
| Started | Feb 08 06:07:24 PM UTC 25 |
| Finished | Feb 08 06:09:02 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881007329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retra ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 18.usbdev_iso_retraction.881007329 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_link_in_err.2832948354 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 225177827 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:07:25 PM UTC 25 |
| Finished | Feb 08 06:07:28 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2832948354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usb dev_link_in_err.2832948354 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_link_resume.857096169 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 6249964851 ps |
| CPU time | 17.99 seconds |
| Started | Feb 08 06:07:25 PM UTC 25 |
| Finished | Feb 08 06:07:45 PM UTC 25 |
| Peak memory | 227660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=857096169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbd ev_link_resume.857096169 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_link_suspend.123319378 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 9172887006 ps |
| CPU time | 14.68 seconds |
| Started | Feb 08 06:07:25 PM UTC 25 |
| Finished | Feb 08 06:07:41 PM UTC 25 |
| Peak memory | 217520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=123319378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usb dev_link_suspend.123319378 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_low_speed_traffic.649225821 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 4253564341 ps |
| CPU time | 49.84 seconds |
| Started | Feb 08 06:07:26 PM UTC 25 |
| Finished | Feb 08 06:08:17 PM UTC 25 |
| Peak memory | 229796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649225821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed _traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 18.usbdev_low_speed_traffic.649225821 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_max_inter_pkt_delay.547537039 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 4179702030 ps |
| CPU time | 131.36 seconds |
| Started | Feb 08 06:07:26 PM UTC 25 |
| Finished | Feb 08 06:09:40 PM UTC 25 |
| Peak memory | 227776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547537039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.547537039 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_max_length_in_transaction.2243453738 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 283230028 ps |
| CPU time | 1.87 seconds |
| Started | Feb 08 06:07:27 PM UTC 25 |
| Finished | Feb 08 06:07:30 PM UTC 25 |
| Peak memory | 215076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243453738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 18.usbdev_max_length_in_transaction.2243453738 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_max_length_out_transaction.1719384871 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 235505216 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:07:27 PM UTC 25 |
| Finished | Feb 08 06:07:30 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1719384871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1719384871 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_max_non_iso_usb_traffic.725821113 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 1389369513 ps |
| CPU time | 14.64 seconds |
| Started | Feb 08 06:07:27 PM UTC 25 |
| Finished | Feb 08 06:07:43 PM UTC 25 |
| Peak memory | 227788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=725821113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 18.usbdev_max_non_iso_usb_traffic.725821113 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_min_inter_pkt_delay.2177119985 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 3130869202 ps |
| CPU time | 30.69 seconds |
| Started | Feb 08 06:07:27 PM UTC 25 |
| Finished | Feb 08 06:07:59 PM UTC 25 |
| Peak memory | 227920 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177119985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.2177119985 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_min_length_in_transaction.3672437023 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 153931981 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:07:27 PM UTC 25 |
| Finished | Feb 08 06:07:30 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672437023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.usbdev_min_length_in_transaction.3672437023 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_min_length_out_transaction.517323130 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 164761520 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:07:28 PM UTC 25 |
| Finished | Feb 08 06:07:31 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=517323130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 18.usbdev_min_length_out_transaction.517323130 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_out_iso.1280420265 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 147260033 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:07:29 PM UTC 25 |
| Finished | Feb 08 06:07:31 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1280420265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_ out_iso.1280420265 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_out_stall.1164031121 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 185953374 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:07:30 PM UTC 25 |
| Finished | Feb 08 06:07:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1164031121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbde v_out_stall.1164031121 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_out_trans_nak.1325822252 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 153308095 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:07:31 PM UTC 25 |
| Finished | Feb 08 06:07:33 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1325822252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.u sbdev_out_trans_nak.1325822252 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_pending_in_trans.4232406453 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 154941221 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:07:31 PM UTC 25 |
| Finished | Feb 08 06:07:33 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4232406453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.usbdev_pending_in_trans.4232406453 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_phy_config_pinflip.955567700 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 184419711 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:07:31 PM UTC 25 |
| Finished | Feb 08 06:07:34 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=955567700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.usbdev_phy_config_pinflip.955567700 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_phy_config_usb_ref_disable.1600635165 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 160072498 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:07:32 PM UTC 25 |
| Finished | Feb 08 06:07:35 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1600635165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.1600635165 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_phy_pins_sense.1232832336 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 35613064 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 06:07:32 PM UTC 25 |
| Finished | Feb 08 06:07:34 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1232832336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18. usbdev_phy_pins_sense.1232832336 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_pkt_received.2069217115 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 165498011 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:07:34 PM UTC 25 |
| Finished | Feb 08 06:07:36 PM UTC 25 |
| Peak memory | 215140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2069217115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.us bdev_pkt_received.2069217115 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_pkt_sent.4202525341 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 227950968 ps |
| CPU time | 1.74 seconds |
| Started | Feb 08 06:07:34 PM UTC 25 |
| Finished | Feb 08 06:07:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4202525341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev _pkt_sent.4202525341 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_random_length_in_transaction.2132498805 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 233188742 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:07:34 PM UTC 25 |
| Finished | Feb 08 06:07:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2132498805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.u sbdev_random_length_in_transaction.2132498805 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_random_length_out_transaction.148334055 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 152540047 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:07:35 PM UTC 25 |
| Finished | Feb 08 06:07:37 PM UTC 25 |
| Peak memory | 215076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=148334055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 18.usbdev_random_length_out_transaction.148334055 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_resume_link_active.82566817 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 20164419995 ps |
| CPU time | 39.18 seconds |
| Started | Feb 08 06:07:35 PM UTC 25 |
| Finished | Feb 08 06:08:16 PM UTC 25 |
| Peak memory | 217208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=82566817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.usbdev_resume_link_active.82566817 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_resume_link_active/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_rx_crc_err.2352933912 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 155931125 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:07:35 PM UTC 25 |
| Finished | Feb 08 06:07:37 PM UTC 25 |
| Peak memory | 215088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2352933912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbd ev_rx_crc_err.2352933912 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_rx_full.3071623526 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 316071771 ps |
| CPU time | 2.05 seconds |
| Started | Feb 08 06:07:35 PM UTC 25 |
| Finished | Feb 08 06:07:38 PM UTC 25 |
| Peak memory | 217304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3071623526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_ rx_full.3071623526 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_setup_stage.2217066991 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 145009630 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:07:36 PM UTC 25 |
| Finished | Feb 08 06:07:39 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2217066991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usb dev_setup_stage.2217066991 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_setup_trans_ignored.1407778250 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 181126219 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:07:37 PM UTC 25 |
| Finished | Feb 08 06:07:40 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1407778250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.usbdev_setup_trans_ignored.1407778250 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_smoke.2555121968 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 210748489 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:07:37 PM UTC 25 |
| Finished | Feb 08 06:07:40 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2555121968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_sm oke.2555121968 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_spurious_pids_ignored.2383378 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 3813458312 ps |
| CPU time | 120.39 seconds |
| Started | Feb 08 06:07:37 PM UTC 25 |
| Finished | Feb 08 06:09:41 PM UTC 25 |
| Peak memory | 229772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 18.usbdev_spurious_pids_ignored.2383378 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_stall_priority_over_nak.169352419 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 179115530 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:07:39 PM UTC 25 |
| Finished | Feb 08 06:07:41 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=169352419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 18.usbdev_stall_priority_over_nak.169352419 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_stall_trans.1793463072 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 152648817 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:07:39 PM UTC 25 |
| Finished | Feb 08 06:07:41 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1793463072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usb dev_stall_trans.1793463072 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_stream_len_max.829350606 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 918190441 ps |
| CPU time | 4.45 seconds |
| Started | Feb 08 06:07:40 PM UTC 25 |
| Finished | Feb 08 06:07:46 PM UTC 25 |
| Peak memory | 217348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=829350606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.u sbdev_stream_len_max.829350606 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_streaming_out.4232270457 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 1797273887 ps |
| CPU time | 15.55 seconds |
| Started | Feb 08 06:07:40 PM UTC 25 |
| Finished | Feb 08 06:07:57 PM UTC 25 |
| Peak memory | 229708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4232270457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbde v_streaming_out.4232270457 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_timeout_missing_host_handshake.2040854309 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 2938434896 ps |
| CPU time | 35.11 seconds |
| Started | Feb 08 06:07:21 PM UTC 25 |
| Finished | Feb 08 06:07:57 PM UTC 25 |
| Peak memory | 217412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040854309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing_host_handshake.2040854309 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_tx_rx_disruption.3146426666 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 608067293 ps |
| CPU time | 2.03 seconds |
| Started | Feb 08 06:07:41 PM UTC 25 |
| Finished | Feb 08 06:07:45 PM UTC 25 |
| Peak memory | 217180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 146426666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_tx_rx_disruption.3146426666 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/18.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/180.usbdev_endpoint_types.451971682 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 164887833 ps |
| CPU time | 0.84 seconds |
| Started | Feb 08 06:18:40 PM UTC 25 |
| Finished | Feb 08 06:18:53 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451971682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 180.usbdev_endpoint_types.451971682 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/180.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/180.usbdev_tx_rx_disruption.708769287 |
| Short name | T3307 |
| Test name | |
| Test status | |
| Simulation time | 583813267 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:18:40 PM UTC 25 |
| Finished | Feb 08 06:18:54 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 08769287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.usbdev_tx_rx_disruption.708769287 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/180.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/181.usbdev_endpoint_types.3335489112 |
| Short name | T3303 |
| Test name | |
| Test status | |
| Simulation time | 374597325 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:18:40 PM UTC 25 |
| Finished | Feb 08 06:18:53 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335489112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 181.usbdev_endpoint_types.3335489112 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/181.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/181.usbdev_tx_rx_disruption.179688176 |
| Short name | T3302 |
| Test name | |
| Test status | |
| Simulation time | 620574762 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:18:40 PM UTC 25 |
| Finished | Feb 08 06:18:53 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 79688176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.usbdev_tx_rx_disruption.179688176 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/181.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/182.usbdev_endpoint_types.2971805891 |
| Short name | T3301 |
| Test name | |
| Test status | |
| Simulation time | 331490140 ps |
| CPU time | 1.05 seconds |
| Started | Feb 08 06:18:40 PM UTC 25 |
| Finished | Feb 08 06:18:53 PM UTC 25 |
| Peak memory | 214732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971805891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 182.usbdev_endpoint_types.2971805891 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/182.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/182.usbdev_tx_rx_disruption.1581989100 |
| Short name | T3312 |
| Test name | |
| Test status | |
| Simulation time | 556409471 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:18:40 PM UTC 25 |
| Finished | Feb 08 06:18:54 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 581989100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.usbdev_tx_rx_disruption.1581989100 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/182.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/183.usbdev_endpoint_types.753120121 |
| Short name | T3299 |
| Test name | |
| Test status | |
| Simulation time | 236792668 ps |
| CPU time | 0.93 seconds |
| Started | Feb 08 06:18:40 PM UTC 25 |
| Finished | Feb 08 06:18:53 PM UTC 25 |
| Peak memory | 214320 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753120121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 183.usbdev_endpoint_types.753120121 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/183.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/183.usbdev_tx_rx_disruption.1843419562 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 618312568 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:18:40 PM UTC 25 |
| Finished | Feb 08 06:18:54 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 843419562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.usbdev_tx_rx_disruption.1843419562 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/183.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/184.usbdev_endpoint_types.592596947 |
| Short name | T3309 |
| Test name | |
| Test status | |
| Simulation time | 578732986 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:18:41 PM UTC 25 |
| Finished | Feb 08 06:18:54 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592596947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 184.usbdev_endpoint_types.592596947 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/184.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/184.usbdev_tx_rx_disruption.356114245 |
| Short name | T3314 |
| Test name | |
| Test status | |
| Simulation time | 609201313 ps |
| CPU time | 1.74 seconds |
| Started | Feb 08 06:18:41 PM UTC 25 |
| Finished | Feb 08 06:18:54 PM UTC 25 |
| Peak memory | 215168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 56114245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.usbdev_tx_rx_disruption.356114245 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/184.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/185.usbdev_endpoint_types.2054340358 |
| Short name | T3300 |
| Test name | |
| Test status | |
| Simulation time | 247360765 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 06:18:41 PM UTC 25 |
| Finished | Feb 08 06:18:53 PM UTC 25 |
| Peak memory | 215032 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054340358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 185.usbdev_endpoint_types.2054340358 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/185.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/185.usbdev_tx_rx_disruption.1540213231 |
| Short name | T3331 |
| Test name | |
| Test status | |
| Simulation time | 603633947 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:18:41 PM UTC 25 |
| Finished | Feb 08 06:19:04 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 540213231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.usbdev_tx_rx_disruption.1540213231 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/185.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/186.usbdev_endpoint_types.2802942029 |
| Short name | T3380 |
| Test name | |
| Test status | |
| Simulation time | 164815121 ps |
| CPU time | 0.79 seconds |
| Started | Feb 08 06:18:41 PM UTC 25 |
| Finished | Feb 08 06:19:23 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802942029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 186.usbdev_endpoint_types.2802942029 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/186.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/186.usbdev_tx_rx_disruption.2497334506 |
| Short name | T3322 |
| Test name | |
| Test status | |
| Simulation time | 517905908 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:18:41 PM UTC 25 |
| Finished | Feb 08 06:19:03 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 497334506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.usbdev_tx_rx_disruption.2497334506 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/186.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/187.usbdev_endpoint_types.1157033927 |
| Short name | T3306 |
| Test name | |
| Test status | |
| Simulation time | 549466431 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:18:41 PM UTC 25 |
| Finished | Feb 08 06:18:54 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157033927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 187.usbdev_endpoint_types.1157033927 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/187.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/187.usbdev_tx_rx_disruption.3480640564 |
| Short name | T3311 |
| Test name | |
| Test status | |
| Simulation time | 532963373 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:18:41 PM UTC 25 |
| Finished | Feb 08 06:18:54 PM UTC 25 |
| Peak memory | 215340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 480640564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.usbdev_tx_rx_disruption.3480640564 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/187.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/188.usbdev_endpoint_types.1728684179 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 478887023 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:18:41 PM UTC 25 |
| Finished | Feb 08 06:18:54 PM UTC 25 |
| Peak memory | 216352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728684179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 188.usbdev_endpoint_types.1728684179 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/188.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/188.usbdev_tx_rx_disruption.146051723 |
| Short name | T3327 |
| Test name | |
| Test status | |
| Simulation time | 559179207 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:18:41 PM UTC 25 |
| Finished | Feb 08 06:19:04 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 46051723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.usbdev_tx_rx_disruption.146051723 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/188.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/189.usbdev_tx_rx_disruption.2807248237 |
| Short name | T3330 |
| Test name | |
| Test status | |
| Simulation time | 665625347 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:18:41 PM UTC 25 |
| Finished | Feb 08 06:19:04 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 807248237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.usbdev_tx_rx_disruption.2807248237 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/189.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_alert_test.2818008009 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 42522759 ps |
| CPU time | 1.02 seconds |
| Started | Feb 08 06:08:06 PM UTC 25 |
| Finished | Feb 08 06:08:08 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818008009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 19.usbdev_alert_test.2818008009 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_aon_wake_disconnect.916288788 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 9899922522 ps |
| CPU time | 15.65 seconds |
| Started | Feb 08 06:07:41 PM UTC 25 |
| Finished | Feb 08 06:07:59 PM UTC 25 |
| Peak memory | 217572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916288788 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.916288788 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_aon_wake_reset.2025379284 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 13394059727 ps |
| CPU time | 20.68 seconds |
| Started | Feb 08 06:07:43 PM UTC 25 |
| Finished | Feb 08 06:08:05 PM UTC 25 |
| Peak memory | 227776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025379284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.2025379284 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_aon_wake_resume.235075454 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 31432397773 ps |
| CPU time | 51.85 seconds |
| Started | Feb 08 06:07:43 PM UTC 25 |
| Finished | Feb 08 06:08:37 PM UTC 25 |
| Peak memory | 217416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235075454 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.235075454 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_av_buffer.1645930616 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 189076409 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:07:43 PM UTC 25 |
| Finished | Feb 08 06:07:46 PM UTC 25 |
| Peak memory | 215036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1645930616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbde v_av_buffer.1645930616 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_bitstuff_err.3785991194 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 152324364 ps |
| CPU time | 0.87 seconds |
| Started | Feb 08 06:07:43 PM UTC 25 |
| Finished | Feb 08 06:07:45 PM UTC 25 |
| Peak memory | 215084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3785991194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.us bdev_bitstuff_err.3785991194 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_data_toggle_clear.546595331 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 254426312 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:07:44 PM UTC 25 |
| Finished | Feb 08 06:07:47 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=546595331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.usbdev_data_toggle_clear.546595331 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_data_toggle_restore.2184143970 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 597669172 ps |
| CPU time | 2.72 seconds |
| Started | Feb 08 06:07:44 PM UTC 25 |
| Finished | Feb 08 06:07:48 PM UTC 25 |
| Peak memory | 217172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184143970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.2184143970 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_device_address.3169693902 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 30109530335 ps |
| CPU time | 79.63 seconds |
| Started | Feb 08 06:07:45 PM UTC 25 |
| Finished | Feb 08 06:09:07 PM UTC 25 |
| Peak memory | 217424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3169693902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19. usbdev_device_address.3169693902 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_device_timeout.1745631747 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 2246197771 ps |
| CPU time | 14.83 seconds |
| Started | Feb 08 06:07:45 PM UTC 25 |
| Finished | Feb 08 06:08:01 PM UTC 25 |
| Peak memory | 217404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745631747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.1745631747 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_disable_endpoint.2759636877 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 765140474 ps |
| CPU time | 2.57 seconds |
| Started | Feb 08 06:07:45 PM UTC 25 |
| Finished | Feb 08 06:07:49 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2759636877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.usbdev_disable_endpoint.2759636877 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_disconnected.3354209958 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 141919894 ps |
| CPU time | 1.02 seconds |
| Started | Feb 08 06:07:47 PM UTC 25 |
| Finished | Feb 08 06:07:50 PM UTC 25 |
| Peak memory | 215028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3354209958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.us bdev_disconnected.3354209958 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_enable.2306149899 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 86239175 ps |
| CPU time | 0.93 seconds |
| Started | Feb 08 06:07:47 PM UTC 25 |
| Finished | Feb 08 06:07:49 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2306149899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_e nable.2306149899 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_endpoint_access.3496694693 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 781755338 ps |
| CPU time | 2.62 seconds |
| Started | Feb 08 06:07:47 PM UTC 25 |
| Finished | Feb 08 06:07:51 PM UTC 25 |
| Peak memory | 217692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3496694693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19 .usbdev_endpoint_access.3496694693 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_endpoint_types.1191850203 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 374706146 ps |
| CPU time | 2.46 seconds |
| Started | Feb 08 06:07:47 PM UTC 25 |
| Finished | Feb 08 06:07:51 PM UTC 25 |
| Peak memory | 217084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191850203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 19.usbdev_endpoint_types.1191850203 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_fifo_rst.171510281 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 206036709 ps |
| CPU time | 2.04 seconds |
| Started | Feb 08 06:07:47 PM UTC 25 |
| Finished | Feb 08 06:07:51 PM UTC 25 |
| Peak memory | 217348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=171510281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_ fifo_rst.171510281 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_in_iso.939198761 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 215273123 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:07:48 PM UTC 25 |
| Finished | Feb 08 06:07:51 PM UTC 25 |
| Peak memory | 227816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939198761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 19.usbdev_in_iso.939198761 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_in_stall.3333104254 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 177551873 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:07:48 PM UTC 25 |
| Finished | Feb 08 06:07:51 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3333104254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev _in_stall.3333104254 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_in_trans.406074760 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 254025388 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:07:48 PM UTC 25 |
| Finished | Feb 08 06:07:51 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=406074760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_ in_trans.406074760 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_invalid_sync.1811586682 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 3622150798 ps |
| CPU time | 28.17 seconds |
| Started | Feb 08 06:07:47 PM UTC 25 |
| Finished | Feb 08 06:08:17 PM UTC 25 |
| Peak memory | 234368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811586682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.1811586682 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_iso_retraction.1216754154 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 5934754258 ps |
| CPU time | 44.03 seconds |
| Started | Feb 08 06:07:50 PM UTC 25 |
| Finished | Feb 08 06:08:36 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216754154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 19.usbdev_iso_retraction.1216754154 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_link_in_err.2158000065 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 242127870 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:07:50 PM UTC 25 |
| Finished | Feb 08 06:07:52 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2158000065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usb dev_link_in_err.2158000065 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_link_resume.2873927979 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 29734476802 ps |
| CPU time | 53.83 seconds |
| Started | Feb 08 06:07:50 PM UTC 25 |
| Finished | Feb 08 06:08:45 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2873927979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usb dev_link_resume.2873927979 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_link_suspend.2047067441 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 5436200137 ps |
| CPU time | 15.54 seconds |
| Started | Feb 08 06:07:50 PM UTC 25 |
| Finished | Feb 08 06:08:07 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2047067441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.us bdev_link_suspend.2047067441 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_low_speed_traffic.2297601555 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 4418751085 ps |
| CPU time | 42.41 seconds |
| Started | Feb 08 06:07:51 PM UTC 25 |
| Finished | Feb 08 06:08:35 PM UTC 25 |
| Peak memory | 229764 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297601555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 19.usbdev_low_speed_traffic.2297601555 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_max_inter_pkt_delay.546398798 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 2375346082 ps |
| CPU time | 70.49 seconds |
| Started | Feb 08 06:07:51 PM UTC 25 |
| Finished | Feb 08 06:09:04 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546398798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.546398798 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_max_length_in_transaction.3391379831 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 242407104 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:07:51 PM UTC 25 |
| Finished | Feb 08 06:07:54 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391379831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 19.usbdev_max_length_in_transaction.3391379831 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_max_length_out_transaction.2792396441 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 188529895 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:07:53 PM UTC 25 |
| Finished | Feb 08 06:07:56 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2792396441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.2792396441 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_max_non_iso_usb_traffic.335731590 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 1895914970 ps |
| CPU time | 14.33 seconds |
| Started | Feb 08 06:07:53 PM UTC 25 |
| Finished | Feb 08 06:08:08 PM UTC 25 |
| Peak memory | 217376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=335731590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 19.usbdev_max_non_iso_usb_traffic.335731590 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_min_inter_pkt_delay.2847187703 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 2685157446 ps |
| CPU time | 22.37 seconds |
| Started | Feb 08 06:07:53 PM UTC 25 |
| Finished | Feb 08 06:08:16 PM UTC 25 |
| Peak memory | 227772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847187703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.2847187703 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_min_length_in_transaction.2217629640 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 163975999 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:07:53 PM UTC 25 |
| Finished | Feb 08 06:07:55 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217629640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 19.usbdev_min_length_in_transaction.2217629640 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_min_length_out_transaction.1504808983 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 142222130 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:07:53 PM UTC 25 |
| Finished | Feb 08 06:07:55 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1504808983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1504808983 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_out_iso.2660831379 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 188179877 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:07:55 PM UTC 25 |
| Finished | Feb 08 06:07:57 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2660831379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_ out_iso.2660831379 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_out_stall.3263463858 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 167490051 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 06:07:56 PM UTC 25 |
| Finished | Feb 08 06:07:59 PM UTC 25 |
| Peak memory | 216780 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3263463858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbde v_out_stall.3263463858 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_out_trans_nak.1038856481 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 186726588 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:07:56 PM UTC 25 |
| Finished | Feb 08 06:07:59 PM UTC 25 |
| Peak memory | 216856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1038856481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.u sbdev_out_trans_nak.1038856481 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_pending_in_trans.1532224059 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 182441026 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:07:56 PM UTC 25 |
| Finished | Feb 08 06:07:59 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1532224059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.usbdev_pending_in_trans.1532224059 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_phy_config_pinflip.2011706429 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 223777629 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 06:07:56 PM UTC 25 |
| Finished | Feb 08 06:07:59 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011706429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 19.usbdev_phy_config_pinflip.2011706429 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_phy_config_usb_ref_disable.558938179 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 145490130 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:07:58 PM UTC 25 |
| Finished | Feb 08 06:08:00 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=558938179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 19.usbdev_phy_config_usb_ref_disable.558938179 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_phy_pins_sense.2084856922 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 32926325 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:07:58 PM UTC 25 |
| Finished | Feb 08 06:08:00 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2084856922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19. usbdev_phy_pins_sense.2084856922 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_pkt_buffer.3416390787 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 20595061650 ps |
| CPU time | 52.3 seconds |
| Started | Feb 08 06:07:59 PM UTC 25 |
| Finished | Feb 08 06:08:53 PM UTC 25 |
| Peak memory | 227736 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3416390787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbd ev_pkt_buffer.3416390787 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_pkt_received.535162126 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 196328549 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:07:59 PM UTC 25 |
| Finished | Feb 08 06:08:01 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=535162126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usb dev_pkt_received.535162126 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_pkt_sent.4195703097 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 159446009 ps |
| CPU time | 1.23 seconds |
| Started | Feb 08 06:08:00 PM UTC 25 |
| Finished | Feb 08 06:08:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4195703097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev _pkt_sent.4195703097 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_random_length_in_transaction.3450923873 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 210437463 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:08:00 PM UTC 25 |
| Finished | Feb 08 06:08:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3450923873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.u sbdev_random_length_in_transaction.3450923873 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_random_length_out_transaction.913618174 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 164535232 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:08:00 PM UTC 25 |
| Finished | Feb 08 06:08:03 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=913618174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 19.usbdev_random_length_out_transaction.913618174 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_resume_link_active.1490354782 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 20161237435 ps |
| CPU time | 35.18 seconds |
| Started | Feb 08 06:08:00 PM UTC 25 |
| Finished | Feb 08 06:08:37 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1490354782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_resume_link_active.1490354782 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_resume_link_active/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_rx_crc_err.983643655 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 157499938 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:08:01 PM UTC 25 |
| Finished | Feb 08 06:08:03 PM UTC 25 |
| Peak memory | 214708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=983643655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbde v_rx_crc_err.983643655 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_rx_full.3314363408 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 294211120 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 06:08:01 PM UTC 25 |
| Finished | Feb 08 06:08:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3314363408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_ rx_full.3314363408 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_setup_stage.3587794133 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 151404567 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:08:01 PM UTC 25 |
| Finished | Feb 08 06:08:03 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3587794133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usb dev_setup_stage.3587794133 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_setup_trans_ignored.2693851409 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 180659224 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:08:02 PM UTC 25 |
| Finished | Feb 08 06:08:04 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2693851409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.usbdev_setup_trans_ignored.2693851409 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_smoke.1145818176 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 185710646 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:08:03 PM UTC 25 |
| Finished | Feb 08 06:08:06 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1145818176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_sm oke.1145818176 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_spurious_pids_ignored.550387976 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 3102651920 ps |
| CPU time | 23.09 seconds |
| Started | Feb 08 06:08:03 PM UTC 25 |
| Finished | Feb 08 06:08:27 PM UTC 25 |
| Peak memory | 229772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550387976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 19.usbdev_spurious_pids_ignored.550387976 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_stall_priority_over_nak.2958548816 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 147224400 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:08:04 PM UTC 25 |
| Finished | Feb 08 06:08:07 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2958548816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 19.usbdev_stall_priority_over_nak.2958548816 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_stall_trans.1914575512 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 189035032 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 06:08:04 PM UTC 25 |
| Finished | Feb 08 06:08:07 PM UTC 25 |
| Peak memory | 215080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1914575512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usb dev_stall_trans.1914575512 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_stream_len_max.3241153756 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 323374041 ps |
| CPU time | 2.08 seconds |
| Started | Feb 08 06:08:04 PM UTC 25 |
| Finished | Feb 08 06:08:08 PM UTC 25 |
| Peak memory | 217280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3241153756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19. usbdev_stream_len_max.3241153756 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_streaming_out.3401813149 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 1564074221 ps |
| CPU time | 15.43 seconds |
| Started | Feb 08 06:08:04 PM UTC 25 |
| Finished | Feb 08 06:08:21 PM UTC 25 |
| Peak memory | 229888 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3401813149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbde v_streaming_out.3401813149 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_timeout_missing_host_handshake.2408613446 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 739666995 ps |
| CPU time | 20.73 seconds |
| Started | Feb 08 06:07:45 PM UTC 25 |
| Finished | Feb 08 06:08:08 PM UTC 25 |
| Peak memory | 217548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408613446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing_host_handshake.2408613446 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_tx_rx_disruption.1851603689 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 582354417 ps |
| CPU time | 1.96 seconds |
| Started | Feb 08 06:08:04 PM UTC 25 |
| Finished | Feb 08 06:08:08 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 851603689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_tx_rx_disruption.1851603689 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/19.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/190.usbdev_endpoint_types.3450537705 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 426593951 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 06:18:41 PM UTC 25 |
| Finished | Feb 08 06:19:03 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450537705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 190.usbdev_endpoint_types.3450537705 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/190.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/190.usbdev_tx_rx_disruption.2881858620 |
| Short name | T3325 |
| Test name | |
| Test status | |
| Simulation time | 450436513 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:18:41 PM UTC 25 |
| Finished | Feb 08 06:19:04 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 881858620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.usbdev_tx_rx_disruption.2881858620 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/190.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/191.usbdev_endpoint_types.2057343147 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 487806409 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:18:41 PM UTC 25 |
| Finished | Feb 08 06:19:04 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057343147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 191.usbdev_endpoint_types.2057343147 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/191.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/191.usbdev_tx_rx_disruption.1361265961 |
| Short name | T3326 |
| Test name | |
| Test status | |
| Simulation time | 504390551 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:18:41 PM UTC 25 |
| Finished | Feb 08 06:19:04 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 361265961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.usbdev_tx_rx_disruption.1361265961 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/191.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/192.usbdev_endpoint_types.3003488296 |
| Short name | T3293 |
| Test name | |
| Test status | |
| Simulation time | 280474251 ps |
| CPU time | 1 seconds |
| Started | Feb 08 06:18:43 PM UTC 25 |
| Finished | Feb 08 06:18:49 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003488296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 192.usbdev_endpoint_types.3003488296 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/192.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/192.usbdev_tx_rx_disruption.3812701860 |
| Short name | T3296 |
| Test name | |
| Test status | |
| Simulation time | 508155243 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:18:43 PM UTC 25 |
| Finished | Feb 08 06:18:49 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 812701860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.usbdev_tx_rx_disruption.3812701860 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/192.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/193.usbdev_endpoint_types.119349534 |
| Short name | T3292 |
| Test name | |
| Test status | |
| Simulation time | 317833090 ps |
| CPU time | 0.93 seconds |
| Started | Feb 08 06:18:43 PM UTC 25 |
| Finished | Feb 08 06:18:49 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119349534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 193.usbdev_endpoint_types.119349534 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/193.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/193.usbdev_tx_rx_disruption.1414857891 |
| Short name | T3295 |
| Test name | |
| Test status | |
| Simulation time | 464251747 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:18:43 PM UTC 25 |
| Finished | Feb 08 06:18:49 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 414857891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.usbdev_tx_rx_disruption.1414857891 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/193.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/194.usbdev_endpoint_types.2235021023 |
| Short name | T3294 |
| Test name | |
| Test status | |
| Simulation time | 348439485 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:18:43 PM UTC 25 |
| Finished | Feb 08 06:18:49 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235021023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 194.usbdev_endpoint_types.2235021023 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/194.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/194.usbdev_tx_rx_disruption.2989971465 |
| Short name | T3297 |
| Test name | |
| Test status | |
| Simulation time | 650784848 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:18:43 PM UTC 25 |
| Finished | Feb 08 06:18:50 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 989971465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.usbdev_tx_rx_disruption.2989971465 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/194.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/195.usbdev_endpoint_types.2272829114 |
| Short name | T3304 |
| Test name | |
| Test status | |
| Simulation time | 424721079 ps |
| CPU time | 1.23 seconds |
| Started | Feb 08 06:18:44 PM UTC 25 |
| Finished | Feb 08 06:18:53 PM UTC 25 |
| Peak memory | 214640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272829114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 195.usbdev_endpoint_types.2272829114 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/195.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/195.usbdev_tx_rx_disruption.60064406 |
| Short name | T3305 |
| Test name | |
| Test status | |
| Simulation time | 518443507 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:18:45 PM UTC 25 |
| Finished | Feb 08 06:18:54 PM UTC 25 |
| Peak memory | 214312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6 0064406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.usbdev_tx_rx_disruption.60064406 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/195.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/196.usbdev_tx_rx_disruption.3516466480 |
| Short name | T3308 |
| Test name | |
| Test status | |
| Simulation time | 482056141 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:18:45 PM UTC 25 |
| Finished | Feb 08 06:18:54 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 516466480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.usbdev_tx_rx_disruption.3516466480 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/196.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/197.usbdev_tx_rx_disruption.396255908 |
| Short name | T3310 |
| Test name | |
| Test status | |
| Simulation time | 530312312 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:18:45 PM UTC 25 |
| Finished | Feb 08 06:18:54 PM UTC 25 |
| Peak memory | 216628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 96255908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.usbdev_tx_rx_disruption.396255908 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/197.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/198.usbdev_tx_rx_disruption.94624367 |
| Short name | T3318 |
| Test name | |
| Test status | |
| Simulation time | 529758918 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:18:49 PM UTC 25 |
| Finished | Feb 08 06:18:59 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 4624367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.usbdev_tx_rx_disruption.94624367 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/198.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/199.usbdev_endpoint_types.1384165113 |
| Short name | T3316 |
| Test name | |
| Test status | |
| Simulation time | 305254227 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 06:18:49 PM UTC 25 |
| Finished | Feb 08 06:18:58 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384165113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 199.usbdev_endpoint_types.1384165113 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/199.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_alert_test.3465044613 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 42060063 ps |
| CPU time | 0.92 seconds |
| Started | Feb 08 05:57:26 PM UTC 25 |
| Finished | Feb 08 05:57:28 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465044613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.usbdev_alert_test.3465044613 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_disconnect.2500878483 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 6289222860 ps |
| CPU time | 14.7 seconds |
| Started | Feb 08 05:56:12 PM UTC 25 |
| Finished | Feb 08 05:56:28 PM UTC 25 |
| Peak memory | 227788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500878483 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.2500878483 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_reset.2049867765 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 15015178386 ps |
| CPU time | 23.93 seconds |
| Started | Feb 08 05:56:12 PM UTC 25 |
| Finished | Feb 08 05:56:37 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049867765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.2049867765 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_resume.4158584560 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 23515391732 ps |
| CPU time | 60.87 seconds |
| Started | Feb 08 05:56:12 PM UTC 25 |
| Finished | Feb 08 05:57:14 PM UTC 25 |
| Peak memory | 227648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158584560 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.4158584560 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_av_buffer.3067056108 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 168744136 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 05:56:12 PM UTC 25 |
| Finished | Feb 08 05:56:14 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3067056108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev _av_buffer.3067056108 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_av_empty.2003377890 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 176889032 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 05:56:13 PM UTC 25 |
| Finished | Feb 08 05:56:15 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2003377890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ av_empty.2003377890 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_av_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_bitstuff_err.2816982579 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 158803440 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 05:56:16 PM UTC 25 |
| Finished | Feb 08 05:56:18 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2816982579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usb dev_bitstuff_err.2816982579 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_data_toggle_clear.1477401714 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 288060219 ps |
| CPU time | 2.01 seconds |
| Started | Feb 08 05:56:16 PM UTC 25 |
| Finished | Feb 08 05:56:19 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1477401714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.1477401714 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_data_toggle_restore.1754906907 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 775867418 ps |
| CPU time | 2.43 seconds |
| Started | Feb 08 05:56:17 PM UTC 25 |
| Finished | Feb 08 05:56:20 PM UTC 25 |
| Peak memory | 217376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754906907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.1754906907 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_device_address.358559846 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 13633545458 ps |
| CPU time | 44.2 seconds |
| Started | Feb 08 05:56:17 PM UTC 25 |
| Finished | Feb 08 05:57:03 PM UTC 25 |
| Peak memory | 217476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=358559846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.us bdev_device_address.358559846 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_device_timeout.4057064730 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 2045891925 ps |
| CPU time | 22.05 seconds |
| Started | Feb 08 05:56:19 PM UTC 25 |
| Finished | Feb 08 05:56:42 PM UTC 25 |
| Peak memory | 217416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057064730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.4057064730 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_disable_endpoint.411843786 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 1046509968 ps |
| CPU time | 2.33 seconds |
| Started | Feb 08 05:56:20 PM UTC 25 |
| Finished | Feb 08 05:56:23 PM UTC 25 |
| Peak memory | 217148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=411843786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2. usbdev_disable_endpoint.411843786 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_disconnected.1823469566 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 149963006 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 05:56:21 PM UTC 25 |
| Finished | Feb 08 05:56:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1823469566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usb dev_disconnected.1823469566 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_enable.2395747462 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 42526201 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 05:56:21 PM UTC 25 |
| Finished | Feb 08 05:56:23 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2395747462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_en able.2395747462 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_endpoint_access.2998443745 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 818399297 ps |
| CPU time | 2.86 seconds |
| Started | Feb 08 05:56:23 PM UTC 25 |
| Finished | Feb 08 05:56:27 PM UTC 25 |
| Peak memory | 217308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2998443745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2. usbdev_endpoint_access.2998443745 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_endpoint_types.3595814047 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 347637793 ps |
| CPU time | 1.76 seconds |
| Started | Feb 08 05:56:25 PM UTC 25 |
| Finished | Feb 08 05:56:27 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595814047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 2.usbdev_endpoint_types.3595814047 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_fifo_rst.2062503807 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 167559759 ps |
| CPU time | 2.31 seconds |
| Started | Feb 08 05:56:25 PM UTC 25 |
| Finished | Feb 08 05:56:28 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2062503807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ fifo_rst.2062503807 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_freq_hiclk.574725267 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 121181840384 ps |
| CPU time | 305.81 seconds |
| Started | Feb 08 05:56:25 PM UTC 25 |
| Finished | Feb 08 06:01:35 PM UTC 25 |
| Peak memory | 217608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574725267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase _delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 2.usbdev_freq_hiclk.574725267 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_freq_hiclk/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_freq_hiclk_max.2130388735 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 106318188630 ps |
| CPU time | 228.4 seconds |
| Started | Feb 08 05:56:27 PM UTC 25 |
| Finished | Feb 08 06:00:19 PM UTC 25 |
| Peak memory | 217708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_track ing=1 +reset_recovery=1 +usb_freq_delta=+120000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2130388735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hi clk_max.2130388735 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_freq_hiclk_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_freq_loclk.2270123269 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 111097604404 ps |
| CPU time | 216.27 seconds |
| Started | Feb 08 05:56:28 PM UTC 25 |
| Finished | Feb 08 06:00:08 PM UTC 25 |
| Peak memory | 217480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270123269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phas e_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 2.usbdev_freq_loclk.2270123269 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_freq_loclk/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_freq_loclk_max.1365063731 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 89981355854 ps |
| CPU time | 230.72 seconds |
| Started | Feb 08 05:56:28 PM UTC 25 |
| Finished | Feb 08 06:00:23 PM UTC 25 |
| Peak memory | 217424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+1 20000 +reset_recovery=1 +usb_freq_delta=-120000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1365063731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_lo clk_max.1365063731 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_freq_loclk_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_freq_phase.3565284195 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 110170949545 ps |
| CPU time | 211.71 seconds |
| Started | Feb 08 05:56:28 PM UTC 25 |
| Finished | Feb 08 06:00:03 PM UTC 25 |
| Peak memory | 217416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3565284195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .usbdev_freq_phase.3565284195 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_freq_phase/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_in_iso.2509647727 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 238843827 ps |
| CPU time | 2.23 seconds |
| Started | Feb 08 05:56:29 PM UTC 25 |
| Finished | Feb 08 05:56:33 PM UTC 25 |
| Peak memory | 227556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509647727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 2.usbdev_in_iso.2509647727 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_in_stall.2118417429 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 150812219 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 05:56:33 PM UTC 25 |
| Finished | Feb 08 05:56:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2118417429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ in_stall.2118417429 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_in_trans.1752011967 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 217190929 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 05:56:37 PM UTC 25 |
| Finished | Feb 08 05:56:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1752011967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ in_trans.1752011967 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_invalid_sync.2720609980 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 4610095548 ps |
| CPU time | 38 seconds |
| Started | Feb 08 05:56:28 PM UTC 25 |
| Finished | Feb 08 05:57:08 PM UTC 25 |
| Peak memory | 234432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720609980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.2720609980 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_iso_retraction.1161851330 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3288119974 ps |
| CPU time | 36.48 seconds |
| Started | Feb 08 05:56:38 PM UTC 25 |
| Finished | Feb 08 05:57:16 PM UTC 25 |
| Peak memory | 217476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161851330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 2.usbdev_iso_retraction.1161851330 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_link_in_err.3660554967 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 174913292 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 05:56:38 PM UTC 25 |
| Finished | Feb 08 05:56:41 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3660554967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbd ev_link_in_err.3660554967 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_link_resume.839340452 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 9162169350 ps |
| CPU time | 27.59 seconds |
| Started | Feb 08 05:56:39 PM UTC 25 |
| Finished | Feb 08 05:57:08 PM UTC 25 |
| Peak memory | 227784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=839340452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbde v_link_resume.839340452 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_max_inter_pkt_delay.3152205880 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 2079840072 ps |
| CPU time | 64.82 seconds |
| Started | Feb 08 05:56:42 PM UTC 25 |
| Finished | Feb 08 05:57:48 PM UTC 25 |
| Peak memory | 229644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152205880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.3152205880 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_max_length_in_transaction.3976526668 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 243731306 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 05:56:43 PM UTC 25 |
| Finished | Feb 08 05:56:46 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976526668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.usbdev_max_length_in_transaction.3976526668 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_max_length_out_transaction.572698680 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 270749896 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 05:56:43 PM UTC 25 |
| Finished | Feb 08 05:56:46 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=572698680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 2.usbdev_max_length_out_transaction.572698680 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_max_non_iso_usb_traffic.3822771577 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 3020786106 ps |
| CPU time | 34.06 seconds |
| Started | Feb 08 05:56:46 PM UTC 25 |
| Finished | Feb 08 05:57:22 PM UTC 25 |
| Peak memory | 229708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3822771577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.usbdev_max_non_iso_usb_traffic.3822771577 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_max_usb_traffic.1059005144 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 3127300290 ps |
| CPU time | 29.93 seconds |
| Started | Feb 08 05:56:47 PM UTC 25 |
| Finished | Feb 08 05:57:18 PM UTC 25 |
| Peak memory | 227712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059005144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_ traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 2.usbdev_max_usb_traffic.1059005144 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_min_inter_pkt_delay.346971478 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 2556214598 ps |
| CPU time | 78.72 seconds |
| Started | Feb 08 05:56:49 PM UTC 25 |
| Finished | Feb 08 05:58:09 PM UTC 25 |
| Peak memory | 227724 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346971478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usb dev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.346971478 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_min_length_in_transaction.3642664762 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 190136651 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 05:56:49 PM UTC 25 |
| Finished | Feb 08 05:56:51 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642664762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.usbdev_min_length_in_transaction.3642664762 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_min_length_out_transaction.456257790 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 174620228 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 05:56:52 PM UTC 25 |
| Finished | Feb 08 05:56:55 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=456257790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 2.usbdev_min_length_out_transaction.456257790 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_nak_trans.154359969 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 220975542 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 05:56:55 PM UTC 25 |
| Finished | Feb 08 05:56:58 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=154359969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ nak_trans.154359969 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_out_iso.1411027050 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 184968022 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 05:56:59 PM UTC 25 |
| Finished | Feb 08 05:57:02 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1411027050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_o ut_iso.1411027050 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_out_stall.1865695340 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 200443363 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 05:56:59 PM UTC 25 |
| Finished | Feb 08 05:57:02 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1865695340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev _out_stall.1865695340 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_out_trans_nak.4228414946 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 159245217 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 05:57:02 PM UTC 25 |
| Finished | Feb 08 05:57:05 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4228414946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.us bdev_out_trans_nak.4228414946 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_pending_in_trans.2647925834 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 151391918 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 05:57:02 PM UTC 25 |
| Finished | Feb 08 05:57:05 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2647925834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .usbdev_pending_in_trans.2647925834 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_pinflip.2393526984 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 284653075 ps |
| CPU time | 1.99 seconds |
| Started | Feb 08 05:57:04 PM UTC 25 |
| Finished | Feb 08 05:57:07 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393526984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.usbdev_phy_config_pinflip.2393526984 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_rand_bus_type.3372920009 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 235856083 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 05:57:07 PM UTC 25 |
| Finished | Feb 08 05:57:09 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3372920009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 2.usbdev_phy_config_rand_bus_type.3372920009 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_phy_config_rand_bus_type/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_usb_ref_disable.3692146393 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 153664332 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 05:57:07 PM UTC 25 |
| Finished | Feb 08 05:57:09 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3692146393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.3692146393 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_phy_pins_sense.1962154343 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 33000321 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 05:57:07 PM UTC 25 |
| Finished | Feb 08 05:57:09 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1962154343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.u sbdev_phy_pins_sense.1962154343 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_buffer.1438580005 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 12961616185 ps |
| CPU time | 49.36 seconds |
| Started | Feb 08 05:57:08 PM UTC 25 |
| Finished | Feb 08 05:57:59 PM UTC 25 |
| Peak memory | 227872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1438580005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbde v_pkt_buffer.1438580005 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_received.2219071802 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 185661113 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 05:57:09 PM UTC 25 |
| Finished | Feb 08 05:57:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2219071802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usb dev_pkt_received.2219071802 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_sent.1482668024 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 171981636 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 05:57:09 PM UTC 25 |
| Finished | Feb 08 05:57:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1482668024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ pkt_sent.1482668024 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_rand_bus_disconnects.2053965879 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 5625062765 ps |
| CPU time | 60.65 seconds |
| Started | Feb 08 05:57:10 PM UTC 25 |
| Finished | Feb 08 05:58:13 PM UTC 25 |
| Peak memory | 234424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053965879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_ TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.2053965879 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_rand_bus_disconnects/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_rand_bus_resets.4082017388 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 6115387502 ps |
| CPU time | 42.42 seconds |
| Started | Feb 08 05:57:12 PM UTC 25 |
| Finished | Feb 08 05:57:56 PM UTC 25 |
| Peak memory | 229904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082017388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.usbdev_rand_bus_resets.4082017388 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_rand_bus_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_rand_suspends.2080285578 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 9894170065 ps |
| CPU time | 52.97 seconds |
| Started | Feb 08 05:57:13 PM UTC 25 |
| Finished | Feb 08 05:58:07 PM UTC 25 |
| Peak memory | 229912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080285578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_ TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.2080285578 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_rand_suspends/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_random_length_in_transaction.960970420 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 234582388 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 05:57:10 PM UTC 25 |
| Finished | Feb 08 05:57:13 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=960970420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usb dev_random_length_in_transaction.960970420 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_random_length_out_transaction.856470798 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 184607952 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 05:57:10 PM UTC 25 |
| Finished | Feb 08 05:57:13 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=856470798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.usbdev_random_length_out_transaction.856470798 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_resume_link_active.3062069622 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 20196426609 ps |
| CPU time | 59.09 seconds |
| Started | Feb 08 05:57:13 PM UTC 25 |
| Finished | Feb 08 05:58:14 PM UTC 25 |
| Peak memory | 217212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3062069622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_resume_link_active.3062069622 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_resume_link_active/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_rx_crc_err.2052938912 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 174399968 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 05:57:14 PM UTC 25 |
| Finished | Feb 08 05:57:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2052938912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbde v_rx_crc_err.2052938912 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_rx_full.1229274263 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 317208721 ps |
| CPU time | 2.09 seconds |
| Started | Feb 08 05:57:14 PM UTC 25 |
| Finished | Feb 08 05:57:17 PM UTC 25 |
| Peak memory | 217172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1229274263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_r x_full.1229274263 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_rx_pid_err.516250462 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 158683616 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 05:57:15 PM UTC 25 |
| Finished | Feb 08 05:57:18 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=516250462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev _rx_pid_err.516250462 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_rx_pid_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_sec_cm.2938869513 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 281520018 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 05:57:25 PM UTC 25 |
| Finished | Feb 08 05:57:28 PM UTC 25 |
| Peak memory | 249524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938869513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 2.usbdev_sec_cm.2938869513 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_setup_priority.3085960423 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 417638040 ps |
| CPU time | 2.12 seconds |
| Started | Feb 08 05:57:17 PM UTC 25 |
| Finished | Feb 08 05:57:21 PM UTC 25 |
| Peak memory | 217168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3085960423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.u sbdev_setup_priority.3085960423 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_setup_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_setup_priority_over_stall_response.1487721355 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 174972896 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 05:57:17 PM UTC 25 |
| Finished | Feb 08 05:57:20 PM UTC 25 |
| Peak memory | 214740 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1487721355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_respons e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 2.usbdev_setup_priority_over_stall_response.1487721355 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_setup_priority_over_stall_response/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_setup_stage.2128037715 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 148240958 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 05:57:17 PM UTC 25 |
| Finished | Feb 08 05:57:20 PM UTC 25 |
| Peak memory | 214648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2128037715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbd ev_setup_stage.2128037715 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_setup_trans_ignored.1364179915 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 142016655 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 05:57:19 PM UTC 25 |
| Finished | Feb 08 05:57:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1364179915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.usbdev_setup_trans_ignored.1364179915 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_smoke.296834752 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 206272616 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 05:57:19 PM UTC 25 |
| Finished | Feb 08 05:57:22 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=296834752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smok e.296834752 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_spurious_pids_ignored.1865483908 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 3057262477 ps |
| CPU time | 31.73 seconds |
| Started | Feb 08 05:57:19 PM UTC 25 |
| Finished | Feb 08 05:57:52 PM UTC 25 |
| Peak memory | 229716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865483908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 2.usbdev_spurious_pids_ignored.1865483908 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_stall_priority_over_nak.1054452167 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 229693745 ps |
| CPU time | 1.82 seconds |
| Started | Feb 08 05:57:21 PM UTC 25 |
| Finished | Feb 08 05:57:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1054452167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.usbdev_stall_priority_over_nak.1054452167 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_stall_trans.811033114 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 188641674 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 05:57:21 PM UTC 25 |
| Finished | Feb 08 05:57:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=811033114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbde v_stall_trans.811033114 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_stream_len_max.387864103 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 1220898813 ps |
| CPU time | 5.44 seconds |
| Started | Feb 08 05:57:22 PM UTC 25 |
| Finished | Feb 08 05:57:29 PM UTC 25 |
| Peak memory | 217364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=387864103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.us bdev_stream_len_max.387864103 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_streaming_out.3767894376 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 3100150287 ps |
| CPU time | 38.57 seconds |
| Started | Feb 08 05:57:22 PM UTC 25 |
| Finished | Feb 08 05:58:02 PM UTC 25 |
| Peak memory | 227708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3767894376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev _streaming_out.3767894376 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_stress_usb_traffic.2059672252 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 5913677493 ps |
| CPU time | 78.98 seconds |
| Started | Feb 08 05:57:23 PM UTC 25 |
| Finished | Feb 08 05:58:44 PM UTC 25 |
| Peak memory | 227956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059672252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM _TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.2059672252 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_stress_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_timeout_missing_host_handshake.3153796782 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 2922036639 ps |
| CPU time | 26.11 seconds |
| Started | Feb 08 05:56:20 PM UTC 25 |
| Finished | Feb 08 05:56:47 PM UTC 25 |
| Peak memory | 217496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153796782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host_handshake.3153796782 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/2.usbdev_tx_rx_disruption.3665345447 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 574341997 ps |
| CPU time | 2.86 seconds |
| Started | Feb 08 05:57:24 PM UTC 25 |
| Finished | Feb 08 05:57:28 PM UTC 25 |
| Peak memory | 217116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 665345447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_tx_rx_disruption.3665345447 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/2.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_alert_test.3690029348 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 31599171 ps |
| CPU time | 0.98 seconds |
| Started | Feb 08 06:08:30 PM UTC 25 |
| Finished | Feb 08 06:08:32 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690029348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 20.usbdev_alert_test.3690029348 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_aon_wake_disconnect.1030854733 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 8958850830 ps |
| CPU time | 12.25 seconds |
| Started | Feb 08 06:08:06 PM UTC 25 |
| Finished | Feb 08 06:08:19 PM UTC 25 |
| Peak memory | 217444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030854733 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.1030854733 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_aon_wake_reset.2953101104 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 14231826191 ps |
| CPU time | 20.32 seconds |
| Started | Feb 08 06:08:07 PM UTC 25 |
| Finished | Feb 08 06:08:29 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953101104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.2953101104 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_aon_wake_resume.3934436725 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 23296564621 ps |
| CPU time | 34.24 seconds |
| Started | Feb 08 06:08:07 PM UTC 25 |
| Finished | Feb 08 06:08:43 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934436725 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.3934436725 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_av_buffer.2108853756 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 144343636 ps |
| CPU time | 0.99 seconds |
| Started | Feb 08 06:08:07 PM UTC 25 |
| Finished | Feb 08 06:08:09 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2108853756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbde v_av_buffer.2108853756 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_bitstuff_err.1731494257 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 167815382 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:08:08 PM UTC 25 |
| Finished | Feb 08 06:08:11 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1731494257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.us bdev_bitstuff_err.1731494257 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_data_toggle_clear.1657438096 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 170241152 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 06:08:08 PM UTC 25 |
| Finished | Feb 08 06:08:11 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1657438096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.1657438096 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_data_toggle_restore.706658002 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 871798459 ps |
| CPU time | 3.79 seconds |
| Started | Feb 08 06:08:08 PM UTC 25 |
| Finished | Feb 08 06:08:13 PM UTC 25 |
| Peak memory | 217316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706658002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_t oggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.706658002 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_device_address.205171010 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 33146690764 ps |
| CPU time | 57.45 seconds |
| Started | Feb 08 06:08:09 PM UTC 25 |
| Finished | Feb 08 06:09:08 PM UTC 25 |
| Peak memory | 217476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=205171010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.u sbdev_device_address.205171010 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_device_timeout.2473200272 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 1292108064 ps |
| CPU time | 29.1 seconds |
| Started | Feb 08 06:08:09 PM UTC 25 |
| Finished | Feb 08 06:08:39 PM UTC 25 |
| Peak memory | 217540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473200272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.2473200272 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_disable_endpoint.2344437818 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 562631305 ps |
| CPU time | 2.03 seconds |
| Started | Feb 08 06:08:10 PM UTC 25 |
| Finished | Feb 08 06:08:13 PM UTC 25 |
| Peak memory | 217000 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2344437818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.usbdev_disable_endpoint.2344437818 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_disconnected.3677578312 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 144809005 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:08:10 PM UTC 25 |
| Finished | Feb 08 06:08:12 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3677578312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.us bdev_disconnected.3677578312 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_enable.3157337437 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 48592811 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:08:10 PM UTC 25 |
| Finished | Feb 08 06:08:12 PM UTC 25 |
| Peak memory | 214756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3157337437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_e nable.3157337437 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_endpoint_access.39530518 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 776207170 ps |
| CPU time | 3.24 seconds |
| Started | Feb 08 06:08:10 PM UTC 25 |
| Finished | Feb 08 06:08:14 PM UTC 25 |
| Peak memory | 217588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=39530518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.u sbdev_endpoint_access.39530518 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_endpoint_types.1824051004 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 753365829 ps |
| CPU time | 2.16 seconds |
| Started | Feb 08 06:08:10 PM UTC 25 |
| Finished | Feb 08 06:08:13 PM UTC 25 |
| Peak memory | 217276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824051004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 20.usbdev_endpoint_types.1824051004 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_fifo_rst.3182688724 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 313323577 ps |
| CPU time | 3.73 seconds |
| Started | Feb 08 06:08:12 PM UTC 25 |
| Finished | Feb 08 06:08:17 PM UTC 25 |
| Peak memory | 217288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3182688724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev _fifo_rst.3182688724 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_in_iso.851415235 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 297201511 ps |
| CPU time | 2.25 seconds |
| Started | Feb 08 06:08:12 PM UTC 25 |
| Finished | Feb 08 06:08:15 PM UTC 25 |
| Peak memory | 227624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851415235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 20.usbdev_in_iso.851415235 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_in_stall.3210929669 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 162492342 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:08:13 PM UTC 25 |
| Finished | Feb 08 06:08:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3210929669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev _in_stall.3210929669 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_in_trans.1560428509 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 199105659 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:08:13 PM UTC 25 |
| Finished | Feb 08 06:08:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1560428509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev _in_trans.1560428509 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_invalid_sync.890413654 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 4105650657 ps |
| CPU time | 113.71 seconds |
| Started | Feb 08 06:08:12 PM UTC 25 |
| Finished | Feb 08 06:10:08 PM UTC 25 |
| Peak memory | 227924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890413654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.890413654 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_iso_retraction.3271868880 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 14962097222 ps |
| CPU time | 99.23 seconds |
| Started | Feb 08 06:08:14 PM UTC 25 |
| Finished | Feb 08 06:09:56 PM UTC 25 |
| Peak memory | 217356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271868880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 20.usbdev_iso_retraction.3271868880 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_link_in_err.1953247161 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 200862076 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:08:14 PM UTC 25 |
| Finished | Feb 08 06:08:17 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1953247161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usb dev_link_in_err.1953247161 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_link_resume.2917252126 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 25646956513 ps |
| CPU time | 54.19 seconds |
| Started | Feb 08 06:08:14 PM UTC 25 |
| Finished | Feb 08 06:09:10 PM UTC 25 |
| Peak memory | 227664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2917252126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usb dev_link_resume.2917252126 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_link_suspend.2763706533 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 10445055308 ps |
| CPU time | 24.3 seconds |
| Started | Feb 08 06:08:16 PM UTC 25 |
| Finished | Feb 08 06:08:41 PM UTC 25 |
| Peak memory | 216712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2763706533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.us bdev_link_suspend.2763706533 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_low_speed_traffic.2155902329 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 3996175199 ps |
| CPU time | 34.53 seconds |
| Started | Feb 08 06:08:16 PM UTC 25 |
| Finished | Feb 08 06:08:52 PM UTC 25 |
| Peak memory | 231240 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155902329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 20.usbdev_low_speed_traffic.2155902329 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_max_inter_pkt_delay.1285832260 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 3987756564 ps |
| CPU time | 40.93 seconds |
| Started | Feb 08 06:08:16 PM UTC 25 |
| Finished | Feb 08 06:08:58 PM UTC 25 |
| Peak memory | 229688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285832260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.1285832260 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_max_length_in_transaction.2140919114 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 246922286 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:08:17 PM UTC 25 |
| Finished | Feb 08 06:08:20 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140919114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 20.usbdev_max_length_in_transaction.2140919114 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_max_length_out_transaction.2659142101 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 180445402 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:08:17 PM UTC 25 |
| Finished | Feb 08 06:08:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2659142101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2659142101 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_max_non_iso_usb_traffic.3752404269 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 2630253424 ps |
| CPU time | 22.12 seconds |
| Started | Feb 08 06:08:17 PM UTC 25 |
| Finished | Feb 08 06:08:41 PM UTC 25 |
| Peak memory | 234368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3752404269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 20.usbdev_max_non_iso_usb_traffic.3752404269 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_min_inter_pkt_delay.333574330 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 2488889188 ps |
| CPU time | 26.08 seconds |
| Started | Feb 08 06:08:18 PM UTC 25 |
| Finished | Feb 08 06:08:45 PM UTC 25 |
| Peak memory | 229780 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333574330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usb dev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.333574330 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_min_length_in_transaction.2239939273 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 183359512 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:08:18 PM UTC 25 |
| Finished | Feb 08 06:08:20 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239939273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 20.usbdev_min_length_in_transaction.2239939273 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_min_length_out_transaction.4198947504 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 191376585 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:08:18 PM UTC 25 |
| Finished | Feb 08 06:08:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4198947504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.4198947504 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_nak_trans.3608471353 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 190056724 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:08:19 PM UTC 25 |
| Finished | Feb 08 06:08:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3608471353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbde v_nak_trans.3608471353 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_out_iso.2577679485 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 193604031 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:08:19 PM UTC 25 |
| Finished | Feb 08 06:08:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2577679485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_ out_iso.2577679485 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_out_stall.2423114746 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 198889542 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:08:20 PM UTC 25 |
| Finished | Feb 08 06:08:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2423114746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbde v_out_stall.2423114746 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_out_trans_nak.4096359973 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 175627635 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:08:21 PM UTC 25 |
| Finished | Feb 08 06:08:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4096359973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.u sbdev_out_trans_nak.4096359973 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_pending_in_trans.4143243260 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 150132107 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:08:21 PM UTC 25 |
| Finished | Feb 08 06:08:24 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4143243260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.usbdev_pending_in_trans.4143243260 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_phy_config_pinflip.1630820521 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 196085047 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:08:21 PM UTC 25 |
| Finished | Feb 08 06:08:24 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630820521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 20.usbdev_phy_config_pinflip.1630820521 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_phy_config_usb_ref_disable.2178566262 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 164519563 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:08:21 PM UTC 25 |
| Finished | Feb 08 06:08:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2178566262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.2178566262 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_phy_pins_sense.2702766236 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 39512923 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 06:08:23 PM UTC 25 |
| Finished | Feb 08 06:08:25 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2702766236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20. usbdev_phy_pins_sense.2702766236 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_pkt_buffer.183207716 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 15411649858 ps |
| CPU time | 51.98 seconds |
| Started | Feb 08 06:08:23 PM UTC 25 |
| Finished | Feb 08 06:09:16 PM UTC 25 |
| Peak memory | 227672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=183207716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbde v_pkt_buffer.183207716 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_pkt_received.17091462 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 200776651 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:08:23 PM UTC 25 |
| Finished | Feb 08 06:08:26 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=17091462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbd ev_pkt_received.17091462 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_pkt_sent.2215971216 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 298327380 ps |
| CPU time | 1.8 seconds |
| Started | Feb 08 06:08:23 PM UTC 25 |
| Finished | Feb 08 06:08:26 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2215971216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev _pkt_sent.2215971216 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_random_length_in_transaction.3944172441 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 234328989 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:08:25 PM UTC 25 |
| Finished | Feb 08 06:08:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3944172441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.u sbdev_random_length_in_transaction.3944172441 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_random_length_out_transaction.779043304 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 191760589 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:08:25 PM UTC 25 |
| Finished | Feb 08 06:08:28 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=779043304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 20.usbdev_random_length_out_transaction.779043304 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_rx_crc_err.2309083858 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 168772393 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:08:25 PM UTC 25 |
| Finished | Feb 08 06:08:28 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2309083858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbd ev_rx_crc_err.2309083858 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_rx_full.3184192614 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 403399539 ps |
| CPU time | 2.29 seconds |
| Started | Feb 08 06:08:25 PM UTC 25 |
| Finished | Feb 08 06:08:29 PM UTC 25 |
| Peak memory | 217112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3184192614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_ rx_full.3184192614 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_setup_stage.2998074577 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 178688477 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:08:27 PM UTC 25 |
| Finished | Feb 08 06:08:30 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2998074577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usb dev_setup_stage.2998074577 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_setup_trans_ignored.2705255111 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 214532180 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:08:27 PM UTC 25 |
| Finished | Feb 08 06:08:30 PM UTC 25 |
| Peak memory | 214900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2705255111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 20.usbdev_setup_trans_ignored.2705255111 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_smoke.4293288886 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 276104812 ps |
| CPU time | 1.85 seconds |
| Started | Feb 08 06:08:27 PM UTC 25 |
| Finished | Feb 08 06:08:30 PM UTC 25 |
| Peak memory | 214944 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4293288886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_sm oke.4293288886 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_spurious_pids_ignored.3350691592 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 2725698895 ps |
| CPU time | 95.78 seconds |
| Started | Feb 08 06:08:27 PM UTC 25 |
| Finished | Feb 08 06:10:06 PM UTC 25 |
| Peak memory | 229812 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350691592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 20.usbdev_spurious_pids_ignored.3350691592 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_stall_priority_over_nak.1624250436 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 173592547 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:08:27 PM UTC 25 |
| Finished | Feb 08 06:08:30 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1624250436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 20.usbdev_stall_priority_over_nak.1624250436 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_stall_trans.2854291649 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 213243581 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 06:08:27 PM UTC 25 |
| Finished | Feb 08 06:08:30 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2854291649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usb dev_stall_trans.2854291649 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_stream_len_max.4275618837 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 405257327 ps |
| CPU time | 1.9 seconds |
| Started | Feb 08 06:08:29 PM UTC 25 |
| Finished | Feb 08 06:08:32 PM UTC 25 |
| Peak memory | 214828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4275618837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20. usbdev_stream_len_max.4275618837 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_streaming_out.413684567 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 2796383565 ps |
| CPU time | 23.8 seconds |
| Started | Feb 08 06:08:29 PM UTC 25 |
| Finished | Feb 08 06:08:54 PM UTC 25 |
| Peak memory | 229784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=413684567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev _streaming_out.413684567 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_timeout_missing_host_handshake.3181005679 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 748456975 ps |
| CPU time | 15.01 seconds |
| Started | Feb 08 06:08:09 PM UTC 25 |
| Finished | Feb 08 06:08:25 PM UTC 25 |
| Peak memory | 217340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181005679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing_host_handshake.3181005679 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/20.usbdev_tx_rx_disruption.3351368474 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 438033915 ps |
| CPU time | 2.7 seconds |
| Started | Feb 08 06:08:29 PM UTC 25 |
| Finished | Feb 08 06:08:33 PM UTC 25 |
| Peak memory | 216820 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 351368474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_tx_rx_disruption.3351368474 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/20.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/205.usbdev_tx_rx_disruption.2366518194 |
| Short name | T3350 |
| Test name | |
| Test status | |
| Simulation time | 489313686 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:18:53 PM UTC 25 |
| Finished | Feb 08 06:19:10 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 366518194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205.usbdev_tx_rx_disruption.2366518194 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/205.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/206.usbdev_tx_rx_disruption.3617503954 |
| Short name | T3337 |
| Test name | |
| Test status | |
| Simulation time | 449461326 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:18:55 PM UTC 25 |
| Finished | Feb 08 06:19:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 617503954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206.usbdev_tx_rx_disruption.3617503954 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/206.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/207.usbdev_tx_rx_disruption.3240719865 |
| Short name | T3321 |
| Test name | |
| Test status | |
| Simulation time | 667423053 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:18:55 PM UTC 25 |
| Finished | Feb 08 06:18:59 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 240719865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.usbdev_tx_rx_disruption.3240719865 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/207.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/208.usbdev_tx_rx_disruption.35642894 |
| Short name | T3320 |
| Test name | |
| Test status | |
| Simulation time | 492697498 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:18:55 PM UTC 25 |
| Finished | Feb 08 06:18:59 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 5642894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208.usbdev_tx_rx_disruption.35642894 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/208.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/209.usbdev_tx_rx_disruption.389605912 |
| Short name | T3335 |
| Test name | |
| Test status | |
| Simulation time | 442616831 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:18:55 PM UTC 25 |
| Finished | Feb 08 06:19:09 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 89605912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 209.usbdev_tx_rx_disruption.389605912 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/209.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_alert_test.1085240031 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 60051561 ps |
| CPU time | 1.05 seconds |
| Started | Feb 08 06:08:52 PM UTC 25 |
| Finished | Feb 08 06:08:54 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085240031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 21.usbdev_alert_test.1085240031 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_aon_wake_disconnect.2143896152 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 6877376364 ps |
| CPU time | 17.41 seconds |
| Started | Feb 08 06:08:30 PM UTC 25 |
| Finished | Feb 08 06:08:49 PM UTC 25 |
| Peak memory | 227588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143896152 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.2143896152 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_aon_wake_reset.2430071189 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 16255131429 ps |
| CPU time | 21.13 seconds |
| Started | Feb 08 06:08:31 PM UTC 25 |
| Finished | Feb 08 06:08:54 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430071189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.2430071189 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_aon_wake_resume.4226588282 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 30344537537 ps |
| CPU time | 47.26 seconds |
| Started | Feb 08 06:08:31 PM UTC 25 |
| Finished | Feb 08 06:09:20 PM UTC 25 |
| Peak memory | 217576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226588282 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.4226588282 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_av_buffer.1242532744 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 160398036 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:08:32 PM UTC 25 |
| Finished | Feb 08 06:08:34 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1242532744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbde v_av_buffer.1242532744 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_bitstuff_err.2966661697 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 152097611 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:08:32 PM UTC 25 |
| Finished | Feb 08 06:08:34 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2966661697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.us bdev_bitstuff_err.2966661697 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_data_toggle_clear.710339343 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 463778300 ps |
| CPU time | 2.79 seconds |
| Started | Feb 08 06:08:32 PM UTC 25 |
| Finished | Feb 08 06:08:36 PM UTC 25 |
| Peak memory | 217304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=710339343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.usbdev_data_toggle_clear.710339343 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_data_toggle_restore.139872184 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 669173077 ps |
| CPU time | 3 seconds |
| Started | Feb 08 06:08:32 PM UTC 25 |
| Finished | Feb 08 06:08:36 PM UTC 25 |
| Peak memory | 217300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139872184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_t oggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.139872184 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_device_address.3223966329 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 35634265963 ps |
| CPU time | 76.02 seconds |
| Started | Feb 08 06:08:33 PM UTC 25 |
| Finished | Feb 08 06:09:51 PM UTC 25 |
| Peak memory | 217552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3223966329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21. usbdev_device_address.3223966329 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_device_timeout.400453762 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 1066006317 ps |
| CPU time | 10.72 seconds |
| Started | Feb 08 06:08:33 PM UTC 25 |
| Finished | Feb 08 06:08:45 PM UTC 25 |
| Peak memory | 217536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400453762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.400453762 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_disable_endpoint.3717878839 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 511076340 ps |
| CPU time | 1.86 seconds |
| Started | Feb 08 06:08:35 PM UTC 25 |
| Finished | Feb 08 06:08:38 PM UTC 25 |
| Peak memory | 215056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3717878839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.usbdev_disable_endpoint.3717878839 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_disconnected.1387815696 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 180174520 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:08:35 PM UTC 25 |
| Finished | Feb 08 06:08:37 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1387815696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.us bdev_disconnected.1387815696 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_enable.976431300 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 46777209 ps |
| CPU time | 1.12 seconds |
| Started | Feb 08 06:08:35 PM UTC 25 |
| Finished | Feb 08 06:08:37 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=976431300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_en able.976431300 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_endpoint_access.1127028402 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 697069694 ps |
| CPU time | 3.92 seconds |
| Started | Feb 08 06:08:36 PM UTC 25 |
| Finished | Feb 08 06:08:42 PM UTC 25 |
| Peak memory | 217648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1127028402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21 .usbdev_endpoint_access.1127028402 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_fifo_rst.2191520887 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 344576414 ps |
| CPU time | 2.64 seconds |
| Started | Feb 08 06:08:37 PM UTC 25 |
| Finished | Feb 08 06:08:40 PM UTC 25 |
| Peak memory | 217652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2191520887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev _fifo_rst.2191520887 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_in_iso.3876227609 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 259059437 ps |
| CPU time | 1.9 seconds |
| Started | Feb 08 06:08:38 PM UTC 25 |
| Finished | Feb 08 06:08:41 PM UTC 25 |
| Peak memory | 227756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876227609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 21.usbdev_in_iso.3876227609 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_in_stall.2987155411 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 145453748 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:08:38 PM UTC 25 |
| Finished | Feb 08 06:08:40 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2987155411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev _in_stall.2987155411 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_in_trans.2493280771 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 177070134 ps |
| CPU time | 0.96 seconds |
| Started | Feb 08 06:08:38 PM UTC 25 |
| Finished | Feb 08 06:08:40 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2493280771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev _in_trans.2493280771 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_invalid_sync.3343704971 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 4212766814 ps |
| CPU time | 119.11 seconds |
| Started | Feb 08 06:08:37 PM UTC 25 |
| Finished | Feb 08 06:10:38 PM UTC 25 |
| Peak memory | 227744 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343704971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.3343704971 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_iso_retraction.3884991687 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 9010105577 ps |
| CPU time | 58.99 seconds |
| Started | Feb 08 06:08:38 PM UTC 25 |
| Finished | Feb 08 06:09:39 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884991687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 21.usbdev_iso_retraction.3884991687 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_link_in_err.3561429557 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 211167221 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:08:38 PM UTC 25 |
| Finished | Feb 08 06:08:41 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3561429557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usb dev_link_in_err.3561429557 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_link_resume.3795880642 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 33575087272 ps |
| CPU time | 71.44 seconds |
| Started | Feb 08 06:08:39 PM UTC 25 |
| Finished | Feb 08 06:09:53 PM UTC 25 |
| Peak memory | 217456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3795880642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usb dev_link_resume.3795880642 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_link_suspend.3550265491 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 4834755742 ps |
| CPU time | 10.74 seconds |
| Started | Feb 08 06:08:39 PM UTC 25 |
| Finished | Feb 08 06:08:51 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3550265491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.us bdev_link_suspend.3550265491 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_low_speed_traffic.1393695098 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 4781052268 ps |
| CPU time | 149.23 seconds |
| Started | Feb 08 06:08:41 PM UTC 25 |
| Finished | Feb 08 06:11:13 PM UTC 25 |
| Peak memory | 229792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393695098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 21.usbdev_low_speed_traffic.1393695098 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_max_inter_pkt_delay.1718883566 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 1671148029 ps |
| CPU time | 52.12 seconds |
| Started | Feb 08 06:08:41 PM UTC 25 |
| Finished | Feb 08 06:09:35 PM UTC 25 |
| Peak memory | 227720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718883566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.1718883566 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_max_length_in_transaction.1773283879 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 237374588 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:08:41 PM UTC 25 |
| Finished | Feb 08 06:08:43 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773283879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 21.usbdev_max_length_in_transaction.1773283879 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_max_length_out_transaction.32957692 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 192374358 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:08:41 PM UTC 25 |
| Finished | Feb 08 06:08:43 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=32957692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 21.usbdev_max_length_out_transaction.32957692 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_max_non_iso_usb_traffic.2693516686 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 2550131222 ps |
| CPU time | 70.13 seconds |
| Started | Feb 08 06:08:42 PM UTC 25 |
| Finished | Feb 08 06:09:54 PM UTC 25 |
| Peak memory | 229756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2693516686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 21.usbdev_max_non_iso_usb_traffic.2693516686 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_min_inter_pkt_delay.2284992382 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 1715574901 ps |
| CPU time | 54.27 seconds |
| Started | Feb 08 06:08:42 PM UTC 25 |
| Finished | Feb 08 06:09:38 PM UTC 25 |
| Peak memory | 227720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284992382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.2284992382 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_min_length_in_transaction.3272324624 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 153160721 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:08:42 PM UTC 25 |
| Finished | Feb 08 06:08:45 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272324624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 21.usbdev_min_length_in_transaction.3272324624 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_min_length_out_transaction.1196350967 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 140018378 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:08:43 PM UTC 25 |
| Finished | Feb 08 06:08:45 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1196350967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.1196350967 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_nak_trans.51165217 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 189783805 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:08:43 PM UTC 25 |
| Finished | Feb 08 06:08:45 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=51165217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_ nak_trans.51165217 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_out_iso.171368321 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 247975253 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:08:43 PM UTC 25 |
| Finished | Feb 08 06:08:45 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=171368321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_o ut_iso.171368321 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_out_stall.883905901 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 152194887 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:08:44 PM UTC 25 |
| Finished | Feb 08 06:08:46 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=883905901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev _out_stall.883905901 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_out_trans_nak.2985638184 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 180736989 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:08:44 PM UTC 25 |
| Finished | Feb 08 06:08:46 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2985638184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.u sbdev_out_trans_nak.2985638184 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_pending_in_trans.1296310148 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 151654835 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:08:44 PM UTC 25 |
| Finished | Feb 08 06:08:46 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1296310148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.usbdev_pending_in_trans.1296310148 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_phy_config_pinflip.1244700855 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 238974126 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 06:08:46 PM UTC 25 |
| Finished | Feb 08 06:08:49 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244700855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 21.usbdev_phy_config_pinflip.1244700855 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_phy_config_usb_ref_disable.565377344 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 177109176 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 06:08:46 PM UTC 25 |
| Finished | Feb 08 06:08:49 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=565377344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 21.usbdev_phy_config_usb_ref_disable.565377344 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_phy_pins_sense.1272798390 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 65920136 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 06:08:47 PM UTC 25 |
| Finished | Feb 08 06:08:49 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1272798390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21. usbdev_phy_pins_sense.1272798390 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_pkt_buffer.3399133444 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 15075096807 ps |
| CPU time | 63.76 seconds |
| Started | Feb 08 06:08:47 PM UTC 25 |
| Finished | Feb 08 06:09:52 PM UTC 25 |
| Peak memory | 227684 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3399133444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbd ev_pkt_buffer.3399133444 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_pkt_received.2195791925 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 164707353 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:08:47 PM UTC 25 |
| Finished | Feb 08 06:08:49 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2195791925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.us bdev_pkt_received.2195791925 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_pkt_sent.1320244909 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 239201681 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:08:47 PM UTC 25 |
| Finished | Feb 08 06:08:49 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1320244909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev _pkt_sent.1320244909 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_random_length_in_transaction.1628005436 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 193244235 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 06:08:47 PM UTC 25 |
| Finished | Feb 08 06:08:49 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1628005436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.u sbdev_random_length_in_transaction.1628005436 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_random_length_out_transaction.1514949841 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 183774609 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:08:48 PM UTC 25 |
| Finished | Feb 08 06:08:51 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1514949841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 21.usbdev_random_length_out_transaction.1514949841 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_rx_crc_err.1206863472 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 202879149 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:08:48 PM UTC 25 |
| Finished | Feb 08 06:08:51 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1206863472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbd ev_rx_crc_err.1206863472 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_setup_stage.1248261120 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 160112479 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:08:48 PM UTC 25 |
| Finished | Feb 08 06:08:51 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1248261120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usb dev_setup_stage.1248261120 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_setup_trans_ignored.344929999 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 151247887 ps |
| CPU time | 0.97 seconds |
| Started | Feb 08 06:08:48 PM UTC 25 |
| Finished | Feb 08 06:08:50 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=344929999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.344929999 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_smoke.621146000 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 239374043 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:08:49 PM UTC 25 |
| Finished | Feb 08 06:08:52 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=621146000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smo ke.621146000 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_spurious_pids_ignored.1561220625 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 2175355532 ps |
| CPU time | 63.42 seconds |
| Started | Feb 08 06:08:49 PM UTC 25 |
| Finished | Feb 08 06:09:55 PM UTC 25 |
| Peak memory | 229768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561220625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 21.usbdev_spurious_pids_ignored.1561220625 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_stall_priority_over_nak.1895864754 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 152567612 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:08:50 PM UTC 25 |
| Finished | Feb 08 06:08:52 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1895864754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 21.usbdev_stall_priority_over_nak.1895864754 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_stall_trans.206478844 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 158641697 ps |
| CPU time | 1.05 seconds |
| Started | Feb 08 06:08:50 PM UTC 25 |
| Finished | Feb 08 06:08:52 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=206478844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbd ev_stall_trans.206478844 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_stream_len_max.576650384 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 830817640 ps |
| CPU time | 2.46 seconds |
| Started | Feb 08 06:08:51 PM UTC 25 |
| Finished | Feb 08 06:08:55 PM UTC 25 |
| Peak memory | 217356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=576650384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.u sbdev_stream_len_max.576650384 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_streaming_out.3802877754 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 2054042331 ps |
| CPU time | 65.74 seconds |
| Started | Feb 08 06:08:51 PM UTC 25 |
| Finished | Feb 08 06:09:59 PM UTC 25 |
| Peak memory | 227660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3802877754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbde v_streaming_out.3802877754 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_timeout_missing_host_handshake.2855998056 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 5689637894 ps |
| CPU time | 62.44 seconds |
| Started | Feb 08 06:08:35 PM UTC 25 |
| Finished | Feb 08 06:09:39 PM UTC 25 |
| Peak memory | 217540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855998056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing_host_handshake.2855998056 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/21.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/210.usbdev_tx_rx_disruption.4037758349 |
| Short name | T3341 |
| Test name | |
| Test status | |
| Simulation time | 510712976 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:18:55 PM UTC 25 |
| Finished | Feb 08 06:19:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 037758349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210.usbdev_tx_rx_disruption.4037758349 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/210.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/211.usbdev_tx_rx_disruption.958267144 |
| Short name | T3319 |
| Test name | |
| Test status | |
| Simulation time | 522398370 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:18:55 PM UTC 25 |
| Finished | Feb 08 06:18:59 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 58267144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211.usbdev_tx_rx_disruption.958267144 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/211.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/212.usbdev_tx_rx_disruption.1479097333 |
| Short name | T3317 |
| Test name | |
| Test status | |
| Simulation time | 429135227 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:18:55 PM UTC 25 |
| Finished | Feb 08 06:18:59 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 479097333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212.usbdev_tx_rx_disruption.1479097333 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/212.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/213.usbdev_tx_rx_disruption.3800073543 |
| Short name | T3339 |
| Test name | |
| Test status | |
| Simulation time | 571681547 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:18:55 PM UTC 25 |
| Finished | Feb 08 06:19:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 800073543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.usbdev_tx_rx_disruption.3800073543 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/213.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/214.usbdev_tx_rx_disruption.2735381175 |
| Short name | T3342 |
| Test name | |
| Test status | |
| Simulation time | 669671473 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:18:55 PM UTC 25 |
| Finished | Feb 08 06:19:09 PM UTC 25 |
| Peak memory | 215088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 735381175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 214.usbdev_tx_rx_disruption.2735381175 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/214.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/215.usbdev_tx_rx_disruption.3226507994 |
| Short name | T3340 |
| Test name | |
| Test status | |
| Simulation time | 517441795 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:18:55 PM UTC 25 |
| Finished | Feb 08 06:19:09 PM UTC 25 |
| Peak memory | 214932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 226507994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 215.usbdev_tx_rx_disruption.3226507994 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/215.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/216.usbdev_tx_rx_disruption.860990021 |
| Short name | T3343 |
| Test name | |
| Test status | |
| Simulation time | 673042105 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:18:55 PM UTC 25 |
| Finished | Feb 08 06:19:09 PM UTC 25 |
| Peak memory | 215024 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 60990021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216.usbdev_tx_rx_disruption.860990021 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/216.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/217.usbdev_tx_rx_disruption.2869561361 |
| Short name | T3349 |
| Test name | |
| Test status | |
| Simulation time | 599010230 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:18:55 PM UTC 25 |
| Finished | Feb 08 06:19:10 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 869561361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217.usbdev_tx_rx_disruption.2869561361 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/217.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/218.usbdev_tx_rx_disruption.3030449118 |
| Short name | T3344 |
| Test name | |
| Test status | |
| Simulation time | 504803576 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:18:55 PM UTC 25 |
| Finished | Feb 08 06:19:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 030449118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.usbdev_tx_rx_disruption.3030449118 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/218.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/219.usbdev_tx_rx_disruption.1155311235 |
| Short name | T3348 |
| Test name | |
| Test status | |
| Simulation time | 497884097 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:18:55 PM UTC 25 |
| Finished | Feb 08 06:19:10 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 155311235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219.usbdev_tx_rx_disruption.1155311235 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/219.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_alert_test.47873831 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 49789900 ps |
| CPU time | 1.05 seconds |
| Started | Feb 08 06:09:18 PM UTC 25 |
| Finished | Feb 08 06:09:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47873831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 22.usbdev_alert_test.47873831 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_aon_wake_disconnect.1900870542 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 6890461870 ps |
| CPU time | 12.9 seconds |
| Started | Feb 08 06:08:52 PM UTC 25 |
| Finished | Feb 08 06:09:06 PM UTC 25 |
| Peak memory | 227780 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900870542 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.1900870542 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_aon_wake_reset.1115298190 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 14646610332 ps |
| CPU time | 24.01 seconds |
| Started | Feb 08 06:08:52 PM UTC 25 |
| Finished | Feb 08 06:09:18 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115298190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.1115298190 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_aon_wake_resume.3301705556 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 31243365536 ps |
| CPU time | 51.74 seconds |
| Started | Feb 08 06:08:52 PM UTC 25 |
| Finished | Feb 08 06:09:46 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301705556 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.3301705556 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_av_buffer.2014488754 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 169929464 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:08:52 PM UTC 25 |
| Finished | Feb 08 06:08:55 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2014488754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbde v_av_buffer.2014488754 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_bitstuff_err.1798599841 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 146681115 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 06:08:52 PM UTC 25 |
| Finished | Feb 08 06:08:55 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1798599841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.us bdev_bitstuff_err.1798599841 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_data_toggle_clear.3279036426 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 146550969 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 06:08:52 PM UTC 25 |
| Finished | Feb 08 06:08:55 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3279036426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.3279036426 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_device_address.118111474 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 17889474473 ps |
| CPU time | 31.36 seconds |
| Started | Feb 08 06:08:54 PM UTC 25 |
| Finished | Feb 08 06:09:27 PM UTC 25 |
| Peak memory | 217412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=118111474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.u sbdev_device_address.118111474 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_device_timeout.1435153714 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 1524071909 ps |
| CPU time | 18.17 seconds |
| Started | Feb 08 06:08:54 PM UTC 25 |
| Finished | Feb 08 06:09:14 PM UTC 25 |
| Peak memory | 217540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435153714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.1435153714 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_disable_endpoint.2361144488 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 832300206 ps |
| CPU time | 3.65 seconds |
| Started | Feb 08 06:08:56 PM UTC 25 |
| Finished | Feb 08 06:09:01 PM UTC 25 |
| Peak memory | 217076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2361144488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.usbdev_disable_endpoint.2361144488 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_disconnected.3739737642 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 157607470 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:08:56 PM UTC 25 |
| Finished | Feb 08 06:08:59 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3739737642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.us bdev_disconnected.3739737642 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_enable.2164578098 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 62398044 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 06:08:56 PM UTC 25 |
| Finished | Feb 08 06:08:58 PM UTC 25 |
| Peak memory | 214940 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2164578098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_e nable.2164578098 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_endpoint_access.3030529774 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 1013898410 ps |
| CPU time | 5.08 seconds |
| Started | Feb 08 06:08:56 PM UTC 25 |
| Finished | Feb 08 06:09:02 PM UTC 25 |
| Peak memory | 217568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3030529774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22 .usbdev_endpoint_access.3030529774 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_endpoint_types.3683221526 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 645523729 ps |
| CPU time | 2.99 seconds |
| Started | Feb 08 06:08:56 PM UTC 25 |
| Finished | Feb 08 06:09:00 PM UTC 25 |
| Peak memory | 217148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683221526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 22.usbdev_endpoint_types.3683221526 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_fifo_rst.1129960905 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 370228229 ps |
| CPU time | 3.22 seconds |
| Started | Feb 08 06:08:56 PM UTC 25 |
| Finished | Feb 08 06:09:01 PM UTC 25 |
| Peak memory | 217552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1129960905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev _fifo_rst.1129960905 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_in_iso.1338608403 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 236463838 ps |
| CPU time | 1.84 seconds |
| Started | Feb 08 06:08:56 PM UTC 25 |
| Finished | Feb 08 06:08:59 PM UTC 25 |
| Peak memory | 227756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338608403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 22.usbdev_in_iso.1338608403 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_in_stall.473743604 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 140190374 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:09:00 PM UTC 25 |
| Finished | Feb 08 06:09:02 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=473743604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_ in_stall.473743604 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_in_trans.3571553001 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 260413837 ps |
| CPU time | 1.85 seconds |
| Started | Feb 08 06:09:00 PM UTC 25 |
| Finished | Feb 08 06:09:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3571553001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev _in_trans.3571553001 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_invalid_sync.4237476155 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 2633753016 ps |
| CPU time | 74.28 seconds |
| Started | Feb 08 06:08:56 PM UTC 25 |
| Finished | Feb 08 06:10:13 PM UTC 25 |
| Peak memory | 227652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237476155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.4237476155 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_iso_retraction.2209330620 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 6635561192 ps |
| CPU time | 51.01 seconds |
| Started | Feb 08 06:09:00 PM UTC 25 |
| Finished | Feb 08 06:09:52 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209330620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 22.usbdev_iso_retraction.2209330620 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_link_in_err.2789669541 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 194873200 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:09:00 PM UTC 25 |
| Finished | Feb 08 06:09:02 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2789669541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usb dev_link_in_err.2789669541 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_link_resume.3799020610 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 32342294258 ps |
| CPU time | 63.27 seconds |
| Started | Feb 08 06:09:01 PM UTC 25 |
| Finished | Feb 08 06:10:06 PM UTC 25 |
| Peak memory | 217576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3799020610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usb dev_link_resume.3799020610 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_link_suspend.3685846901 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 6044181805 ps |
| CPU time | 12.47 seconds |
| Started | Feb 08 06:09:01 PM UTC 25 |
| Finished | Feb 08 06:09:15 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3685846901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.us bdev_link_suspend.3685846901 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_low_speed_traffic.2901456351 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 5033756719 ps |
| CPU time | 49.93 seconds |
| Started | Feb 08 06:09:02 PM UTC 25 |
| Finished | Feb 08 06:09:54 PM UTC 25 |
| Peak memory | 234500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901456351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 22.usbdev_low_speed_traffic.2901456351 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_max_inter_pkt_delay.879819830 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 3574640569 ps |
| CPU time | 37.98 seconds |
| Started | Feb 08 06:09:02 PM UTC 25 |
| Finished | Feb 08 06:09:42 PM UTC 25 |
| Peak memory | 229832 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879819830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.879819830 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_max_length_in_transaction.166791350 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 298102326 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:09:04 PM UTC 25 |
| Finished | Feb 08 06:09:06 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166791350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 22.usbdev_max_length_in_transaction.166791350 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_max_length_out_transaction.1575357276 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 212162392 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:09:04 PM UTC 25 |
| Finished | Feb 08 06:09:06 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1575357276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1575357276 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_max_non_iso_usb_traffic.2162080692 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 3234268537 ps |
| CPU time | 89.92 seconds |
| Started | Feb 08 06:09:04 PM UTC 25 |
| Finished | Feb 08 06:10:36 PM UTC 25 |
| Peak memory | 229648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2162080692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 22.usbdev_max_non_iso_usb_traffic.2162080692 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_min_inter_pkt_delay.3569124791 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 2842746359 ps |
| CPU time | 74.63 seconds |
| Started | Feb 08 06:09:04 PM UTC 25 |
| Finished | Feb 08 06:10:20 PM UTC 25 |
| Peak memory | 227856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569124791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.3569124791 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_min_length_in_transaction.2554187725 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 222978675 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:09:04 PM UTC 25 |
| Finished | Feb 08 06:09:07 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554187725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 22.usbdev_min_length_in_transaction.2554187725 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_min_length_out_transaction.563015420 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 156847081 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:09:05 PM UTC 25 |
| Finished | Feb 08 06:09:07 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=563015420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 22.usbdev_min_length_out_transaction.563015420 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_out_iso.1312943043 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 170927102 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:09:07 PM UTC 25 |
| Finished | Feb 08 06:09:10 PM UTC 25 |
| Peak memory | 214984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1312943043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_ out_iso.1312943043 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_out_stall.3871524227 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 170061200 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:09:08 PM UTC 25 |
| Finished | Feb 08 06:09:10 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3871524227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbde v_out_stall.3871524227 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_out_trans_nak.165157118 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 200734756 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:09:08 PM UTC 25 |
| Finished | Feb 08 06:09:10 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=165157118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.us bdev_out_trans_nak.165157118 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_pending_in_trans.1748814485 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 157473453 ps |
| CPU time | 1.21 seconds |
| Started | Feb 08 06:09:08 PM UTC 25 |
| Finished | Feb 08 06:09:10 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1748814485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.usbdev_pending_in_trans.1748814485 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_phy_config_pinflip.317639401 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 235333416 ps |
| CPU time | 1.71 seconds |
| Started | Feb 08 06:09:10 PM UTC 25 |
| Finished | Feb 08 06:09:13 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=317639401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 22.usbdev_phy_config_pinflip.317639401 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_phy_config_usb_ref_disable.698291312 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 157460886 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:09:10 PM UTC 25 |
| Finished | Feb 08 06:09:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=698291312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 22.usbdev_phy_config_usb_ref_disable.698291312 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_phy_pins_sense.530127171 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 36942534 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:09:10 PM UTC 25 |
| Finished | Feb 08 06:09:12 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=530127171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.u sbdev_phy_pins_sense.530127171 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_pkt_buffer.1792867207 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 18967199319 ps |
| CPU time | 55.78 seconds |
| Started | Feb 08 06:09:11 PM UTC 25 |
| Finished | Feb 08 06:10:09 PM UTC 25 |
| Peak memory | 231696 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1792867207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbd ev_pkt_buffer.1792867207 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_pkt_received.3506128638 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 178873006 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:09:11 PM UTC 25 |
| Finished | Feb 08 06:09:14 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3506128638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.us bdev_pkt_received.3506128638 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_pkt_sent.2302822302 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 171619606 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:09:11 PM UTC 25 |
| Finished | Feb 08 06:09:14 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2302822302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev _pkt_sent.2302822302 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_random_length_in_transaction.2057771493 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 205957986 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:09:11 PM UTC 25 |
| Finished | Feb 08 06:09:14 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2057771493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.u sbdev_random_length_in_transaction.2057771493 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_random_length_out_transaction.2356089278 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 211541298 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:09:11 PM UTC 25 |
| Finished | Feb 08 06:09:14 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2356089278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 22.usbdev_random_length_out_transaction.2356089278 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_rx_crc_err.1655421240 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 145713200 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:09:11 PM UTC 25 |
| Finished | Feb 08 06:09:14 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1655421240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbd ev_rx_crc_err.1655421240 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_rx_full.372486089 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 249264382 ps |
| CPU time | 1.74 seconds |
| Started | Feb 08 06:09:12 PM UTC 25 |
| Finished | Feb 08 06:09:15 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=372486089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_r x_full.372486089 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_setup_stage.3715555452 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 153382432 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:09:14 PM UTC 25 |
| Finished | Feb 08 06:09:16 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3715555452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usb dev_setup_stage.3715555452 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_setup_trans_ignored.1200462482 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 152285022 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:09:14 PM UTC 25 |
| Finished | Feb 08 06:09:16 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1200462482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 22.usbdev_setup_trans_ignored.1200462482 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_smoke.2006584540 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 257421614 ps |
| CPU time | 1.76 seconds |
| Started | Feb 08 06:09:15 PM UTC 25 |
| Finished | Feb 08 06:09:18 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2006584540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_sm oke.2006584540 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_spurious_pids_ignored.1307646256 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 1913566320 ps |
| CPU time | 21.72 seconds |
| Started | Feb 08 06:09:15 PM UTC 25 |
| Finished | Feb 08 06:09:38 PM UTC 25 |
| Peak memory | 229748 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307646256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 22.usbdev_spurious_pids_ignored.1307646256 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_stall_priority_over_nak.4120104775 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 169880608 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:09:15 PM UTC 25 |
| Finished | Feb 08 06:09:18 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4120104775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 22.usbdev_stall_priority_over_nak.4120104775 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_stall_trans.1783080919 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 175741044 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:09:15 PM UTC 25 |
| Finished | Feb 08 06:09:18 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1783080919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usb dev_stall_trans.1783080919 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_stream_len_max.3528127269 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 1271327105 ps |
| CPU time | 6.03 seconds |
| Started | Feb 08 06:09:15 PM UTC 25 |
| Finished | Feb 08 06:09:23 PM UTC 25 |
| Peak memory | 217552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3528127269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22. usbdev_stream_len_max.3528127269 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_streaming_out.2227657035 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 2460142784 ps |
| CPU time | 69.28 seconds |
| Started | Feb 08 06:09:15 PM UTC 25 |
| Finished | Feb 08 06:10:26 PM UTC 25 |
| Peak memory | 229776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2227657035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbde v_streaming_out.2227657035 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_timeout_missing_host_handshake.2591638592 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 1400232871 ps |
| CPU time | 11.1 seconds |
| Started | Feb 08 06:08:54 PM UTC 25 |
| Finished | Feb 08 06:09:07 PM UTC 25 |
| Peak memory | 217356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591638592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_host_handshake.2591638592 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/22.usbdev_tx_rx_disruption.759575023 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 549315522 ps |
| CPU time | 3.33 seconds |
| Started | Feb 08 06:09:16 PM UTC 25 |
| Finished | Feb 08 06:09:21 PM UTC 25 |
| Peak memory | 217188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 59575023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_tx_rx_disruption.759575023 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/22.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/220.usbdev_tx_rx_disruption.4098335284 |
| Short name | T3351 |
| Test name | |
| Test status | |
| Simulation time | 619783212 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:18:55 PM UTC 25 |
| Finished | Feb 08 06:19:10 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 098335284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220.usbdev_tx_rx_disruption.4098335284 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/220.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/221.usbdev_tx_rx_disruption.410626010 |
| Short name | T3345 |
| Test name | |
| Test status | |
| Simulation time | 508826829 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:18:55 PM UTC 25 |
| Finished | Feb 08 06:19:09 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 10626010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221.usbdev_tx_rx_disruption.410626010 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/221.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/222.usbdev_tx_rx_disruption.1415680329 |
| Short name | T3352 |
| Test name | |
| Test status | |
| Simulation time | 658352079 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:18:55 PM UTC 25 |
| Finished | Feb 08 06:19:10 PM UTC 25 |
| Peak memory | 215092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 415680329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.usbdev_tx_rx_disruption.1415680329 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/222.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/223.usbdev_tx_rx_disruption.3945227791 |
| Short name | T3346 |
| Test name | |
| Test status | |
| Simulation time | 578043400 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:18:55 PM UTC 25 |
| Finished | Feb 08 06:19:10 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 945227791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.usbdev_tx_rx_disruption.3945227791 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/223.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/224.usbdev_tx_rx_disruption.4061009732 |
| Short name | T3353 |
| Test name | |
| Test status | |
| Simulation time | 557656130 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:18:55 PM UTC 25 |
| Finished | Feb 08 06:19:10 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 061009732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224.usbdev_tx_rx_disruption.4061009732 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/224.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/225.usbdev_tx_rx_disruption.84459284 |
| Short name | T3347 |
| Test name | |
| Test status | |
| Simulation time | 508856807 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:18:55 PM UTC 25 |
| Finished | Feb 08 06:19:10 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 4459284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225.usbdev_tx_rx_disruption.84459284 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/225.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/226.usbdev_tx_rx_disruption.1018818761 |
| Short name | T3355 |
| Test name | |
| Test status | |
| Simulation time | 539209606 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:18:57 PM UTC 25 |
| Finished | Feb 08 06:19:10 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 018818761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.usbdev_tx_rx_disruption.1018818761 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/226.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/227.usbdev_tx_rx_disruption.839753874 |
| Short name | T3354 |
| Test name | |
| Test status | |
| Simulation time | 648101759 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:18:57 PM UTC 25 |
| Finished | Feb 08 06:19:10 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 39753874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227.usbdev_tx_rx_disruption.839753874 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/227.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/228.usbdev_tx_rx_disruption.2036978008 |
| Short name | T3328 |
| Test name | |
| Test status | |
| Simulation time | 477503907 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:19:00 PM UTC 25 |
| Finished | Feb 08 06:19:04 PM UTC 25 |
| Peak memory | 214928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 036978008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 228.usbdev_tx_rx_disruption.2036978008 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/228.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/229.usbdev_tx_rx_disruption.964076006 |
| Short name | T3404 |
| Test name | |
| Test status | |
| Simulation time | 557150143 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:19:00 PM UTC 25 |
| Finished | Feb 08 06:19:34 PM UTC 25 |
| Peak memory | 215116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 64076006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229.usbdev_tx_rx_disruption.964076006 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/229.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_alert_test.3908562857 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 52088376 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:09:47 PM UTC 25 |
| Finished | Feb 08 06:09:49 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908562857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 23.usbdev_alert_test.3908562857 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_aon_wake_disconnect.716934084 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 6317091742 ps |
| CPU time | 13.54 seconds |
| Started | Feb 08 06:09:18 PM UTC 25 |
| Finished | Feb 08 06:09:33 PM UTC 25 |
| Peak memory | 227456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716934084 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.716934084 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_aon_wake_reset.700837162 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 19873914488 ps |
| CPU time | 39.1 seconds |
| Started | Feb 08 06:09:18 PM UTC 25 |
| Finished | Feb 08 06:09:59 PM UTC 25 |
| Peak memory | 217148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700837162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TE ST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.700837162 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_aon_wake_resume.4113485290 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 31154406106 ps |
| CPU time | 65.14 seconds |
| Started | Feb 08 06:09:18 PM UTC 25 |
| Finished | Feb 08 06:10:25 PM UTC 25 |
| Peak memory | 217384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113485290 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.4113485290 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_av_buffer.2021844548 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 153862711 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:09:19 PM UTC 25 |
| Finished | Feb 08 06:09:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2021844548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbde v_av_buffer.2021844548 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_bitstuff_err.2804241980 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 151126920 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:09:19 PM UTC 25 |
| Finished | Feb 08 06:09:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2804241980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.us bdev_bitstuff_err.2804241980 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_data_toggle_clear.2723754936 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 270906456 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:09:19 PM UTC 25 |
| Finished | Feb 08 06:09:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2723754936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.2723754936 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_data_toggle_restore.1346884199 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 587154855 ps |
| CPU time | 2.96 seconds |
| Started | Feb 08 06:09:20 PM UTC 25 |
| Finished | Feb 08 06:09:24 PM UTC 25 |
| Peak memory | 217172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346884199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.1346884199 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_device_address.4107933542 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 50966009684 ps |
| CPU time | 91.42 seconds |
| Started | Feb 08 06:09:21 PM UTC 25 |
| Finished | Feb 08 06:10:54 PM UTC 25 |
| Peak memory | 217416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4107933542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23. usbdev_device_address.4107933542 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_device_timeout.2194046479 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 723451646 ps |
| CPU time | 19.39 seconds |
| Started | Feb 08 06:09:22 PM UTC 25 |
| Finished | Feb 08 06:09:43 PM UTC 25 |
| Peak memory | 217464 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194046479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.2194046479 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_disable_endpoint.615451197 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 490155570 ps |
| CPU time | 2.42 seconds |
| Started | Feb 08 06:09:23 PM UTC 25 |
| Finished | Feb 08 06:09:27 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=615451197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23 .usbdev_disable_endpoint.615451197 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_disconnected.2610474980 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 163936259 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:09:23 PM UTC 25 |
| Finished | Feb 08 06:09:26 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2610474980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.us bdev_disconnected.2610474980 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_enable.4033254953 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 39246546 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 06:09:23 PM UTC 25 |
| Finished | Feb 08 06:09:25 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4033254953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_e nable.4033254953 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_endpoint_access.1035533313 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 907289320 ps |
| CPU time | 4.44 seconds |
| Started | Feb 08 06:09:23 PM UTC 25 |
| Finished | Feb 08 06:09:29 PM UTC 25 |
| Peak memory | 217324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1035533313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23 .usbdev_endpoint_access.1035533313 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_endpoint_types.3156412926 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 189420918 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:09:24 PM UTC 25 |
| Finished | Feb 08 06:09:27 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156412926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 23.usbdev_endpoint_types.3156412926 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_fifo_rst.411493268 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 220861553 ps |
| CPU time | 2.15 seconds |
| Started | Feb 08 06:09:26 PM UTC 25 |
| Finished | Feb 08 06:09:29 PM UTC 25 |
| Peak memory | 217472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=411493268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_ fifo_rst.411493268 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_in_iso.2426762580 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 177964830 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:09:27 PM UTC 25 |
| Finished | Feb 08 06:09:29 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426762580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 23.usbdev_in_iso.2426762580 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_in_stall.1985191947 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 145297172 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:09:28 PM UTC 25 |
| Finished | Feb 08 06:09:31 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1985191947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev _in_stall.1985191947 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_in_trans.1526069995 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 195015777 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:09:28 PM UTC 25 |
| Finished | Feb 08 06:09:31 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1526069995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev _in_trans.1526069995 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_invalid_sync.3168780642 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 3461237317 ps |
| CPU time | 39.21 seconds |
| Started | Feb 08 06:09:27 PM UTC 25 |
| Finished | Feb 08 06:10:08 PM UTC 25 |
| Peak memory | 229772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168780642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.3168780642 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_iso_retraction.149528422 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 7495971325 ps |
| CPU time | 60.23 seconds |
| Started | Feb 08 06:09:28 PM UTC 25 |
| Finished | Feb 08 06:10:31 PM UTC 25 |
| Peak memory | 217416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149528422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retra ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 23.usbdev_iso_retraction.149528422 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_link_in_err.2990823258 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 235136994 ps |
| CPU time | 1.74 seconds |
| Started | Feb 08 06:09:30 PM UTC 25 |
| Finished | Feb 08 06:09:33 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2990823258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usb dev_link_in_err.2990823258 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_link_resume.3046560117 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 30645429240 ps |
| CPU time | 63.88 seconds |
| Started | Feb 08 06:09:30 PM UTC 25 |
| Finished | Feb 08 06:10:35 PM UTC 25 |
| Peak memory | 217584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3046560117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usb dev_link_resume.3046560117 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_link_suspend.2151266280 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 10262746076 ps |
| CPU time | 21.17 seconds |
| Started | Feb 08 06:09:30 PM UTC 25 |
| Finished | Feb 08 06:09:52 PM UTC 25 |
| Peak memory | 217384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2151266280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.us bdev_link_suspend.2151266280 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_low_speed_traffic.2580524806 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 3277221765 ps |
| CPU time | 26.29 seconds |
| Started | Feb 08 06:09:30 PM UTC 25 |
| Finished | Feb 08 06:09:58 PM UTC 25 |
| Peak memory | 227852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580524806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 23.usbdev_low_speed_traffic.2580524806 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_max_inter_pkt_delay.13331593 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 3573369959 ps |
| CPU time | 108.17 seconds |
| Started | Feb 08 06:09:32 PM UTC 25 |
| Finished | Feb 08 06:11:23 PM UTC 25 |
| Peak memory | 227752 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13331593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.13331593 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_max_length_in_transaction.3560910532 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 310652130 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:09:32 PM UTC 25 |
| Finished | Feb 08 06:09:35 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560910532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 23.usbdev_max_length_in_transaction.3560910532 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_max_length_out_transaction.4086566550 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 233050170 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:09:33 PM UTC 25 |
| Finished | Feb 08 06:09:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4086566550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.4086566550 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_max_non_iso_usb_traffic.1725138260 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 2793633875 ps |
| CPU time | 25.49 seconds |
| Started | Feb 08 06:09:33 PM UTC 25 |
| Finished | Feb 08 06:10:00 PM UTC 25 |
| Peak memory | 229776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1725138260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 23.usbdev_max_non_iso_usb_traffic.1725138260 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_min_inter_pkt_delay.1488621914 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 2109752456 ps |
| CPU time | 72.13 seconds |
| Started | Feb 08 06:09:36 PM UTC 25 |
| Finished | Feb 08 06:10:50 PM UTC 25 |
| Peak memory | 227392 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488621914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.1488621914 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_min_length_in_transaction.4286739411 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 155693707 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:09:36 PM UTC 25 |
| Finished | Feb 08 06:09:38 PM UTC 25 |
| Peak memory | 214920 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286739411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 23.usbdev_min_length_in_transaction.4286739411 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_min_length_out_transaction.2148340886 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 169427001 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:09:37 PM UTC 25 |
| Finished | Feb 08 06:09:40 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2148340886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.2148340886 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_nak_trans.3443041123 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 295924881 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 06:09:37 PM UTC 25 |
| Finished | Feb 08 06:09:40 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3443041123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbde v_nak_trans.3443041123 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_out_iso.4202194201 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 176332170 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:09:40 PM UTC 25 |
| Finished | Feb 08 06:09:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4202194201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_ out_iso.4202194201 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_out_stall.2307419306 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 149339653 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:09:40 PM UTC 25 |
| Finished | Feb 08 06:09:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2307419306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbde v_out_stall.2307419306 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_out_trans_nak.1645266097 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 190427132 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:09:40 PM UTC 25 |
| Finished | Feb 08 06:09:42 PM UTC 25 |
| Peak memory | 214904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1645266097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.u sbdev_out_trans_nak.1645266097 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_pending_in_trans.3835284735 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 153593974 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:09:40 PM UTC 25 |
| Finished | Feb 08 06:09:42 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3835284735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.usbdev_pending_in_trans.3835284735 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_phy_config_pinflip.1005892202 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 290376708 ps |
| CPU time | 1.95 seconds |
| Started | Feb 08 06:09:41 PM UTC 25 |
| Finished | Feb 08 06:09:44 PM UTC 25 |
| Peak memory | 214120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005892202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 23.usbdev_phy_config_pinflip.1005892202 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_phy_config_usb_ref_disable.627676680 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 210580525 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:09:41 PM UTC 25 |
| Finished | Feb 08 06:09:44 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=627676680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 23.usbdev_phy_config_usb_ref_disable.627676680 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_phy_pins_sense.2617331874 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 31862676 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:09:41 PM UTC 25 |
| Finished | Feb 08 06:09:44 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2617331874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23. usbdev_phy_pins_sense.2617331874 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_pkt_buffer.2067475036 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 14956210675 ps |
| CPU time | 38.74 seconds |
| Started | Feb 08 06:09:41 PM UTC 25 |
| Finished | Feb 08 06:10:22 PM UTC 25 |
| Peak memory | 227808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2067475036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbd ev_pkt_buffer.2067475036 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_pkt_received.4102961468 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 233399969 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:09:41 PM UTC 25 |
| Finished | Feb 08 06:09:44 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4102961468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.us bdev_pkt_received.4102961468 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_pkt_sent.2211070718 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 226381016 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:09:43 PM UTC 25 |
| Finished | Feb 08 06:09:46 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2211070718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev _pkt_sent.2211070718 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_random_length_in_transaction.2074562599 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 214284924 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:09:43 PM UTC 25 |
| Finished | Feb 08 06:09:45 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2074562599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.u sbdev_random_length_in_transaction.2074562599 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_random_length_out_transaction.373367830 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 186314999 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:09:43 PM UTC 25 |
| Finished | Feb 08 06:09:45 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=373367830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 23.usbdev_random_length_out_transaction.373367830 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_rx_crc_err.4065022681 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 143323468 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:09:43 PM UTC 25 |
| Finished | Feb 08 06:09:45 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4065022681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbd ev_rx_crc_err.4065022681 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_rx_full.262301826 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 366588411 ps |
| CPU time | 1.83 seconds |
| Started | Feb 08 06:09:44 PM UTC 25 |
| Finished | Feb 08 06:09:47 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=262301826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_r x_full.262301826 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_setup_stage.913072471 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 154533797 ps |
| CPU time | 0.97 seconds |
| Started | Feb 08 06:09:44 PM UTC 25 |
| Finished | Feb 08 06:09:46 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=913072471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbd ev_setup_stage.913072471 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_setup_trans_ignored.4020070856 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 163218714 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:09:44 PM UTC 25 |
| Finished | Feb 08 06:09:47 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4020070856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 23.usbdev_setup_trans_ignored.4020070856 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_smoke.4099808426 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 217357611 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:09:45 PM UTC 25 |
| Finished | Feb 08 06:09:48 PM UTC 25 |
| Peak memory | 214936 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4099808426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_sm oke.4099808426 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_spurious_pids_ignored.1938423835 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 2073530363 ps |
| CPU time | 17.23 seconds |
| Started | Feb 08 06:09:45 PM UTC 25 |
| Finished | Feb 08 06:10:04 PM UTC 25 |
| Peak memory | 234360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938423835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 23.usbdev_spurious_pids_ignored.1938423835 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_stall_priority_over_nak.2249786420 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 180319808 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:09:45 PM UTC 25 |
| Finished | Feb 08 06:09:48 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2249786420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 23.usbdev_stall_priority_over_nak.2249786420 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_stall_trans.75437142 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 174563626 ps |
| CPU time | 1.23 seconds |
| Started | Feb 08 06:09:47 PM UTC 25 |
| Finished | Feb 08 06:09:49 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=75437142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbde v_stall_trans.75437142 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_stream_len_max.2939946787 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 450063480 ps |
| CPU time | 1.8 seconds |
| Started | Feb 08 06:09:47 PM UTC 25 |
| Finished | Feb 08 06:09:50 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2939946787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23. usbdev_stream_len_max.2939946787 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_streaming_out.3230570711 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 2266783255 ps |
| CPU time | 63.45 seconds |
| Started | Feb 08 06:09:47 PM UTC 25 |
| Finished | Feb 08 06:10:52 PM UTC 25 |
| Peak memory | 227664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3230570711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbde v_streaming_out.3230570711 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_timeout_missing_host_handshake.2122773035 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 5555912140 ps |
| CPU time | 41.74 seconds |
| Started | Feb 08 06:09:22 PM UTC 25 |
| Finished | Feb 08 06:10:05 PM UTC 25 |
| Peak memory | 217612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122773035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing_host_handshake.2122773035 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/23.usbdev_tx_rx_disruption.419168093 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 701493975 ps |
| CPU time | 3.29 seconds |
| Started | Feb 08 06:09:47 PM UTC 25 |
| Finished | Feb 08 06:09:51 PM UTC 25 |
| Peak memory | 217124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 19168093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_tx_rx_disruption.419168093 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/23.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/230.usbdev_tx_rx_disruption.4115118004 |
| Short name | T3324 |
| Test name | |
| Test status | |
| Simulation time | 450636981 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:19:00 PM UTC 25 |
| Finished | Feb 08 06:19:04 PM UTC 25 |
| Peak memory | 214944 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 115118004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230.usbdev_tx_rx_disruption.4115118004 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/230.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/231.usbdev_tx_rx_disruption.636339347 |
| Short name | T3391 |
| Test name | |
| Test status | |
| Simulation time | 471213220 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:19:00 PM UTC 25 |
| Finished | Feb 08 06:19:24 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6 36339347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.usbdev_tx_rx_disruption.636339347 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/231.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/232.usbdev_tx_rx_disruption.831805019 |
| Short name | T3332 |
| Test name | |
| Test status | |
| Simulation time | 654552949 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:19:00 PM UTC 25 |
| Finished | Feb 08 06:19:04 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 31805019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 232.usbdev_tx_rx_disruption.831805019 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/232.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/233.usbdev_tx_rx_disruption.3214153965 |
| Short name | T3388 |
| Test name | |
| Test status | |
| Simulation time | 461150752 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:19:00 PM UTC 25 |
| Finished | Feb 08 06:19:24 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 214153965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233.usbdev_tx_rx_disruption.3214153965 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/233.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/234.usbdev_tx_rx_disruption.2289753608 |
| Short name | T3361 |
| Test name | |
| Test status | |
| Simulation time | 549000882 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:19:04 PM UTC 25 |
| Finished | Feb 08 06:19:14 PM UTC 25 |
| Peak memory | 215056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 289753608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.usbdev_tx_rx_disruption.2289753608 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/234.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/235.usbdev_tx_rx_disruption.2017842182 |
| Short name | T3357 |
| Test name | |
| Test status | |
| Simulation time | 607451469 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:19:04 PM UTC 25 |
| Finished | Feb 08 06:19:11 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 017842182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.usbdev_tx_rx_disruption.2017842182 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/235.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/236.usbdev_tx_rx_disruption.1130218907 |
| Short name | T3358 |
| Test name | |
| Test status | |
| Simulation time | 469076264 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:19:04 PM UTC 25 |
| Finished | Feb 08 06:19:13 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 130218907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 236.usbdev_tx_rx_disruption.1130218907 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/236.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/237.usbdev_tx_rx_disruption.3604862796 |
| Short name | T3356 |
| Test name | |
| Test status | |
| Simulation time | 624928366 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:19:04 PM UTC 25 |
| Finished | Feb 08 06:19:11 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 604862796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 237.usbdev_tx_rx_disruption.3604862796 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/237.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/238.usbdev_tx_rx_disruption.1769000727 |
| Short name | T3298 |
| Test name | |
| Test status | |
| Simulation time | 542815167 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:19:05 PM UTC 25 |
| Finished | Feb 08 06:19:10 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 769000727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238.usbdev_tx_rx_disruption.1769000727 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/238.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/239.usbdev_tx_rx_disruption.3452825681 |
| Short name | T3362 |
| Test name | |
| Test status | |
| Simulation time | 630133169 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:19:05 PM UTC 25 |
| Finished | Feb 08 06:19:14 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 452825681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 239.usbdev_tx_rx_disruption.3452825681 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/239.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_alert_test.157126565 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 34095711 ps |
| CPU time | 0.94 seconds |
| Started | Feb 08 06:10:09 PM UTC 25 |
| Finished | Feb 08 06:10:11 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157126565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 24.usbdev_alert_test.157126565 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_aon_wake_disconnect.3272937886 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 5844347001 ps |
| CPU time | 9.8 seconds |
| Started | Feb 08 06:09:48 PM UTC 25 |
| Finished | Feb 08 06:09:59 PM UTC 25 |
| Peak memory | 227652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272937886 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.3272937886 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_aon_wake_reset.2101974789 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 20445681247 ps |
| CPU time | 42.14 seconds |
| Started | Feb 08 06:09:48 PM UTC 25 |
| Finished | Feb 08 06:10:32 PM UTC 25 |
| Peak memory | 217576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101974789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.2101974789 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_aon_wake_resume.1095289250 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 30371440842 ps |
| CPU time | 50.19 seconds |
| Started | Feb 08 06:09:50 PM UTC 25 |
| Finished | Feb 08 06:10:41 PM UTC 25 |
| Peak memory | 217576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095289250 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.1095289250 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_av_buffer.4125523317 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 145024305 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:09:50 PM UTC 25 |
| Finished | Feb 08 06:09:52 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4125523317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbde v_av_buffer.4125523317 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_bitstuff_err.1018300731 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 227902427 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:09:50 PM UTC 25 |
| Finished | Feb 08 06:09:52 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1018300731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.us bdev_bitstuff_err.1018300731 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_data_toggle_clear.1247530138 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 502598021 ps |
| CPU time | 2.95 seconds |
| Started | Feb 08 06:09:51 PM UTC 25 |
| Finished | Feb 08 06:09:55 PM UTC 25 |
| Peak memory | 217004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1247530138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.1247530138 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_data_toggle_restore.2907203531 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 326858712 ps |
| CPU time | 2 seconds |
| Started | Feb 08 06:09:51 PM UTC 25 |
| Finished | Feb 08 06:09:54 PM UTC 25 |
| Peak memory | 214960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907203531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.2907203531 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_device_address.2092870249 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 42060449814 ps |
| CPU time | 81.95 seconds |
| Started | Feb 08 06:09:51 PM UTC 25 |
| Finished | Feb 08 06:11:15 PM UTC 25 |
| Peak memory | 217468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2092870249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24. usbdev_device_address.2092870249 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_device_timeout.1202623478 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 4287789468 ps |
| CPU time | 28.16 seconds |
| Started | Feb 08 06:09:53 PM UTC 25 |
| Finished | Feb 08 06:10:23 PM UTC 25 |
| Peak memory | 217520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202623478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.1202623478 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_disable_endpoint.4227221687 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 797087551 ps |
| CPU time | 3.01 seconds |
| Started | Feb 08 06:09:53 PM UTC 25 |
| Finished | Feb 08 06:09:58 PM UTC 25 |
| Peak memory | 216956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4227221687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.usbdev_disable_endpoint.4227221687 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_disconnected.3610335315 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 145461832 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:09:53 PM UTC 25 |
| Finished | Feb 08 06:09:56 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3610335315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.us bdev_disconnected.3610335315 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_enable.3577755101 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 58436895 ps |
| CPU time | 1.02 seconds |
| Started | Feb 08 06:09:54 PM UTC 25 |
| Finished | Feb 08 06:09:56 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3577755101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_e nable.3577755101 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_endpoint_access.3031879932 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 674009994 ps |
| CPU time | 3.31 seconds |
| Started | Feb 08 06:09:54 PM UTC 25 |
| Finished | Feb 08 06:09:58 PM UTC 25 |
| Peak memory | 217632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3031879932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24 .usbdev_endpoint_access.3031879932 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_endpoint_types.741365740 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 385362949 ps |
| CPU time | 1.89 seconds |
| Started | Feb 08 06:09:54 PM UTC 25 |
| Finished | Feb 08 06:09:57 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741365740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 24.usbdev_endpoint_types.741365740 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_fifo_rst.4201659421 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 335778431 ps |
| CPU time | 2.85 seconds |
| Started | Feb 08 06:09:55 PM UTC 25 |
| Finished | Feb 08 06:09:59 PM UTC 25 |
| Peak memory | 217280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4201659421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev _fifo_rst.4201659421 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_in_iso.2485103207 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 216275628 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:09:55 PM UTC 25 |
| Finished | Feb 08 06:09:58 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485103207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 24.usbdev_in_iso.2485103207 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_in_stall.2230805748 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 144916053 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:09:55 PM UTC 25 |
| Finished | Feb 08 06:09:58 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2230805748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev _in_stall.2230805748 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_in_trans.430912320 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 200457976 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:09:57 PM UTC 25 |
| Finished | Feb 08 06:10:00 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=430912320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_ in_trans.430912320 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_invalid_sync.486299458 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 3298057507 ps |
| CPU time | 26.54 seconds |
| Started | Feb 08 06:09:55 PM UTC 25 |
| Finished | Feb 08 06:10:23 PM UTC 25 |
| Peak memory | 227868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486299458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.486299458 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_iso_retraction.1069076299 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 4690002141 ps |
| CPU time | 31.7 seconds |
| Started | Feb 08 06:09:57 PM UTC 25 |
| Finished | Feb 08 06:10:30 PM UTC 25 |
| Peak memory | 217548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069076299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 24.usbdev_iso_retraction.1069076299 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_link_in_err.2590159524 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 201348243 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:09:57 PM UTC 25 |
| Finished | Feb 08 06:10:00 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2590159524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usb dev_link_in_err.2590159524 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_link_resume.3403915797 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 33317182240 ps |
| CPU time | 60.71 seconds |
| Started | Feb 08 06:09:57 PM UTC 25 |
| Finished | Feb 08 06:11:00 PM UTC 25 |
| Peak memory | 217584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3403915797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usb dev_link_resume.3403915797 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_link_suspend.3371164827 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 10072063041 ps |
| CPU time | 14.89 seconds |
| Started | Feb 08 06:09:57 PM UTC 25 |
| Finished | Feb 08 06:10:13 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3371164827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.us bdev_link_suspend.3371164827 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_low_speed_traffic.1616973540 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 4590798575 ps |
| CPU time | 124.01 seconds |
| Started | Feb 08 06:09:58 PM UTC 25 |
| Finished | Feb 08 06:12:05 PM UTC 25 |
| Peak memory | 234648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616973540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 24.usbdev_low_speed_traffic.1616973540 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_max_inter_pkt_delay.495831555 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 1975414612 ps |
| CPU time | 57.52 seconds |
| Started | Feb 08 06:09:58 PM UTC 25 |
| Finished | Feb 08 06:10:58 PM UTC 25 |
| Peak memory | 227528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495831555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.495831555 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_max_length_in_transaction.967832610 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 237939718 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:09:59 PM UTC 25 |
| Finished | Feb 08 06:10:01 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967832610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 24.usbdev_max_length_in_transaction.967832610 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_max_length_out_transaction.3384891175 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 195087122 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:09:59 PM UTC 25 |
| Finished | Feb 08 06:10:01 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3384891175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.3384891175 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_max_non_iso_usb_traffic.3597575734 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 2431601328 ps |
| CPU time | 23.45 seconds |
| Started | Feb 08 06:09:59 PM UTC 25 |
| Finished | Feb 08 06:10:23 PM UTC 25 |
| Peak memory | 227692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3597575734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 24.usbdev_max_non_iso_usb_traffic.3597575734 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_min_inter_pkt_delay.1221336884 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 2019903639 ps |
| CPU time | 17.42 seconds |
| Started | Feb 08 06:10:00 PM UTC 25 |
| Finished | Feb 08 06:10:19 PM UTC 25 |
| Peak memory | 227708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221336884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.1221336884 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_min_length_in_transaction.3399111048 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 164952469 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:10:00 PM UTC 25 |
| Finished | Feb 08 06:10:03 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399111048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 24.usbdev_min_length_in_transaction.3399111048 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_min_length_out_transaction.2488643186 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 148097695 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:10:00 PM UTC 25 |
| Finished | Feb 08 06:10:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2488643186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2488643186 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_nak_trans.3368445331 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 218550238 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:10:00 PM UTC 25 |
| Finished | Feb 08 06:10:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3368445331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbde v_nak_trans.3368445331 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_out_iso.2083944792 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 173953633 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:10:00 PM UTC 25 |
| Finished | Feb 08 06:10:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2083944792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_ out_iso.2083944792 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_out_stall.2193891889 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 162943684 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:10:00 PM UTC 25 |
| Finished | Feb 08 06:10:03 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2193891889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbde v_out_stall.2193891889 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_out_trans_nak.1722427720 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 169980871 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:10:00 PM UTC 25 |
| Finished | Feb 08 06:10:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1722427720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.u sbdev_out_trans_nak.1722427720 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_pending_in_trans.2027240591 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 237934067 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:10:02 PM UTC 25 |
| Finished | Feb 08 06:10:04 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2027240591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.usbdev_pending_in_trans.2027240591 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_phy_config_pinflip.1806842162 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 179363387 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:10:02 PM UTC 25 |
| Finished | Feb 08 06:10:04 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806842162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 24.usbdev_phy_config_pinflip.1806842162 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_phy_config_usb_ref_disable.598867703 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 167409661 ps |
| CPU time | 1 seconds |
| Started | Feb 08 06:10:03 PM UTC 25 |
| Finished | Feb 08 06:10:05 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=598867703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 24.usbdev_phy_config_usb_ref_disable.598867703 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_phy_pins_sense.2585592920 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 31802199 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 06:10:04 PM UTC 25 |
| Finished | Feb 08 06:10:06 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2585592920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24. usbdev_phy_pins_sense.2585592920 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_pkt_buffer.3212270440 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 22681328964 ps |
| CPU time | 66.34 seconds |
| Started | Feb 08 06:10:04 PM UTC 25 |
| Finished | Feb 08 06:11:12 PM UTC 25 |
| Peak memory | 227684 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3212270440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbd ev_pkt_buffer.3212270440 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_pkt_received.2474240628 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 168180208 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:10:04 PM UTC 25 |
| Finished | Feb 08 06:10:07 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2474240628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.us bdev_pkt_received.2474240628 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_pkt_sent.1658482181 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 216115872 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:10:04 PM UTC 25 |
| Finished | Feb 08 06:10:07 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1658482181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev _pkt_sent.1658482181 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_random_length_in_transaction.1047545563 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 206918777 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:10:04 PM UTC 25 |
| Finished | Feb 08 06:10:07 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1047545563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.u sbdev_random_length_in_transaction.1047545563 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_random_length_out_transaction.511151384 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 258867440 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:10:04 PM UTC 25 |
| Finished | Feb 08 06:10:07 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=511151384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 24.usbdev_random_length_out_transaction.511151384 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_rx_crc_err.539995660 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 167262792 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:10:06 PM UTC 25 |
| Finished | Feb 08 06:10:08 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=539995660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbde v_rx_crc_err.539995660 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_rx_full.1012757277 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 442744863 ps |
| CPU time | 2.46 seconds |
| Started | Feb 08 06:10:06 PM UTC 25 |
| Finished | Feb 08 06:10:09 PM UTC 25 |
| Peak memory | 217132 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1012757277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_ rx_full.1012757277 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_setup_stage.3017648645 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 158072940 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 06:10:06 PM UTC 25 |
| Finished | Feb 08 06:10:08 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3017648645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usb dev_setup_stage.3017648645 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_setup_trans_ignored.2505967623 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 160207979 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:10:06 PM UTC 25 |
| Finished | Feb 08 06:10:08 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2505967623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 24.usbdev_setup_trans_ignored.2505967623 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_smoke.2127506256 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 208960489 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:10:06 PM UTC 25 |
| Finished | Feb 08 06:10:09 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2127506256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_sm oke.2127506256 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_spurious_pids_ignored.4244738331 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 3493541896 ps |
| CPU time | 36.5 seconds |
| Started | Feb 08 06:10:07 PM UTC 25 |
| Finished | Feb 08 06:10:45 PM UTC 25 |
| Peak memory | 227648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244738331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 24.usbdev_spurious_pids_ignored.4244738331 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_stall_priority_over_nak.2746130370 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 173544749 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:10:07 PM UTC 25 |
| Finished | Feb 08 06:10:10 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2746130370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 24.usbdev_stall_priority_over_nak.2746130370 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_stall_trans.3608041082 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 179021418 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:10:07 PM UTC 25 |
| Finished | Feb 08 06:10:10 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3608041082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usb dev_stall_trans.3608041082 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_stream_len_max.2009741850 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 1012450022 ps |
| CPU time | 4.91 seconds |
| Started | Feb 08 06:10:09 PM UTC 25 |
| Finished | Feb 08 06:10:15 PM UTC 25 |
| Peak memory | 217128 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2009741850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24. usbdev_stream_len_max.2009741850 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_streaming_out.3577099502 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 2376818847 ps |
| CPU time | 18.98 seconds |
| Started | Feb 08 06:10:07 PM UTC 25 |
| Finished | Feb 08 06:10:28 PM UTC 25 |
| Peak memory | 229900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3577099502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbde v_streaming_out.3577099502 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_timeout_missing_host_handshake.808829468 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 851287544 ps |
| CPU time | 17.46 seconds |
| Started | Feb 08 06:09:53 PM UTC 25 |
| Finished | Feb 08 06:10:12 PM UTC 25 |
| Peak memory | 217476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808829468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing_host_handshake.808829468 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_tx_rx_disruption.2179267593 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 578660326 ps |
| CPU time | 2.84 seconds |
| Started | Feb 08 06:10:09 PM UTC 25 |
| Finished | Feb 08 06:10:13 PM UTC 25 |
| Peak memory | 217372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 179267593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_tx_rx_disruption.2179267593 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/24.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/240.usbdev_tx_rx_disruption.1554988856 |
| Short name | T3359 |
| Test name | |
| Test status | |
| Simulation time | 552589560 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:19:05 PM UTC 25 |
| Finished | Feb 08 06:19:13 PM UTC 25 |
| Peak memory | 215000 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 554988856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 240.usbdev_tx_rx_disruption.1554988856 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/240.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/241.usbdev_tx_rx_disruption.1927327357 |
| Short name | T3406 |
| Test name | |
| Test status | |
| Simulation time | 583496389 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:19:05 PM UTC 25 |
| Finished | Feb 08 06:19:34 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 927327357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241.usbdev_tx_rx_disruption.1927327357 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/241.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/242.usbdev_tx_rx_disruption.2155388677 |
| Short name | T3363 |
| Test name | |
| Test status | |
| Simulation time | 653359153 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:19:05 PM UTC 25 |
| Finished | Feb 08 06:19:14 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 155388677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242.usbdev_tx_rx_disruption.2155388677 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/242.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/243.usbdev_tx_rx_disruption.79106314 |
| Short name | T3333 |
| Test name | |
| Test status | |
| Simulation time | 546709033 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:19:05 PM UTC 25 |
| Finished | Feb 08 06:19:08 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 9106314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243.usbdev_tx_rx_disruption.79106314 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/243.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/244.usbdev_tx_rx_disruption.243050292 |
| Short name | T3334 |
| Test name | |
| Test status | |
| Simulation time | 521855348 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:19:05 PM UTC 25 |
| Finished | Feb 08 06:19:08 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 43050292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 244.usbdev_tx_rx_disruption.243050292 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/244.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/245.usbdev_tx_rx_disruption.206570702 |
| Short name | T3338 |
| Test name | |
| Test status | |
| Simulation time | 599962712 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:19:06 PM UTC 25 |
| Finished | Feb 08 06:19:09 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 06570702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245.usbdev_tx_rx_disruption.206570702 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/245.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/246.usbdev_tx_rx_disruption.1220777405 |
| Short name | T3336 |
| Test name | |
| Test status | |
| Simulation time | 608705160 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:19:06 PM UTC 25 |
| Finished | Feb 08 06:19:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 220777405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 246.usbdev_tx_rx_disruption.1220777405 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/246.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/247.usbdev_tx_rx_disruption.4040464171 |
| Short name | T3365 |
| Test name | |
| Test status | |
| Simulation time | 459017627 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:19:08 PM UTC 25 |
| Finished | Feb 08 06:19:18 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 040464171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.usbdev_tx_rx_disruption.4040464171 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/247.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/248.usbdev_tx_rx_disruption.1317285464 |
| Short name | T3371 |
| Test name | |
| Test status | |
| Simulation time | 491353703 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:19:09 PM UTC 25 |
| Finished | Feb 08 06:19:20 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 317285464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248.usbdev_tx_rx_disruption.1317285464 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/248.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/249.usbdev_tx_rx_disruption.851178217 |
| Short name | T3370 |
| Test name | |
| Test status | |
| Simulation time | 484077763 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:19:09 PM UTC 25 |
| Finished | Feb 08 06:19:20 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 51178217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249.usbdev_tx_rx_disruption.851178217 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/249.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_alert_test.4078147081 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 35046691 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 06:10:31 PM UTC 25 |
| Finished | Feb 08 06:10:34 PM UTC 25 |
| Peak memory | 214228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078147081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 25.usbdev_alert_test.4078147081 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_aon_wake_disconnect.3035816771 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 10196735208 ps |
| CPU time | 17.69 seconds |
| Started | Feb 08 06:10:09 PM UTC 25 |
| Finished | Feb 08 06:10:28 PM UTC 25 |
| Peak memory | 217636 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035816771 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.3035816771 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_aon_wake_reset.1440107679 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 19954016600 ps |
| CPU time | 32.21 seconds |
| Started | Feb 08 06:10:09 PM UTC 25 |
| Finished | Feb 08 06:10:42 PM UTC 25 |
| Peak memory | 217384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440107679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.1440107679 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_aon_wake_resume.2225171237 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 30717940452 ps |
| CPU time | 46.76 seconds |
| Started | Feb 08 06:10:09 PM UTC 25 |
| Finished | Feb 08 06:10:57 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225171237 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.2225171237 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_av_buffer.3016372051 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 172520596 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:10:10 PM UTC 25 |
| Finished | Feb 08 06:10:13 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3016372051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbde v_av_buffer.3016372051 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_bitstuff_err.2546151698 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 148753060 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:10:10 PM UTC 25 |
| Finished | Feb 08 06:10:13 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2546151698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.us bdev_bitstuff_err.2546151698 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_data_toggle_clear.3940605410 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 189641238 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:10:10 PM UTC 25 |
| Finished | Feb 08 06:10:13 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3940605410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.3940605410 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_data_toggle_restore.1441320743 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 1304918763 ps |
| CPU time | 3.89 seconds |
| Started | Feb 08 06:10:10 PM UTC 25 |
| Finished | Feb 08 06:10:16 PM UTC 25 |
| Peak memory | 217316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441320743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.1441320743 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_device_address.600491648 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 46329272324 ps |
| CPU time | 110.71 seconds |
| Started | Feb 08 06:10:10 PM UTC 25 |
| Finished | Feb 08 06:12:03 PM UTC 25 |
| Peak memory | 217428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=600491648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.u sbdev_device_address.600491648 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_device_timeout.931722105 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 1516820664 ps |
| CPU time | 43.67 seconds |
| Started | Feb 08 06:10:10 PM UTC 25 |
| Finished | Feb 08 06:10:56 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931722105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.931722105 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_disable_endpoint.4288053238 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 859167123 ps |
| CPU time | 3.35 seconds |
| Started | Feb 08 06:10:12 PM UTC 25 |
| Finished | Feb 08 06:10:16 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4288053238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.usbdev_disable_endpoint.4288053238 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_disconnected.1569490064 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 150816369 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:10:13 PM UTC 25 |
| Finished | Feb 08 06:10:15 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1569490064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.us bdev_disconnected.1569490064 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_enable.1041578500 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 42855270 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:10:14 PM UTC 25 |
| Finished | Feb 08 06:10:17 PM UTC 25 |
| Peak memory | 214300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1041578500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_e nable.1041578500 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_endpoint_access.3384112638 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 783609695 ps |
| CPU time | 4.35 seconds |
| Started | Feb 08 06:10:14 PM UTC 25 |
| Finished | Feb 08 06:10:20 PM UTC 25 |
| Peak memory | 216908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3384112638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25 .usbdev_endpoint_access.3384112638 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_fifo_rst.1592665980 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 295921490 ps |
| CPU time | 2.84 seconds |
| Started | Feb 08 06:10:14 PM UTC 25 |
| Finished | Feb 08 06:10:18 PM UTC 25 |
| Peak memory | 217280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1592665980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev _fifo_rst.1592665980 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_in_iso.1945228193 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 184046869 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:10:14 PM UTC 25 |
| Finished | Feb 08 06:10:17 PM UTC 25 |
| Peak memory | 227756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945228193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 25.usbdev_in_iso.1945228193 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_in_stall.893084882 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 160903072 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:10:16 PM UTC 25 |
| Finished | Feb 08 06:10:18 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=893084882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_ in_stall.893084882 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_in_trans.3535885621 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 179057265 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:10:16 PM UTC 25 |
| Finished | Feb 08 06:10:18 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3535885621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev _in_trans.3535885621 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_invalid_sync.1469154732 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 2538345843 ps |
| CPU time | 69.52 seconds |
| Started | Feb 08 06:10:14 PM UTC 25 |
| Finished | Feb 08 06:11:26 PM UTC 25 |
| Peak memory | 229692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469154732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.1469154732 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_iso_retraction.1999473521 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 3845516696 ps |
| CPU time | 46.21 seconds |
| Started | Feb 08 06:10:17 PM UTC 25 |
| Finished | Feb 08 06:11:05 PM UTC 25 |
| Peak memory | 217348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999473521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 25.usbdev_iso_retraction.1999473521 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_link_in_err.1837795982 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 227602895 ps |
| CPU time | 1.71 seconds |
| Started | Feb 08 06:10:17 PM UTC 25 |
| Finished | Feb 08 06:10:20 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1837795982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usb dev_link_in_err.1837795982 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_link_resume.954871788 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 27016346898 ps |
| CPU time | 52.28 seconds |
| Started | Feb 08 06:10:18 PM UTC 25 |
| Finished | Feb 08 06:11:12 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=954871788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbd ev_link_resume.954871788 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_link_suspend.1805309569 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 11374408706 ps |
| CPU time | 24.33 seconds |
| Started | Feb 08 06:10:18 PM UTC 25 |
| Finished | Feb 08 06:10:44 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1805309569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.us bdev_link_suspend.1805309569 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_low_speed_traffic.4139283755 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 5466481561 ps |
| CPU time | 56.41 seconds |
| Started | Feb 08 06:10:19 PM UTC 25 |
| Finished | Feb 08 06:11:18 PM UTC 25 |
| Peak memory | 229536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139283755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 25.usbdev_low_speed_traffic.4139283755 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_max_inter_pkt_delay.3633359079 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 1632247226 ps |
| CPU time | 12.67 seconds |
| Started | Feb 08 06:10:19 PM UTC 25 |
| Finished | Feb 08 06:10:33 PM UTC 25 |
| Peak memory | 229420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633359079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.3633359079 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_max_length_in_transaction.4195539149 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 237287646 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:10:20 PM UTC 25 |
| Finished | Feb 08 06:10:22 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195539149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 25.usbdev_max_length_in_transaction.4195539149 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_max_length_out_transaction.688546122 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 191139554 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:10:20 PM UTC 25 |
| Finished | Feb 08 06:10:22 PM UTC 25 |
| Peak memory | 215048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=688546122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 25.usbdev_max_length_out_transaction.688546122 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_min_inter_pkt_delay.4166287865 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 4066312326 ps |
| CPU time | 106.33 seconds |
| Started | Feb 08 06:10:20 PM UTC 25 |
| Finished | Feb 08 06:12:08 PM UTC 25 |
| Peak memory | 229840 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166287865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.4166287865 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_min_length_in_transaction.454679185 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 168048061 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:10:21 PM UTC 25 |
| Finished | Feb 08 06:10:24 PM UTC 25 |
| Peak memory | 214784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454679185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 25.usbdev_min_length_in_transaction.454679185 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_min_length_out_transaction.3256783449 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 144269964 ps |
| CPU time | 1.21 seconds |
| Started | Feb 08 06:10:21 PM UTC 25 |
| Finished | Feb 08 06:10:23 PM UTC 25 |
| Peak memory | 214720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3256783449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.3256783449 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_nak_trans.3509031875 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 241841631 ps |
| CPU time | 1.71 seconds |
| Started | Feb 08 06:10:21 PM UTC 25 |
| Finished | Feb 08 06:10:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3509031875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbde v_nak_trans.3509031875 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_out_iso.3878934027 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 163835625 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:10:23 PM UTC 25 |
| Finished | Feb 08 06:10:25 PM UTC 25 |
| Peak memory | 215072 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3878934027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_ out_iso.3878934027 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_out_stall.3078079844 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 211402879 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:10:23 PM UTC 25 |
| Finished | Feb 08 06:10:25 PM UTC 25 |
| Peak memory | 215048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3078079844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbde v_out_stall.3078079844 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_out_trans_nak.271992946 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 232465927 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:10:23 PM UTC 25 |
| Finished | Feb 08 06:10:25 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=271992946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.us bdev_out_trans_nak.271992946 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_pending_in_trans.2322711095 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 153159498 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:10:24 PM UTC 25 |
| Finished | Feb 08 06:10:27 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2322711095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.usbdev_pending_in_trans.2322711095 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_phy_config_pinflip.856876695 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 211838651 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:10:24 PM UTC 25 |
| Finished | Feb 08 06:10:27 PM UTC 25 |
| Peak memory | 215076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=856876695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 25.usbdev_phy_config_pinflip.856876695 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_phy_config_usb_ref_disable.2759734272 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 144660759 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:10:24 PM UTC 25 |
| Finished | Feb 08 06:10:27 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2759734272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.2759734272 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_phy_pins_sense.1121540100 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 41478915 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:10:24 PM UTC 25 |
| Finished | Feb 08 06:10:27 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1121540100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25. usbdev_phy_pins_sense.1121540100 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_pkt_buffer.4285374223 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 19198710420 ps |
| CPU time | 50.82 seconds |
| Started | Feb 08 06:10:24 PM UTC 25 |
| Finished | Feb 08 06:11:17 PM UTC 25 |
| Peak memory | 227748 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4285374223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbd ev_pkt_buffer.4285374223 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_pkt_received.1122521178 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 182849204 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:10:24 PM UTC 25 |
| Finished | Feb 08 06:10:27 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1122521178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.us bdev_pkt_received.1122521178 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_pkt_sent.3985549317 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 164174751 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:10:26 PM UTC 25 |
| Finished | Feb 08 06:10:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3985549317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev _pkt_sent.3985549317 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_random_length_in_transaction.3514260737 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 236754006 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:10:26 PM UTC 25 |
| Finished | Feb 08 06:10:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3514260737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.u sbdev_random_length_in_transaction.3514260737 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_random_length_out_transaction.2216715028 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 189670250 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 06:10:26 PM UTC 25 |
| Finished | Feb 08 06:10:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2216715028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 25.usbdev_random_length_out_transaction.2216715028 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_rx_crc_err.568913209 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 143265480 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 06:10:27 PM UTC 25 |
| Finished | Feb 08 06:10:30 PM UTC 25 |
| Peak memory | 215036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=568913209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbde v_rx_crc_err.568913209 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_rx_full.2703046013 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 327760669 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:10:27 PM UTC 25 |
| Finished | Feb 08 06:10:30 PM UTC 25 |
| Peak memory | 215052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2703046013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_ rx_full.2703046013 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_setup_stage.3143057004 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 238817427 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:10:27 PM UTC 25 |
| Finished | Feb 08 06:10:30 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3143057004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usb dev_setup_stage.3143057004 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_setup_trans_ignored.1822559744 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 168166429 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:10:27 PM UTC 25 |
| Finished | Feb 08 06:10:30 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1822559744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 25.usbdev_setup_trans_ignored.1822559744 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_smoke.1228810489 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 232067059 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 06:10:29 PM UTC 25 |
| Finished | Feb 08 06:10:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1228810489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_sm oke.1228810489 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_spurious_pids_ignored.3223581147 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 2534687859 ps |
| CPU time | 68.73 seconds |
| Started | Feb 08 06:10:29 PM UTC 25 |
| Finished | Feb 08 06:11:39 PM UTC 25 |
| Peak memory | 227720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223581147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 25.usbdev_spurious_pids_ignored.3223581147 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_stall_priority_over_nak.2413098567 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 180490073 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 06:10:29 PM UTC 25 |
| Finished | Feb 08 06:10:31 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2413098567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 25.usbdev_stall_priority_over_nak.2413098567 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_stall_trans.1174695819 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 173133044 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:10:29 PM UTC 25 |
| Finished | Feb 08 06:10:32 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1174695819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usb dev_stall_trans.1174695819 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_stream_len_max.613657833 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 1238100035 ps |
| CPU time | 5.98 seconds |
| Started | Feb 08 06:10:29 PM UTC 25 |
| Finished | Feb 08 06:10:36 PM UTC 25 |
| Peak memory | 217552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=613657833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.u sbdev_stream_len_max.613657833 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_streaming_out.2225109343 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 1875539843 ps |
| CPU time | 17.68 seconds |
| Started | Feb 08 06:10:29 PM UTC 25 |
| Finished | Feb 08 06:10:48 PM UTC 25 |
| Peak memory | 217548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2225109343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbde v_streaming_out.2225109343 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_timeout_missing_host_handshake.2995815724 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 1488072288 ps |
| CPU time | 33.46 seconds |
| Started | Feb 08 06:10:12 PM UTC 25 |
| Finished | Feb 08 06:10:47 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995815724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_host_handshake.2995815724 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_tx_rx_disruption.2046974062 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 536547934 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:10:30 PM UTC 25 |
| Finished | Feb 08 06:10:33 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 046974062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_tx_rx_disruption.2046974062 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/25.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/250.usbdev_tx_rx_disruption.3372727383 |
| Short name | T3373 |
| Test name | |
| Test status | |
| Simulation time | 525688478 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:19:10 PM UTC 25 |
| Finished | Feb 08 06:19:20 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 372727383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250.usbdev_tx_rx_disruption.3372727383 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/250.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/251.usbdev_tx_rx_disruption.1086436563 |
| Short name | T3374 |
| Test name | |
| Test status | |
| Simulation time | 555583549 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:19:10 PM UTC 25 |
| Finished | Feb 08 06:19:20 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 086436563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.usbdev_tx_rx_disruption.1086436563 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/251.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/252.usbdev_tx_rx_disruption.2552976376 |
| Short name | T3375 |
| Test name | |
| Test status | |
| Simulation time | 648731119 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:19:10 PM UTC 25 |
| Finished | Feb 08 06:19:20 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 552976376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 252.usbdev_tx_rx_disruption.2552976376 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/252.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/253.usbdev_tx_rx_disruption.3199112594 |
| Short name | T3372 |
| Test name | |
| Test status | |
| Simulation time | 550334082 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:19:10 PM UTC 25 |
| Finished | Feb 08 06:19:20 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 199112594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253.usbdev_tx_rx_disruption.3199112594 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/253.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/254.usbdev_tx_rx_disruption.866824979 |
| Short name | T3360 |
| Test name | |
| Test status | |
| Simulation time | 668569922 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:19:10 PM UTC 25 |
| Finished | Feb 08 06:19:14 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 66824979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.usbdev_tx_rx_disruption.866824979 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/254.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/255.usbdev_tx_rx_disruption.308336102 |
| Short name | T3429 |
| Test name | |
| Test status | |
| Simulation time | 667991241 ps |
| CPU time | 1.67 seconds |
| Started | Feb 08 06:19:11 PM UTC 25 |
| Finished | Feb 08 06:19:41 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 08336102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 255.usbdev_tx_rx_disruption.308336102 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/255.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/256.usbdev_tx_rx_disruption.1512953849 |
| Short name | T3425 |
| Test name | |
| Test status | |
| Simulation time | 529856725 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:19:11 PM UTC 25 |
| Finished | Feb 08 06:19:41 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 512953849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 256.usbdev_tx_rx_disruption.1512953849 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/256.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/257.usbdev_tx_rx_disruption.1701443636 |
| Short name | T3423 |
| Test name | |
| Test status | |
| Simulation time | 531413197 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:19:11 PM UTC 25 |
| Finished | Feb 08 06:19:41 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 701443636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257.usbdev_tx_rx_disruption.1701443636 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/257.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/258.usbdev_tx_rx_disruption.3637359785 |
| Short name | T3424 |
| Test name | |
| Test status | |
| Simulation time | 557077029 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:19:11 PM UTC 25 |
| Finished | Feb 08 06:19:41 PM UTC 25 |
| Peak memory | 215088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 637359785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 258.usbdev_tx_rx_disruption.3637359785 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/258.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/259.usbdev_tx_rx_disruption.3483724837 |
| Short name | T3428 |
| Test name | |
| Test status | |
| Simulation time | 592847477 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:19:11 PM UTC 25 |
| Finished | Feb 08 06:19:41 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 483724837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.usbdev_tx_rx_disruption.3483724837 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/259.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_alert_test.2753948228 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 38477858 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 06:10:52 PM UTC 25 |
| Finished | Feb 08 06:10:54 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753948228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 26.usbdev_alert_test.2753948228 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_aon_wake_disconnect.1761063640 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 5708358786 ps |
| CPU time | 11.23 seconds |
| Started | Feb 08 06:10:31 PM UTC 25 |
| Finished | Feb 08 06:10:44 PM UTC 25 |
| Peak memory | 227588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761063640 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.1761063640 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_aon_wake_reset.1961126402 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 20545606871 ps |
| CPU time | 28.24 seconds |
| Started | Feb 08 06:10:31 PM UTC 25 |
| Finished | Feb 08 06:11:01 PM UTC 25 |
| Peak memory | 216940 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961126402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.1961126402 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_aon_wake_resume.2074763313 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 26156911676 ps |
| CPU time | 46.2 seconds |
| Started | Feb 08 06:10:31 PM UTC 25 |
| Finished | Feb 08 06:11:19 PM UTC 25 |
| Peak memory | 227592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074763313 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.2074763313 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_av_buffer.2367838258 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 170021959 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:10:31 PM UTC 25 |
| Finished | Feb 08 06:10:34 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2367838258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbde v_av_buffer.2367838258 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_bitstuff_err.2171597516 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 151497564 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:10:32 PM UTC 25 |
| Finished | Feb 08 06:10:34 PM UTC 25 |
| Peak memory | 215128 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2171597516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.us bdev_bitstuff_err.2171597516 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_data_toggle_clear.3752937445 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 233326987 ps |
| CPU time | 1.79 seconds |
| Started | Feb 08 06:10:33 PM UTC 25 |
| Finished | Feb 08 06:10:36 PM UTC 25 |
| Peak memory | 214924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3752937445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.3752937445 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_data_toggle_restore.119090706 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 343823213 ps |
| CPU time | 2.09 seconds |
| Started | Feb 08 06:10:33 PM UTC 25 |
| Finished | Feb 08 06:10:36 PM UTC 25 |
| Peak memory | 216980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119090706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_t oggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.119090706 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_device_address.2433865037 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 39594341296 ps |
| CPU time | 66.3 seconds |
| Started | Feb 08 06:10:33 PM UTC 25 |
| Finished | Feb 08 06:11:41 PM UTC 25 |
| Peak memory | 217616 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2433865037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26. usbdev_device_address.2433865037 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_device_timeout.2699856471 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 1518564461 ps |
| CPU time | 14.84 seconds |
| Started | Feb 08 06:10:33 PM UTC 25 |
| Finished | Feb 08 06:10:49 PM UTC 25 |
| Peak memory | 217340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699856471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.2699856471 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_disable_endpoint.4037230301 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 533668533 ps |
| CPU time | 1.94 seconds |
| Started | Feb 08 06:10:34 PM UTC 25 |
| Finished | Feb 08 06:10:37 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4037230301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.usbdev_disable_endpoint.4037230301 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_disconnected.2247804112 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 156735996 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:10:34 PM UTC 25 |
| Finished | Feb 08 06:10:36 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2247804112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.us bdev_disconnected.2247804112 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_enable.3552555219 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 43486240 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:10:34 PM UTC 25 |
| Finished | Feb 08 06:10:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3552555219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_e nable.3552555219 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_endpoint_access.595675455 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 968892735 ps |
| CPU time | 2.68 seconds |
| Started | Feb 08 06:10:35 PM UTC 25 |
| Finished | Feb 08 06:10:39 PM UTC 25 |
| Peak memory | 217312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=595675455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26. usbdev_endpoint_access.595675455 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_endpoint_types.341891593 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 273564784 ps |
| CPU time | 1.92 seconds |
| Started | Feb 08 06:10:35 PM UTC 25 |
| Finished | Feb 08 06:10:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341891593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 26.usbdev_endpoint_types.341891593 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_fifo_rst.1154807709 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 287385608 ps |
| CPU time | 3.17 seconds |
| Started | Feb 08 06:10:37 PM UTC 25 |
| Finished | Feb 08 06:10:41 PM UTC 25 |
| Peak memory | 217404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1154807709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev _fifo_rst.1154807709 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_in_iso.3447506438 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 229742851 ps |
| CPU time | 1.96 seconds |
| Started | Feb 08 06:10:37 PM UTC 25 |
| Finished | Feb 08 06:10:40 PM UTC 25 |
| Peak memory | 233664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447506438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 26.usbdev_in_iso.3447506438 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_in_stall.4268230605 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 175387527 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:10:37 PM UTC 25 |
| Finished | Feb 08 06:10:40 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4268230605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev _in_stall.4268230605 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_in_trans.500484554 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 184740905 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:10:37 PM UTC 25 |
| Finished | Feb 08 06:10:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=500484554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_ in_trans.500484554 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_invalid_sync.4219122940 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 3163477086 ps |
| CPU time | 28.13 seconds |
| Started | Feb 08 06:10:37 PM UTC 25 |
| Finished | Feb 08 06:11:07 PM UTC 25 |
| Peak memory | 227852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219122940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.4219122940 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_iso_retraction.1924573490 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 13372524709 ps |
| CPU time | 106.03 seconds |
| Started | Feb 08 06:10:37 PM UTC 25 |
| Finished | Feb 08 06:12:26 PM UTC 25 |
| Peak memory | 217512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924573490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 26.usbdev_iso_retraction.1924573490 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_link_in_err.1860156261 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 241563461 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:10:37 PM UTC 25 |
| Finished | Feb 08 06:10:40 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1860156261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usb dev_link_in_err.1860156261 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_link_resume.3910571328 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 23554544530 ps |
| CPU time | 36.49 seconds |
| Started | Feb 08 06:10:38 PM UTC 25 |
| Finished | Feb 08 06:11:16 PM UTC 25 |
| Peak memory | 227664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3910571328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usb dev_link_resume.3910571328 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_link_suspend.2576068375 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 5991844909 ps |
| CPU time | 12.2 seconds |
| Started | Feb 08 06:10:40 PM UTC 25 |
| Finished | Feb 08 06:10:53 PM UTC 25 |
| Peak memory | 217416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2576068375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.us bdev_link_suspend.2576068375 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_low_speed_traffic.2928898794 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 3512709303 ps |
| CPU time | 31.47 seconds |
| Started | Feb 08 06:10:40 PM UTC 25 |
| Finished | Feb 08 06:11:13 PM UTC 25 |
| Peak memory | 230036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928898794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 26.usbdev_low_speed_traffic.2928898794 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_max_inter_pkt_delay.2010956479 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 2068153547 ps |
| CPU time | 63.44 seconds |
| Started | Feb 08 06:10:41 PM UTC 25 |
| Finished | Feb 08 06:11:46 PM UTC 25 |
| Peak memory | 234596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010956479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.2010956479 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_max_length_in_transaction.997897071 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 236977093 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:10:41 PM UTC 25 |
| Finished | Feb 08 06:10:44 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997897071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 26.usbdev_max_length_in_transaction.997897071 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_max_length_out_transaction.3967504216 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 199192324 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:10:41 PM UTC 25 |
| Finished | Feb 08 06:10:44 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3967504216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3967504216 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_min_inter_pkt_delay.3702133349 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 3068859946 ps |
| CPU time | 26.18 seconds |
| Started | Feb 08 06:10:41 PM UTC 25 |
| Finished | Feb 08 06:11:09 PM UTC 25 |
| Peak memory | 227736 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702133349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.3702133349 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_min_length_in_transaction.418198559 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 158135564 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 06:10:41 PM UTC 25 |
| Finished | Feb 08 06:10:44 PM UTC 25 |
| Peak memory | 215156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418198559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 26.usbdev_min_length_in_transaction.418198559 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_min_length_out_transaction.3722378451 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 143007561 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:10:43 PM UTC 25 |
| Finished | Feb 08 06:10:45 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3722378451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3722378451 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_nak_trans.3029001241 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 216224903 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:10:43 PM UTC 25 |
| Finished | Feb 08 06:10:45 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3029001241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbde v_nak_trans.3029001241 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_out_iso.2475307068 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 166064289 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:10:43 PM UTC 25 |
| Finished | Feb 08 06:10:45 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2475307068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_ out_iso.2475307068 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_out_stall.2117791706 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 170488753 ps |
| CPU time | 0.94 seconds |
| Started | Feb 08 06:10:44 PM UTC 25 |
| Finished | Feb 08 06:10:46 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2117791706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbde v_out_stall.2117791706 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_out_trans_nak.4274888737 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 186035907 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:10:45 PM UTC 25 |
| Finished | Feb 08 06:10:48 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4274888737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.u sbdev_out_trans_nak.4274888737 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_pending_in_trans.3147141912 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 187550256 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:10:45 PM UTC 25 |
| Finished | Feb 08 06:10:48 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3147141912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.usbdev_pending_in_trans.3147141912 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_phy_config_pinflip.1342484006 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 226023691 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:10:45 PM UTC 25 |
| Finished | Feb 08 06:10:48 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342484006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 26.usbdev_phy_config_pinflip.1342484006 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_phy_config_usb_ref_disable.2623713053 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 140163964 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 06:10:45 PM UTC 25 |
| Finished | Feb 08 06:10:48 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2623713053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2623713053 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_phy_pins_sense.3239535842 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 48895201 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:10:45 PM UTC 25 |
| Finished | Feb 08 06:10:48 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3239535842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26. usbdev_phy_pins_sense.3239535842 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_pkt_buffer.598306382 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 11132431472 ps |
| CPU time | 29.79 seconds |
| Started | Feb 08 06:10:47 PM UTC 25 |
| Finished | Feb 08 06:11:18 PM UTC 25 |
| Peak memory | 227804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=598306382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbde v_pkt_buffer.598306382 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_pkt_received.1112374852 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 166649773 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:10:47 PM UTC 25 |
| Finished | Feb 08 06:10:50 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1112374852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.us bdev_pkt_received.1112374852 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_pkt_sent.4022375094 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 236005455 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:10:47 PM UTC 25 |
| Finished | Feb 08 06:10:50 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4022375094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev _pkt_sent.4022375094 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_random_length_in_transaction.3768203816 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 298379976 ps |
| CPU time | 1.76 seconds |
| Started | Feb 08 06:10:47 PM UTC 25 |
| Finished | Feb 08 06:10:50 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3768203816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.u sbdev_random_length_in_transaction.3768203816 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_random_length_out_transaction.605174399 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 170656018 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:10:47 PM UTC 25 |
| Finished | Feb 08 06:10:50 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=605174399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 26.usbdev_random_length_out_transaction.605174399 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_rx_crc_err.3086389409 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 179726406 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:10:48 PM UTC 25 |
| Finished | Feb 08 06:10:51 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3086389409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbd ev_rx_crc_err.3086389409 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_rx_full.3656365542 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 277537265 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:10:48 PM UTC 25 |
| Finished | Feb 08 06:10:51 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3656365542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_ rx_full.3656365542 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_setup_stage.4294963144 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 193465358 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:10:50 PM UTC 25 |
| Finished | Feb 08 06:10:52 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4294963144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usb dev_setup_stage.4294963144 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_setup_trans_ignored.2990599110 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 151412980 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 06:10:50 PM UTC 25 |
| Finished | Feb 08 06:10:52 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2990599110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 26.usbdev_setup_trans_ignored.2990599110 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_smoke.1732622804 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 232140729 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:10:50 PM UTC 25 |
| Finished | Feb 08 06:10:52 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1732622804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_sm oke.1732622804 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_spurious_pids_ignored.1611782463 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 2245557151 ps |
| CPU time | 23.88 seconds |
| Started | Feb 08 06:10:50 PM UTC 25 |
| Finished | Feb 08 06:11:15 PM UTC 25 |
| Peak memory | 234468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611782463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 26.usbdev_spurious_pids_ignored.1611782463 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_stall_priority_over_nak.3307965400 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 188946460 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:10:50 PM UTC 25 |
| Finished | Feb 08 06:10:52 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3307965400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 26.usbdev_stall_priority_over_nak.3307965400 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_stall_trans.853242606 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 177249638 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:10:52 PM UTC 25 |
| Finished | Feb 08 06:10:54 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=853242606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbd ev_stall_trans.853242606 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_stream_len_max.186275060 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 848885502 ps |
| CPU time | 2.42 seconds |
| Started | Feb 08 06:10:52 PM UTC 25 |
| Finished | Feb 08 06:10:55 PM UTC 25 |
| Peak memory | 217348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=186275060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.u sbdev_stream_len_max.186275060 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_streaming_out.668166561 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 1518982788 ps |
| CPU time | 38.73 seconds |
| Started | Feb 08 06:10:52 PM UTC 25 |
| Finished | Feb 08 06:11:32 PM UTC 25 |
| Peak memory | 227792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=668166561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev _streaming_out.668166561 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_timeout_missing_host_handshake.2752954489 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 2229311143 ps |
| CPU time | 15 seconds |
| Started | Feb 08 06:10:33 PM UTC 25 |
| Finished | Feb 08 06:10:49 PM UTC 25 |
| Peak memory | 217464 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752954489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing_host_handshake.2752954489 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_tx_rx_disruption.205038906 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 528730167 ps |
| CPU time | 2.77 seconds |
| Started | Feb 08 06:10:52 PM UTC 25 |
| Finished | Feb 08 06:10:56 PM UTC 25 |
| Peak memory | 217316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 05038906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_tx_rx_disruption.205038906 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/26.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/260.usbdev_tx_rx_disruption.3400346897 |
| Short name | T3432 |
| Test name | |
| Test status | |
| Simulation time | 599217816 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:19:11 PM UTC 25 |
| Finished | Feb 08 06:19:42 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 400346897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260.usbdev_tx_rx_disruption.3400346897 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/260.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/261.usbdev_tx_rx_disruption.2732081949 |
| Short name | T3427 |
| Test name | |
| Test status | |
| Simulation time | 481252633 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:19:11 PM UTC 25 |
| Finished | Feb 08 06:19:41 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 732081949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261.usbdev_tx_rx_disruption.2732081949 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/261.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/262.usbdev_tx_rx_disruption.561136173 |
| Short name | T3430 |
| Test name | |
| Test status | |
| Simulation time | 587869436 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:19:11 PM UTC 25 |
| Finished | Feb 08 06:19:41 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 61136173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.usbdev_tx_rx_disruption.561136173 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/262.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/263.usbdev_tx_rx_disruption.2238891400 |
| Short name | T3433 |
| Test name | |
| Test status | |
| Simulation time | 640809510 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:19:11 PM UTC 25 |
| Finished | Feb 08 06:19:42 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 238891400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.usbdev_tx_rx_disruption.2238891400 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/263.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/264.usbdev_tx_rx_disruption.4188129172 |
| Short name | T3444 |
| Test name | |
| Test status | |
| Simulation time | 473210931 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:19:12 PM UTC 25 |
| Finished | Feb 08 06:19:44 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 188129172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 264.usbdev_tx_rx_disruption.4188129172 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/264.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/265.usbdev_tx_rx_disruption.1902099398 |
| Short name | T3448 |
| Test name | |
| Test status | |
| Simulation time | 484010068 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:19:12 PM UTC 25 |
| Finished | Feb 08 06:19:45 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 902099398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 265.usbdev_tx_rx_disruption.1902099398 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/265.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/266.usbdev_tx_rx_disruption.2176457940 |
| Short name | T3468 |
| Test name | |
| Test status | |
| Simulation time | 526059195 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:19:12 PM UTC 25 |
| Finished | Feb 08 06:19:55 PM UTC 25 |
| Peak memory | 216704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 176457940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266.usbdev_tx_rx_disruption.2176457940 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/266.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/267.usbdev_tx_rx_disruption.1699099188 |
| Short name | T3447 |
| Test name | |
| Test status | |
| Simulation time | 496507571 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:19:12 PM UTC 25 |
| Finished | Feb 08 06:19:44 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 699099188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267.usbdev_tx_rx_disruption.1699099188 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/267.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/268.usbdev_tx_rx_disruption.3218172082 |
| Short name | T3446 |
| Test name | |
| Test status | |
| Simulation time | 523245522 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:19:12 PM UTC 25 |
| Finished | Feb 08 06:19:44 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 218172082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.usbdev_tx_rx_disruption.3218172082 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/268.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/269.usbdev_tx_rx_disruption.2158679520 |
| Short name | T3443 |
| Test name | |
| Test status | |
| Simulation time | 488829359 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:19:12 PM UTC 25 |
| Finished | Feb 08 06:19:44 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 158679520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269.usbdev_tx_rx_disruption.2158679520 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/269.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_alert_test.4182205576 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 50244403 ps |
| CPU time | 0.92 seconds |
| Started | Feb 08 06:11:10 PM UTC 25 |
| Finished | Feb 08 06:11:12 PM UTC 25 |
| Peak memory | 214932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182205576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 27.usbdev_alert_test.4182205576 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_aon_wake_disconnect.749682510 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 4622168381 ps |
| CPU time | 9.23 seconds |
| Started | Feb 08 06:10:52 PM UTC 25 |
| Finished | Feb 08 06:11:02 PM UTC 25 |
| Peak memory | 227588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749682510 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.749682510 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_aon_wake_reset.4245670492 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 19688040397 ps |
| CPU time | 24.09 seconds |
| Started | Feb 08 06:10:52 PM UTC 25 |
| Finished | Feb 08 06:11:17 PM UTC 25 |
| Peak memory | 217384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245670492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.4245670492 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_aon_wake_resume.879606565 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 28774491501 ps |
| CPU time | 49.8 seconds |
| Started | Feb 08 06:10:52 PM UTC 25 |
| Finished | Feb 08 06:11:43 PM UTC 25 |
| Peak memory | 217440 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879606565 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.879606565 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_av_buffer.3637074281 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 212524930 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:10:52 PM UTC 25 |
| Finished | Feb 08 06:10:55 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3637074281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbde v_av_buffer.3637074281 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_bitstuff_err.1544770533 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 224387615 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:10:53 PM UTC 25 |
| Finished | Feb 08 06:10:56 PM UTC 25 |
| Peak memory | 215128 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1544770533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.us bdev_bitstuff_err.1544770533 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_data_toggle_clear.1202514767 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 274665655 ps |
| CPU time | 1.67 seconds |
| Started | Feb 08 06:10:53 PM UTC 25 |
| Finished | Feb 08 06:10:56 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1202514767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.1202514767 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_data_toggle_restore.2185663617 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 578434094 ps |
| CPU time | 3.06 seconds |
| Started | Feb 08 06:10:53 PM UTC 25 |
| Finished | Feb 08 06:10:58 PM UTC 25 |
| Peak memory | 217300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185663617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.2185663617 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_device_address.911494009 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 33366715154 ps |
| CPU time | 81.53 seconds |
| Started | Feb 08 06:10:53 PM UTC 25 |
| Finished | Feb 08 06:12:17 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=911494009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.u sbdev_device_address.911494009 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_device_timeout.2822061644 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 427595288 ps |
| CPU time | 8.05 seconds |
| Started | Feb 08 06:10:53 PM UTC 25 |
| Finished | Feb 08 06:11:03 PM UTC 25 |
| Peak memory | 217504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822061644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.2822061644 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_disable_endpoint.2194413407 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 771291613 ps |
| CPU time | 3.21 seconds |
| Started | Feb 08 06:10:55 PM UTC 25 |
| Finished | Feb 08 06:11:00 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2194413407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.usbdev_disable_endpoint.2194413407 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_disconnected.1274785931 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 152516909 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 06:10:55 PM UTC 25 |
| Finished | Feb 08 06:10:57 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1274785931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.us bdev_disconnected.1274785931 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_enable.124692750 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 83196588 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 06:10:55 PM UTC 25 |
| Finished | Feb 08 06:10:58 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=124692750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_en able.124692750 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_endpoint_access.479412262 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 1159991634 ps |
| CPU time | 4.91 seconds |
| Started | Feb 08 06:10:55 PM UTC 25 |
| Finished | Feb 08 06:11:01 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=479412262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27. usbdev_endpoint_access.479412262 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_endpoint_types.3438014613 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 145017666 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 06:10:55 PM UTC 25 |
| Finished | Feb 08 06:10:58 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438014613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 27.usbdev_endpoint_types.3438014613 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_fifo_rst.1955623076 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 182849593 ps |
| CPU time | 3.11 seconds |
| Started | Feb 08 06:10:57 PM UTC 25 |
| Finished | Feb 08 06:11:01 PM UTC 25 |
| Peak memory | 217288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1955623076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev _fifo_rst.1955623076 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_in_iso.4157114600 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 238424561 ps |
| CPU time | 1.71 seconds |
| Started | Feb 08 06:10:57 PM UTC 25 |
| Finished | Feb 08 06:11:00 PM UTC 25 |
| Peak memory | 227756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157114600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 27.usbdev_in_iso.4157114600 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_in_stall.3756407438 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 140931749 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:10:57 PM UTC 25 |
| Finished | Feb 08 06:10:59 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3756407438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev _in_stall.3756407438 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_in_trans.3063144158 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 208084104 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:10:57 PM UTC 25 |
| Finished | Feb 08 06:10:59 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3063144158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev _in_trans.3063144158 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_invalid_sync.2548327322 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 3163533563 ps |
| CPU time | 24.39 seconds |
| Started | Feb 08 06:10:57 PM UTC 25 |
| Finished | Feb 08 06:11:23 PM UTC 25 |
| Peak memory | 229700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548327322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.2548327322 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_iso_retraction.4168001771 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 13857257511 ps |
| CPU time | 90.38 seconds |
| Started | Feb 08 06:10:58 PM UTC 25 |
| Finished | Feb 08 06:12:31 PM UTC 25 |
| Peak memory | 217348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168001771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 27.usbdev_iso_retraction.4168001771 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_link_in_err.4060551656 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 166530114 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 06:10:58 PM UTC 25 |
| Finished | Feb 08 06:11:00 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4060551656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usb dev_link_in_err.4060551656 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_link_resume.1148877485 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 32689658679 ps |
| CPU time | 55.97 seconds |
| Started | Feb 08 06:10:58 PM UTC 25 |
| Finished | Feb 08 06:11:56 PM UTC 25 |
| Peak memory | 217456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1148877485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usb dev_link_resume.1148877485 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_link_suspend.4212838273 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 5165972057 ps |
| CPU time | 15.57 seconds |
| Started | Feb 08 06:10:58 PM UTC 25 |
| Finished | Feb 08 06:11:15 PM UTC 25 |
| Peak memory | 227592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4212838273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.us bdev_link_suspend.4212838273 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_low_speed_traffic.99449084 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 3948323904 ps |
| CPU time | 47.95 seconds |
| Started | Feb 08 06:10:58 PM UTC 25 |
| Finished | Feb 08 06:11:48 PM UTC 25 |
| Peak memory | 229772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99449084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_ traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 27.usbdev_low_speed_traffic.99449084 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_max_inter_pkt_delay.3846020610 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 2496628455 ps |
| CPU time | 71.94 seconds |
| Started | Feb 08 06:10:59 PM UTC 25 |
| Finished | Feb 08 06:12:13 PM UTC 25 |
| Peak memory | 229824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846020610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.3846020610 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_max_length_in_transaction.773862343 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 257746463 ps |
| CPU time | 1.72 seconds |
| Started | Feb 08 06:11:01 PM UTC 25 |
| Finished | Feb 08 06:11:04 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773862343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 27.usbdev_max_length_in_transaction.773862343 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_max_length_out_transaction.709747124 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 252163763 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:11:01 PM UTC 25 |
| Finished | Feb 08 06:11:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=709747124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 27.usbdev_max_length_out_transaction.709747124 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_min_inter_pkt_delay.2800906468 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 4185085889 ps |
| CPU time | 37.78 seconds |
| Started | Feb 08 06:11:01 PM UTC 25 |
| Finished | Feb 08 06:11:40 PM UTC 25 |
| Peak memory | 217496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800906468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.2800906468 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_min_length_in_transaction.2573267725 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 174216527 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:11:01 PM UTC 25 |
| Finished | Feb 08 06:11:03 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573267725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 27.usbdev_min_length_in_transaction.2573267725 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_min_length_out_transaction.1363568811 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 163046247 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 06:11:01 PM UTC 25 |
| Finished | Feb 08 06:11:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1363568811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1363568811 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_nak_trans.3175920877 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 228172678 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:11:01 PM UTC 25 |
| Finished | Feb 08 06:11:04 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3175920877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbde v_nak_trans.3175920877 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_out_iso.2448049160 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 192421897 ps |
| CPU time | 1.12 seconds |
| Started | Feb 08 06:11:02 PM UTC 25 |
| Finished | Feb 08 06:11:04 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2448049160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_ out_iso.2448049160 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_out_stall.3133527034 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 155838260 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:11:02 PM UTC 25 |
| Finished | Feb 08 06:11:05 PM UTC 25 |
| Peak memory | 215016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3133527034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbde v_out_stall.3133527034 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_out_trans_nak.1713392448 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 183187757 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 06:11:02 PM UTC 25 |
| Finished | Feb 08 06:11:05 PM UTC 25 |
| Peak memory | 215044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1713392448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.u sbdev_out_trans_nak.1713392448 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_pending_in_trans.2123954184 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 154979340 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 06:11:04 PM UTC 25 |
| Finished | Feb 08 06:11:06 PM UTC 25 |
| Peak memory | 215088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2123954184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.usbdev_pending_in_trans.2123954184 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_phy_config_pinflip.1628268816 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 307904558 ps |
| CPU time | 2.1 seconds |
| Started | Feb 08 06:11:04 PM UTC 25 |
| Finished | Feb 08 06:11:07 PM UTC 25 |
| Peak memory | 217156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628268816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 27.usbdev_phy_config_pinflip.1628268816 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_phy_config_usb_ref_disable.3792764376 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 156585245 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:11:04 PM UTC 25 |
| Finished | Feb 08 06:11:06 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3792764376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.3792764376 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_phy_pins_sense.137335827 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 57265671 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:11:05 PM UTC 25 |
| Finished | Feb 08 06:11:07 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=137335827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.u sbdev_phy_pins_sense.137335827 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_pkt_buffer.2500278351 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 20156419613 ps |
| CPU time | 56.41 seconds |
| Started | Feb 08 06:11:05 PM UTC 25 |
| Finished | Feb 08 06:12:03 PM UTC 25 |
| Peak memory | 227692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2500278351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbd ev_pkt_buffer.2500278351 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_pkt_received.3825229107 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 167404377 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:11:05 PM UTC 25 |
| Finished | Feb 08 06:11:08 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3825229107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.us bdev_pkt_received.3825229107 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_pkt_sent.3101008738 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 168596034 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:11:05 PM UTC 25 |
| Finished | Feb 08 06:11:08 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3101008738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev _pkt_sent.3101008738 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_random_length_in_transaction.434935382 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 218411949 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:11:05 PM UTC 25 |
| Finished | Feb 08 06:11:08 PM UTC 25 |
| Peak memory | 214968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=434935382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.us bdev_random_length_in_transaction.434935382 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_random_length_out_transaction.4071622421 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 179629212 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:11:05 PM UTC 25 |
| Finished | Feb 08 06:11:07 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4071622421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 27.usbdev_random_length_out_transaction.4071622421 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_rx_crc_err.3863903743 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 174463283 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:11:07 PM UTC 25 |
| Finished | Feb 08 06:11:09 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3863903743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbd ev_rx_crc_err.3863903743 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_setup_stage.1495711875 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 202574107 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:11:07 PM UTC 25 |
| Finished | Feb 08 06:11:09 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1495711875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usb dev_setup_stage.1495711875 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_setup_trans_ignored.2710415469 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 188435022 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:11:07 PM UTC 25 |
| Finished | Feb 08 06:11:09 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2710415469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 27.usbdev_setup_trans_ignored.2710415469 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_smoke.204470798 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 182548093 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:11:08 PM UTC 25 |
| Finished | Feb 08 06:11:11 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=204470798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smo ke.204470798 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_spurious_pids_ignored.1358606457 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 2030708283 ps |
| CPU time | 22.4 seconds |
| Started | Feb 08 06:11:08 PM UTC 25 |
| Finished | Feb 08 06:11:32 PM UTC 25 |
| Peak memory | 229604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358606457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 27.usbdev_spurious_pids_ignored.1358606457 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_stall_priority_over_nak.1766962139 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 210770484 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:11:08 PM UTC 25 |
| Finished | Feb 08 06:11:11 PM UTC 25 |
| Peak memory | 215060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1766962139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 27.usbdev_stall_priority_over_nak.1766962139 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_stall_trans.2811233337 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 183623517 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 06:11:08 PM UTC 25 |
| Finished | Feb 08 06:11:11 PM UTC 25 |
| Peak memory | 215084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2811233337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usb dev_stall_trans.2811233337 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_stream_len_max.2409764365 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 1219567531 ps |
| CPU time | 3.3 seconds |
| Started | Feb 08 06:11:10 PM UTC 25 |
| Finished | Feb 08 06:11:14 PM UTC 25 |
| Peak memory | 217360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2409764365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27. usbdev_stream_len_max.2409764365 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_streaming_out.3127689445 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 2045066434 ps |
| CPU time | 22.61 seconds |
| Started | Feb 08 06:11:08 PM UTC 25 |
| Finished | Feb 08 06:11:32 PM UTC 25 |
| Peak memory | 227788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3127689445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbde v_streaming_out.3127689445 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_timeout_missing_host_handshake.803724766 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 1780274585 ps |
| CPU time | 44.06 seconds |
| Started | Feb 08 06:10:55 PM UTC 25 |
| Finished | Feb 08 06:11:41 PM UTC 25 |
| Peak memory | 217348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803724766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_host_handshake.803724766 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_tx_rx_disruption.2603180576 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 509025027 ps |
| CPU time | 2.77 seconds |
| Started | Feb 08 06:11:10 PM UTC 25 |
| Finished | Feb 08 06:11:13 PM UTC 25 |
| Peak memory | 217180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 603180576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_tx_rx_disruption.2603180576 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/27.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/270.usbdev_tx_rx_disruption.1441909542 |
| Short name | T3452 |
| Test name | |
| Test status | |
| Simulation time | 581719030 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:19:12 PM UTC 25 |
| Finished | Feb 08 06:19:48 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 441909542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.usbdev_tx_rx_disruption.1441909542 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/270.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/271.usbdev_tx_rx_disruption.787165476 |
| Short name | T3467 |
| Test name | |
| Test status | |
| Simulation time | 483621649 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 06:19:12 PM UTC 25 |
| Finished | Feb 08 06:19:55 PM UTC 25 |
| Peak memory | 215176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 87165476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271.usbdev_tx_rx_disruption.787165476 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/271.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/272.usbdev_tx_rx_disruption.569286503 |
| Short name | T3451 |
| Test name | |
| Test status | |
| Simulation time | 503840246 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:19:12 PM UTC 25 |
| Finished | Feb 08 06:19:48 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 69286503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272.usbdev_tx_rx_disruption.569286503 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/272.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/273.usbdev_tx_rx_disruption.494780978 |
| Short name | T3426 |
| Test name | |
| Test status | |
| Simulation time | 451800866 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:19:12 PM UTC 25 |
| Finished | Feb 08 06:19:41 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 94780978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273.usbdev_tx_rx_disruption.494780978 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/273.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/274.usbdev_tx_rx_disruption.3417197248 |
| Short name | T3378 |
| Test name | |
| Test status | |
| Simulation time | 575409283 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:19:14 PM UTC 25 |
| Finished | Feb 08 06:19:23 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 417197248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 274.usbdev_tx_rx_disruption.3417197248 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/274.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/275.usbdev_tx_rx_disruption.2464421460 |
| Short name | T3377 |
| Test name | |
| Test status | |
| Simulation time | 464068240 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:19:14 PM UTC 25 |
| Finished | Feb 08 06:19:23 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 464421460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275.usbdev_tx_rx_disruption.2464421460 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/275.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/276.usbdev_tx_rx_disruption.3122927568 |
| Short name | T3379 |
| Test name | |
| Test status | |
| Simulation time | 589285539 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:19:14 PM UTC 25 |
| Finished | Feb 08 06:19:23 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 122927568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276.usbdev_tx_rx_disruption.3122927568 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/276.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/277.usbdev_tx_rx_disruption.652267392 |
| Short name | T3367 |
| Test name | |
| Test status | |
| Simulation time | 502372860 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:19:15 PM UTC 25 |
| Finished | Feb 08 06:19:19 PM UTC 25 |
| Peak memory | 214756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6 52267392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 277.usbdev_tx_rx_disruption.652267392 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/277.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/278.usbdev_tx_rx_disruption.380718895 |
| Short name | T3366 |
| Test name | |
| Test status | |
| Simulation time | 500927179 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:19:15 PM UTC 25 |
| Finished | Feb 08 06:19:19 PM UTC 25 |
| Peak memory | 214852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 80718895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 278.usbdev_tx_rx_disruption.380718895 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/278.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/279.usbdev_tx_rx_disruption.4147180679 |
| Short name | T3368 |
| Test name | |
| Test status | |
| Simulation time | 584771257 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:19:15 PM UTC 25 |
| Finished | Feb 08 06:19:19 PM UTC 25 |
| Peak memory | 215052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 147180679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.usbdev_tx_rx_disruption.4147180679 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/279.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_alert_test.4236756846 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 67106657 ps |
| CPU time | 0.89 seconds |
| Started | Feb 08 06:11:27 PM UTC 25 |
| Finished | Feb 08 06:11:29 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236756846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 28.usbdev_alert_test.4236756846 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_aon_wake_disconnect.2014638528 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 5964157246 ps |
| CPU time | 10.21 seconds |
| Started | Feb 08 06:11:10 PM UTC 25 |
| Finished | Feb 08 06:11:21 PM UTC 25 |
| Peak memory | 227652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014638528 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.2014638528 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_aon_wake_reset.3210257285 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 15183135096 ps |
| CPU time | 20.41 seconds |
| Started | Feb 08 06:11:10 PM UTC 25 |
| Finished | Feb 08 06:11:31 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210257285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.3210257285 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_aon_wake_resume.2205061588 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 30416234929 ps |
| CPU time | 46.06 seconds |
| Started | Feb 08 06:11:11 PM UTC 25 |
| Finished | Feb 08 06:11:58 PM UTC 25 |
| Peak memory | 217424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205061588 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.2205061588 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_av_buffer.2505227784 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 182925844 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:11:11 PM UTC 25 |
| Finished | Feb 08 06:11:14 PM UTC 25 |
| Peak memory | 215056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2505227784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbde v_av_buffer.2505227784 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_bitstuff_err.1577557301 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 147920502 ps |
| CPU time | 0.96 seconds |
| Started | Feb 08 06:11:12 PM UTC 25 |
| Finished | Feb 08 06:11:14 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1577557301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.us bdev_bitstuff_err.1577557301 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_data_toggle_clear.1262927403 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 229466900 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:11:12 PM UTC 25 |
| Finished | Feb 08 06:11:15 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1262927403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.1262927403 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_data_toggle_restore.1199620369 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 291598037 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:11:12 PM UTC 25 |
| Finished | Feb 08 06:11:15 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199620369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.1199620369 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_device_address.2183180111 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 19910921914 ps |
| CPU time | 34.35 seconds |
| Started | Feb 08 06:11:12 PM UTC 25 |
| Finished | Feb 08 06:11:48 PM UTC 25 |
| Peak memory | 217424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2183180111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28. usbdev_device_address.2183180111 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_device_timeout.139507047 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 5501942769 ps |
| CPU time | 40.73 seconds |
| Started | Feb 08 06:11:15 PM UTC 25 |
| Finished | Feb 08 06:11:57 PM UTC 25 |
| Peak memory | 217364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139507047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.139507047 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_disable_endpoint.1836687063 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 633095968 ps |
| CPU time | 2.04 seconds |
| Started | Feb 08 06:11:15 PM UTC 25 |
| Finished | Feb 08 06:11:18 PM UTC 25 |
| Peak memory | 217324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1836687063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.usbdev_disable_endpoint.1836687063 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_disconnected.3756184929 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 138027117 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:11:15 PM UTC 25 |
| Finished | Feb 08 06:11:17 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3756184929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.us bdev_disconnected.3756184929 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_enable.4081933187 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 57315201 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 06:11:15 PM UTC 25 |
| Finished | Feb 08 06:11:17 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4081933187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_e nable.4081933187 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_endpoint_access.433363677 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 752799140 ps |
| CPU time | 3.21 seconds |
| Started | Feb 08 06:11:15 PM UTC 25 |
| Finished | Feb 08 06:11:19 PM UTC 25 |
| Peak memory | 217376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=433363677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28. usbdev_endpoint_access.433363677 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_fifo_rst.3095355857 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 259956739 ps |
| CPU time | 2.17 seconds |
| Started | Feb 08 06:11:17 PM UTC 25 |
| Finished | Feb 08 06:11:20 PM UTC 25 |
| Peak memory | 217616 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3095355857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev _fifo_rst.3095355857 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_in_iso.2199122320 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 228486727 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:11:17 PM UTC 25 |
| Finished | Feb 08 06:11:19 PM UTC 25 |
| Peak memory | 227748 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199122320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 28.usbdev_in_iso.2199122320 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_in_stall.2313494304 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 232131532 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:11:17 PM UTC 25 |
| Finished | Feb 08 06:11:19 PM UTC 25 |
| Peak memory | 215060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2313494304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev _in_stall.2313494304 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_in_trans.3001732821 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 183523383 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:11:17 PM UTC 25 |
| Finished | Feb 08 06:11:19 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3001732821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev _in_trans.3001732821 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_invalid_sync.211787486 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 2582615227 ps |
| CPU time | 67.65 seconds |
| Started | Feb 08 06:11:17 PM UTC 25 |
| Finished | Feb 08 06:12:26 PM UTC 25 |
| Peak memory | 227724 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211787486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.211787486 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_iso_retraction.3625034717 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 8187696115 ps |
| CPU time | 60.2 seconds |
| Started | Feb 08 06:11:17 PM UTC 25 |
| Finished | Feb 08 06:12:19 PM UTC 25 |
| Peak memory | 217368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625034717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 28.usbdev_iso_retraction.3625034717 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_link_in_err.440880559 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 212973785 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:11:18 PM UTC 25 |
| Finished | Feb 08 06:11:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=440880559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbd ev_link_in_err.440880559 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_link_resume.2944957869 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 15230697449 ps |
| CPU time | 31.19 seconds |
| Started | Feb 08 06:11:18 PM UTC 25 |
| Finished | Feb 08 06:11:51 PM UTC 25 |
| Peak memory | 217584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2944957869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usb dev_link_resume.2944957869 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_link_suspend.3377115371 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 4319045290 ps |
| CPU time | 12.04 seconds |
| Started | Feb 08 06:11:18 PM UTC 25 |
| Finished | Feb 08 06:11:32 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3377115371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.us bdev_link_suspend.3377115371 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_low_speed_traffic.4118312837 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 3999033975 ps |
| CPU time | 39.88 seconds |
| Started | Feb 08 06:11:19 PM UTC 25 |
| Finished | Feb 08 06:12:00 PM UTC 25 |
| Peak memory | 234520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118312837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 28.usbdev_low_speed_traffic.4118312837 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_max_inter_pkt_delay.3116397982 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 2141995021 ps |
| CPU time | 23.41 seconds |
| Started | Feb 08 06:11:19 PM UTC 25 |
| Finished | Feb 08 06:11:43 PM UTC 25 |
| Peak memory | 227776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116397982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.3116397982 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_max_length_in_transaction.305319752 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 240231205 ps |
| CPU time | 1.8 seconds |
| Started | Feb 08 06:11:19 PM UTC 25 |
| Finished | Feb 08 06:11:22 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305319752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 28.usbdev_max_length_in_transaction.305319752 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_max_length_out_transaction.3994777466 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 186884699 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:11:19 PM UTC 25 |
| Finished | Feb 08 06:11:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3994777466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3994777466 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_min_inter_pkt_delay.551562443 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 2047848983 ps |
| CPU time | 22.59 seconds |
| Started | Feb 08 06:11:20 PM UTC 25 |
| Finished | Feb 08 06:11:44 PM UTC 25 |
| Peak memory | 234484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551562443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usb dev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.551562443 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_min_length_in_transaction.2716658242 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 163781242 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:11:21 PM UTC 25 |
| Finished | Feb 08 06:11:23 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716658242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 28.usbdev_min_length_in_transaction.2716658242 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_min_length_out_transaction.1632435003 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 160529706 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:11:21 PM UTC 25 |
| Finished | Feb 08 06:11:23 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1632435003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1632435003 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_nak_trans.973842465 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 180333068 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:11:21 PM UTC 25 |
| Finished | Feb 08 06:11:23 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=973842465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev _nak_trans.973842465 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_out_iso.199746150 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 185247414 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:11:21 PM UTC 25 |
| Finished | Feb 08 06:11:23 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=199746150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_o ut_iso.199746150 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_out_stall.2023915491 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 204558262 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:11:21 PM UTC 25 |
| Finished | Feb 08 06:11:23 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2023915491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbde v_out_stall.2023915491 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_out_trans_nak.2574394061 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 156101594 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:11:21 PM UTC 25 |
| Finished | Feb 08 06:11:23 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2574394061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.u sbdev_out_trans_nak.2574394061 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_pending_in_trans.1870352700 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 210460407 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:11:21 PM UTC 25 |
| Finished | Feb 08 06:11:24 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1870352700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.usbdev_pending_in_trans.1870352700 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_phy_config_pinflip.1489333361 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 198861626 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:11:22 PM UTC 25 |
| Finished | Feb 08 06:11:25 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489333361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 28.usbdev_phy_config_pinflip.1489333361 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_phy_config_usb_ref_disable.3892865319 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 135906334 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:11:22 PM UTC 25 |
| Finished | Feb 08 06:11:25 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3892865319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3892865319 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_phy_pins_sense.2639489134 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 37340100 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 06:11:22 PM UTC 25 |
| Finished | Feb 08 06:11:24 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2639489134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28. usbdev_phy_pins_sense.2639489134 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_pkt_buffer.117122724 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 20340270428 ps |
| CPU time | 54.56 seconds |
| Started | Feb 08 06:11:22 PM UTC 25 |
| Finished | Feb 08 06:12:18 PM UTC 25 |
| Peak memory | 227744 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=117122724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbde v_pkt_buffer.117122724 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_pkt_received.2209785092 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 211197544 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:11:23 PM UTC 25 |
| Finished | Feb 08 06:11:26 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2209785092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.us bdev_pkt_received.2209785092 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_pkt_sent.2508769862 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 208581430 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:11:23 PM UTC 25 |
| Finished | Feb 08 06:11:26 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2508769862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev _pkt_sent.2508769862 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_random_length_in_transaction.2922505523 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 182242626 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:11:23 PM UTC 25 |
| Finished | Feb 08 06:11:26 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2922505523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.u sbdev_random_length_in_transaction.2922505523 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_random_length_out_transaction.2705328524 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 199799954 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:11:23 PM UTC 25 |
| Finished | Feb 08 06:11:26 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2705328524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 28.usbdev_random_length_out_transaction.2705328524 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_rx_crc_err.3473496023 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 160417757 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:11:25 PM UTC 25 |
| Finished | Feb 08 06:11:28 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3473496023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbd ev_rx_crc_err.3473496023 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_rx_full.833996924 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 311491506 ps |
| CPU time | 1.81 seconds |
| Started | Feb 08 06:11:25 PM UTC 25 |
| Finished | Feb 08 06:11:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=833996924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_r x_full.833996924 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_setup_stage.1435444756 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 145002372 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:11:25 PM UTC 25 |
| Finished | Feb 08 06:11:28 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1435444756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usb dev_setup_stage.1435444756 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_setup_trans_ignored.2094191775 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 168758463 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:11:25 PM UTC 25 |
| Finished | Feb 08 06:11:27 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2094191775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.usbdev_setup_trans_ignored.2094191775 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_smoke.2528772504 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 233947042 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:11:25 PM UTC 25 |
| Finished | Feb 08 06:11:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2528772504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_sm oke.2528772504 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_spurious_pids_ignored.2249649385 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 2154889176 ps |
| CPU time | 68.02 seconds |
| Started | Feb 08 06:11:25 PM UTC 25 |
| Finished | Feb 08 06:12:35 PM UTC 25 |
| Peak memory | 229980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249649385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 28.usbdev_spurious_pids_ignored.2249649385 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_stall_priority_over_nak.213161653 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 235850302 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:11:25 PM UTC 25 |
| Finished | Feb 08 06:11:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=213161653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 28.usbdev_stall_priority_over_nak.213161653 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_stall_trans.1898862769 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 152692357 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:11:27 PM UTC 25 |
| Finished | Feb 08 06:11:29 PM UTC 25 |
| Peak memory | 214896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1898862769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usb dev_stall_trans.1898862769 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_stream_len_max.3780976392 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 1397290266 ps |
| CPU time | 6.67 seconds |
| Started | Feb 08 06:11:27 PM UTC 25 |
| Finished | Feb 08 06:11:35 PM UTC 25 |
| Peak memory | 217496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3780976392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28. usbdev_stream_len_max.3780976392 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_streaming_out.829684209 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 1687740440 ps |
| CPU time | 44.01 seconds |
| Started | Feb 08 06:11:27 PM UTC 25 |
| Finished | Feb 08 06:12:12 PM UTC 25 |
| Peak memory | 227416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=829684209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev _streaming_out.829684209 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_timeout_missing_host_handshake.1178975398 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 985567101 ps |
| CPU time | 21.9 seconds |
| Started | Feb 08 06:11:15 PM UTC 25 |
| Finished | Feb 08 06:11:38 PM UTC 25 |
| Peak memory | 217156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178975398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing_host_handshake.1178975398 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_tx_rx_disruption.1938252668 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 474541532 ps |
| CPU time | 1.91 seconds |
| Started | Feb 08 06:11:27 PM UTC 25 |
| Finished | Feb 08 06:11:30 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 938252668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_tx_rx_disruption.1938252668 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/28.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/280.usbdev_tx_rx_disruption.3193775897 |
| Short name | T3369 |
| Test name | |
| Test status | |
| Simulation time | 618652716 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:19:15 PM UTC 25 |
| Finished | Feb 08 06:19:19 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 193775897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280.usbdev_tx_rx_disruption.3193775897 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/280.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/281.usbdev_tx_rx_disruption.559102876 |
| Short name | T3431 |
| Test name | |
| Test status | |
| Simulation time | 638684760 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:19:18 PM UTC 25 |
| Finished | Feb 08 06:19:41 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 59102876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 281.usbdev_tx_rx_disruption.559102876 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/281.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/282.usbdev_tx_rx_disruption.945489339 |
| Short name | T3381 |
| Test name | |
| Test status | |
| Simulation time | 547905681 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:19:21 PM UTC 25 |
| Finished | Feb 08 06:19:23 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 45489339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 282.usbdev_tx_rx_disruption.945489339 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/282.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/283.usbdev_tx_rx_disruption.537613492 |
| Short name | T3383 |
| Test name | |
| Test status | |
| Simulation time | 628956244 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:19:21 PM UTC 25 |
| Finished | Feb 08 06:19:24 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 37613492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283.usbdev_tx_rx_disruption.537613492 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/283.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/284.usbdev_tx_rx_disruption.24765362 |
| Short name | T3385 |
| Test name | |
| Test status | |
| Simulation time | 595336023 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:19:21 PM UTC 25 |
| Finished | Feb 08 06:19:24 PM UTC 25 |
| Peak memory | 215072 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 4765362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 284.usbdev_tx_rx_disruption.24765362 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/284.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/285.usbdev_tx_rx_disruption.2794432223 |
| Short name | T3387 |
| Test name | |
| Test status | |
| Simulation time | 570320593 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:19:21 PM UTC 25 |
| Finished | Feb 08 06:19:24 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 794432223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285.usbdev_tx_rx_disruption.2794432223 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/285.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/286.usbdev_tx_rx_disruption.1779184419 |
| Short name | T3389 |
| Test name | |
| Test status | |
| Simulation time | 677638783 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 06:19:21 PM UTC 25 |
| Finished | Feb 08 06:19:24 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 779184419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 286.usbdev_tx_rx_disruption.1779184419 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/286.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/287.usbdev_tx_rx_disruption.2594653030 |
| Short name | T3382 |
| Test name | |
| Test status | |
| Simulation time | 572567629 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:19:21 PM UTC 25 |
| Finished | Feb 08 06:19:24 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 594653030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287.usbdev_tx_rx_disruption.2594653030 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/287.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/288.usbdev_tx_rx_disruption.903716684 |
| Short name | T3384 |
| Test name | |
| Test status | |
| Simulation time | 524242999 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:19:21 PM UTC 25 |
| Finished | Feb 08 06:19:24 PM UTC 25 |
| Peak memory | 215140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 03716684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.usbdev_tx_rx_disruption.903716684 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/288.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/289.usbdev_tx_rx_disruption.2786717505 |
| Short name | T3390 |
| Test name | |
| Test status | |
| Simulation time | 605089311 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:19:21 PM UTC 25 |
| Finished | Feb 08 06:19:24 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 786717505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 289.usbdev_tx_rx_disruption.2786717505 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/289.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_alert_test.1246667648 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 37588294 ps |
| CPU time | 1.02 seconds |
| Started | Feb 08 06:11:49 PM UTC 25 |
| Finished | Feb 08 06:11:52 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246667648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 29.usbdev_alert_test.1246667648 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_aon_wake_disconnect.530852056 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 7068881534 ps |
| CPU time | 11.99 seconds |
| Started | Feb 08 06:11:28 PM UTC 25 |
| Finished | Feb 08 06:11:42 PM UTC 25 |
| Peak memory | 227588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530852056 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.530852056 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_aon_wake_reset.3280255364 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 13395150525 ps |
| CPU time | 20.03 seconds |
| Started | Feb 08 06:11:28 PM UTC 25 |
| Finished | Feb 08 06:11:50 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280255364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.3280255364 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_aon_wake_resume.3900231064 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 25659137524 ps |
| CPU time | 42.96 seconds |
| Started | Feb 08 06:11:28 PM UTC 25 |
| Finished | Feb 08 06:12:13 PM UTC 25 |
| Peak memory | 227592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900231064 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.3900231064 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_av_buffer.3430649776 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 153051535 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:11:28 PM UTC 25 |
| Finished | Feb 08 06:11:31 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3430649776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbde v_av_buffer.3430649776 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_bitstuff_err.4179991933 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 163790900 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:11:30 PM UTC 25 |
| Finished | Feb 08 06:11:32 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4179991933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.us bdev_bitstuff_err.4179991933 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_data_toggle_clear.1769648271 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 257536939 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:11:30 PM UTC 25 |
| Finished | Feb 08 06:11:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1769648271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.1769648271 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_data_toggle_restore.564249887 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 877834529 ps |
| CPU time | 3.07 seconds |
| Started | Feb 08 06:11:30 PM UTC 25 |
| Finished | Feb 08 06:11:34 PM UTC 25 |
| Peak memory | 217316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564249887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_t oggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.564249887 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_device_address.3073296519 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 46587873795 ps |
| CPU time | 74.78 seconds |
| Started | Feb 08 06:11:30 PM UTC 25 |
| Finished | Feb 08 06:12:46 PM UTC 25 |
| Peak memory | 217504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3073296519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29. usbdev_device_address.3073296519 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_device_timeout.548733582 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 1575879990 ps |
| CPU time | 14.24 seconds |
| Started | Feb 08 06:11:31 PM UTC 25 |
| Finished | Feb 08 06:11:46 PM UTC 25 |
| Peak memory | 217460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548733582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.548733582 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_disable_endpoint.4102768612 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 820663757 ps |
| CPU time | 2.42 seconds |
| Started | Feb 08 06:11:32 PM UTC 25 |
| Finished | Feb 08 06:11:36 PM UTC 25 |
| Peak memory | 217216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4102768612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.usbdev_disable_endpoint.4102768612 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_disconnected.2023525311 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 158647517 ps |
| CPU time | 0.98 seconds |
| Started | Feb 08 06:11:32 PM UTC 25 |
| Finished | Feb 08 06:11:34 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2023525311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.us bdev_disconnected.2023525311 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_enable.1367603159 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 48232215 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 06:11:34 PM UTC 25 |
| Finished | Feb 08 06:11:36 PM UTC 25 |
| Peak memory | 214968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1367603159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_e nable.1367603159 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_endpoint_access.932855413 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 1037517241 ps |
| CPU time | 3.72 seconds |
| Started | Feb 08 06:11:34 PM UTC 25 |
| Finished | Feb 08 06:11:39 PM UTC 25 |
| Peak memory | 217452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=932855413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29. usbdev_endpoint_access.932855413 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_endpoint_types.1360877988 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 244142065 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 06:11:34 PM UTC 25 |
| Finished | Feb 08 06:11:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360877988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 29.usbdev_endpoint_types.1360877988 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_fifo_rst.2658975984 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 177529267 ps |
| CPU time | 2.57 seconds |
| Started | Feb 08 06:11:34 PM UTC 25 |
| Finished | Feb 08 06:11:37 PM UTC 25 |
| Peak memory | 217288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2658975984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev _fifo_rst.2658975984 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_in_iso.1727096471 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 250402721 ps |
| CPU time | 2.14 seconds |
| Started | Feb 08 06:11:34 PM UTC 25 |
| Finished | Feb 08 06:11:37 PM UTC 25 |
| Peak memory | 227628 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727096471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 29.usbdev_in_iso.1727096471 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_in_stall.237729638 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 146718484 ps |
| CPU time | 1.05 seconds |
| Started | Feb 08 06:11:35 PM UTC 25 |
| Finished | Feb 08 06:11:38 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=237729638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_ in_stall.237729638 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_in_trans.1637964045 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 215018155 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:11:35 PM UTC 25 |
| Finished | Feb 08 06:11:38 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1637964045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev _in_trans.1637964045 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_invalid_sync.3604950486 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 3035545521 ps |
| CPU time | 82.33 seconds |
| Started | Feb 08 06:11:34 PM UTC 25 |
| Finished | Feb 08 06:12:58 PM UTC 25 |
| Peak memory | 229928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604950486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.3604950486 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_iso_retraction.959733524 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 11828352842 ps |
| CPU time | 145.22 seconds |
| Started | Feb 08 06:11:35 PM UTC 25 |
| Finished | Feb 08 06:14:03 PM UTC 25 |
| Peak memory | 219312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959733524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retra ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 29.usbdev_iso_retraction.959733524 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_link_in_err.501046502 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 192517648 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:11:37 PM UTC 25 |
| Finished | Feb 08 06:11:39 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=501046502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbd ev_link_in_err.501046502 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_link_resume.1841761721 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 27919459039 ps |
| CPU time | 64.67 seconds |
| Started | Feb 08 06:11:37 PM UTC 25 |
| Finished | Feb 08 06:12:43 PM UTC 25 |
| Peak memory | 227664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1841761721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usb dev_link_resume.1841761721 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_link_suspend.298507941 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 9490438394 ps |
| CPU time | 16.33 seconds |
| Started | Feb 08 06:11:37 PM UTC 25 |
| Finished | Feb 08 06:11:54 PM UTC 25 |
| Peak memory | 217584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=298507941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usb dev_link_suspend.298507941 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_max_inter_pkt_delay.2398538708 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 2366094834 ps |
| CPU time | 66.64 seconds |
| Started | Feb 08 06:11:38 PM UTC 25 |
| Finished | Feb 08 06:12:47 PM UTC 25 |
| Peak memory | 229704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398538708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.2398538708 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_max_length_in_transaction.2950622811 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 253368819 ps |
| CPU time | 1.83 seconds |
| Started | Feb 08 06:11:38 PM UTC 25 |
| Finished | Feb 08 06:11:41 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950622811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 29.usbdev_max_length_in_transaction.2950622811 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_max_length_out_transaction.1129169622 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 226582478 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:11:38 PM UTC 25 |
| Finished | Feb 08 06:11:41 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1129169622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1129169622 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_min_inter_pkt_delay.1399585594 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 3653288292 ps |
| CPU time | 36.9 seconds |
| Started | Feb 08 06:11:39 PM UTC 25 |
| Finished | Feb 08 06:12:18 PM UTC 25 |
| Peak memory | 227556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399585594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.1399585594 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_min_length_in_transaction.2269258200 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 174661617 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:11:39 PM UTC 25 |
| Finished | Feb 08 06:11:42 PM UTC 25 |
| Peak memory | 214704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269258200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 29.usbdev_min_length_in_transaction.2269258200 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_min_length_out_transaction.2455705750 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 139348697 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 06:11:39 PM UTC 25 |
| Finished | Feb 08 06:11:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2455705750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2455705750 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_nak_trans.2938316562 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 227294082 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:11:41 PM UTC 25 |
| Finished | Feb 08 06:11:44 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2938316562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbde v_nak_trans.2938316562 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_out_iso.4189688026 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 155803157 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:11:41 PM UTC 25 |
| Finished | Feb 08 06:11:43 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4189688026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_ out_iso.4189688026 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_out_stall.1803230610 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 149922089 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 06:11:41 PM UTC 25 |
| Finished | Feb 08 06:11:43 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1803230610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbde v_out_stall.1803230610 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_out_trans_nak.837213388 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 167903796 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:11:43 PM UTC 25 |
| Finished | Feb 08 06:11:46 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=837213388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.us bdev_out_trans_nak.837213388 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_pending_in_trans.4124033334 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 158106273 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:11:43 PM UTC 25 |
| Finished | Feb 08 06:11:46 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4124033334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.usbdev_pending_in_trans.4124033334 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_phy_config_pinflip.3031877814 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 233551899 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 06:11:43 PM UTC 25 |
| Finished | Feb 08 06:11:46 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031877814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 29.usbdev_phy_config_pinflip.3031877814 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_phy_config_usb_ref_disable.72978878 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 162205322 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:11:43 PM UTC 25 |
| Finished | Feb 08 06:11:46 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=72978878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 29.usbdev_phy_config_usb_ref_disable.72978878 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_phy_pins_sense.414215533 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 50407875 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:11:43 PM UTC 25 |
| Finished | Feb 08 06:11:46 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=414215533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.u sbdev_phy_pins_sense.414215533 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_pkt_buffer.3858269742 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 9561628059 ps |
| CPU time | 25.12 seconds |
| Started | Feb 08 06:11:43 PM UTC 25 |
| Finished | Feb 08 06:12:10 PM UTC 25 |
| Peak memory | 227620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3858269742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbd ev_pkt_buffer.3858269742 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_pkt_received.1402772992 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 171159289 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:11:43 PM UTC 25 |
| Finished | Feb 08 06:11:46 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1402772992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.us bdev_pkt_received.1402772992 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_pkt_sent.3045520722 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 170724192 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:11:44 PM UTC 25 |
| Finished | Feb 08 06:11:47 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3045520722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev _pkt_sent.3045520722 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_random_length_in_transaction.2708949986 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 202008457 ps |
| CPU time | 1.21 seconds |
| Started | Feb 08 06:11:44 PM UTC 25 |
| Finished | Feb 08 06:11:47 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2708949986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.u sbdev_random_length_in_transaction.2708949986 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_random_length_out_transaction.413113070 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 191754210 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 06:11:45 PM UTC 25 |
| Finished | Feb 08 06:11:47 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=413113070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 29.usbdev_random_length_out_transaction.413113070 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_rx_crc_err.3517131405 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 236922765 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:11:45 PM UTC 25 |
| Finished | Feb 08 06:11:48 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3517131405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbd ev_rx_crc_err.3517131405 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_rx_full.3223665457 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 482203388 ps |
| CPU time | 2.24 seconds |
| Started | Feb 08 06:11:45 PM UTC 25 |
| Finished | Feb 08 06:11:48 PM UTC 25 |
| Peak memory | 217304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3223665457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_ rx_full.3223665457 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_setup_stage.2067901536 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 194203910 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:11:46 PM UTC 25 |
| Finished | Feb 08 06:11:49 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2067901536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usb dev_setup_stage.2067901536 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_setup_trans_ignored.259735517 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 169059165 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 06:11:47 PM UTC 25 |
| Finished | Feb 08 06:11:50 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=259735517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.259735517 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_smoke.3006753219 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 199090699 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 06:11:47 PM UTC 25 |
| Finished | Feb 08 06:11:50 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3006753219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_sm oke.3006753219 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_spurious_pids_ignored.4031021595 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 2663195575 ps |
| CPU time | 22.35 seconds |
| Started | Feb 08 06:11:47 PM UTC 25 |
| Finished | Feb 08 06:12:11 PM UTC 25 |
| Peak memory | 234288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031021595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 29.usbdev_spurious_pids_ignored.4031021595 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_stall_priority_over_nak.3218320530 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 199503228 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 06:11:47 PM UTC 25 |
| Finished | Feb 08 06:11:50 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3218320530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 29.usbdev_stall_priority_over_nak.3218320530 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_stall_trans.2439694235 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 251806384 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:11:47 PM UTC 25 |
| Finished | Feb 08 06:11:51 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2439694235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usb dev_stall_trans.2439694235 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_stream_len_max.3932516462 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 960589015 ps |
| CPU time | 2.69 seconds |
| Started | Feb 08 06:11:48 PM UTC 25 |
| Finished | Feb 08 06:11:52 PM UTC 25 |
| Peak memory | 217476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3932516462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29. usbdev_stream_len_max.3932516462 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_streaming_out.199651744 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 2532742801 ps |
| CPU time | 67.4 seconds |
| Started | Feb 08 06:11:47 PM UTC 25 |
| Finished | Feb 08 06:12:57 PM UTC 25 |
| Peak memory | 227600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=199651744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev _streaming_out.199651744 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_timeout_missing_host_handshake.1972066950 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 1173011504 ps |
| CPU time | 28.02 seconds |
| Started | Feb 08 06:11:31 PM UTC 25 |
| Finished | Feb 08 06:12:00 PM UTC 25 |
| Peak memory | 217336 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972066950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing_host_handshake.1972066950 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_tx_rx_disruption.4222871407 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 643918727 ps |
| CPU time | 1.78 seconds |
| Started | Feb 08 06:11:48 PM UTC 25 |
| Finished | Feb 08 06:11:51 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 222871407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_tx_rx_disruption.4222871407 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/29.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/290.usbdev_tx_rx_disruption.2440263760 |
| Short name | T3386 |
| Test name | |
| Test status | |
| Simulation time | 506209881 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 06:19:21 PM UTC 25 |
| Finished | Feb 08 06:19:24 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 440263760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290.usbdev_tx_rx_disruption.2440263760 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/290.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/291.usbdev_tx_rx_disruption.3820419383 |
| Short name | T3405 |
| Test name | |
| Test status | |
| Simulation time | 653959609 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:19:21 PM UTC 25 |
| Finished | Feb 08 06:19:34 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 820419383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 291.usbdev_tx_rx_disruption.3820419383 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/291.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/292.usbdev_tx_rx_disruption.1263356619 |
| Short name | T3435 |
| Test name | |
| Test status | |
| Simulation time | 554044773 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:19:22 PM UTC 25 |
| Finished | Feb 08 06:19:43 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 263356619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 292.usbdev_tx_rx_disruption.1263356619 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/292.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/293.usbdev_tx_rx_disruption.361310414 |
| Short name | T3398 |
| Test name | |
| Test status | |
| Simulation time | 550900633 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 06:19:24 PM UTC 25 |
| Finished | Feb 08 06:19:33 PM UTC 25 |
| Peak memory | 214924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 61310414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293.usbdev_tx_rx_disruption.361310414 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/293.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/294.usbdev_tx_rx_disruption.1591196599 |
| Short name | T3400 |
| Test name | |
| Test status | |
| Simulation time | 627964646 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:19:24 PM UTC 25 |
| Finished | Feb 08 06:19:33 PM UTC 25 |
| Peak memory | 214856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 591196599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.usbdev_tx_rx_disruption.1591196599 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/294.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/295.usbdev_tx_rx_disruption.4051607836 |
| Short name | T3402 |
| Test name | |
| Test status | |
| Simulation time | 613615980 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:19:24 PM UTC 25 |
| Finished | Feb 08 06:19:34 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 051607836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.usbdev_tx_rx_disruption.4051607836 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/295.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/296.usbdev_tx_rx_disruption.1490804718 |
| Short name | T3450 |
| Test name | |
| Test status | |
| Simulation time | 526714006 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:19:25 PM UTC 25 |
| Finished | Feb 08 06:19:45 PM UTC 25 |
| Peak memory | 217236 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 490804718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296.usbdev_tx_rx_disruption.1490804718 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/296.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/297.usbdev_tx_rx_disruption.2769587958 |
| Short name | T3399 |
| Test name | |
| Test status | |
| Simulation time | 485906665 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:19:25 PM UTC 25 |
| Finished | Feb 08 06:19:33 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 769587958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297.usbdev_tx_rx_disruption.2769587958 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/297.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/298.usbdev_tx_rx_disruption.84360804 |
| Short name | T3401 |
| Test name | |
| Test status | |
| Simulation time | 457075265 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:19:25 PM UTC 25 |
| Finished | Feb 08 06:19:33 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 4360804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298.usbdev_tx_rx_disruption.84360804 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/298.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/299.usbdev_tx_rx_disruption.1491499412 |
| Short name | T3403 |
| Test name | |
| Test status | |
| Simulation time | 562574082 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:19:25 PM UTC 25 |
| Finished | Feb 08 06:19:34 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 491499412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299.usbdev_tx_rx_disruption.1491499412 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/299.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_alert_test.3594456500 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 116749063 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 05:58:34 PM UTC 25 |
| Finished | Feb 08 05:58:37 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594456500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 3.usbdev_alert_test.3594456500 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_reset.860577158 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 20137328571 ps |
| CPU time | 56.71 seconds |
| Started | Feb 08 05:57:28 PM UTC 25 |
| Finished | Feb 08 05:58:27 PM UTC 25 |
| Peak memory | 217380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860577158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TE ST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.860577158 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_resume.3022008859 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 23356733221 ps |
| CPU time | 37.78 seconds |
| Started | Feb 08 05:57:28 PM UTC 25 |
| Finished | Feb 08 05:58:08 PM UTC 25 |
| Peak memory | 227776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022008859 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.3022008859 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_av_buffer.1699819395 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 159411613 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 05:57:30 PM UTC 25 |
| Finished | Feb 08 05:57:32 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1699819395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev _av_buffer.1699819395 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_av_empty.1786001037 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 183834915 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 05:57:30 PM UTC 25 |
| Finished | Feb 08 05:57:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1786001037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ av_empty.1786001037 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_av_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_av_overflow.1895132931 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 152082063 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 05:57:33 PM UTC 25 |
| Finished | Feb 08 05:57:35 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1895132931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbd ev_av_overflow.1895132931 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_av_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_bitstuff_err.3006181078 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 164510659 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 05:57:33 PM UTC 25 |
| Finished | Feb 08 05:57:35 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3006181078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usb dev_bitstuff_err.3006181078 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_data_toggle_clear.3631112805 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 439439986 ps |
| CPU time | 2.67 seconds |
| Started | Feb 08 05:57:36 PM UTC 25 |
| Finished | Feb 08 05:57:40 PM UTC 25 |
| Peak memory | 217112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3631112805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.3631112805 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_device_address.2088479483 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 36273195902 ps |
| CPU time | 85.06 seconds |
| Started | Feb 08 05:57:41 PM UTC 25 |
| Finished | Feb 08 05:59:09 PM UTC 25 |
| Peak memory | 217416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2088479483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.u sbdev_device_address.2088479483 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_device_timeout.1949408592 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 1055422895 ps |
| CPU time | 9.15 seconds |
| Started | Feb 08 05:57:43 PM UTC 25 |
| Finished | Feb 08 05:57:53 PM UTC 25 |
| Peak memory | 217472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949408592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.1949408592 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_disable_endpoint.4108543536 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 655446434 ps |
| CPU time | 3.44 seconds |
| Started | Feb 08 05:57:43 PM UTC 25 |
| Finished | Feb 08 05:57:48 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4108543536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 .usbdev_disable_endpoint.4108543536 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_disconnected.1499284640 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 141928136 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 05:57:47 PM UTC 25 |
| Finished | Feb 08 05:57:50 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1499284640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usb dev_disconnected.1499284640 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_enable.810738133 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 28272517 ps |
| CPU time | 1.05 seconds |
| Started | Feb 08 05:57:48 PM UTC 25 |
| Finished | Feb 08 05:57:50 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=810738133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ena ble.810738133 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_endpoint_access.4290538496 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 1191963693 ps |
| CPU time | 5.1 seconds |
| Started | Feb 08 05:57:49 PM UTC 25 |
| Finished | Feb 08 05:57:56 PM UTC 25 |
| Peak memory | 217564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4290538496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3. usbdev_endpoint_access.4290538496 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_fifo_rst.3535691165 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 187229332 ps |
| CPU time | 2.09 seconds |
| Started | Feb 08 05:57:52 PM UTC 25 |
| Finished | Feb 08 05:57:55 PM UTC 25 |
| Peak memory | 217536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3535691165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ fifo_rst.3535691165 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_freq_hiclk.2592624794 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 121188500452 ps |
| CPU time | 218.23 seconds |
| Started | Feb 08 05:57:53 PM UTC 25 |
| Finished | Feb 08 06:01:34 PM UTC 25 |
| Peak memory | 217408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592624794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phas e_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 3.usbdev_freq_hiclk.2592624794 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_freq_hiclk/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_freq_hiclk_max.3070294989 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 99163458842 ps |
| CPU time | 219.54 seconds |
| Started | Feb 08 05:57:54 PM UTC 25 |
| Finished | Feb 08 06:01:37 PM UTC 25 |
| Peak memory | 217472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_track ing=1 +reset_recovery=1 +usb_freq_delta=+120000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3070294989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hi clk_max.3070294989 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_freq_hiclk_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_freq_loclk.1400629153 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 99105988770 ps |
| CPU time | 215.93 seconds |
| Started | Feb 08 05:57:55 PM UTC 25 |
| Finished | Feb 08 06:01:34 PM UTC 25 |
| Peak memory | 217424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400629153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phas e_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 3.usbdev_freq_loclk.1400629153 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_freq_loclk/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_freq_loclk_max.2429963621 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 103200752277 ps |
| CPU time | 202.22 seconds |
| Started | Feb 08 05:57:56 PM UTC 25 |
| Finished | Feb 08 06:01:22 PM UTC 25 |
| Peak memory | 217532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+1 20000 +reset_recovery=1 +usb_freq_delta=-120000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2429963621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_lo clk_max.2429963621 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_freq_loclk_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_freq_phase.2706314897 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 84177845240 ps |
| CPU time | 169.97 seconds |
| Started | Feb 08 05:57:56 PM UTC 25 |
| Finished | Feb 08 06:00:49 PM UTC 25 |
| Peak memory | 217416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2706314897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 .usbdev_freq_phase.2706314897 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_freq_phase/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_in_iso.2279020697 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 179126969 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 05:57:58 PM UTC 25 |
| Finished | Feb 08 05:58:01 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279020697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 3.usbdev_in_iso.2279020697 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_in_stall.2802065887 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 145225346 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 05:58:00 PM UTC 25 |
| Finished | Feb 08 05:58:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2802065887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ in_stall.2802065887 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_in_trans.4104390078 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 199672396 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 05:58:02 PM UTC 25 |
| Finished | Feb 08 05:58:05 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4104390078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ in_trans.4104390078 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_invalid_sync.3940545417 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 3380427702 ps |
| CPU time | 42.61 seconds |
| Started | Feb 08 05:57:56 PM UTC 25 |
| Finished | Feb 08 05:58:41 PM UTC 25 |
| Peak memory | 227684 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940545417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.3940545417 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_iso_retraction.1553207118 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 11415383805 ps |
| CPU time | 80.62 seconds |
| Started | Feb 08 05:58:02 PM UTC 25 |
| Finished | Feb 08 05:59:25 PM UTC 25 |
| Peak memory | 217488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553207118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 3.usbdev_iso_retraction.1553207118 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_link_in_err.2039577270 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 230568927 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 05:58:04 PM UTC 25 |
| Finished | Feb 08 05:58:07 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2039577270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbd ev_link_in_err.2039577270 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_link_resume.46825554 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 29420810819 ps |
| CPU time | 57.37 seconds |
| Started | Feb 08 05:58:04 PM UTC 25 |
| Finished | Feb 08 05:59:03 PM UTC 25 |
| Peak memory | 217384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=46825554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev _link_resume.46825554 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_link_suspend.2201350090 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 5348847898 ps |
| CPU time | 16.16 seconds |
| Started | Feb 08 05:58:05 PM UTC 25 |
| Finished | Feb 08 05:58:23 PM UTC 25 |
| Peak memory | 227660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2201350090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usb dev_link_suspend.2201350090 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_low_speed_traffic.2251889986 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 4436127306 ps |
| CPU time | 40.4 seconds |
| Started | Feb 08 05:58:05 PM UTC 25 |
| Finished | Feb 08 05:58:47 PM UTC 25 |
| Peak memory | 234388 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251889986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 3.usbdev_low_speed_traffic.2251889986 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_max_inter_pkt_delay.1964286765 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 2227859627 ps |
| CPU time | 19.39 seconds |
| Started | Feb 08 05:58:07 PM UTC 25 |
| Finished | Feb 08 05:58:28 PM UTC 25 |
| Peak memory | 234352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964286765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.1964286765 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_max_length_in_transaction.3222989996 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 250032958 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 05:58:09 PM UTC 25 |
| Finished | Feb 08 05:58:11 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222989996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 3.usbdev_max_length_in_transaction.3222989996 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_max_length_out_transaction.1944475103 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 203108989 ps |
| CPU time | 1.67 seconds |
| Started | Feb 08 05:58:09 PM UTC 25 |
| Finished | Feb 08 05:58:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1944475103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1944475103 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_max_non_iso_usb_traffic.3483124076 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 2524376263 ps |
| CPU time | 26.64 seconds |
| Started | Feb 08 05:58:10 PM UTC 25 |
| Finished | Feb 08 05:58:38 PM UTC 25 |
| Peak memory | 229700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3483124076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 3.usbdev_max_non_iso_usb_traffic.3483124076 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_max_usb_traffic.1613813107 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 2547573743 ps |
| CPU time | 23.05 seconds |
| Started | Feb 08 05:58:10 PM UTC 25 |
| Finished | Feb 08 05:58:34 PM UTC 25 |
| Peak memory | 234356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613813107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_ traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 3.usbdev_max_usb_traffic.1613813107 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_min_inter_pkt_delay.754002849 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 3031220955 ps |
| CPU time | 34.39 seconds |
| Started | Feb 08 05:58:11 PM UTC 25 |
| Finished | Feb 08 05:58:47 PM UTC 25 |
| Peak memory | 229708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754002849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usb dev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.754002849 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_min_length_in_transaction.1368233444 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 198044924 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 05:58:12 PM UTC 25 |
| Finished | Feb 08 05:58:15 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368233444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 3.usbdev_min_length_in_transaction.1368233444 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_min_length_out_transaction.247962898 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 151047562 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 05:58:12 PM UTC 25 |
| Finished | Feb 08 05:58:15 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=247962898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 3.usbdev_min_length_out_transaction.247962898 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_nak_trans.1758425539 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 259299897 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 05:58:14 PM UTC 25 |
| Finished | Feb 08 05:58:16 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1758425539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev _nak_trans.1758425539 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_out_iso.2193261783 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 168824509 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 05:58:15 PM UTC 25 |
| Finished | Feb 08 05:58:17 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2193261783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_o ut_iso.2193261783 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_out_stall.3230874964 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 182606206 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 05:58:16 PM UTC 25 |
| Finished | Feb 08 05:58:19 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3230874964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev _out_stall.3230874964 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_out_trans_nak.3330425563 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 179370963 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 05:58:16 PM UTC 25 |
| Finished | Feb 08 05:58:19 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3330425563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.us bdev_out_trans_nak.3330425563 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_pending_in_trans.1256633437 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 153416768 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 05:58:17 PM UTC 25 |
| Finished | Feb 08 05:58:20 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1256633437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 .usbdev_pending_in_trans.1256633437 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_pinflip.2218596035 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 212786179 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 05:58:17 PM UTC 25 |
| Finished | Feb 08 05:58:20 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218596035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 3.usbdev_phy_config_pinflip.2218596035 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_rand_bus_type.1917975267 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 195838893 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 05:58:18 PM UTC 25 |
| Finished | Feb 08 05:58:21 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1917975267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 3.usbdev_phy_config_rand_bus_type.1917975267 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_phy_config_rand_bus_type/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_usb_ref_disable.3981185007 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 224227031 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 05:58:20 PM UTC 25 |
| Finished | Feb 08 05:58:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3981185007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.3981185007 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_phy_pins_sense.3588941715 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 42948323 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 05:58:20 PM UTC 25 |
| Finished | Feb 08 05:58:22 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3588941715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.u sbdev_phy_pins_sense.3588941715 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_pkt_buffer.3753819296 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 15619975974 ps |
| CPU time | 48.58 seconds |
| Started | Feb 08 05:58:20 PM UTC 25 |
| Finished | Feb 08 05:59:10 PM UTC 25 |
| Peak memory | 227924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3753819296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbde v_pkt_buffer.3753819296 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_pkt_received.3948138060 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 159918983 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 05:58:21 PM UTC 25 |
| Finished | Feb 08 05:58:23 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3948138060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usb dev_pkt_received.3948138060 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_pkt_sent.2940037716 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 210686806 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 05:58:21 PM UTC 25 |
| Finished | Feb 08 05:58:23 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2940037716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ pkt_sent.2940037716 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_rand_bus_disconnects.2276645372 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 2899313836 ps |
| CPU time | 86.73 seconds |
| Started | Feb 08 05:58:24 PM UTC 25 |
| Finished | Feb 08 05:59:53 PM UTC 25 |
| Peak memory | 229624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276645372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_ TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.2276645372 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_rand_bus_disconnects/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_rand_bus_resets.2215647 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 7677351574 ps |
| CPU time | 69.54 seconds |
| Started | Feb 08 05:58:24 PM UTC 25 |
| Finished | Feb 08 05:59:35 PM UTC 25 |
| Peak memory | 229900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.2215647 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_rand_bus_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_rand_suspends.711855420 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 13999096091 ps |
| CPU time | 107.79 seconds |
| Started | Feb 08 05:58:24 PM UTC 25 |
| Finished | Feb 08 06:00:14 PM UTC 25 |
| Peak memory | 229700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711855420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.711855420 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_rand_suspends/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_random_length_in_transaction.1422554731 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 262029137 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 05:58:22 PM UTC 25 |
| Finished | Feb 08 05:58:25 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1422554731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.us bdev_random_length_in_transaction.1422554731 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_random_length_out_transaction.674478435 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 153819389 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 05:58:22 PM UTC 25 |
| Finished | Feb 08 05:58:25 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=674478435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 3.usbdev_random_length_out_transaction.674478435 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_resume_link_active.3972836171 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 20172834909 ps |
| CPU time | 40.99 seconds |
| Started | Feb 08 05:58:24 PM UTC 25 |
| Finished | Feb 08 05:59:07 PM UTC 25 |
| Peak memory | 217148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3972836171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_resume_link_active.3972836171 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_resume_link_active/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_rx_crc_err.1835359790 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 142092037 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 05:58:25 PM UTC 25 |
| Finished | Feb 08 05:58:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1835359790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbde v_rx_crc_err.1835359790 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_rx_pid_err.3867587570 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 217337394 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 05:58:26 PM UTC 25 |
| Finished | Feb 08 05:58:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3867587570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbde v_rx_pid_err.3867587570 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_rx_pid_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_sec_cm.2116636384 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 881294740 ps |
| CPU time | 3.35 seconds |
| Started | Feb 08 05:58:33 PM UTC 25 |
| Finished | Feb 08 05:58:38 PM UTC 25 |
| Peak memory | 251436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116636384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 3.usbdev_sec_cm.2116636384 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_setup_priority.1699169624 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 374886465 ps |
| CPU time | 2.29 seconds |
| Started | Feb 08 05:58:26 PM UTC 25 |
| Finished | Feb 08 05:58:29 PM UTC 25 |
| Peak memory | 217364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1699169624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.u sbdev_setup_priority.1699169624 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_setup_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_setup_priority_over_stall_response.3512680285 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 189724501 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 05:58:28 PM UTC 25 |
| Finished | Feb 08 05:58:30 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3512680285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_respons e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 3.usbdev_setup_priority_over_stall_response.3512680285 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_setup_priority_over_stall_response/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_setup_stage.190929426 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 148125691 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 05:58:28 PM UTC 25 |
| Finished | Feb 08 05:58:30 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=190929426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbde v_setup_stage.190929426 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_setup_trans_ignored.3112293035 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 180236800 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 05:58:28 PM UTC 25 |
| Finished | Feb 08 05:58:30 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3112293035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.usbdev_setup_trans_ignored.3112293035 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_smoke.2290092287 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 230178316 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 05:58:29 PM UTC 25 |
| Finished | Feb 08 05:58:32 PM UTC 25 |
| Peak memory | 214804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2290092287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smo ke.2290092287 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_spurious_pids_ignored.3418931407 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 3559055173 ps |
| CPU time | 37.42 seconds |
| Started | Feb 08 05:58:29 PM UTC 25 |
| Finished | Feb 08 05:59:08 PM UTC 25 |
| Peak memory | 229752 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418931407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 3.usbdev_spurious_pids_ignored.3418931407 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_stall_priority_over_nak.710997795 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 165518574 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 05:58:29 PM UTC 25 |
| Finished | Feb 08 05:58:32 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=710997795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 3.usbdev_stall_priority_over_nak.710997795 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_stall_trans.1480948197 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 194481930 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 05:58:29 PM UTC 25 |
| Finished | Feb 08 05:58:32 PM UTC 25 |
| Peak memory | 214840 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1480948197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbd ev_stall_trans.1480948197 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_stream_len_max.253603047 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 334377840 ps |
| CPU time | 1.88 seconds |
| Started | Feb 08 05:58:32 PM UTC 25 |
| Finished | Feb 08 05:58:35 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=253603047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.us bdev_stream_len_max.253603047 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_streaming_out.1705417156 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 2475764654 ps |
| CPU time | 35.08 seconds |
| Started | Feb 08 05:58:30 PM UTC 25 |
| Finished | Feb 08 05:59:07 PM UTC 25 |
| Peak memory | 229712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1705417156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev _streaming_out.1705417156 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_stress_usb_traffic.3280972374 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 11946089620 ps |
| CPU time | 86.38 seconds |
| Started | Feb 08 05:58:32 PM UTC 25 |
| Finished | Feb 08 06:00:00 PM UTC 25 |
| Peak memory | 229896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280972374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM _TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.3280972374 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_stress_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_timeout_missing_host_handshake.910556304 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 4299869460 ps |
| CPU time | 32.21 seconds |
| Started | Feb 08 05:57:43 PM UTC 25 |
| Finished | Feb 08 05:58:17 PM UTC 25 |
| Peak memory | 217468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910556304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host_handshake.910556304 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/3.usbdev_tx_rx_disruption.284741391 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 600760923 ps |
| CPU time | 2.56 seconds |
| Started | Feb 08 05:58:33 PM UTC 25 |
| Finished | Feb 08 05:58:37 PM UTC 25 |
| Peak memory | 217104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 84741391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_tx_rx_disruption.284741391 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/3.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_alert_test.3357563984 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 37107414 ps |
| CPU time | 0.95 seconds |
| Started | Feb 08 06:12:09 PM UTC 25 |
| Finished | Feb 08 06:12:11 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357563984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 30.usbdev_alert_test.3357563984 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_aon_wake_disconnect.3878951736 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 9237651899 ps |
| CPU time | 18.93 seconds |
| Started | Feb 08 06:11:49 PM UTC 25 |
| Finished | Feb 08 06:12:10 PM UTC 25 |
| Peak memory | 217380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878951736 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.3878951736 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_aon_wake_reset.3335842328 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 13381494036 ps |
| CPU time | 23.76 seconds |
| Started | Feb 08 06:11:49 PM UTC 25 |
| Finished | Feb 08 06:12:15 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335842328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.3335842328 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_aon_wake_resume.3216643271 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 24078095501 ps |
| CPU time | 43.37 seconds |
| Started | Feb 08 06:11:49 PM UTC 25 |
| Finished | Feb 08 06:12:34 PM UTC 25 |
| Peak memory | 227784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216643271 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.3216643271 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_av_buffer.379898546 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 220460368 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:11:49 PM UTC 25 |
| Finished | Feb 08 06:11:52 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=379898546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev _av_buffer.379898546 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_bitstuff_err.1472044043 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 169339329 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:11:49 PM UTC 25 |
| Finished | Feb 08 06:11:52 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1472044043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.us bdev_bitstuff_err.1472044043 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_data_toggle_clear.3428979304 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 362889213 ps |
| CPU time | 2.35 seconds |
| Started | Feb 08 06:11:49 PM UTC 25 |
| Finished | Feb 08 06:11:53 PM UTC 25 |
| Peak memory | 217308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3428979304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.3428979304 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_data_toggle_restore.131970180 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 611317817 ps |
| CPU time | 3.12 seconds |
| Started | Feb 08 06:11:51 PM UTC 25 |
| Finished | Feb 08 06:11:55 PM UTC 25 |
| Peak memory | 217172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131970180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_t oggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.131970180 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_device_address.3517836284 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 25689524989 ps |
| CPU time | 51.15 seconds |
| Started | Feb 08 06:11:51 PM UTC 25 |
| Finished | Feb 08 06:12:44 PM UTC 25 |
| Peak memory | 217668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3517836284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30. usbdev_device_address.3517836284 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_device_timeout.1463992811 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 1343936405 ps |
| CPU time | 28.17 seconds |
| Started | Feb 08 06:11:51 PM UTC 25 |
| Finished | Feb 08 06:12:21 PM UTC 25 |
| Peak memory | 217468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463992811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.1463992811 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_disable_endpoint.3225042272 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 970666489 ps |
| CPU time | 3.19 seconds |
| Started | Feb 08 06:11:52 PM UTC 25 |
| Finished | Feb 08 06:11:57 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3225042272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.usbdev_disable_endpoint.3225042272 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_disconnected.2404289735 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 142009166 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:11:52 PM UTC 25 |
| Finished | Feb 08 06:11:55 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2404289735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.us bdev_disconnected.2404289735 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_enable.2082534704 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 54853700 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:11:52 PM UTC 25 |
| Finished | Feb 08 06:11:55 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2082534704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_e nable.2082534704 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_endpoint_access.1045215481 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 1040067743 ps |
| CPU time | 4.27 seconds |
| Started | Feb 08 06:11:52 PM UTC 25 |
| Finished | Feb 08 06:11:58 PM UTC 25 |
| Peak memory | 217452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1045215481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30 .usbdev_endpoint_access.1045215481 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_endpoint_types.1339839825 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 681327662 ps |
| CPU time | 3.14 seconds |
| Started | Feb 08 06:11:52 PM UTC 25 |
| Finished | Feb 08 06:11:57 PM UTC 25 |
| Peak memory | 217148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339839825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 30.usbdev_endpoint_types.1339839825 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_fifo_rst.3994794967 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 313891158 ps |
| CPU time | 4.09 seconds |
| Started | Feb 08 06:11:53 PM UTC 25 |
| Finished | Feb 08 06:11:58 PM UTC 25 |
| Peak memory | 217468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3994794967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev _fifo_rst.3994794967 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_in_iso.3407616612 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 253579915 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 06:11:54 PM UTC 25 |
| Finished | Feb 08 06:11:57 PM UTC 25 |
| Peak memory | 227756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407616612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 30.usbdev_in_iso.3407616612 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_in_stall.975307649 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 146547608 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:11:54 PM UTC 25 |
| Finished | Feb 08 06:11:56 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=975307649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_ in_stall.975307649 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_in_trans.4047098291 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 231631001 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 06:11:54 PM UTC 25 |
| Finished | Feb 08 06:11:57 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4047098291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev _in_trans.4047098291 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_invalid_sync.3460737737 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 2847558881 ps |
| CPU time | 22.33 seconds |
| Started | Feb 08 06:11:53 PM UTC 25 |
| Finished | Feb 08 06:12:16 PM UTC 25 |
| Peak memory | 229820 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460737737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.3460737737 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_iso_retraction.1908925324 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 8161999926 ps |
| CPU time | 92.15 seconds |
| Started | Feb 08 06:11:55 PM UTC 25 |
| Finished | Feb 08 06:13:29 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908925324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 30.usbdev_iso_retraction.1908925324 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_link_in_err.3471720053 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 212036716 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:11:55 PM UTC 25 |
| Finished | Feb 08 06:11:58 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3471720053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usb dev_link_in_err.3471720053 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_link_resume.2084040709 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 25937499805 ps |
| CPU time | 41.1 seconds |
| Started | Feb 08 06:11:56 PM UTC 25 |
| Finished | Feb 08 06:12:39 PM UTC 25 |
| Peak memory | 227592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2084040709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usb dev_link_resume.2084040709 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_link_suspend.2814966534 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 3874084512 ps |
| CPU time | 12.88 seconds |
| Started | Feb 08 06:11:56 PM UTC 25 |
| Finished | Feb 08 06:12:11 PM UTC 25 |
| Peak memory | 227592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2814966534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.us bdev_link_suspend.2814966534 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_low_speed_traffic.2010205041 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 3682378802 ps |
| CPU time | 30.62 seconds |
| Started | Feb 08 06:11:57 PM UTC 25 |
| Finished | Feb 08 06:12:29 PM UTC 25 |
| Peak memory | 234376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010205041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 30.usbdev_low_speed_traffic.2010205041 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_max_inter_pkt_delay.1390061944 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 1905913266 ps |
| CPU time | 15.01 seconds |
| Started | Feb 08 06:11:58 PM UTC 25 |
| Finished | Feb 08 06:12:14 PM UTC 25 |
| Peak memory | 217340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390061944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.1390061944 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_max_length_in_transaction.1050062186 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 234475589 ps |
| CPU time | 1.23 seconds |
| Started | Feb 08 06:11:58 PM UTC 25 |
| Finished | Feb 08 06:12:00 PM UTC 25 |
| Peak memory | 215044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050062186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 30.usbdev_max_length_in_transaction.1050062186 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_max_length_out_transaction.558192687 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 209025369 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:11:58 PM UTC 25 |
| Finished | Feb 08 06:12:01 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=558192687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 30.usbdev_max_length_out_transaction.558192687 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_min_inter_pkt_delay.2375668243 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 1855909795 ps |
| CPU time | 17.78 seconds |
| Started | Feb 08 06:11:58 PM UTC 25 |
| Finished | Feb 08 06:12:17 PM UTC 25 |
| Peak memory | 227740 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375668243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.2375668243 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_min_length_in_transaction.2156966774 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 158302211 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:11:58 PM UTC 25 |
| Finished | Feb 08 06:12:01 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156966774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 30.usbdev_min_length_in_transaction.2156966774 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_min_length_out_transaction.1909918430 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 156054960 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:11:58 PM UTC 25 |
| Finished | Feb 08 06:12:01 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1909918430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1909918430 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_nak_trans.3855804806 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 288007510 ps |
| CPU time | 1.9 seconds |
| Started | Feb 08 06:11:59 PM UTC 25 |
| Finished | Feb 08 06:12:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3855804806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbde v_nak_trans.3855804806 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_out_iso.3087035420 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 170918717 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:11:59 PM UTC 25 |
| Finished | Feb 08 06:12:02 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3087035420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_ out_iso.3087035420 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_out_stall.1395533521 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 217391492 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:11:59 PM UTC 25 |
| Finished | Feb 08 06:12:02 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1395533521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbde v_out_stall.1395533521 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_out_trans_nak.2808350787 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 219219449 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:12:00 PM UTC 25 |
| Finished | Feb 08 06:12:02 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2808350787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.u sbdev_out_trans_nak.2808350787 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_pending_in_trans.3369785964 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 229353066 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:12:01 PM UTC 25 |
| Finished | Feb 08 06:12:03 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3369785964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.usbdev_pending_in_trans.3369785964 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_phy_config_pinflip.1721135124 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 264853870 ps |
| CPU time | 1.89 seconds |
| Started | Feb 08 06:12:01 PM UTC 25 |
| Finished | Feb 08 06:12:04 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721135124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 30.usbdev_phy_config_pinflip.1721135124 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_phy_config_usb_ref_disable.2479807864 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 162216853 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:12:01 PM UTC 25 |
| Finished | Feb 08 06:12:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2479807864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.2479807864 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_phy_pins_sense.1351024522 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 34687407 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:12:02 PM UTC 25 |
| Finished | Feb 08 06:12:05 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1351024522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30. usbdev_phy_pins_sense.1351024522 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_pkt_buffer.3901955346 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 15273878764 ps |
| CPU time | 40.02 seconds |
| Started | Feb 08 06:12:02 PM UTC 25 |
| Finished | Feb 08 06:12:44 PM UTC 25 |
| Peak memory | 227676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3901955346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbd ev_pkt_buffer.3901955346 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_pkt_received.3839138736 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 160213116 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:12:02 PM UTC 25 |
| Finished | Feb 08 06:12:05 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3839138736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.us bdev_pkt_received.3839138736 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_pkt_sent.1737489278 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 159272818 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:12:04 PM UTC 25 |
| Finished | Feb 08 06:12:07 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1737489278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev _pkt_sent.1737489278 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_random_length_in_transaction.187695132 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 175908511 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:12:04 PM UTC 25 |
| Finished | Feb 08 06:12:07 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=187695132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.us bdev_random_length_in_transaction.187695132 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_random_length_out_transaction.3647901071 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 232822476 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:12:04 PM UTC 25 |
| Finished | Feb 08 06:12:07 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3647901071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 30.usbdev_random_length_out_transaction.3647901071 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_rx_crc_err.2857511838 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 180580620 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:12:04 PM UTC 25 |
| Finished | Feb 08 06:12:07 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2857511838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbd ev_rx_crc_err.2857511838 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_rx_full.3659320757 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 371036486 ps |
| CPU time | 2.32 seconds |
| Started | Feb 08 06:12:04 PM UTC 25 |
| Finished | Feb 08 06:12:08 PM UTC 25 |
| Peak memory | 217176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3659320757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_ rx_full.3659320757 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_setup_stage.3932052048 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 166854420 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:12:04 PM UTC 25 |
| Finished | Feb 08 06:12:07 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3932052048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usb dev_setup_stage.3932052048 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_setup_trans_ignored.1382399928 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 166022179 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:12:07 PM UTC 25 |
| Finished | Feb 08 06:12:10 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1382399928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 30.usbdev_setup_trans_ignored.1382399928 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_smoke.1106813194 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 223447118 ps |
| CPU time | 1.74 seconds |
| Started | Feb 08 06:12:07 PM UTC 25 |
| Finished | Feb 08 06:12:10 PM UTC 25 |
| Peak memory | 215072 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1106813194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_sm oke.1106813194 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_spurious_pids_ignored.1863386623 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 2546327543 ps |
| CPU time | 26.49 seconds |
| Started | Feb 08 06:12:07 PM UTC 25 |
| Finished | Feb 08 06:12:35 PM UTC 25 |
| Peak memory | 234276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863386623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 30.usbdev_spurious_pids_ignored.1863386623 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_stall_priority_over_nak.2500561561 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 171835420 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:12:07 PM UTC 25 |
| Finished | Feb 08 06:12:10 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2500561561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 30.usbdev_stall_priority_over_nak.2500561561 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_stall_trans.4235357153 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 184120838 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:12:07 PM UTC 25 |
| Finished | Feb 08 06:12:10 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4235357153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usb dev_stall_trans.4235357153 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_stream_len_max.2488993259 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 649867508 ps |
| CPU time | 2.84 seconds |
| Started | Feb 08 06:12:08 PM UTC 25 |
| Finished | Feb 08 06:12:13 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2488993259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30. usbdev_stream_len_max.2488993259 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_streaming_out.1310342170 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 3813716439 ps |
| CPU time | 97.85 seconds |
| Started | Feb 08 06:12:07 PM UTC 25 |
| Finished | Feb 08 06:13:47 PM UTC 25 |
| Peak memory | 227816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1310342170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbde v_streaming_out.1310342170 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_timeout_missing_host_handshake.4249173120 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 5035016603 ps |
| CPU time | 33.07 seconds |
| Started | Feb 08 06:11:51 PM UTC 25 |
| Finished | Feb 08 06:12:26 PM UTC 25 |
| Peak memory | 217464 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249173120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing_host_handshake.4249173120 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_tx_rx_disruption.1279142975 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 474169758 ps |
| CPU time | 2.75 seconds |
| Started | Feb 08 06:12:09 PM UTC 25 |
| Finished | Feb 08 06:12:13 PM UTC 25 |
| Peak memory | 217180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 279142975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_tx_rx_disruption.1279142975 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/30.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/300.usbdev_tx_rx_disruption.4012553779 |
| Short name | T3449 |
| Test name | |
| Test status | |
| Simulation time | 495455749 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:19:25 PM UTC 25 |
| Finished | Feb 08 06:19:45 PM UTC 25 |
| Peak memory | 217164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 012553779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 300.usbdev_tx_rx_disruption.4012553779 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/300.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/301.usbdev_tx_rx_disruption.3318188783 |
| Short name | T3407 |
| Test name | |
| Test status | |
| Simulation time | 613590970 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:19:25 PM UTC 25 |
| Finished | Feb 08 06:19:38 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 318188783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 301.usbdev_tx_rx_disruption.3318188783 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/301.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/302.usbdev_tx_rx_disruption.2260936122 |
| Short name | T3445 |
| Test name | |
| Test status | |
| Simulation time | 519329760 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:19:25 PM UTC 25 |
| Finished | Feb 08 06:19:44 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 260936122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 302.usbdev_tx_rx_disruption.2260936122 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/302.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/303.usbdev_tx_rx_disruption.2951056329 |
| Short name | T3394 |
| Test name | |
| Test status | |
| Simulation time | 533788798 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:19:25 PM UTC 25 |
| Finished | Feb 08 06:19:28 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 951056329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 303.usbdev_tx_rx_disruption.2951056329 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/303.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/304.usbdev_tx_rx_disruption.198229758 |
| Short name | T3393 |
| Test name | |
| Test status | |
| Simulation time | 556119558 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:19:25 PM UTC 25 |
| Finished | Feb 08 06:19:28 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 98229758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 304.usbdev_tx_rx_disruption.198229758 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/304.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/305.usbdev_tx_rx_disruption.4094506496 |
| Short name | T3397 |
| Test name | |
| Test status | |
| Simulation time | 584080541 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:19:25 PM UTC 25 |
| Finished | Feb 08 06:19:29 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 094506496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 305.usbdev_tx_rx_disruption.4094506496 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/305.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/306.usbdev_tx_rx_disruption.3678433923 |
| Short name | T3392 |
| Test name | |
| Test status | |
| Simulation time | 461202946 ps |
| CPU time | 1.23 seconds |
| Started | Feb 08 06:19:25 PM UTC 25 |
| Finished | Feb 08 06:19:28 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 678433923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 306.usbdev_tx_rx_disruption.3678433923 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/306.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/307.usbdev_tx_rx_disruption.427142610 |
| Short name | T3396 |
| Test name | |
| Test status | |
| Simulation time | 504410129 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:19:26 PM UTC 25 |
| Finished | Feb 08 06:19:28 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 27142610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 307.usbdev_tx_rx_disruption.427142610 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/307.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/308.usbdev_tx_rx_disruption.3192083827 |
| Short name | T3395 |
| Test name | |
| Test status | |
| Simulation time | 501703952 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:19:26 PM UTC 25 |
| Finished | Feb 08 06:19:28 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 192083827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 308.usbdev_tx_rx_disruption.3192083827 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/308.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/309.usbdev_tx_rx_disruption.1309145375 |
| Short name | T3418 |
| Test name | |
| Test status | |
| Simulation time | 640632145 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:19:29 PM UTC 25 |
| Finished | Feb 08 06:19:39 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 309145375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 309.usbdev_tx_rx_disruption.1309145375 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/309.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_alert_test.1201045424 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 64476387 ps |
| CPU time | 0.92 seconds |
| Started | Feb 08 06:12:24 PM UTC 25 |
| Finished | Feb 08 06:12:26 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201045424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 31.usbdev_alert_test.1201045424 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_aon_wake_disconnect.3834719016 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 7117800079 ps |
| CPU time | 11.75 seconds |
| Started | Feb 08 06:12:09 PM UTC 25 |
| Finished | Feb 08 06:12:22 PM UTC 25 |
| Peak memory | 227588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834719016 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.3834719016 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_aon_wake_reset.602750110 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 18899048626 ps |
| CPU time | 32.83 seconds |
| Started | Feb 08 06:12:09 PM UTC 25 |
| Finished | Feb 08 06:12:43 PM UTC 25 |
| Peak memory | 217640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602750110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TE ST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.602750110 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_aon_wake_resume.2893311585 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 25456019393 ps |
| CPU time | 32.6 seconds |
| Started | Feb 08 06:12:09 PM UTC 25 |
| Finished | Feb 08 06:12:43 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893311585 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.2893311585 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_av_buffer.3509624109 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 167020952 ps |
| CPU time | 0.96 seconds |
| Started | Feb 08 06:12:10 PM UTC 25 |
| Finished | Feb 08 06:12:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3509624109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbde v_av_buffer.3509624109 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_bitstuff_err.1715996130 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 150644489 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:12:12 PM UTC 25 |
| Finished | Feb 08 06:12:14 PM UTC 25 |
| Peak memory | 215068 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1715996130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.us bdev_bitstuff_err.1715996130 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_data_toggle_clear.2522271573 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 290149558 ps |
| CPU time | 1.95 seconds |
| Started | Feb 08 06:12:12 PM UTC 25 |
| Finished | Feb 08 06:12:15 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2522271573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.2522271573 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_data_toggle_restore.710358390 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 463319320 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:12:12 PM UTC 25 |
| Finished | Feb 08 06:12:15 PM UTC 25 |
| Peak memory | 215060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710358390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_t oggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.710358390 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_device_address.3428140489 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 19568782915 ps |
| CPU time | 35.69 seconds |
| Started | Feb 08 06:12:12 PM UTC 25 |
| Finished | Feb 08 06:12:49 PM UTC 25 |
| Peak memory | 217488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3428140489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31. usbdev_device_address.3428140489 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_device_timeout.192621471 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 1151663434 ps |
| CPU time | 24.28 seconds |
| Started | Feb 08 06:12:12 PM UTC 25 |
| Finished | Feb 08 06:12:38 PM UTC 25 |
| Peak memory | 217340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192621471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.192621471 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_disable_endpoint.2103143866 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 831146811 ps |
| CPU time | 2.26 seconds |
| Started | Feb 08 06:12:12 PM UTC 25 |
| Finished | Feb 08 06:12:15 PM UTC 25 |
| Peak memory | 216952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2103143866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.usbdev_disable_endpoint.2103143866 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_disconnected.1288544466 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 154714283 ps |
| CPU time | 1 seconds |
| Started | Feb 08 06:12:12 PM UTC 25 |
| Finished | Feb 08 06:12:14 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1288544466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.us bdev_disconnected.1288544466 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_enable.741685294 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 35294964 ps |
| CPU time | 0.98 seconds |
| Started | Feb 08 06:12:12 PM UTC 25 |
| Finished | Feb 08 06:12:14 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=741685294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_en able.741685294 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_endpoint_access.3571283073 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 890738337 ps |
| CPU time | 4.18 seconds |
| Started | Feb 08 06:12:13 PM UTC 25 |
| Finished | Feb 08 06:12:19 PM UTC 25 |
| Peak memory | 217444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3571283073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31 .usbdev_endpoint_access.3571283073 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_fifo_rst.3585447084 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 268458343 ps |
| CPU time | 2.85 seconds |
| Started | Feb 08 06:12:13 PM UTC 25 |
| Finished | Feb 08 06:12:17 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3585447084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev _fifo_rst.3585447084 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_in_iso.2687455268 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 258295846 ps |
| CPU time | 1.99 seconds |
| Started | Feb 08 06:12:13 PM UTC 25 |
| Finished | Feb 08 06:12:17 PM UTC 25 |
| Peak memory | 227756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687455268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 31.usbdev_in_iso.2687455268 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_in_stall.2785949760 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 148568458 ps |
| CPU time | 1 seconds |
| Started | Feb 08 06:12:15 PM UTC 25 |
| Finished | Feb 08 06:12:17 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2785949760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev _in_stall.2785949760 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_in_trans.846622293 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 231570781 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:12:15 PM UTC 25 |
| Finished | Feb 08 06:12:18 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=846622293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_ in_trans.846622293 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_invalid_sync.1037735748 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 4319588408 ps |
| CPU time | 39.05 seconds |
| Started | Feb 08 06:12:13 PM UTC 25 |
| Finished | Feb 08 06:12:54 PM UTC 25 |
| Peak memory | 234364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037735748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.1037735748 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_iso_retraction.1210883023 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 12236089638 ps |
| CPU time | 96.15 seconds |
| Started | Feb 08 06:12:15 PM UTC 25 |
| Finished | Feb 08 06:13:53 PM UTC 25 |
| Peak memory | 217576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210883023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 31.usbdev_iso_retraction.1210883023 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_link_in_err.2981678805 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 245764083 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:12:15 PM UTC 25 |
| Finished | Feb 08 06:12:18 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2981678805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usb dev_link_in_err.2981678805 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_link_resume.2894640979 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 6788232921 ps |
| CPU time | 12.98 seconds |
| Started | Feb 08 06:12:15 PM UTC 25 |
| Finished | Feb 08 06:12:29 PM UTC 25 |
| Peak memory | 217424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2894640979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usb dev_link_resume.2894640979 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_link_suspend.3865506749 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 6149950720 ps |
| CPU time | 10.68 seconds |
| Started | Feb 08 06:12:15 PM UTC 25 |
| Finished | Feb 08 06:12:28 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3865506749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.us bdev_link_suspend.3865506749 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_low_speed_traffic.1801328204 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 3772830618 ps |
| CPU time | 111.31 seconds |
| Started | Feb 08 06:12:16 PM UTC 25 |
| Finished | Feb 08 06:14:10 PM UTC 25 |
| Peak memory | 229800 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801328204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 31.usbdev_low_speed_traffic.1801328204 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_max_inter_pkt_delay.628468406 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 3959059505 ps |
| CPU time | 27.24 seconds |
| Started | Feb 08 06:12:16 PM UTC 25 |
| Finished | Feb 08 06:12:45 PM UTC 25 |
| Peak memory | 229696 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628468406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.628468406 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_max_length_in_transaction.802637715 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 278198138 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:12:16 PM UTC 25 |
| Finished | Feb 08 06:12:19 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802637715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 31.usbdev_max_length_in_transaction.802637715 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_max_length_out_transaction.1313394939 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 193253348 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:12:17 PM UTC 25 |
| Finished | Feb 08 06:12:19 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1313394939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.1313394939 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_min_inter_pkt_delay.2578705034 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 1967276324 ps |
| CPU time | 18.37 seconds |
| Started | Feb 08 06:12:19 PM UTC 25 |
| Finished | Feb 08 06:12:39 PM UTC 25 |
| Peak memory | 234552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578705034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.2578705034 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_min_length_in_transaction.2525883142 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 165225041 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 06:12:19 PM UTC 25 |
| Finished | Feb 08 06:12:21 PM UTC 25 |
| Peak memory | 215088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525883142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 31.usbdev_min_length_in_transaction.2525883142 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_min_length_out_transaction.654485170 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 195018464 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:12:19 PM UTC 25 |
| Finished | Feb 08 06:12:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=654485170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 31.usbdev_min_length_out_transaction.654485170 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_nak_trans.2493634446 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 226731647 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:12:19 PM UTC 25 |
| Finished | Feb 08 06:12:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2493634446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbde v_nak_trans.2493634446 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_out_iso.1228102154 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 176421370 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:12:19 PM UTC 25 |
| Finished | Feb 08 06:12:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1228102154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_ out_iso.1228102154 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_out_stall.2546148426 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 171798162 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 06:12:19 PM UTC 25 |
| Finished | Feb 08 06:12:21 PM UTC 25 |
| Peak memory | 215020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2546148426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbde v_out_stall.2546148426 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_out_trans_nak.507662499 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 190407563 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:12:19 PM UTC 25 |
| Finished | Feb 08 06:12:22 PM UTC 25 |
| Peak memory | 215008 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=507662499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.us bdev_out_trans_nak.507662499 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_pending_in_trans.1590706244 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 154042153 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:12:19 PM UTC 25 |
| Finished | Feb 08 06:12:22 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1590706244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.usbdev_pending_in_trans.1590706244 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_phy_config_pinflip.3072791917 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 204257610 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:12:19 PM UTC 25 |
| Finished | Feb 08 06:12:22 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072791917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 31.usbdev_phy_config_pinflip.3072791917 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_phy_config_usb_ref_disable.3201245137 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 155664731 ps |
| CPU time | 0.99 seconds |
| Started | Feb 08 06:12:19 PM UTC 25 |
| Finished | Feb 08 06:12:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3201245137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3201245137 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_phy_pins_sense.1054040409 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 32967858 ps |
| CPU time | 0.89 seconds |
| Started | Feb 08 06:12:21 PM UTC 25 |
| Finished | Feb 08 06:12:23 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1054040409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31. usbdev_phy_pins_sense.1054040409 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_pkt_buffer.1252667426 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 7071607021 ps |
| CPU time | 22.58 seconds |
| Started | Feb 08 06:12:21 PM UTC 25 |
| Finished | Feb 08 06:12:45 PM UTC 25 |
| Peak memory | 227744 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1252667426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbd ev_pkt_buffer.1252667426 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_pkt_received.3640028994 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 202927099 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:12:21 PM UTC 25 |
| Finished | Feb 08 06:12:24 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3640028994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.us bdev_pkt_received.3640028994 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_pkt_sent.3213907470 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 235312977 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:12:21 PM UTC 25 |
| Finished | Feb 08 06:12:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3213907470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev _pkt_sent.3213907470 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_random_length_in_transaction.431131004 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 166065398 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:12:21 PM UTC 25 |
| Finished | Feb 08 06:12:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=431131004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.us bdev_random_length_in_transaction.431131004 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_random_length_out_transaction.2659882906 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 199467188 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 06:12:21 PM UTC 25 |
| Finished | Feb 08 06:12:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2659882906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 31.usbdev_random_length_out_transaction.2659882906 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_rx_crc_err.3185278474 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 176191358 ps |
| CPU time | 0.95 seconds |
| Started | Feb 08 06:12:21 PM UTC 25 |
| Finished | Feb 08 06:12:24 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3185278474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbd ev_rx_crc_err.3185278474 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_rx_full.3175176684 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 364450945 ps |
| CPU time | 2.25 seconds |
| Started | Feb 08 06:12:23 PM UTC 25 |
| Finished | Feb 08 06:12:26 PM UTC 25 |
| Peak memory | 216860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3175176684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_ rx_full.3175176684 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_setup_stage.2938296616 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 171714218 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:12:23 PM UTC 25 |
| Finished | Feb 08 06:12:25 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2938296616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usb dev_setup_stage.2938296616 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_setup_trans_ignored.3290244258 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 212451238 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 06:12:23 PM UTC 25 |
| Finished | Feb 08 06:12:25 PM UTC 25 |
| Peak memory | 214948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3290244258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 31.usbdev_setup_trans_ignored.3290244258 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_smoke.3684489202 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 229163055 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:12:23 PM UTC 25 |
| Finished | Feb 08 06:12:26 PM UTC 25 |
| Peak memory | 214880 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3684489202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_sm oke.3684489202 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_spurious_pids_ignored.4125902572 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 2386274465 ps |
| CPU time | 22.59 seconds |
| Started | Feb 08 06:12:23 PM UTC 25 |
| Finished | Feb 08 06:12:47 PM UTC 25 |
| Peak memory | 234480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125902572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 31.usbdev_spurious_pids_ignored.4125902572 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_stall_priority_over_nak.1727089209 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 169226494 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:12:23 PM UTC 25 |
| Finished | Feb 08 06:12:25 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1727089209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 31.usbdev_stall_priority_over_nak.1727089209 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_stall_trans.3331471605 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 156589770 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:12:23 PM UTC 25 |
| Finished | Feb 08 06:12:26 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3331471605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usb dev_stall_trans.3331471605 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_stream_len_max.1434812361 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 829696256 ps |
| CPU time | 2.54 seconds |
| Started | Feb 08 06:12:23 PM UTC 25 |
| Finished | Feb 08 06:12:27 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1434812361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31. usbdev_stream_len_max.1434812361 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_streaming_out.1495216405 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 2382459742 ps |
| CPU time | 63.02 seconds |
| Started | Feb 08 06:12:23 PM UTC 25 |
| Finished | Feb 08 06:13:28 PM UTC 25 |
| Peak memory | 227652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1495216405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbde v_streaming_out.1495216405 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_timeout_missing_host_handshake.2163009090 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 748711234 ps |
| CPU time | 5.88 seconds |
| Started | Feb 08 06:12:12 PM UTC 25 |
| Finished | Feb 08 06:12:19 PM UTC 25 |
| Peak memory | 217596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163009090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing_host_handshake.2163009090 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_tx_rx_disruption.2997967187 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 513980770 ps |
| CPU time | 2.11 seconds |
| Started | Feb 08 06:12:23 PM UTC 25 |
| Finished | Feb 08 06:12:27 PM UTC 25 |
| Peak memory | 217116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 997967187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_tx_rx_disruption.2997967187 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/31.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/310.usbdev_tx_rx_disruption.4070703475 |
| Short name | T3415 |
| Test name | |
| Test status | |
| Simulation time | 578947350 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:19:29 PM UTC 25 |
| Finished | Feb 08 06:19:39 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 070703475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 310.usbdev_tx_rx_disruption.4070703475 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/310.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/311.usbdev_tx_rx_disruption.2816313036 |
| Short name | T3420 |
| Test name | |
| Test status | |
| Simulation time | 590162509 ps |
| CPU time | 1.72 seconds |
| Started | Feb 08 06:19:29 PM UTC 25 |
| Finished | Feb 08 06:19:39 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 816313036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 311.usbdev_tx_rx_disruption.2816313036 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/311.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/312.usbdev_tx_rx_disruption.1637785603 |
| Short name | T3416 |
| Test name | |
| Test status | |
| Simulation time | 527224778 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:19:29 PM UTC 25 |
| Finished | Feb 08 06:19:39 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 637785603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 312.usbdev_tx_rx_disruption.1637785603 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/312.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/313.usbdev_tx_rx_disruption.3267573604 |
| Short name | T3419 |
| Test name | |
| Test status | |
| Simulation time | 591524648 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:19:29 PM UTC 25 |
| Finished | Feb 08 06:19:39 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 267573604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 313.usbdev_tx_rx_disruption.3267573604 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/313.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/314.usbdev_tx_rx_disruption.447573588 |
| Short name | T3417 |
| Test name | |
| Test status | |
| Simulation time | 531470099 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:19:29 PM UTC 25 |
| Finished | Feb 08 06:19:39 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 47573588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 314.usbdev_tx_rx_disruption.447573588 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/314.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/315.usbdev_tx_rx_disruption.2738308163 |
| Short name | T3472 |
| Test name | |
| Test status | |
| Simulation time | 443859439 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:19:32 PM UTC 25 |
| Finished | Feb 08 06:19:59 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 738308163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 315.usbdev_tx_rx_disruption.2738308163 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/315.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/316.usbdev_tx_rx_disruption.744516543 |
| Short name | T3471 |
| Test name | |
| Test status | |
| Simulation time | 532870330 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:19:32 PM UTC 25 |
| Finished | Feb 08 06:19:59 PM UTC 25 |
| Peak memory | 214828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 44516543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 316.usbdev_tx_rx_disruption.744516543 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/316.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/317.usbdev_tx_rx_disruption.606472262 |
| Short name | T3473 |
| Test name | |
| Test status | |
| Simulation time | 610483095 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:19:32 PM UTC 25 |
| Finished | Feb 08 06:19:59 PM UTC 25 |
| Peak memory | 214860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6 06472262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 317.usbdev_tx_rx_disruption.606472262 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/317.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/318.usbdev_tx_rx_disruption.3272082870 |
| Short name | T3478 |
| Test name | |
| Test status | |
| Simulation time | 668100749 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:19:33 PM UTC 25 |
| Finished | Feb 08 06:19:59 PM UTC 25 |
| Peak memory | 214752 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 272082870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 318.usbdev_tx_rx_disruption.3272082870 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/318.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/319.usbdev_tx_rx_disruption.2178868622 |
| Short name | T3470 |
| Test name | |
| Test status | |
| Simulation time | 542291570 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:19:33 PM UTC 25 |
| Finished | Feb 08 06:19:59 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 178868622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 319.usbdev_tx_rx_disruption.2178868622 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/319.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_alert_test.2097821861 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 35643048 ps |
| CPU time | 0.98 seconds |
| Started | Feb 08 06:12:40 PM UTC 25 |
| Finished | Feb 08 06:12:42 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097821861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 32.usbdev_alert_test.2097821861 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_aon_wake_disconnect.3489116313 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 4831342681 ps |
| CPU time | 7.76 seconds |
| Started | Feb 08 06:12:26 PM UTC 25 |
| Finished | Feb 08 06:12:34 PM UTC 25 |
| Peak memory | 227652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489116313 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.3489116313 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_aon_wake_reset.3352217258 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 15128121280 ps |
| CPU time | 23.35 seconds |
| Started | Feb 08 06:12:26 PM UTC 25 |
| Finished | Feb 08 06:12:50 PM UTC 25 |
| Peak memory | 227784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352217258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3352217258 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_aon_wake_resume.2694242139 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 29292965054 ps |
| CPU time | 42.86 seconds |
| Started | Feb 08 06:12:26 PM UTC 25 |
| Finished | Feb 08 06:13:10 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694242139 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.2694242139 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_av_buffer.3576811733 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 200166564 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:12:26 PM UTC 25 |
| Finished | Feb 08 06:12:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3576811733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbde v_av_buffer.3576811733 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_bitstuff_err.895455886 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 141210049 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:12:26 PM UTC 25 |
| Finished | Feb 08 06:12:28 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=895455886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usb dev_bitstuff_err.895455886 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_data_toggle_clear.4183586020 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 382877659 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:12:28 PM UTC 25 |
| Finished | Feb 08 06:12:30 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4183586020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.4183586020 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_data_toggle_restore.3276348285 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 1042588665 ps |
| CPU time | 4.03 seconds |
| Started | Feb 08 06:12:28 PM UTC 25 |
| Finished | Feb 08 06:12:33 PM UTC 25 |
| Peak memory | 217372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276348285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.3276348285 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_device_address.3138475219 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 24741196922 ps |
| CPU time | 45.08 seconds |
| Started | Feb 08 06:12:28 PM UTC 25 |
| Finished | Feb 08 06:13:15 PM UTC 25 |
| Peak memory | 217480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3138475219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32. usbdev_device_address.3138475219 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_device_timeout.4210324711 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 752455752 ps |
| CPU time | 14.12 seconds |
| Started | Feb 08 06:12:28 PM UTC 25 |
| Finished | Feb 08 06:12:43 PM UTC 25 |
| Peak memory | 217348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210324711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.4210324711 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_disable_endpoint.2982307781 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 680430291 ps |
| CPU time | 3.01 seconds |
| Started | Feb 08 06:12:28 PM UTC 25 |
| Finished | Feb 08 06:12:32 PM UTC 25 |
| Peak memory | 217280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2982307781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.usbdev_disable_endpoint.2982307781 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_disconnected.2090150400 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 174979217 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:12:28 PM UTC 25 |
| Finished | Feb 08 06:12:31 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2090150400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.us bdev_disconnected.2090150400 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_enable.2801280815 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 40520742 ps |
| CPU time | 0.9 seconds |
| Started | Feb 08 06:12:28 PM UTC 25 |
| Finished | Feb 08 06:12:30 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2801280815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_e nable.2801280815 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_endpoint_access.727605771 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 786016149 ps |
| CPU time | 2.62 seconds |
| Started | Feb 08 06:12:28 PM UTC 25 |
| Finished | Feb 08 06:12:32 PM UTC 25 |
| Peak memory | 217176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=727605771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32. usbdev_endpoint_access.727605771 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_endpoint_types.3054313926 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 347330425 ps |
| CPU time | 1.83 seconds |
| Started | Feb 08 06:12:28 PM UTC 25 |
| Finished | Feb 08 06:12:31 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054313926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 32.usbdev_endpoint_types.3054313926 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_fifo_rst.398075052 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 167107521 ps |
| CPU time | 2.06 seconds |
| Started | Feb 08 06:12:28 PM UTC 25 |
| Finished | Feb 08 06:12:32 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=398075052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_ fifo_rst.398075052 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_in_iso.503882702 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 213214742 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 06:12:29 PM UTC 25 |
| Finished | Feb 08 06:12:32 PM UTC 25 |
| Peak memory | 227816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503882702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 32.usbdev_in_iso.503882702 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_in_stall.4232644506 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 136046091 ps |
| CPU time | 0.96 seconds |
| Started | Feb 08 06:12:29 PM UTC 25 |
| Finished | Feb 08 06:12:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4232644506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev _in_stall.4232644506 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_in_trans.4245861262 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 183745126 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:12:29 PM UTC 25 |
| Finished | Feb 08 06:12:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4245861262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev _in_trans.4245861262 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_invalid_sync.2500970528 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 3583056261 ps |
| CPU time | 36.7 seconds |
| Started | Feb 08 06:12:28 PM UTC 25 |
| Finished | Feb 08 06:13:07 PM UTC 25 |
| Peak memory | 229788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500970528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.2500970528 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_iso_retraction.3175566641 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 9619600410 ps |
| CPU time | 112.37 seconds |
| Started | Feb 08 06:12:29 PM UTC 25 |
| Finished | Feb 08 06:14:24 PM UTC 25 |
| Peak memory | 217576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175566641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 32.usbdev_iso_retraction.3175566641 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_link_in_err.2786838347 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 280023617 ps |
| CPU time | 1.67 seconds |
| Started | Feb 08 06:12:30 PM UTC 25 |
| Finished | Feb 08 06:12:32 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2786838347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usb dev_link_in_err.2786838347 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_link_resume.3023568645 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 28643913695 ps |
| CPU time | 46.64 seconds |
| Started | Feb 08 06:12:31 PM UTC 25 |
| Finished | Feb 08 06:13:19 PM UTC 25 |
| Peak memory | 217392 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3023568645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usb dev_link_resume.3023568645 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_link_suspend.1460379122 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 9648522036 ps |
| CPU time | 16.22 seconds |
| Started | Feb 08 06:12:32 PM UTC 25 |
| Finished | Feb 08 06:12:50 PM UTC 25 |
| Peak memory | 217384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1460379122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.us bdev_link_suspend.1460379122 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_low_speed_traffic.2867210856 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 5369346966 ps |
| CPU time | 41.2 seconds |
| Started | Feb 08 06:12:32 PM UTC 25 |
| Finished | Feb 08 06:13:15 PM UTC 25 |
| Peak memory | 234452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867210856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 32.usbdev_low_speed_traffic.2867210856 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_max_inter_pkt_delay.1057237875 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 2226585431 ps |
| CPU time | 63.66 seconds |
| Started | Feb 08 06:12:32 PM UTC 25 |
| Finished | Feb 08 06:13:38 PM UTC 25 |
| Peak memory | 227848 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057237875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.1057237875 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_max_length_in_transaction.3368856888 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 300203029 ps |
| CPU time | 1.67 seconds |
| Started | Feb 08 06:12:32 PM UTC 25 |
| Finished | Feb 08 06:12:35 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368856888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 32.usbdev_max_length_in_transaction.3368856888 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_max_length_out_transaction.373797294 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 196176325 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:12:32 PM UTC 25 |
| Finished | Feb 08 06:12:35 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=373797294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 32.usbdev_max_length_out_transaction.373797294 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_min_inter_pkt_delay.3992020406 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 3783506535 ps |
| CPU time | 37.12 seconds |
| Started | Feb 08 06:12:32 PM UTC 25 |
| Finished | Feb 08 06:13:11 PM UTC 25 |
| Peak memory | 227664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992020406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.3992020406 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_min_length_in_transaction.103064078 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 165010488 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:12:32 PM UTC 25 |
| Finished | Feb 08 06:12:35 PM UTC 25 |
| Peak memory | 215156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103064078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 32.usbdev_min_length_in_transaction.103064078 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_min_length_out_transaction.781586167 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 191378319 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:12:34 PM UTC 25 |
| Finished | Feb 08 06:12:37 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=781586167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 32.usbdev_min_length_out_transaction.781586167 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_nak_trans.130692287 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 208969165 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:12:34 PM UTC 25 |
| Finished | Feb 08 06:12:37 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=130692287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev _nak_trans.130692287 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_out_iso.283124891 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 211355227 ps |
| CPU time | 1.12 seconds |
| Started | Feb 08 06:12:34 PM UTC 25 |
| Finished | Feb 08 06:12:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=283124891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_o ut_iso.283124891 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_out_stall.1833784385 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 175960222 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:12:34 PM UTC 25 |
| Finished | Feb 08 06:12:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1833784385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbde v_out_stall.1833784385 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_out_trans_nak.745876760 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 155917154 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 06:12:34 PM UTC 25 |
| Finished | Feb 08 06:12:36 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=745876760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.us bdev_out_trans_nak.745876760 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_pending_in_trans.2286184734 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 194128369 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:12:34 PM UTC 25 |
| Finished | Feb 08 06:12:36 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2286184734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.usbdev_pending_in_trans.2286184734 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_phy_config_pinflip.2649681802 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 234102044 ps |
| CPU time | 1.23 seconds |
| Started | Feb 08 06:12:35 PM UTC 25 |
| Finished | Feb 08 06:12:38 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649681802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 32.usbdev_phy_config_pinflip.2649681802 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_phy_config_usb_ref_disable.333397712 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 164474030 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:12:35 PM UTC 25 |
| Finished | Feb 08 06:12:38 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=333397712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 32.usbdev_phy_config_usb_ref_disable.333397712 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_phy_pins_sense.758151814 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 37545360 ps |
| CPU time | 0.88 seconds |
| Started | Feb 08 06:12:35 PM UTC 25 |
| Finished | Feb 08 06:12:37 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=758151814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.u sbdev_phy_pins_sense.758151814 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_pkt_buffer.201453455 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 13943261743 ps |
| CPU time | 40.12 seconds |
| Started | Feb 08 06:12:36 PM UTC 25 |
| Finished | Feb 08 06:13:18 PM UTC 25 |
| Peak memory | 234420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=201453455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbde v_pkt_buffer.201453455 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_pkt_received.637831469 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 147603168 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 06:12:36 PM UTC 25 |
| Finished | Feb 08 06:12:39 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=637831469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usb dev_pkt_received.637831469 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_pkt_sent.3346220200 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 213332114 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:12:37 PM UTC 25 |
| Finished | Feb 08 06:12:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3346220200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev _pkt_sent.3346220200 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_random_length_in_transaction.763921788 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 168040124 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:12:37 PM UTC 25 |
| Finished | Feb 08 06:12:39 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=763921788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.us bdev_random_length_in_transaction.763921788 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_random_length_out_transaction.1833464742 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 211218388 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:12:37 PM UTC 25 |
| Finished | Feb 08 06:12:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1833464742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 32.usbdev_random_length_out_transaction.1833464742 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_rx_crc_err.2572147102 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 166993097 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 06:12:38 PM UTC 25 |
| Finished | Feb 08 06:12:41 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2572147102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbd ev_rx_crc_err.2572147102 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_rx_full.3797428744 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 273994730 ps |
| CPU time | 1.72 seconds |
| Started | Feb 08 06:12:38 PM UTC 25 |
| Finished | Feb 08 06:12:41 PM UTC 25 |
| Peak memory | 215016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3797428744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_ rx_full.3797428744 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_setup_stage.1084329586 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 155134649 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:12:38 PM UTC 25 |
| Finished | Feb 08 06:12:41 PM UTC 25 |
| Peak memory | 214904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1084329586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usb dev_setup_stage.1084329586 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_setup_trans_ignored.1171178127 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 155307132 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:12:38 PM UTC 25 |
| Finished | Feb 08 06:12:41 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1171178127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 32.usbdev_setup_trans_ignored.1171178127 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_smoke.931524014 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 261378974 ps |
| CPU time | 1.77 seconds |
| Started | Feb 08 06:12:38 PM UTC 25 |
| Finished | Feb 08 06:12:41 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=931524014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smo ke.931524014 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_spurious_pids_ignored.2763792676 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 1697649004 ps |
| CPU time | 44.89 seconds |
| Started | Feb 08 06:12:38 PM UTC 25 |
| Finished | Feb 08 06:13:25 PM UTC 25 |
| Peak memory | 229704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763792676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 32.usbdev_spurious_pids_ignored.2763792676 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_stall_priority_over_nak.1462554033 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 180885006 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:12:38 PM UTC 25 |
| Finished | Feb 08 06:12:41 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1462554033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 32.usbdev_stall_priority_over_nak.1462554033 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_stall_trans.3413109850 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 210312571 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:12:40 PM UTC 25 |
| Finished | Feb 08 06:12:43 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3413109850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usb dev_stall_trans.3413109850 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_stream_len_max.2846367668 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 1255212937 ps |
| CPU time | 4.1 seconds |
| Started | Feb 08 06:12:40 PM UTC 25 |
| Finished | Feb 08 06:12:45 PM UTC 25 |
| Peak memory | 217368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2846367668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32. usbdev_stream_len_max.2846367668 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_streaming_out.1045960817 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 2630791808 ps |
| CPU time | 30.17 seconds |
| Started | Feb 08 06:12:40 PM UTC 25 |
| Finished | Feb 08 06:13:12 PM UTC 25 |
| Peak memory | 227652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1045960817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbde v_streaming_out.1045960817 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_timeout_missing_host_handshake.502167747 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 552160077 ps |
| CPU time | 13.49 seconds |
| Started | Feb 08 06:12:28 PM UTC 25 |
| Finished | Feb 08 06:12:43 PM UTC 25 |
| Peak memory | 217276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502167747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing_host_handshake.502167747 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_tx_rx_disruption.3589347904 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 458176724 ps |
| CPU time | 1.81 seconds |
| Started | Feb 08 06:12:40 PM UTC 25 |
| Finished | Feb 08 06:12:43 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 589347904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_tx_rx_disruption.3589347904 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/32.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/320.usbdev_tx_rx_disruption.661694096 |
| Short name | T3479 |
| Test name | |
| Test status | |
| Simulation time | 612851028 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:19:33 PM UTC 25 |
| Finished | Feb 08 06:19:59 PM UTC 25 |
| Peak memory | 214828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6 61694096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 320.usbdev_tx_rx_disruption.661694096 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/320.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/321.usbdev_tx_rx_disruption.3021030270 |
| Short name | T3421 |
| Test name | |
| Test status | |
| Simulation time | 522350797 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:19:34 PM UTC 25 |
| Finished | Feb 08 06:19:39 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 021030270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 321.usbdev_tx_rx_disruption.3021030270 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/321.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/322.usbdev_tx_rx_disruption.3166364903 |
| Short name | T3422 |
| Test name | |
| Test status | |
| Simulation time | 540044573 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:19:34 PM UTC 25 |
| Finished | Feb 08 06:19:40 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 166364903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 322.usbdev_tx_rx_disruption.3166364903 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/322.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/323.usbdev_tx_rx_disruption.1977999386 |
| Short name | T3414 |
| Test name | |
| Test status | |
| Simulation time | 635450869 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:19:35 PM UTC 25 |
| Finished | Feb 08 06:19:39 PM UTC 25 |
| Peak memory | 214692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 977999386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 323.usbdev_tx_rx_disruption.1977999386 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/323.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/324.usbdev_tx_rx_disruption.451688910 |
| Short name | T3409 |
| Test name | |
| Test status | |
| Simulation time | 623654680 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:19:35 PM UTC 25 |
| Finished | Feb 08 06:19:39 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 51688910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 324.usbdev_tx_rx_disruption.451688910 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/324.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/325.usbdev_tx_rx_disruption.3001594982 |
| Short name | T3408 |
| Test name | |
| Test status | |
| Simulation time | 435736663 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 06:19:35 PM UTC 25 |
| Finished | Feb 08 06:19:38 PM UTC 25 |
| Peak memory | 214612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 001594982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 325.usbdev_tx_rx_disruption.3001594982 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/325.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/326.usbdev_tx_rx_disruption.4191473042 |
| Short name | T3412 |
| Test name | |
| Test status | |
| Simulation time | 500772887 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:19:35 PM UTC 25 |
| Finished | Feb 08 06:19:39 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 191473042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 326.usbdev_tx_rx_disruption.4191473042 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/326.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/327.usbdev_tx_rx_disruption.126671544 |
| Short name | T3413 |
| Test name | |
| Test status | |
| Simulation time | 508968781 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:19:35 PM UTC 25 |
| Finished | Feb 08 06:19:39 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 26671544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 327.usbdev_tx_rx_disruption.126671544 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/327.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/328.usbdev_tx_rx_disruption.4030162305 |
| Short name | T3411 |
| Test name | |
| Test status | |
| Simulation time | 532895681 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:19:35 PM UTC 25 |
| Finished | Feb 08 06:19:39 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 030162305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 328.usbdev_tx_rx_disruption.4030162305 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/328.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/329.usbdev_tx_rx_disruption.1084226079 |
| Short name | T3410 |
| Test name | |
| Test status | |
| Simulation time | 485034693 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:19:35 PM UTC 25 |
| Finished | Feb 08 06:19:39 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 084226079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 329.usbdev_tx_rx_disruption.1084226079 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/329.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_alert_test.1377087170 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 37146244 ps |
| CPU time | 0.82 seconds |
| Started | Feb 08 06:12:56 PM UTC 25 |
| Finished | Feb 08 06:12:58 PM UTC 25 |
| Peak memory | 215152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377087170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 33.usbdev_alert_test.1377087170 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_aon_wake_disconnect.2735595569 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 10826772301 ps |
| CPU time | 19.21 seconds |
| Started | Feb 08 06:12:40 PM UTC 25 |
| Finished | Feb 08 06:13:01 PM UTC 25 |
| Peak memory | 217572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735595569 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.2735595569 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_aon_wake_reset.3207814136 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 18996047653 ps |
| CPU time | 29.05 seconds |
| Started | Feb 08 06:12:41 PM UTC 25 |
| Finished | Feb 08 06:13:12 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207814136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.3207814136 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_aon_wake_resume.1591796263 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 29399674622 ps |
| CPU time | 42.62 seconds |
| Started | Feb 08 06:12:41 PM UTC 25 |
| Finished | Feb 08 06:13:26 PM UTC 25 |
| Peak memory | 217576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591796263 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.1591796263 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_av_buffer.1226736824 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 207370492 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:12:41 PM UTC 25 |
| Finished | Feb 08 06:12:44 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1226736824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbde v_av_buffer.1226736824 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_bitstuff_err.1708393681 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 188410192 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:12:41 PM UTC 25 |
| Finished | Feb 08 06:12:44 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1708393681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.us bdev_bitstuff_err.1708393681 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_data_toggle_clear.897208934 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 375050103 ps |
| CPU time | 1.8 seconds |
| Started | Feb 08 06:12:43 PM UTC 25 |
| Finished | Feb 08 06:12:46 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=897208934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.usbdev_data_toggle_clear.897208934 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_data_toggle_restore.1876194892 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 654777194 ps |
| CPU time | 2.16 seconds |
| Started | Feb 08 06:12:43 PM UTC 25 |
| Finished | Feb 08 06:12:46 PM UTC 25 |
| Peak memory | 217172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876194892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.1876194892 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_device_address.3179295844 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 24835369588 ps |
| CPU time | 51.84 seconds |
| Started | Feb 08 06:12:43 PM UTC 25 |
| Finished | Feb 08 06:13:37 PM UTC 25 |
| Peak memory | 217540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3179295844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33. usbdev_device_address.3179295844 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_device_timeout.1371814840 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 612448318 ps |
| CPU time | 12.32 seconds |
| Started | Feb 08 06:12:43 PM UTC 25 |
| Finished | Feb 08 06:12:57 PM UTC 25 |
| Peak memory | 217584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371814840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.1371814840 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_disable_endpoint.3841026373 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 1111124099 ps |
| CPU time | 3.17 seconds |
| Started | Feb 08 06:12:45 PM UTC 25 |
| Finished | Feb 08 06:12:49 PM UTC 25 |
| Peak memory | 217088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3841026373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.usbdev_disable_endpoint.3841026373 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_disconnected.2959969328 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 153365811 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 06:12:45 PM UTC 25 |
| Finished | Feb 08 06:12:47 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2959969328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.us bdev_disconnected.2959969328 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_enable.2230735257 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 49654106 ps |
| CPU time | 0.89 seconds |
| Started | Feb 08 06:12:45 PM UTC 25 |
| Finished | Feb 08 06:12:47 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2230735257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_e nable.2230735257 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_endpoint_access.1053925694 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 747338711 ps |
| CPU time | 2.34 seconds |
| Started | Feb 08 06:12:45 PM UTC 25 |
| Finished | Feb 08 06:12:49 PM UTC 25 |
| Peak memory | 217272 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1053925694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33 .usbdev_endpoint_access.1053925694 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_fifo_rst.2968743195 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 245443831 ps |
| CPU time | 2.98 seconds |
| Started | Feb 08 06:12:45 PM UTC 25 |
| Finished | Feb 08 06:12:49 PM UTC 25 |
| Peak memory | 217472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2968743195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev _fifo_rst.2968743195 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_in_iso.991105036 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 182659644 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 06:12:45 PM UTC 25 |
| Finished | Feb 08 06:12:47 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991105036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 33.usbdev_in_iso.991105036 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_in_stall.3674494923 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 159995574 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:12:45 PM UTC 25 |
| Finished | Feb 08 06:12:48 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3674494923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev _in_stall.3674494923 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_in_trans.296885110 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 262517641 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:12:45 PM UTC 25 |
| Finished | Feb 08 06:12:48 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=296885110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_ in_trans.296885110 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_invalid_sync.111599617 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 4183290588 ps |
| CPU time | 126.57 seconds |
| Started | Feb 08 06:12:45 PM UTC 25 |
| Finished | Feb 08 06:14:54 PM UTC 25 |
| Peak memory | 229968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111599617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.111599617 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_iso_retraction.3094060437 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 3963347225 ps |
| CPU time | 30.05 seconds |
| Started | Feb 08 06:12:45 PM UTC 25 |
| Finished | Feb 08 06:13:17 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094060437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 33.usbdev_iso_retraction.3094060437 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_link_in_err.3682611100 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 195804598 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:12:46 PM UTC 25 |
| Finished | Feb 08 06:12:49 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3682611100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usb dev_link_in_err.3682611100 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_link_resume.402908806 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 12557132014 ps |
| CPU time | 18.95 seconds |
| Started | Feb 08 06:12:46 PM UTC 25 |
| Finished | Feb 08 06:13:07 PM UTC 25 |
| Peak memory | 217576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=402908806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbd ev_link_resume.402908806 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_link_suspend.4230657360 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 6354164422 ps |
| CPU time | 8.7 seconds |
| Started | Feb 08 06:12:46 PM UTC 25 |
| Finished | Feb 08 06:12:56 PM UTC 25 |
| Peak memory | 227592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4230657360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.us bdev_link_suspend.4230657360 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_low_speed_traffic.3041324041 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 2652350770 ps |
| CPU time | 28.71 seconds |
| Started | Feb 08 06:12:47 PM UTC 25 |
| Finished | Feb 08 06:13:17 PM UTC 25 |
| Peak memory | 229772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041324041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 33.usbdev_low_speed_traffic.3041324041 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_max_inter_pkt_delay.2791480942 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 2792502806 ps |
| CPU time | 88.13 seconds |
| Started | Feb 08 06:12:48 PM UTC 25 |
| Finished | Feb 08 06:14:18 PM UTC 25 |
| Peak memory | 227900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791480942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.2791480942 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_max_length_in_transaction.400459377 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 237032307 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:12:48 PM UTC 25 |
| Finished | Feb 08 06:12:51 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400459377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 33.usbdev_max_length_in_transaction.400459377 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_max_length_out_transaction.705372981 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 206774610 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:12:48 PM UTC 25 |
| Finished | Feb 08 06:12:51 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=705372981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 33.usbdev_max_length_out_transaction.705372981 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_min_inter_pkt_delay.3027708796 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 1930554231 ps |
| CPU time | 15.8 seconds |
| Started | Feb 08 06:12:48 PM UTC 25 |
| Finished | Feb 08 06:13:05 PM UTC 25 |
| Peak memory | 229708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027708796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.3027708796 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_min_length_in_transaction.783907657 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 176451108 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 06:12:48 PM UTC 25 |
| Finished | Feb 08 06:12:51 PM UTC 25 |
| Peak memory | 215156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783907657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 33.usbdev_min_length_in_transaction.783907657 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_min_length_out_transaction.2070271307 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 199597564 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 06:12:48 PM UTC 25 |
| Finished | Feb 08 06:12:51 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2070271307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2070271307 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_nak_trans.1555935921 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 205807741 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:12:48 PM UTC 25 |
| Finished | Feb 08 06:12:51 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1555935921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbde v_nak_trans.1555935921 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_out_iso.1976825262 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 178256471 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:12:48 PM UTC 25 |
| Finished | Feb 08 06:12:51 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1976825262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_ out_iso.1976825262 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_out_stall.3692898139 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 195236367 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:12:50 PM UTC 25 |
| Finished | Feb 08 06:12:53 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3692898139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbde v_out_stall.3692898139 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_out_trans_nak.2982873739 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 189973498 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:12:50 PM UTC 25 |
| Finished | Feb 08 06:12:53 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2982873739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.u sbdev_out_trans_nak.2982873739 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_pending_in_trans.3542978147 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 209564247 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:12:50 PM UTC 25 |
| Finished | Feb 08 06:12:53 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3542978147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.usbdev_pending_in_trans.3542978147 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_phy_config_pinflip.622877540 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 220029874 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 06:12:50 PM UTC 25 |
| Finished | Feb 08 06:12:53 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=622877540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 33.usbdev_phy_config_pinflip.622877540 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_phy_config_usb_ref_disable.1811221957 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 145638929 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:12:50 PM UTC 25 |
| Finished | Feb 08 06:12:53 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1811221957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.1811221957 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_phy_pins_sense.3287138177 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 37543829 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:12:50 PM UTC 25 |
| Finished | Feb 08 06:12:53 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3287138177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33. usbdev_phy_pins_sense.3287138177 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_pkt_buffer.1243923417 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 11399551519 ps |
| CPU time | 38.79 seconds |
| Started | Feb 08 06:12:50 PM UTC 25 |
| Finished | Feb 08 06:13:31 PM UTC 25 |
| Peak memory | 227756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1243923417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbd ev_pkt_buffer.1243923417 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_pkt_received.2556792036 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 184118508 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:12:52 PM UTC 25 |
| Finished | Feb 08 06:12:54 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2556792036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.us bdev_pkt_received.2556792036 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_pkt_sent.2132039192 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 165327877 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:12:52 PM UTC 25 |
| Finished | Feb 08 06:12:54 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2132039192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev _pkt_sent.2132039192 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_random_length_in_transaction.1098397354 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 185298276 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:12:52 PM UTC 25 |
| Finished | Feb 08 06:12:54 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1098397354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.u sbdev_random_length_in_transaction.1098397354 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_random_length_out_transaction.179898287 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 195616008 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:12:52 PM UTC 25 |
| Finished | Feb 08 06:12:55 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=179898287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 33.usbdev_random_length_out_transaction.179898287 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_rx_crc_err.737383133 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 154013986 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:12:52 PM UTC 25 |
| Finished | Feb 08 06:12:54 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=737383133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbde v_rx_crc_err.737383133 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_rx_full.1683029858 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 257720636 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 06:12:52 PM UTC 25 |
| Finished | Feb 08 06:12:54 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1683029858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_ rx_full.1683029858 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_setup_stage.39803989 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 184971006 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:12:52 PM UTC 25 |
| Finished | Feb 08 06:12:54 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=39803989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbde v_setup_stage.39803989 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_setup_trans_ignored.2441090534 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 146723018 ps |
| CPU time | 0.99 seconds |
| Started | Feb 08 06:12:53 PM UTC 25 |
| Finished | Feb 08 06:12:55 PM UTC 25 |
| Peak memory | 215064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2441090534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 33.usbdev_setup_trans_ignored.2441090534 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_smoke.2205626040 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 252512504 ps |
| CPU time | 1.88 seconds |
| Started | Feb 08 06:12:53 PM UTC 25 |
| Finished | Feb 08 06:12:56 PM UTC 25 |
| Peak memory | 215064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2205626040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_sm oke.2205626040 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_spurious_pids_ignored.3496050740 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 3055351000 ps |
| CPU time | 29.97 seconds |
| Started | Feb 08 06:12:54 PM UTC 25 |
| Finished | Feb 08 06:13:26 PM UTC 25 |
| Peak memory | 229940 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496050740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 33.usbdev_spurious_pids_ignored.3496050740 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_stall_priority_over_nak.3836668330 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 155760876 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:12:55 PM UTC 25 |
| Finished | Feb 08 06:12:57 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3836668330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 33.usbdev_stall_priority_over_nak.3836668330 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_stall_trans.4130947271 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 195924273 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:12:55 PM UTC 25 |
| Finished | Feb 08 06:12:57 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4130947271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usb dev_stall_trans.4130947271 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_stream_len_max.1933417974 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 579875899 ps |
| CPU time | 2.78 seconds |
| Started | Feb 08 06:12:55 PM UTC 25 |
| Finished | Feb 08 06:12:59 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1933417974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33. usbdev_stream_len_max.1933417974 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_streaming_out.241987157 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 1994368419 ps |
| CPU time | 54.49 seconds |
| Started | Feb 08 06:12:55 PM UTC 25 |
| Finished | Feb 08 06:13:51 PM UTC 25 |
| Peak memory | 227856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=241987157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev _streaming_out.241987157 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_timeout_missing_host_handshake.3750671199 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 1682294580 ps |
| CPU time | 37.85 seconds |
| Started | Feb 08 06:12:43 PM UTC 25 |
| Finished | Feb 08 06:13:23 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750671199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing_host_handshake.3750671199 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_tx_rx_disruption.2611398694 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 508501654 ps |
| CPU time | 1.79 seconds |
| Started | Feb 08 06:12:55 PM UTC 25 |
| Finished | Feb 08 06:12:58 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 611398694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_tx_rx_disruption.2611398694 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/33.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/330.usbdev_tx_rx_disruption.1061487437 |
| Short name | T3480 |
| Test name | |
| Test status | |
| Simulation time | 658789966 ps |
| CPU time | 1.67 seconds |
| Started | Feb 08 06:19:39 PM UTC 25 |
| Finished | Feb 08 06:19:59 PM UTC 25 |
| Peak memory | 214728 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 061487437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 330.usbdev_tx_rx_disruption.1061487437 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/330.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/331.usbdev_tx_rx_disruption.1959594884 |
| Short name | T3475 |
| Test name | |
| Test status | |
| Simulation time | 465512150 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:19:39 PM UTC 25 |
| Finished | Feb 08 06:19:59 PM UTC 25 |
| Peak memory | 214384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 959594884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 331.usbdev_tx_rx_disruption.1959594884 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/331.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/332.usbdev_tx_rx_disruption.1586399687 |
| Short name | T3515 |
| Test name | |
| Test status | |
| Simulation time | 454094382 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:19:39 PM UTC 25 |
| Finished | Feb 08 06:20:10 PM UTC 25 |
| Peak memory | 216704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 586399687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 332.usbdev_tx_rx_disruption.1586399687 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/332.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/333.usbdev_tx_rx_disruption.1535076000 |
| Short name | T3514 |
| Test name | |
| Test status | |
| Simulation time | 526450359 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:19:39 PM UTC 25 |
| Finished | Feb 08 06:20:10 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 535076000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 333.usbdev_tx_rx_disruption.1535076000 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/333.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/334.usbdev_tx_rx_disruption.139221970 |
| Short name | T3481 |
| Test name | |
| Test status | |
| Simulation time | 646741403 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:19:40 PM UTC 25 |
| Finished | Feb 08 06:19:59 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 39221970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 334.usbdev_tx_rx_disruption.139221970 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/334.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/335.usbdev_tx_rx_disruption.3395643424 |
| Short name | T3517 |
| Test name | |
| Test status | |
| Simulation time | 532425677 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:19:40 PM UTC 25 |
| Finished | Feb 08 06:20:10 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 395643424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 335.usbdev_tx_rx_disruption.3395643424 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/335.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/336.usbdev_tx_rx_disruption.1566709099 |
| Short name | T3486 |
| Test name | |
| Test status | |
| Simulation time | 537911810 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:19:40 PM UTC 25 |
| Finished | Feb 08 06:20:03 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 566709099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 336.usbdev_tx_rx_disruption.1566709099 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/336.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/337.usbdev_tx_rx_disruption.2690514977 |
| Short name | T3483 |
| Test name | |
| Test status | |
| Simulation time | 503259191 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:19:40 PM UTC 25 |
| Finished | Feb 08 06:20:03 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 690514977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 337.usbdev_tx_rx_disruption.2690514977 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/337.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/338.usbdev_tx_rx_disruption.3573589074 |
| Short name | T3441 |
| Test name | |
| Test status | |
| Simulation time | 609907529 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:19:41 PM UTC 25 |
| Finished | Feb 08 06:19:44 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 573589074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 338.usbdev_tx_rx_disruption.3573589074 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/338.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/339.usbdev_tx_rx_disruption.498667299 |
| Short name | T3440 |
| Test name | |
| Test status | |
| Simulation time | 603567288 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:19:41 PM UTC 25 |
| Finished | Feb 08 06:19:44 PM UTC 25 |
| Peak memory | 215656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 98667299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 339.usbdev_tx_rx_disruption.498667299 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/339.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_alert_test.2891217953 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 44425920 ps |
| CPU time | 0.99 seconds |
| Started | Feb 08 06:13:15 PM UTC 25 |
| Finished | Feb 08 06:13:17 PM UTC 25 |
| Peak memory | 214736 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891217953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 34.usbdev_alert_test.2891217953 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_aon_wake_disconnect.2830251575 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 5684516043 ps |
| CPU time | 7.82 seconds |
| Started | Feb 08 06:12:56 PM UTC 25 |
| Finished | Feb 08 06:13:05 PM UTC 25 |
| Peak memory | 227572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830251575 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.2830251575 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_aon_wake_reset.800676169 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 15060175879 ps |
| CPU time | 20.36 seconds |
| Started | Feb 08 06:12:56 PM UTC 25 |
| Finished | Feb 08 06:13:18 PM UTC 25 |
| Peak memory | 227784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800676169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TE ST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.800676169 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_aon_wake_resume.190595240 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 29203272002 ps |
| CPU time | 43.72 seconds |
| Started | Feb 08 06:12:56 PM UTC 25 |
| Finished | Feb 08 06:13:41 PM UTC 25 |
| Peak memory | 217376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190595240 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.190595240 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_av_buffer.117287410 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 167769876 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:12:56 PM UTC 25 |
| Finished | Feb 08 06:12:59 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=117287410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev _av_buffer.117287410 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_bitstuff_err.4152117247 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 143566127 ps |
| CPU time | 0.96 seconds |
| Started | Feb 08 06:12:56 PM UTC 25 |
| Finished | Feb 08 06:12:59 PM UTC 25 |
| Peak memory | 216944 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4152117247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.us bdev_bitstuff_err.4152117247 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_data_toggle_clear.3317902572 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 385343912 ps |
| CPU time | 2.16 seconds |
| Started | Feb 08 06:12:56 PM UTC 25 |
| Finished | Feb 08 06:13:00 PM UTC 25 |
| Peak memory | 216676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3317902572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.3317902572 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_data_toggle_restore.555092149 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 843983442 ps |
| CPU time | 2.65 seconds |
| Started | Feb 08 06:12:58 PM UTC 25 |
| Finished | Feb 08 06:13:02 PM UTC 25 |
| Peak memory | 217308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555092149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_t oggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.555092149 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_device_address.2856497506 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 40071947772 ps |
| CPU time | 86.57 seconds |
| Started | Feb 08 06:12:58 PM UTC 25 |
| Finished | Feb 08 06:14:26 PM UTC 25 |
| Peak memory | 217408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2856497506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34. usbdev_device_address.2856497506 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_device_timeout.2215751509 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 861726311 ps |
| CPU time | 20.16 seconds |
| Started | Feb 08 06:12:58 PM UTC 25 |
| Finished | Feb 08 06:13:19 PM UTC 25 |
| Peak memory | 217400 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215751509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.2215751509 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_disable_endpoint.2466904355 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 451109291 ps |
| CPU time | 2.55 seconds |
| Started | Feb 08 06:12:58 PM UTC 25 |
| Finished | Feb 08 06:13:02 PM UTC 25 |
| Peak memory | 217088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2466904355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.usbdev_disable_endpoint.2466904355 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_disconnected.3673925305 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 173404163 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:12:58 PM UTC 25 |
| Finished | Feb 08 06:13:01 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3673925305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.us bdev_disconnected.3673925305 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_enable.995287112 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 96820481 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 06:12:58 PM UTC 25 |
| Finished | Feb 08 06:13:01 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=995287112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_en able.995287112 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_endpoint_access.466977810 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 863835584 ps |
| CPU time | 2.64 seconds |
| Started | Feb 08 06:12:59 PM UTC 25 |
| Finished | Feb 08 06:13:03 PM UTC 25 |
| Peak memory | 217428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=466977810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34. usbdev_endpoint_access.466977810 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_fifo_rst.120158122 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 162078607 ps |
| CPU time | 2.42 seconds |
| Started | Feb 08 06:13:00 PM UTC 25 |
| Finished | Feb 08 06:13:03 PM UTC 25 |
| Peak memory | 217544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=120158122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_ fifo_rst.120158122 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_in_iso.273446819 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 244795104 ps |
| CPU time | 1.79 seconds |
| Started | Feb 08 06:13:00 PM UTC 25 |
| Finished | Feb 08 06:13:03 PM UTC 25 |
| Peak memory | 227816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273446819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 34.usbdev_in_iso.273446819 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_in_stall.779330989 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 164975509 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:13:01 PM UTC 25 |
| Finished | Feb 08 06:13:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=779330989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_ in_stall.779330989 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_in_trans.1116411843 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 197817913 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 06:13:01 PM UTC 25 |
| Finished | Feb 08 06:13:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1116411843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev _in_trans.1116411843 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_invalid_sync.3416958412 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 3995821823 ps |
| CPU time | 45.98 seconds |
| Started | Feb 08 06:13:00 PM UTC 25 |
| Finished | Feb 08 06:13:47 PM UTC 25 |
| Peak memory | 227688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416958412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.3416958412 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_iso_retraction.3081303432 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 4036085591 ps |
| CPU time | 30.21 seconds |
| Started | Feb 08 06:13:02 PM UTC 25 |
| Finished | Feb 08 06:13:34 PM UTC 25 |
| Peak memory | 217164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081303432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 34.usbdev_iso_retraction.3081303432 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_link_in_err.773656351 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 192764773 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 06:13:02 PM UTC 25 |
| Finished | Feb 08 06:13:04 PM UTC 25 |
| Peak memory | 214824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=773656351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbd ev_link_in_err.773656351 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_link_resume.257747727 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 33069576135 ps |
| CPU time | 64.86 seconds |
| Started | Feb 08 06:13:02 PM UTC 25 |
| Finished | Feb 08 06:14:09 PM UTC 25 |
| Peak memory | 217384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=257747727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbd ev_link_resume.257747727 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_link_suspend.2526780374 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 9246184836 ps |
| CPU time | 17.12 seconds |
| Started | Feb 08 06:13:02 PM UTC 25 |
| Finished | Feb 08 06:13:21 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2526780374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.us bdev_link_suspend.2526780374 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_low_speed_traffic.4116342964 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 4094318379 ps |
| CPU time | 121.1 seconds |
| Started | Feb 08 06:13:03 PM UTC 25 |
| Finished | Feb 08 06:15:07 PM UTC 25 |
| Peak memory | 227816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116342964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 34.usbdev_low_speed_traffic.4116342964 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_max_inter_pkt_delay.778008101 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 2894034391 ps |
| CPU time | 86.25 seconds |
| Started | Feb 08 06:13:03 PM UTC 25 |
| Finished | Feb 08 06:14:32 PM UTC 25 |
| Peak memory | 227708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778008101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.778008101 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_max_length_in_transaction.2557479288 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 261636333 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:13:03 PM UTC 25 |
| Finished | Feb 08 06:13:06 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557479288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 34.usbdev_max_length_in_transaction.2557479288 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_max_length_out_transaction.3808275885 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 183623109 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:13:05 PM UTC 25 |
| Finished | Feb 08 06:13:07 PM UTC 25 |
| Peak memory | 214888 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3808275885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3808275885 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_min_inter_pkt_delay.2150023555 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 3837977030 ps |
| CPU time | 108.11 seconds |
| Started | Feb 08 06:13:05 PM UTC 25 |
| Finished | Feb 08 06:14:55 PM UTC 25 |
| Peak memory | 229492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150023555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.2150023555 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_min_length_in_transaction.971816926 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 159802752 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:13:05 PM UTC 25 |
| Finished | Feb 08 06:13:07 PM UTC 25 |
| Peak memory | 215156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971816926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 34.usbdev_min_length_in_transaction.971816926 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_min_length_out_transaction.415280700 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 145131262 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:13:05 PM UTC 25 |
| Finished | Feb 08 06:13:07 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=415280700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 34.usbdev_min_length_out_transaction.415280700 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_nak_trans.454350959 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 247146037 ps |
| CPU time | 1.74 seconds |
| Started | Feb 08 06:13:05 PM UTC 25 |
| Finished | Feb 08 06:13:08 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=454350959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev _nak_trans.454350959 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_out_iso.1171846629 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 217579961 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:13:06 PM UTC 25 |
| Finished | Feb 08 06:13:08 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1171846629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_ out_iso.1171846629 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_out_stall.457835489 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 200665454 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:13:06 PM UTC 25 |
| Finished | Feb 08 06:13:09 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=457835489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev _out_stall.457835489 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_out_trans_nak.3210388102 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 160765912 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:13:08 PM UTC 25 |
| Finished | Feb 08 06:13:10 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3210388102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.u sbdev_out_trans_nak.3210388102 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_pending_in_trans.3606482914 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 153938026 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:13:08 PM UTC 25 |
| Finished | Feb 08 06:13:10 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3606482914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.usbdev_pending_in_trans.3606482914 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_phy_config_pinflip.413994974 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 206486628 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:13:08 PM UTC 25 |
| Finished | Feb 08 06:13:10 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=413994974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 34.usbdev_phy_config_pinflip.413994974 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_phy_config_usb_ref_disable.3052306073 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 147412360 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:13:09 PM UTC 25 |
| Finished | Feb 08 06:13:11 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3052306073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.3052306073 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_phy_pins_sense.4147496527 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 58280580 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 06:13:09 PM UTC 25 |
| Finished | Feb 08 06:13:11 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4147496527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34. usbdev_phy_pins_sense.4147496527 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_pkt_buffer.1937525479 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 16113696894 ps |
| CPU time | 41.97 seconds |
| Started | Feb 08 06:13:09 PM UTC 25 |
| Finished | Feb 08 06:13:53 PM UTC 25 |
| Peak memory | 227672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1937525479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbd ev_pkt_buffer.1937525479 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_pkt_received.2588661752 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 177686205 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:13:09 PM UTC 25 |
| Finished | Feb 08 06:13:12 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2588661752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.us bdev_pkt_received.2588661752 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_pkt_sent.58280020 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 199408508 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:13:09 PM UTC 25 |
| Finished | Feb 08 06:13:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=58280020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_p kt_sent.58280020 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_random_length_in_transaction.3202095917 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 179787003 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:13:10 PM UTC 25 |
| Finished | Feb 08 06:13:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3202095917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.u sbdev_random_length_in_transaction.3202095917 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_random_length_out_transaction.2450787692 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 188874332 ps |
| CPU time | 1.71 seconds |
| Started | Feb 08 06:13:10 PM UTC 25 |
| Finished | Feb 08 06:13:13 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2450787692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 34.usbdev_random_length_out_transaction.2450787692 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_rx_crc_err.3856514046 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 159978582 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:13:12 PM UTC 25 |
| Finished | Feb 08 06:13:14 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3856514046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbd ev_rx_crc_err.3856514046 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_rx_full.2324664336 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 429399714 ps |
| CPU time | 2.27 seconds |
| Started | Feb 08 06:13:12 PM UTC 25 |
| Finished | Feb 08 06:13:15 PM UTC 25 |
| Peak memory | 217112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2324664336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_ rx_full.2324664336 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_setup_stage.1774460299 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 161625090 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:13:12 PM UTC 25 |
| Finished | Feb 08 06:13:14 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1774460299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usb dev_setup_stage.1774460299 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_setup_trans_ignored.3853868949 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 148969270 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:13:12 PM UTC 25 |
| Finished | Feb 08 06:13:14 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3853868949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 34.usbdev_setup_trans_ignored.3853868949 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_smoke.1194790610 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 238141297 ps |
| CPU time | 1.76 seconds |
| Started | Feb 08 06:13:12 PM UTC 25 |
| Finished | Feb 08 06:13:15 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1194790610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_sm oke.1194790610 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_spurious_pids_ignored.1009073831 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 2904275616 ps |
| CPU time | 23.41 seconds |
| Started | Feb 08 06:13:13 PM UTC 25 |
| Finished | Feb 08 06:13:38 PM UTC 25 |
| Peak memory | 229596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009073831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 34.usbdev_spurious_pids_ignored.1009073831 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_stall_priority_over_nak.2892315673 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 190672558 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:13:14 PM UTC 25 |
| Finished | Feb 08 06:13:16 PM UTC 25 |
| Peak memory | 214888 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2892315673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 34.usbdev_stall_priority_over_nak.2892315673 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_stall_trans.2018669625 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 244892105 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 06:13:14 PM UTC 25 |
| Finished | Feb 08 06:13:16 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2018669625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usb dev_stall_trans.2018669625 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_stream_len_max.2411555806 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 1023979822 ps |
| CPU time | 3.25 seconds |
| Started | Feb 08 06:13:14 PM UTC 25 |
| Finished | Feb 08 06:13:18 PM UTC 25 |
| Peak memory | 217432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2411555806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34. usbdev_stream_len_max.2411555806 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_streaming_out.1499169253 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 2936285119 ps |
| CPU time | 22.42 seconds |
| Started | Feb 08 06:13:14 PM UTC 25 |
| Finished | Feb 08 06:13:37 PM UTC 25 |
| Peak memory | 227652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1499169253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbde v_streaming_out.1499169253 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_timeout_missing_host_handshake.550275713 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 1100154900 ps |
| CPU time | 25.24 seconds |
| Started | Feb 08 06:12:58 PM UTC 25 |
| Finished | Feb 08 06:13:25 PM UTC 25 |
| Peak memory | 217484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550275713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_host_handshake.550275713 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_tx_rx_disruption.232644081 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 565394531 ps |
| CPU time | 2.67 seconds |
| Started | Feb 08 06:13:14 PM UTC 25 |
| Finished | Feb 08 06:13:18 PM UTC 25 |
| Peak memory | 217188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 32644081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_tx_rx_disruption.232644081 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/34.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/340.usbdev_tx_rx_disruption.1177271213 |
| Short name | T3437 |
| Test name | |
| Test status | |
| Simulation time | 609198868 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:19:41 PM UTC 25 |
| Finished | Feb 08 06:19:44 PM UTC 25 |
| Peak memory | 216456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 177271213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 340.usbdev_tx_rx_disruption.1177271213 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/340.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/341.usbdev_tx_rx_disruption.2977804133 |
| Short name | T3436 |
| Test name | |
| Test status | |
| Simulation time | 465207126 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:19:41 PM UTC 25 |
| Finished | Feb 08 06:19:44 PM UTC 25 |
| Peak memory | 215632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 977804133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 341.usbdev_tx_rx_disruption.2977804133 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/341.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/342.usbdev_tx_rx_disruption.190298548 |
| Short name | T3439 |
| Test name | |
| Test status | |
| Simulation time | 484438135 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:19:41 PM UTC 25 |
| Finished | Feb 08 06:19:44 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 90298548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 342.usbdev_tx_rx_disruption.190298548 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/342.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/343.usbdev_tx_rx_disruption.1315526189 |
| Short name | T3442 |
| Test name | |
| Test status | |
| Simulation time | 498182926 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:19:41 PM UTC 25 |
| Finished | Feb 08 06:19:44 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 315526189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 343.usbdev_tx_rx_disruption.1315526189 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/343.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/344.usbdev_tx_rx_disruption.1293896760 |
| Short name | T3438 |
| Test name | |
| Test status | |
| Simulation time | 498209618 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:19:41 PM UTC 25 |
| Finished | Feb 08 06:19:44 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 293896760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 344.usbdev_tx_rx_disruption.1293896760 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/344.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/346.usbdev_tx_rx_disruption.809144832 |
| Short name | T3469 |
| Test name | |
| Test status | |
| Simulation time | 518653405 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:19:43 PM UTC 25 |
| Finished | Feb 08 06:19:58 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 09144832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 346.usbdev_tx_rx_disruption.809144832 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/346.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/347.usbdev_tx_rx_disruption.2544581665 |
| Short name | T3477 |
| Test name | |
| Test status | |
| Simulation time | 473868745 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:19:43 PM UTC 25 |
| Finished | Feb 08 06:19:59 PM UTC 25 |
| Peak memory | 217092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 544581665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 347.usbdev_tx_rx_disruption.2544581665 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/347.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/348.usbdev_tx_rx_disruption.1232721435 |
| Short name | T3476 |
| Test name | |
| Test status | |
| Simulation time | 474042370 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:19:43 PM UTC 25 |
| Finished | Feb 08 06:19:59 PM UTC 25 |
| Peak memory | 216892 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 232721435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 348.usbdev_tx_rx_disruption.1232721435 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/348.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/349.usbdev_tx_rx_disruption.545380069 |
| Short name | T3490 |
| Test name | |
| Test status | |
| Simulation time | 502584575 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:19:43 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 214996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 45380069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 349.usbdev_tx_rx_disruption.545380069 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/349.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_alert_test.2793777 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 70312062 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 06:13:33 PM UTC 25 |
| Finished | Feb 08 06:13:35 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 35.usbdev_alert_test.2793777 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_aon_wake_disconnect.2727615431 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 6502772970 ps |
| CPU time | 11.31 seconds |
| Started | Feb 08 06:13:15 PM UTC 25 |
| Finished | Feb 08 06:13:28 PM UTC 25 |
| Peak memory | 227304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727615431 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.2727615431 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_aon_wake_reset.837621863 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 20120124018 ps |
| CPU time | 25.63 seconds |
| Started | Feb 08 06:13:15 PM UTC 25 |
| Finished | Feb 08 06:13:42 PM UTC 25 |
| Peak memory | 217380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837621863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TE ST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.837621863 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_aon_wake_resume.1460413616 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 23649959922 ps |
| CPU time | 40.16 seconds |
| Started | Feb 08 06:13:17 PM UTC 25 |
| Finished | Feb 08 06:13:59 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460413616 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.1460413616 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_av_buffer.93535362 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 155616861 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:13:17 PM UTC 25 |
| Finished | Feb 08 06:13:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=93535362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_ av_buffer.93535362 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_bitstuff_err.2067545516 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 166509204 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:13:17 PM UTC 25 |
| Finished | Feb 08 06:13:20 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2067545516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.us bdev_bitstuff_err.2067545516 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_data_toggle_clear.2109266366 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 279272401 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:13:17 PM UTC 25 |
| Finished | Feb 08 06:13:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2109266366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.2109266366 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_data_toggle_restore.2009412294 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 586455197 ps |
| CPU time | 3.44 seconds |
| Started | Feb 08 06:13:17 PM UTC 25 |
| Finished | Feb 08 06:13:22 PM UTC 25 |
| Peak memory | 217108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009412294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.2009412294 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_device_address.597010870 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 32956377362 ps |
| CPU time | 58.12 seconds |
| Started | Feb 08 06:13:17 PM UTC 25 |
| Finished | Feb 08 06:14:17 PM UTC 25 |
| Peak memory | 217348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=597010870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.u sbdev_device_address.597010870 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_device_timeout.1263239058 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 3538054477 ps |
| CPU time | 25.38 seconds |
| Started | Feb 08 06:13:17 PM UTC 25 |
| Finished | Feb 08 06:13:44 PM UTC 25 |
| Peak memory | 217604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263239058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.1263239058 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_disable_endpoint.537356908 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 550636492 ps |
| CPU time | 2.39 seconds |
| Started | Feb 08 06:13:19 PM UTC 25 |
| Finished | Feb 08 06:13:22 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=537356908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35 .usbdev_disable_endpoint.537356908 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_disconnected.1171172249 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 133582893 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:13:19 PM UTC 25 |
| Finished | Feb 08 06:13:21 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1171172249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.us bdev_disconnected.1171172249 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_enable.919995912 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 66687578 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 06:13:19 PM UTC 25 |
| Finished | Feb 08 06:13:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=919995912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_en able.919995912 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_endpoint_access.2556276604 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 719345973 ps |
| CPU time | 2.33 seconds |
| Started | Feb 08 06:13:19 PM UTC 25 |
| Finished | Feb 08 06:13:22 PM UTC 25 |
| Peak memory | 217396 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2556276604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35 .usbdev_endpoint_access.2556276604 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_endpoint_types.2753996939 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 418263152 ps |
| CPU time | 1.95 seconds |
| Started | Feb 08 06:13:19 PM UTC 25 |
| Finished | Feb 08 06:13:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753996939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 35.usbdev_endpoint_types.2753996939 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_fifo_rst.3529598541 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 300649804 ps |
| CPU time | 3.25 seconds |
| Started | Feb 08 06:13:21 PM UTC 25 |
| Finished | Feb 08 06:13:25 PM UTC 25 |
| Peak memory | 217544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3529598541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev _fifo_rst.3529598541 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_in_iso.1017958033 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 201934299 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:13:21 PM UTC 25 |
| Finished | Feb 08 06:13:23 PM UTC 25 |
| Peak memory | 227756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017958033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 35.usbdev_in_iso.1017958033 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_in_stall.2719043048 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 147134032 ps |
| CPU time | 0.98 seconds |
| Started | Feb 08 06:13:21 PM UTC 25 |
| Finished | Feb 08 06:13:23 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2719043048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev _in_stall.2719043048 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_in_trans.1730993071 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 269425139 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:13:21 PM UTC 25 |
| Finished | Feb 08 06:13:23 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1730993071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev _in_trans.1730993071 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_invalid_sync.1094186164 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 3083565237 ps |
| CPU time | 24.3 seconds |
| Started | Feb 08 06:13:21 PM UTC 25 |
| Finished | Feb 08 06:13:46 PM UTC 25 |
| Peak memory | 227660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094186164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.1094186164 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_iso_retraction.1980913537 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 13028183952 ps |
| CPU time | 159.85 seconds |
| Started | Feb 08 06:13:21 PM UTC 25 |
| Finished | Feb 08 06:16:03 PM UTC 25 |
| Peak memory | 219136 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980913537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 35.usbdev_iso_retraction.1980913537 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_link_in_err.985635390 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 213305207 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:13:22 PM UTC 25 |
| Finished | Feb 08 06:13:25 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=985635390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbd ev_link_in_err.985635390 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_link_resume.2425316782 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 13144973027 ps |
| CPU time | 26.87 seconds |
| Started | Feb 08 06:13:22 PM UTC 25 |
| Finished | Feb 08 06:13:50 PM UTC 25 |
| Peak memory | 217456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2425316782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usb dev_link_resume.2425316782 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_link_suspend.3861845918 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 10258884078 ps |
| CPU time | 16.08 seconds |
| Started | Feb 08 06:13:22 PM UTC 25 |
| Finished | Feb 08 06:13:40 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3861845918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.us bdev_link_suspend.3861845918 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_low_speed_traffic.1462391580 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 4439316895 ps |
| CPU time | 38.54 seconds |
| Started | Feb 08 06:13:24 PM UTC 25 |
| Finished | Feb 08 06:14:04 PM UTC 25 |
| Peak memory | 234432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462391580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 35.usbdev_low_speed_traffic.1462391580 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_max_inter_pkt_delay.3221467931 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 1712012538 ps |
| CPU time | 14.18 seconds |
| Started | Feb 08 06:13:24 PM UTC 25 |
| Finished | Feb 08 06:13:39 PM UTC 25 |
| Peak memory | 227584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221467931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.3221467931 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_max_length_in_transaction.2200031298 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 242823659 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 06:13:24 PM UTC 25 |
| Finished | Feb 08 06:13:26 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200031298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 35.usbdev_max_length_in_transaction.2200031298 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_max_length_out_transaction.2507782422 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 254858064 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:13:24 PM UTC 25 |
| Finished | Feb 08 06:13:26 PM UTC 25 |
| Peak memory | 215076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2507782422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2507782422 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_min_inter_pkt_delay.1541643512 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 1821784247 ps |
| CPU time | 46 seconds |
| Started | Feb 08 06:13:24 PM UTC 25 |
| Finished | Feb 08 06:14:11 PM UTC 25 |
| Peak memory | 234368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541643512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.1541643512 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_min_length_in_transaction.1114614192 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 160875531 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:13:24 PM UTC 25 |
| Finished | Feb 08 06:13:26 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114614192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 35.usbdev_min_length_in_transaction.1114614192 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_min_length_out_transaction.1028496299 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 211287821 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:13:24 PM UTC 25 |
| Finished | Feb 08 06:13:26 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1028496299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.1028496299 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_nak_trans.1079062684 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 223170216 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:13:25 PM UTC 25 |
| Finished | Feb 08 06:13:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1079062684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbde v_nak_trans.1079062684 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_out_iso.2392160262 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 209486940 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:13:26 PM UTC 25 |
| Finished | Feb 08 06:13:29 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2392160262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_ out_iso.2392160262 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_out_stall.645384459 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 154087974 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:13:26 PM UTC 25 |
| Finished | Feb 08 06:13:29 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=645384459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev _out_stall.645384459 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_out_trans_nak.1575934352 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 167230986 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:13:26 PM UTC 25 |
| Finished | Feb 08 06:13:29 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1575934352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.u sbdev_out_trans_nak.1575934352 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_pending_in_trans.2283980748 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 150944515 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 06:13:26 PM UTC 25 |
| Finished | Feb 08 06:13:29 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2283980748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.usbdev_pending_in_trans.2283980748 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_phy_config_pinflip.161435978 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 189757862 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:13:26 PM UTC 25 |
| Finished | Feb 08 06:13:29 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=161435978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 35.usbdev_phy_config_pinflip.161435978 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_phy_config_usb_ref_disable.2090080574 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 142476623 ps |
| CPU time | 1.21 seconds |
| Started | Feb 08 06:13:28 PM UTC 25 |
| Finished | Feb 08 06:13:30 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2090080574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.2090080574 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_phy_pins_sense.651121397 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 44037890 ps |
| CPU time | 0.96 seconds |
| Started | Feb 08 06:13:28 PM UTC 25 |
| Finished | Feb 08 06:13:30 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=651121397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.u sbdev_phy_pins_sense.651121397 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_pkt_buffer.3888239130 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 11691188921 ps |
| CPU time | 35.52 seconds |
| Started | Feb 08 06:13:28 PM UTC 25 |
| Finished | Feb 08 06:14:05 PM UTC 25 |
| Peak memory | 227692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3888239130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbd ev_pkt_buffer.3888239130 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_pkt_received.863851993 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 171011883 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:13:28 PM UTC 25 |
| Finished | Feb 08 06:13:31 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=863851993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usb dev_pkt_received.863851993 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_pkt_sent.365267959 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 280879102 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:13:28 PM UTC 25 |
| Finished | Feb 08 06:13:31 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=365267959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_ pkt_sent.365267959 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_random_length_in_transaction.4136776497 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 174262060 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:13:30 PM UTC 25 |
| Finished | Feb 08 06:13:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4136776497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.u sbdev_random_length_in_transaction.4136776497 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_random_length_out_transaction.955628003 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 164034251 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:13:30 PM UTC 25 |
| Finished | Feb 08 06:13:32 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=955628003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 35.usbdev_random_length_out_transaction.955628003 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_rx_crc_err.290089078 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 146609332 ps |
| CPU time | 1.23 seconds |
| Started | Feb 08 06:13:30 PM UTC 25 |
| Finished | Feb 08 06:13:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=290089078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbde v_rx_crc_err.290089078 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_rx_full.2551351948 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 268292563 ps |
| CPU time | 1.96 seconds |
| Started | Feb 08 06:13:30 PM UTC 25 |
| Finished | Feb 08 06:13:33 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2551351948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_ rx_full.2551351948 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_setup_stage.1173777994 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 159451525 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:13:30 PM UTC 25 |
| Finished | Feb 08 06:13:32 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1173777994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usb dev_setup_stage.1173777994 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_setup_trans_ignored.2622966493 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 238417288 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:13:30 PM UTC 25 |
| Finished | Feb 08 06:13:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2622966493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 35.usbdev_setup_trans_ignored.2622966493 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_smoke.3835766354 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 244143786 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 06:13:30 PM UTC 25 |
| Finished | Feb 08 06:13:33 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3835766354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_sm oke.3835766354 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_spurious_pids_ignored.2618081901 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 2677055180 ps |
| CPU time | 70.96 seconds |
| Started | Feb 08 06:13:30 PM UTC 25 |
| Finished | Feb 08 06:14:43 PM UTC 25 |
| Peak memory | 234552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618081901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 35.usbdev_spurious_pids_ignored.2618081901 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_stall_priority_over_nak.4174649346 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 163045075 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:13:31 PM UTC 25 |
| Finished | Feb 08 06:13:34 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4174649346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 35.usbdev_stall_priority_over_nak.4174649346 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_stall_trans.3698861250 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 160062772 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:13:31 PM UTC 25 |
| Finished | Feb 08 06:13:34 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3698861250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usb dev_stall_trans.3698861250 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_stream_len_max.4219964725 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 388764361 ps |
| CPU time | 1.89 seconds |
| Started | Feb 08 06:13:31 PM UTC 25 |
| Finished | Feb 08 06:13:34 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4219964725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35. usbdev_stream_len_max.4219964725 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_streaming_out.828148481 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 2097084294 ps |
| CPU time | 54.04 seconds |
| Started | Feb 08 06:13:31 PM UTC 25 |
| Finished | Feb 08 06:14:27 PM UTC 25 |
| Peak memory | 227664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=828148481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev _streaming_out.828148481 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_timeout_missing_host_handshake.362052877 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 904633638 ps |
| CPU time | 19.33 seconds |
| Started | Feb 08 06:13:19 PM UTC 25 |
| Finished | Feb 08 06:13:39 PM UTC 25 |
| Peak memory | 217412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362052877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing_host_handshake.362052877 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_tx_rx_disruption.682561438 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 551331305 ps |
| CPU time | 1.96 seconds |
| Started | Feb 08 06:13:33 PM UTC 25 |
| Finished | Feb 08 06:13:36 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6 82561438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_tx_rx_disruption.682561438 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/35.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/350.usbdev_tx_rx_disruption.1705338841 |
| Short name | T3491 |
| Test name | |
| Test status | |
| Simulation time | 630255264 ps |
| CPU time | 1.72 seconds |
| Started | Feb 08 06:19:43 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 705338841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 350.usbdev_tx_rx_disruption.1705338841 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/350.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/351.usbdev_tx_rx_disruption.3414536157 |
| Short name | T3474 |
| Test name | |
| Test status | |
| Simulation time | 461255284 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:19:43 PM UTC 25 |
| Finished | Feb 08 06:19:59 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 414536157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 351.usbdev_tx_rx_disruption.3414536157 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/351.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/352.usbdev_tx_rx_disruption.1932928761 |
| Short name | T3455 |
| Test name | |
| Test status | |
| Simulation time | 426028938 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:19:43 PM UTC 25 |
| Finished | Feb 08 06:19:49 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 932928761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 352.usbdev_tx_rx_disruption.1932928761 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/352.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/353.usbdev_tx_rx_disruption.2690622292 |
| Short name | T3493 |
| Test name | |
| Test status | |
| Simulation time | 601600919 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:19:43 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 690622292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 353.usbdev_tx_rx_disruption.2690622292 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/353.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/354.usbdev_tx_rx_disruption.2910935824 |
| Short name | T3488 |
| Test name | |
| Test status | |
| Simulation time | 484447397 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:19:43 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 910935824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 354.usbdev_tx_rx_disruption.2910935824 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/354.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/355.usbdev_tx_rx_disruption.105276367 |
| Short name | T3458 |
| Test name | |
| Test status | |
| Simulation time | 596269063 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:19:43 PM UTC 25 |
| Finished | Feb 08 06:19:49 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 05276367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 355.usbdev_tx_rx_disruption.105276367 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/355.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/356.usbdev_tx_rx_disruption.4061925669 |
| Short name | T3494 |
| Test name | |
| Test status | |
| Simulation time | 514707687 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:19:43 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 061925669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 356.usbdev_tx_rx_disruption.4061925669 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/356.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/357.usbdev_tx_rx_disruption.3055300702 |
| Short name | T3456 |
| Test name | |
| Test status | |
| Simulation time | 587183119 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:19:43 PM UTC 25 |
| Finished | Feb 08 06:19:49 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 055300702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 357.usbdev_tx_rx_disruption.3055300702 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/357.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/358.usbdev_tx_rx_disruption.1585742129 |
| Short name | T3489 |
| Test name | |
| Test status | |
| Simulation time | 502135713 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:19:43 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 585742129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 358.usbdev_tx_rx_disruption.1585742129 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/358.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/359.usbdev_tx_rx_disruption.896747985 |
| Short name | T3496 |
| Test name | |
| Test status | |
| Simulation time | 532586002 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:19:43 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 96747985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 359.usbdev_tx_rx_disruption.896747985 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/359.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_alert_test.1322062678 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 58632858 ps |
| CPU time | 0.98 seconds |
| Started | Feb 08 06:13:51 PM UTC 25 |
| Finished | Feb 08 06:13:54 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322062678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 36.usbdev_alert_test.1322062678 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_aon_wake_disconnect.350605878 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 9180810900 ps |
| CPU time | 15.62 seconds |
| Started | Feb 08 06:13:33 PM UTC 25 |
| Finished | Feb 08 06:13:50 PM UTC 25 |
| Peak memory | 217572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350605878 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.350605878 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_aon_wake_reset.2842221169 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 21170771752 ps |
| CPU time | 34.68 seconds |
| Started | Feb 08 06:13:33 PM UTC 25 |
| Finished | Feb 08 06:14:09 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842221169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.2842221169 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_aon_wake_resume.3982728007 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 29619961369 ps |
| CPU time | 40.55 seconds |
| Started | Feb 08 06:13:33 PM UTC 25 |
| Finished | Feb 08 06:14:15 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982728007 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.3982728007 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_av_buffer.560065420 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 160760248 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:13:33 PM UTC 25 |
| Finished | Feb 08 06:13:36 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=560065420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev _av_buffer.560065420 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_bitstuff_err.3649533048 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 152169651 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:13:34 PM UTC 25 |
| Finished | Feb 08 06:13:37 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3649533048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.us bdev_bitstuff_err.3649533048 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_data_toggle_clear.2915558726 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 225307439 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:13:34 PM UTC 25 |
| Finished | Feb 08 06:13:37 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2915558726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.2915558726 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_data_toggle_restore.430606466 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 1138450898 ps |
| CPU time | 3.66 seconds |
| Started | Feb 08 06:13:35 PM UTC 25 |
| Finished | Feb 08 06:13:39 PM UTC 25 |
| Peak memory | 217380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430606466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_t oggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.430606466 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_device_address.1048505888 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 29026372995 ps |
| CPU time | 50.4 seconds |
| Started | Feb 08 06:13:35 PM UTC 25 |
| Finished | Feb 08 06:14:27 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1048505888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36. usbdev_device_address.1048505888 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_device_timeout.2718020300 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 2015639186 ps |
| CPU time | 17.07 seconds |
| Started | Feb 08 06:13:35 PM UTC 25 |
| Finished | Feb 08 06:13:53 PM UTC 25 |
| Peak memory | 217340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718020300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.2718020300 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_disable_endpoint.3391597720 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 991734442 ps |
| CPU time | 2.66 seconds |
| Started | Feb 08 06:13:36 PM UTC 25 |
| Finished | Feb 08 06:13:40 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3391597720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.usbdev_disable_endpoint.3391597720 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_disconnected.2036587749 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 152487420 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:13:36 PM UTC 25 |
| Finished | Feb 08 06:13:38 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2036587749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.us bdev_disconnected.2036587749 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_enable.3381885471 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 99074014 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:13:38 PM UTC 25 |
| Finished | Feb 08 06:13:40 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3381885471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_e nable.3381885471 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_endpoint_access.999298555 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 839560977 ps |
| CPU time | 2.64 seconds |
| Started | Feb 08 06:13:38 PM UTC 25 |
| Finished | Feb 08 06:13:41 PM UTC 25 |
| Peak memory | 217392 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=999298555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36. usbdev_endpoint_access.999298555 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_endpoint_types.1108485332 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 602373750 ps |
| CPU time | 2.67 seconds |
| Started | Feb 08 06:13:38 PM UTC 25 |
| Finished | Feb 08 06:13:41 PM UTC 25 |
| Peak memory | 216396 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108485332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 36.usbdev_endpoint_types.1108485332 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_fifo_rst.3655155104 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 204397413 ps |
| CPU time | 1.91 seconds |
| Started | Feb 08 06:13:38 PM UTC 25 |
| Finished | Feb 08 06:13:41 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3655155104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev _fifo_rst.3655155104 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_in_iso.3009282381 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 209417802 ps |
| CPU time | 1.78 seconds |
| Started | Feb 08 06:13:39 PM UTC 25 |
| Finished | Feb 08 06:13:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009282381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 36.usbdev_in_iso.3009282381 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_in_stall.1567678500 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 134882191 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:13:39 PM UTC 25 |
| Finished | Feb 08 06:13:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1567678500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev _in_stall.1567678500 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_in_trans.4186532555 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 223535574 ps |
| CPU time | 1.8 seconds |
| Started | Feb 08 06:13:39 PM UTC 25 |
| Finished | Feb 08 06:13:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4186532555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev _in_trans.4186532555 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_invalid_sync.1366557186 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 4241111616 ps |
| CPU time | 40.44 seconds |
| Started | Feb 08 06:13:38 PM UTC 25 |
| Finished | Feb 08 06:14:20 PM UTC 25 |
| Peak memory | 229096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366557186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.1366557186 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_iso_retraction.1299561130 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 12516474776 ps |
| CPU time | 156.89 seconds |
| Started | Feb 08 06:13:39 PM UTC 25 |
| Finished | Feb 08 06:16:19 PM UTC 25 |
| Peak memory | 217576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299561130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 36.usbdev_iso_retraction.1299561130 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_link_in_err.3436365750 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 259719914 ps |
| CPU time | 1.81 seconds |
| Started | Feb 08 06:13:41 PM UTC 25 |
| Finished | Feb 08 06:13:44 PM UTC 25 |
| Peak memory | 214808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3436365750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usb dev_link_in_err.3436365750 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_link_resume.2718625780 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 23184792214 ps |
| CPU time | 42.86 seconds |
| Started | Feb 08 06:13:41 PM UTC 25 |
| Finished | Feb 08 06:14:25 PM UTC 25 |
| Peak memory | 227388 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2718625780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usb dev_link_resume.2718625780 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_link_suspend.3860263125 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 10701087110 ps |
| CPU time | 19.9 seconds |
| Started | Feb 08 06:13:41 PM UTC 25 |
| Finished | Feb 08 06:14:02 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3860263125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.us bdev_link_suspend.3860263125 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_low_speed_traffic.2014535027 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 4768541672 ps |
| CPU time | 53.51 seconds |
| Started | Feb 08 06:13:41 PM UTC 25 |
| Finished | Feb 08 06:14:36 PM UTC 25 |
| Peak memory | 229824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014535027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 36.usbdev_low_speed_traffic.2014535027 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_max_inter_pkt_delay.2295512783 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 2595281500 ps |
| CPU time | 77.09 seconds |
| Started | Feb 08 06:13:41 PM UTC 25 |
| Finished | Feb 08 06:15:00 PM UTC 25 |
| Peak memory | 229704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295512783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.2295512783 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_max_length_in_transaction.2258996904 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 321056647 ps |
| CPU time | 1.92 seconds |
| Started | Feb 08 06:13:41 PM UTC 25 |
| Finished | Feb 08 06:13:44 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258996904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 36.usbdev_max_length_in_transaction.2258996904 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_max_length_out_transaction.2095216566 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 209003786 ps |
| CPU time | 1.72 seconds |
| Started | Feb 08 06:13:42 PM UTC 25 |
| Finished | Feb 08 06:13:45 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2095216566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2095216566 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_min_inter_pkt_delay.3654678842 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 2418458369 ps |
| CPU time | 67.98 seconds |
| Started | Feb 08 06:13:42 PM UTC 25 |
| Finished | Feb 08 06:14:52 PM UTC 25 |
| Peak memory | 227676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654678842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.3654678842 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_min_length_in_transaction.1557051395 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 152881108 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:13:42 PM UTC 25 |
| Finished | Feb 08 06:13:45 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557051395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 36.usbdev_min_length_in_transaction.1557051395 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_min_length_out_transaction.2886798537 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 218064372 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:13:42 PM UTC 25 |
| Finished | Feb 08 06:13:45 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2886798537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2886798537 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_nak_trans.4092323304 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 168248724 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:13:43 PM UTC 25 |
| Finished | Feb 08 06:13:45 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4092323304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbde v_nak_trans.4092323304 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_out_iso.896457542 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 146536460 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:13:44 PM UTC 25 |
| Finished | Feb 08 06:13:46 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=896457542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_o ut_iso.896457542 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_out_stall.2187174734 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 190332885 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:13:44 PM UTC 25 |
| Finished | Feb 08 06:13:47 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2187174734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbde v_out_stall.2187174734 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_out_trans_nak.2489937182 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 162645289 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:13:44 PM UTC 25 |
| Finished | Feb 08 06:13:46 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2489937182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.u sbdev_out_trans_nak.2489937182 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_pending_in_trans.58420432 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 175566301 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:13:45 PM UTC 25 |
| Finished | Feb 08 06:13:48 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=58420432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36. usbdev_pending_in_trans.58420432 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_phy_config_pinflip.28378257 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 225390527 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:13:45 PM UTC 25 |
| Finished | Feb 08 06:13:48 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=28378257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 36.usbdev_phy_config_pinflip.28378257 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_phy_config_usb_ref_disable.3084393873 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 165183968 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 06:13:45 PM UTC 25 |
| Finished | Feb 08 06:13:47 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3084393873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3084393873 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_phy_pins_sense.4202967470 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 87484139 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 06:13:46 PM UTC 25 |
| Finished | Feb 08 06:13:49 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4202967470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36. usbdev_phy_pins_sense.4202967470 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_pkt_buffer.4240969822 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 22570685721 ps |
| CPU time | 65.6 seconds |
| Started | Feb 08 06:13:46 PM UTC 25 |
| Finished | Feb 08 06:14:54 PM UTC 25 |
| Peak memory | 227764 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4240969822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbd ev_pkt_buffer.4240969822 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_pkt_received.3845153019 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 190289913 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:13:47 PM UTC 25 |
| Finished | Feb 08 06:13:49 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3845153019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.us bdev_pkt_received.3845153019 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_pkt_sent.1468364458 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 178549139 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:13:47 PM UTC 25 |
| Finished | Feb 08 06:13:49 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1468364458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev _pkt_sent.1468364458 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_random_length_in_transaction.302959050 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 242681501 ps |
| CPU time | 1.76 seconds |
| Started | Feb 08 06:13:47 PM UTC 25 |
| Finished | Feb 08 06:13:50 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=302959050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.us bdev_random_length_in_transaction.302959050 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_random_length_out_transaction.2469407175 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 206249516 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:13:48 PM UTC 25 |
| Finished | Feb 08 06:13:51 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2469407175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 36.usbdev_random_length_out_transaction.2469407175 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_rx_crc_err.1708459812 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 203767521 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:13:48 PM UTC 25 |
| Finished | Feb 08 06:13:51 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1708459812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbd ev_rx_crc_err.1708459812 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_rx_full.2859994142 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 402188658 ps |
| CPU time | 2.48 seconds |
| Started | Feb 08 06:13:48 PM UTC 25 |
| Finished | Feb 08 06:13:52 PM UTC 25 |
| Peak memory | 217176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2859994142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_ rx_full.2859994142 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_setup_stage.4144283712 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 148727108 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:13:48 PM UTC 25 |
| Finished | Feb 08 06:13:51 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4144283712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usb dev_setup_stage.4144283712 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_setup_trans_ignored.2262722138 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 213225557 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:13:49 PM UTC 25 |
| Finished | Feb 08 06:13:51 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2262722138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.usbdev_setup_trans_ignored.2262722138 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_smoke.1641149785 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 231337329 ps |
| CPU time | 1.79 seconds |
| Started | Feb 08 06:13:49 PM UTC 25 |
| Finished | Feb 08 06:13:52 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1641149785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_sm oke.1641149785 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_spurious_pids_ignored.69650187 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 2161270635 ps |
| CPU time | 16.64 seconds |
| Started | Feb 08 06:13:49 PM UTC 25 |
| Finished | Feb 08 06:14:07 PM UTC 25 |
| Peak memory | 234364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69650187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 36.usbdev_spurious_pids_ignored.69650187 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_stall_priority_over_nak.4177957236 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 179723282 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:13:49 PM UTC 25 |
| Finished | Feb 08 06:13:51 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4177957236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 36.usbdev_stall_priority_over_nak.4177957236 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_stall_trans.3472020219 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 143949659 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:13:50 PM UTC 25 |
| Finished | Feb 08 06:13:53 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3472020219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usb dev_stall_trans.3472020219 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_stream_len_max.3073079208 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 199864241 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:13:50 PM UTC 25 |
| Finished | Feb 08 06:13:53 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3073079208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36. usbdev_stream_len_max.3073079208 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_streaming_out.1947091801 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 2242792916 ps |
| CPU time | 16.95 seconds |
| Started | Feb 08 06:13:50 PM UTC 25 |
| Finished | Feb 08 06:14:08 PM UTC 25 |
| Peak memory | 229700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1947091801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbde v_streaming_out.1947091801 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_timeout_missing_host_handshake.1230290570 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 1703189409 ps |
| CPU time | 38.94 seconds |
| Started | Feb 08 06:13:36 PM UTC 25 |
| Finished | Feb 08 06:14:16 PM UTC 25 |
| Peak memory | 217348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230290570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing_host_handshake.1230290570 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_tx_rx_disruption.1444013897 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 491833668 ps |
| CPU time | 2.76 seconds |
| Started | Feb 08 06:13:50 PM UTC 25 |
| Finished | Feb 08 06:13:54 PM UTC 25 |
| Peak memory | 217116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 444013897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_tx_rx_disruption.1444013897 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/36.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/360.usbdev_tx_rx_disruption.2618029182 |
| Short name | T3454 |
| Test name | |
| Test status | |
| Simulation time | 574996951 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:19:44 PM UTC 25 |
| Finished | Feb 08 06:19:48 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 618029182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 360.usbdev_tx_rx_disruption.2618029182 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/360.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/361.usbdev_tx_rx_disruption.533569810 |
| Short name | T3462 |
| Test name | |
| Test status | |
| Simulation time | 459561886 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:19:44 PM UTC 25 |
| Finished | Feb 08 06:19:54 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 33569810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 361.usbdev_tx_rx_disruption.533569810 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/361.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/362.usbdev_tx_rx_disruption.743484099 |
| Short name | T3465 |
| Test name | |
| Test status | |
| Simulation time | 555498188 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:19:44 PM UTC 25 |
| Finished | Feb 08 06:19:54 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 43484099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 362.usbdev_tx_rx_disruption.743484099 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/362.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/363.usbdev_tx_rx_disruption.4132340069 |
| Short name | T3453 |
| Test name | |
| Test status | |
| Simulation time | 542829288 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:19:44 PM UTC 25 |
| Finished | Feb 08 06:19:48 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 132340069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 363.usbdev_tx_rx_disruption.4132340069 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/363.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/364.usbdev_tx_rx_disruption.3210578895 |
| Short name | T3466 |
| Test name | |
| Test status | |
| Simulation time | 632366058 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 06:19:44 PM UTC 25 |
| Finished | Feb 08 06:19:55 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 210578895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 364.usbdev_tx_rx_disruption.3210578895 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/364.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/365.usbdev_tx_rx_disruption.3839716229 |
| Short name | T3498 |
| Test name | |
| Test status | |
| Simulation time | 515094056 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:19:46 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 839716229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 365.usbdev_tx_rx_disruption.3839716229 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/365.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/366.usbdev_tx_rx_disruption.988947537 |
| Short name | T3457 |
| Test name | |
| Test status | |
| Simulation time | 589582730 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:19:46 PM UTC 25 |
| Finished | Feb 08 06:19:49 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 88947537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 366.usbdev_tx_rx_disruption.988947537 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/366.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/367.usbdev_tx_rx_disruption.3678728209 |
| Short name | T3503 |
| Test name | |
| Test status | |
| Simulation time | 640175899 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:19:46 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 678728209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 367.usbdev_tx_rx_disruption.3678728209 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/367.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/368.usbdev_tx_rx_disruption.3227572320 |
| Short name | T3500 |
| Test name | |
| Test status | |
| Simulation time | 575570556 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:19:46 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 227572320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 368.usbdev_tx_rx_disruption.3227572320 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/368.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/369.usbdev_tx_rx_disruption.1685054487 |
| Short name | T3501 |
| Test name | |
| Test status | |
| Simulation time | 502436011 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:19:46 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 685054487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 369.usbdev_tx_rx_disruption.1685054487 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/369.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_alert_test.3219742672 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 99978089 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 06:14:12 PM UTC 25 |
| Finished | Feb 08 06:14:14 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219742672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 37.usbdev_alert_test.3219742672 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_aon_wake_disconnect.1398990744 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 9696389001 ps |
| CPU time | 22.86 seconds |
| Started | Feb 08 06:13:51 PM UTC 25 |
| Finished | Feb 08 06:14:16 PM UTC 25 |
| Peak memory | 217572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398990744 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.1398990744 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_aon_wake_reset.4128337007 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 16193100374 ps |
| CPU time | 28.8 seconds |
| Started | Feb 08 06:13:53 PM UTC 25 |
| Finished | Feb 08 06:14:23 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128337007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.4128337007 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_aon_wake_resume.3465780477 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 25948389582 ps |
| CPU time | 39.81 seconds |
| Started | Feb 08 06:13:53 PM UTC 25 |
| Finished | Feb 08 06:14:34 PM UTC 25 |
| Peak memory | 227592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465780477 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.3465780477 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_av_buffer.2152391537 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 165917290 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:13:53 PM UTC 25 |
| Finished | Feb 08 06:13:56 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2152391537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbde v_av_buffer.2152391537 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_bitstuff_err.4071713138 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 163407382 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:13:53 PM UTC 25 |
| Finished | Feb 08 06:13:56 PM UTC 25 |
| Peak memory | 214968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4071713138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.us bdev_bitstuff_err.4071713138 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_data_toggle_clear.3428575773 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 307514030 ps |
| CPU time | 2.05 seconds |
| Started | Feb 08 06:13:53 PM UTC 25 |
| Finished | Feb 08 06:13:56 PM UTC 25 |
| Peak memory | 216956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3428575773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.3428575773 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_data_toggle_restore.1738214555 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 619662691 ps |
| CPU time | 3.37 seconds |
| Started | Feb 08 06:13:53 PM UTC 25 |
| Finished | Feb 08 06:13:58 PM UTC 25 |
| Peak memory | 217108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738214555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.1738214555 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_device_address.372295853 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 39572839390 ps |
| CPU time | 70.45 seconds |
| Started | Feb 08 06:13:53 PM UTC 25 |
| Finished | Feb 08 06:15:06 PM UTC 25 |
| Peak memory | 217492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=372295853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.u sbdev_device_address.372295853 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_device_timeout.3160258757 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 693853652 ps |
| CPU time | 19.15 seconds |
| Started | Feb 08 06:13:55 PM UTC 25 |
| Finished | Feb 08 06:14:16 PM UTC 25 |
| Peak memory | 217548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160258757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.3160258757 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_disable_endpoint.3029608320 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 774158583 ps |
| CPU time | 3.89 seconds |
| Started | Feb 08 06:13:55 PM UTC 25 |
| Finished | Feb 08 06:14:00 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3029608320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.usbdev_disable_endpoint.3029608320 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_disconnected.4052834740 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 137369058 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:13:55 PM UTC 25 |
| Finished | Feb 08 06:13:58 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4052834740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.us bdev_disconnected.4052834740 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_enable.2038252896 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 29333614 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 06:13:55 PM UTC 25 |
| Finished | Feb 08 06:13:58 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2038252896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_e nable.2038252896 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_endpoint_access.3472936763 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 877714920 ps |
| CPU time | 3.08 seconds |
| Started | Feb 08 06:13:55 PM UTC 25 |
| Finished | Feb 08 06:14:00 PM UTC 25 |
| Peak memory | 217380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3472936763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37 .usbdev_endpoint_access.3472936763 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_fifo_rst.241467513 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 189400684 ps |
| CPU time | 2.1 seconds |
| Started | Feb 08 06:13:55 PM UTC 25 |
| Finished | Feb 08 06:13:59 PM UTC 25 |
| Peak memory | 217544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=241467513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_ fifo_rst.241467513 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_in_iso.2687390185 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 215153496 ps |
| CPU time | 1.98 seconds |
| Started | Feb 08 06:13:57 PM UTC 25 |
| Finished | Feb 08 06:14:00 PM UTC 25 |
| Peak memory | 227756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687390185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 37.usbdev_in_iso.2687390185 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_in_stall.839437577 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 167409969 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:13:58 PM UTC 25 |
| Finished | Feb 08 06:14:00 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=839437577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_ in_stall.839437577 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_in_trans.3696391166 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 282303932 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:13:59 PM UTC 25 |
| Finished | Feb 08 06:14:02 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3696391166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev _in_trans.3696391166 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_invalid_sync.50020461 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 4108737932 ps |
| CPU time | 119.62 seconds |
| Started | Feb 08 06:13:57 PM UTC 25 |
| Finished | Feb 08 06:15:59 PM UTC 25 |
| Peak memory | 227660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50020461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 37.usbdev_invalid_sync.50020461 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_iso_retraction.1368742740 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 4998677537 ps |
| CPU time | 34.03 seconds |
| Started | Feb 08 06:13:59 PM UTC 25 |
| Finished | Feb 08 06:14:35 PM UTC 25 |
| Peak memory | 217356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368742740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 37.usbdev_iso_retraction.1368742740 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_link_in_err.1650548677 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 153362908 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:13:59 PM UTC 25 |
| Finished | Feb 08 06:14:01 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1650548677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usb dev_link_in_err.1650548677 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_link_resume.2296828775 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 31968142236 ps |
| CPU time | 52.01 seconds |
| Started | Feb 08 06:14:00 PM UTC 25 |
| Finished | Feb 08 06:14:54 PM UTC 25 |
| Peak memory | 217456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2296828775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usb dev_link_resume.2296828775 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_link_suspend.106475442 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 3546038216 ps |
| CPU time | 8.61 seconds |
| Started | Feb 08 06:14:00 PM UTC 25 |
| Finished | Feb 08 06:14:10 PM UTC 25 |
| Peak memory | 217360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=106475442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usb dev_link_suspend.106475442 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_low_speed_traffic.1328462789 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 4661504239 ps |
| CPU time | 39.91 seconds |
| Started | Feb 08 06:14:01 PM UTC 25 |
| Finished | Feb 08 06:14:42 PM UTC 25 |
| Peak memory | 234300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328462789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 37.usbdev_low_speed_traffic.1328462789 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_max_inter_pkt_delay.3672195854 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 1598022930 ps |
| CPU time | 15.27 seconds |
| Started | Feb 08 06:14:01 PM UTC 25 |
| Finished | Feb 08 06:14:17 PM UTC 25 |
| Peak memory | 227676 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672195854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.3672195854 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_max_length_in_transaction.1117785193 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 296209138 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:14:01 PM UTC 25 |
| Finished | Feb 08 06:14:03 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117785193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 37.usbdev_max_length_in_transaction.1117785193 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_max_length_out_transaction.1402521468 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 191070911 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:14:02 PM UTC 25 |
| Finished | Feb 08 06:14:04 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1402521468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1402521468 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_min_inter_pkt_delay.400514997 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 1880836416 ps |
| CPU time | 15.68 seconds |
| Started | Feb 08 06:14:02 PM UTC 25 |
| Finished | Feb 08 06:14:19 PM UTC 25 |
| Peak memory | 229836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400514997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usb dev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.400514997 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_min_length_in_transaction.240328795 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 173282443 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:14:03 PM UTC 25 |
| Finished | Feb 08 06:14:06 PM UTC 25 |
| Peak memory | 215156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240328795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 37.usbdev_min_length_in_transaction.240328795 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_min_length_out_transaction.4090274463 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 163182356 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:14:03 PM UTC 25 |
| Finished | Feb 08 06:14:06 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4090274463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.4090274463 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_nak_trans.3045365334 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 206241560 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:14:03 PM UTC 25 |
| Finished | Feb 08 06:14:06 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3045365334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbde v_nak_trans.3045365334 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_out_iso.163031923 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 155595123 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:14:03 PM UTC 25 |
| Finished | Feb 08 06:14:06 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=163031923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_o ut_iso.163031923 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_out_stall.1914369253 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 159310896 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:14:05 PM UTC 25 |
| Finished | Feb 08 06:14:07 PM UTC 25 |
| Peak memory | 215016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1914369253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbde v_out_stall.1914369253 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_out_trans_nak.3877851300 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 212239224 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:14:05 PM UTC 25 |
| Finished | Feb 08 06:14:07 PM UTC 25 |
| Peak memory | 215044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3877851300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.u sbdev_out_trans_nak.3877851300 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_pending_in_trans.1372261111 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 145592748 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:14:05 PM UTC 25 |
| Finished | Feb 08 06:14:07 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1372261111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.usbdev_pending_in_trans.1372261111 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_phy_config_pinflip.402300015 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 249754780 ps |
| CPU time | 1.77 seconds |
| Started | Feb 08 06:14:05 PM UTC 25 |
| Finished | Feb 08 06:14:08 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=402300015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 37.usbdev_phy_config_pinflip.402300015 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_phy_config_usb_ref_disable.766583505 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 149345233 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:14:07 PM UTC 25 |
| Finished | Feb 08 06:14:09 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=766583505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 37.usbdev_phy_config_usb_ref_disable.766583505 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_phy_pins_sense.3735974402 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 51584495 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 06:14:07 PM UTC 25 |
| Finished | Feb 08 06:14:09 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3735974402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37. usbdev_phy_pins_sense.3735974402 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_pkt_buffer.209155065 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 13596768276 ps |
| CPU time | 37.67 seconds |
| Started | Feb 08 06:14:07 PM UTC 25 |
| Finished | Feb 08 06:14:46 PM UTC 25 |
| Peak memory | 227760 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=209155065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbde v_pkt_buffer.209155065 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_pkt_received.1568273063 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 255833273 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 06:14:07 PM UTC 25 |
| Finished | Feb 08 06:14:09 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1568273063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.us bdev_pkt_received.1568273063 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_pkt_sent.2937937108 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 238428219 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:14:07 PM UTC 25 |
| Finished | Feb 08 06:14:09 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2937937108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev _pkt_sent.2937937108 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_random_length_in_transaction.1808431889 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 184061342 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:14:08 PM UTC 25 |
| Finished | Feb 08 06:14:11 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1808431889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.u sbdev_random_length_in_transaction.1808431889 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_random_length_out_transaction.498977126 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 172452270 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:14:08 PM UTC 25 |
| Finished | Feb 08 06:14:11 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=498977126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 37.usbdev_random_length_out_transaction.498977126 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_rx_crc_err.3184864560 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 171406748 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:14:08 PM UTC 25 |
| Finished | Feb 08 06:14:11 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3184864560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbd ev_rx_crc_err.3184864560 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_rx_full.2564605478 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 257783508 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:14:08 PM UTC 25 |
| Finished | Feb 08 06:14:11 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2564605478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_ rx_full.2564605478 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_setup_stage.1893205195 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 146452032 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:14:10 PM UTC 25 |
| Finished | Feb 08 06:14:12 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1893205195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usb dev_setup_stage.1893205195 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_setup_trans_ignored.3246824551 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 182867474 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:14:10 PM UTC 25 |
| Finished | Feb 08 06:14:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3246824551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 37.usbdev_setup_trans_ignored.3246824551 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_smoke.2552484329 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 260974108 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:14:10 PM UTC 25 |
| Finished | Feb 08 06:14:13 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2552484329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_sm oke.2552484329 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_spurious_pids_ignored.395460698 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 1896552184 ps |
| CPU time | 18.08 seconds |
| Started | Feb 08 06:14:10 PM UTC 25 |
| Finished | Feb 08 06:14:29 PM UTC 25 |
| Peak memory | 234320 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395460698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 37.usbdev_spurious_pids_ignored.395460698 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_stall_priority_over_nak.2195171704 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 176528963 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:14:10 PM UTC 25 |
| Finished | Feb 08 06:14:13 PM UTC 25 |
| Peak memory | 215028 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2195171704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 37.usbdev_stall_priority_over_nak.2195171704 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_stall_trans.339751499 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 180422129 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:14:10 PM UTC 25 |
| Finished | Feb 08 06:14:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=339751499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbd ev_stall_trans.339751499 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_stream_len_max.69735493 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 842118127 ps |
| CPU time | 3.93 seconds |
| Started | Feb 08 06:14:12 PM UTC 25 |
| Finished | Feb 08 06:14:17 PM UTC 25 |
| Peak memory | 217040 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=69735493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.us bdev_stream_len_max.69735493 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_streaming_out.3554889982 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 3206954637 ps |
| CPU time | 90.3 seconds |
| Started | Feb 08 06:14:12 PM UTC 25 |
| Finished | Feb 08 06:15:44 PM UTC 25 |
| Peak memory | 227328 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3554889982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbde v_streaming_out.3554889982 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_timeout_missing_host_handshake.2156009590 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 609881364 ps |
| CPU time | 5.7 seconds |
| Started | Feb 08 06:13:55 PM UTC 25 |
| Finished | Feb 08 06:14:02 PM UTC 25 |
| Peak memory | 217348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156009590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing_host_handshake.2156009590 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_tx_rx_disruption.753352811 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 532365451 ps |
| CPU time | 2.87 seconds |
| Started | Feb 08 06:14:12 PM UTC 25 |
| Finished | Feb 08 06:14:16 PM UTC 25 |
| Peak memory | 217316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 53352811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_tx_rx_disruption.753352811 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/37.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/370.usbdev_tx_rx_disruption.3931160957 |
| Short name | T3487 |
| Test name | |
| Test status | |
| Simulation time | 570139283 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:19:46 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215024 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 931160957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 370.usbdev_tx_rx_disruption.3931160957 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/370.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/371.usbdev_tx_rx_disruption.3345085308 |
| Short name | T3502 |
| Test name | |
| Test status | |
| Simulation time | 546767267 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:19:46 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 345085308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 371.usbdev_tx_rx_disruption.3345085308 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/371.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/372.usbdev_tx_rx_disruption.1485147808 |
| Short name | T3492 |
| Test name | |
| Test status | |
| Simulation time | 483962982 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:19:46 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 485147808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 372.usbdev_tx_rx_disruption.1485147808 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/372.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/373.usbdev_tx_rx_disruption.2240845068 |
| Short name | T3497 |
| Test name | |
| Test status | |
| Simulation time | 588858345 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 06:19:46 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 240845068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 373.usbdev_tx_rx_disruption.2240845068 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/373.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/374.usbdev_tx_rx_disruption.3908247358 |
| Short name | T3510 |
| Test name | |
| Test status | |
| Simulation time | 471154844 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:19:46 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 908247358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 374.usbdev_tx_rx_disruption.3908247358 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/374.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/375.usbdev_tx_rx_disruption.2257729511 |
| Short name | T3499 |
| Test name | |
| Test status | |
| Simulation time | 531209131 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:19:46 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 257729511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 375.usbdev_tx_rx_disruption.2257729511 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/375.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/376.usbdev_tx_rx_disruption.2043744311 |
| Short name | T3495 |
| Test name | |
| Test status | |
| Simulation time | 398016830 ps |
| CPU time | 1.21 seconds |
| Started | Feb 08 06:19:46 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 043744311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 376.usbdev_tx_rx_disruption.2043744311 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/376.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/377.usbdev_tx_rx_disruption.2309131365 |
| Short name | T3504 |
| Test name | |
| Test status | |
| Simulation time | 513559355 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:19:46 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 309131365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 377.usbdev_tx_rx_disruption.2309131365 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/377.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/378.usbdev_tx_rx_disruption.2102096915 |
| Short name | T3505 |
| Test name | |
| Test status | |
| Simulation time | 502502880 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:19:46 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 102096915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 378.usbdev_tx_rx_disruption.2102096915 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/378.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/379.usbdev_tx_rx_disruption.1149152582 |
| Short name | T3511 |
| Test name | |
| Test status | |
| Simulation time | 482307517 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:19:46 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 149152582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 379.usbdev_tx_rx_disruption.1149152582 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/379.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_alert_test.2113980852 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 34275038 ps |
| CPU time | 0.98 seconds |
| Started | Feb 08 06:14:28 PM UTC 25 |
| Finished | Feb 08 06:14:31 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113980852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 38.usbdev_alert_test.2113980852 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_aon_wake_disconnect.3764128850 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 6203842684 ps |
| CPU time | 20.62 seconds |
| Started | Feb 08 06:14:12 PM UTC 25 |
| Finished | Feb 08 06:14:34 PM UTC 25 |
| Peak memory | 227588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764128850 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.3764128850 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_aon_wake_reset.1531668776 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 13718322972 ps |
| CPU time | 17.64 seconds |
| Started | Feb 08 06:14:12 PM UTC 25 |
| Finished | Feb 08 06:14:31 PM UTC 25 |
| Peak memory | 227592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531668776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.1531668776 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_aon_wake_resume.1308772565 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 29455127615 ps |
| CPU time | 43.28 seconds |
| Started | Feb 08 06:14:12 PM UTC 25 |
| Finished | Feb 08 06:14:57 PM UTC 25 |
| Peak memory | 217384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308772565 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.1308772565 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_av_buffer.993468507 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 212301123 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:14:12 PM UTC 25 |
| Finished | Feb 08 06:14:15 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=993468507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev _av_buffer.993468507 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_bitstuff_err.3861068798 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 149789356 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:14:13 PM UTC 25 |
| Finished | Feb 08 06:14:16 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3861068798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.us bdev_bitstuff_err.3861068798 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_data_toggle_clear.4246736920 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 364515437 ps |
| CPU time | 2.09 seconds |
| Started | Feb 08 06:14:13 PM UTC 25 |
| Finished | Feb 08 06:14:17 PM UTC 25 |
| Peak memory | 217116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4246736920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.4246736920 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_data_toggle_restore.3373768175 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 478170997 ps |
| CPU time | 2.08 seconds |
| Started | Feb 08 06:14:13 PM UTC 25 |
| Finished | Feb 08 06:14:17 PM UTC 25 |
| Peak memory | 217108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373768175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.3373768175 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_device_address.4086712671 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 28342813299 ps |
| CPU time | 52.51 seconds |
| Started | Feb 08 06:14:13 PM UTC 25 |
| Finished | Feb 08 06:15:08 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4086712671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38. usbdev_device_address.4086712671 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_device_timeout.4145273859 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 266898451 ps |
| CPU time | 4.58 seconds |
| Started | Feb 08 06:14:13 PM UTC 25 |
| Finished | Feb 08 06:14:19 PM UTC 25 |
| Peak memory | 217340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145273859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.4145273859 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_disable_endpoint.572153440 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 563003124 ps |
| CPU time | 2.12 seconds |
| Started | Feb 08 06:14:15 PM UTC 25 |
| Finished | Feb 08 06:14:18 PM UTC 25 |
| Peak memory | 217344 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=572153440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38 .usbdev_disable_endpoint.572153440 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_disconnected.4271904826 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 162046810 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 06:14:15 PM UTC 25 |
| Finished | Feb 08 06:14:17 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4271904826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.us bdev_disconnected.4271904826 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_enable.2215772764 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 63529632 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 06:14:16 PM UTC 25 |
| Finished | Feb 08 06:14:18 PM UTC 25 |
| Peak memory | 215016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2215772764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_e nable.2215772764 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_endpoint_access.3848564810 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 1013380234 ps |
| CPU time | 3.82 seconds |
| Started | Feb 08 06:14:16 PM UTC 25 |
| Finished | Feb 08 06:14:21 PM UTC 25 |
| Peak memory | 217488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3848564810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38 .usbdev_endpoint_access.3848564810 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_endpoint_types.1219334664 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 287627611 ps |
| CPU time | 1.96 seconds |
| Started | Feb 08 06:14:17 PM UTC 25 |
| Finished | Feb 08 06:14:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219334664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 38.usbdev_endpoint_types.1219334664 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_fifo_rst.142504511 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 273002331 ps |
| CPU time | 2.36 seconds |
| Started | Feb 08 06:14:18 PM UTC 25 |
| Finished | Feb 08 06:14:21 PM UTC 25 |
| Peak memory | 217552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=142504511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_ fifo_rst.142504511 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_in_iso.3685692582 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 255676954 ps |
| CPU time | 2.02 seconds |
| Started | Feb 08 06:14:18 PM UTC 25 |
| Finished | Feb 08 06:14:21 PM UTC 25 |
| Peak memory | 227756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685692582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 38.usbdev_in_iso.3685692582 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_in_stall.3257667677 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 144341887 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 06:14:18 PM UTC 25 |
| Finished | Feb 08 06:14:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3257667677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev _in_stall.3257667677 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_in_trans.3511196342 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 164547656 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 06:14:18 PM UTC 25 |
| Finished | Feb 08 06:14:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3511196342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev _in_trans.3511196342 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_invalid_sync.2634937395 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 3008068474 ps |
| CPU time | 85.69 seconds |
| Started | Feb 08 06:14:18 PM UTC 25 |
| Finished | Feb 08 06:15:45 PM UTC 25 |
| Peak memory | 227660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634937395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.2634937395 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_iso_retraction.3416891689 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 9952662318 ps |
| CPU time | 76.87 seconds |
| Started | Feb 08 06:14:18 PM UTC 25 |
| Finished | Feb 08 06:15:37 PM UTC 25 |
| Peak memory | 217612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416891689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 38.usbdev_iso_retraction.3416891689 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_link_in_err.2581951107 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 163572265 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:14:18 PM UTC 25 |
| Finished | Feb 08 06:14:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2581951107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usb dev_link_in_err.2581951107 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_link_resume.148634056 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 24253908407 ps |
| CPU time | 43.64 seconds |
| Started | Feb 08 06:14:18 PM UTC 25 |
| Finished | Feb 08 06:15:03 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=148634056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbd ev_link_resume.148634056 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_link_suspend.4161988765 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 4695270258 ps |
| CPU time | 8.53 seconds |
| Started | Feb 08 06:14:19 PM UTC 25 |
| Finished | Feb 08 06:14:29 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4161988765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.us bdev_link_suspend.4161988765 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_low_speed_traffic.2746683253 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 2415587287 ps |
| CPU time | 20.22 seconds |
| Started | Feb 08 06:14:19 PM UTC 25 |
| Finished | Feb 08 06:14:41 PM UTC 25 |
| Peak memory | 227584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746683253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 38.usbdev_low_speed_traffic.2746683253 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_max_inter_pkt_delay.1369204508 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 2092893976 ps |
| CPU time | 57.17 seconds |
| Started | Feb 08 06:14:20 PM UTC 25 |
| Finished | Feb 08 06:15:18 PM UTC 25 |
| Peak memory | 227828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369204508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.1369204508 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_max_length_in_transaction.2251961532 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 270038173 ps |
| CPU time | 1.94 seconds |
| Started | Feb 08 06:14:20 PM UTC 25 |
| Finished | Feb 08 06:14:23 PM UTC 25 |
| Peak memory | 214832 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251961532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 38.usbdev_max_length_in_transaction.2251961532 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_max_length_out_transaction.3983373843 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 217572147 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:14:20 PM UTC 25 |
| Finished | Feb 08 06:14:22 PM UTC 25 |
| Peak memory | 214788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3983373843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3983373843 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_min_inter_pkt_delay.346066842 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 2721683068 ps |
| CPU time | 26.58 seconds |
| Started | Feb 08 06:14:20 PM UTC 25 |
| Finished | Feb 08 06:14:48 PM UTC 25 |
| Peak memory | 229816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346066842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usb dev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.346066842 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_min_length_in_transaction.995180073 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 182432127 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:14:21 PM UTC 25 |
| Finished | Feb 08 06:14:24 PM UTC 25 |
| Peak memory | 215156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995180073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 38.usbdev_min_length_in_transaction.995180073 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_min_length_out_transaction.1817183088 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 168753408 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:14:21 PM UTC 25 |
| Finished | Feb 08 06:14:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1817183088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1817183088 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_nak_trans.4292858012 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 180018648 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:14:21 PM UTC 25 |
| Finished | Feb 08 06:14:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4292858012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbde v_nak_trans.4292858012 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_out_iso.3825361091 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 189801951 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:14:21 PM UTC 25 |
| Finished | Feb 08 06:14:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3825361091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_ out_iso.3825361091 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_out_stall.3564595923 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 180216954 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:14:21 PM UTC 25 |
| Finished | Feb 08 06:14:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3564595923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbde v_out_stall.3564595923 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_out_trans_nak.1189815448 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 182099007 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:14:22 PM UTC 25 |
| Finished | Feb 08 06:14:25 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1189815448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.u sbdev_out_trans_nak.1189815448 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_pending_in_trans.4280913850 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 149486171 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:14:23 PM UTC 25 |
| Finished | Feb 08 06:14:25 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4280913850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.usbdev_pending_in_trans.4280913850 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_phy_config_pinflip.1381573492 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 239486341 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 06:14:23 PM UTC 25 |
| Finished | Feb 08 06:14:25 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381573492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 38.usbdev_phy_config_pinflip.1381573492 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_phy_config_usb_ref_disable.2697283609 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 174040349 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:14:23 PM UTC 25 |
| Finished | Feb 08 06:14:25 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2697283609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.2697283609 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_phy_pins_sense.2465477585 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 35218282 ps |
| CPU time | 0.89 seconds |
| Started | Feb 08 06:14:24 PM UTC 25 |
| Finished | Feb 08 06:14:26 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2465477585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38. usbdev_phy_pins_sense.2465477585 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_pkt_buffer.3703919903 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 16743891725 ps |
| CPU time | 44.87 seconds |
| Started | Feb 08 06:14:24 PM UTC 25 |
| Finished | Feb 08 06:15:10 PM UTC 25 |
| Peak memory | 227684 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3703919903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbd ev_pkt_buffer.3703919903 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_pkt_received.2634859137 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 187821136 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:14:24 PM UTC 25 |
| Finished | Feb 08 06:14:27 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2634859137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.us bdev_pkt_received.2634859137 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_pkt_sent.1096069995 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 230952498 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:14:24 PM UTC 25 |
| Finished | Feb 08 06:14:27 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1096069995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev _pkt_sent.1096069995 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_random_length_in_transaction.2989880444 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 193421001 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:14:26 PM UTC 25 |
| Finished | Feb 08 06:14:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2989880444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.u sbdev_random_length_in_transaction.2989880444 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_random_length_out_transaction.3839994898 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 237060106 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:14:26 PM UTC 25 |
| Finished | Feb 08 06:14:29 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3839994898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 38.usbdev_random_length_out_transaction.3839994898 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_rx_crc_err.3904741738 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 173016763 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:14:26 PM UTC 25 |
| Finished | Feb 08 06:14:28 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3904741738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbd ev_rx_crc_err.3904741738 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_rx_full.577360440 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 291643702 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:14:26 PM UTC 25 |
| Finished | Feb 08 06:14:29 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=577360440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_r x_full.577360440 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_setup_stage.3513936089 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 201829637 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:14:26 PM UTC 25 |
| Finished | Feb 08 06:14:29 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3513936089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usb dev_setup_stage.3513936089 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_setup_trans_ignored.1009656794 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 153031699 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 06:14:26 PM UTC 25 |
| Finished | Feb 08 06:14:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1009656794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 38.usbdev_setup_trans_ignored.1009656794 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_smoke.1202549190 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 239173746 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:14:26 PM UTC 25 |
| Finished | Feb 08 06:14:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1202549190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_sm oke.1202549190 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_spurious_pids_ignored.2132800455 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 1927961509 ps |
| CPU time | 52.63 seconds |
| Started | Feb 08 06:14:26 PM UTC 25 |
| Finished | Feb 08 06:15:20 PM UTC 25 |
| Peak memory | 234488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132800455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 38.usbdev_spurious_pids_ignored.2132800455 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_stall_priority_over_nak.554426464 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 178007603 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:14:28 PM UTC 25 |
| Finished | Feb 08 06:14:31 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=554426464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 38.usbdev_stall_priority_over_nak.554426464 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_stall_trans.300226384 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 161974023 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:14:28 PM UTC 25 |
| Finished | Feb 08 06:14:30 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=300226384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbd ev_stall_trans.300226384 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_stream_len_max.3541793156 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 1158771890 ps |
| CPU time | 4.73 seconds |
| Started | Feb 08 06:14:28 PM UTC 25 |
| Finished | Feb 08 06:14:34 PM UTC 25 |
| Peak memory | 217344 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3541793156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38. usbdev_stream_len_max.3541793156 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_streaming_out.4011790412 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 2140487702 ps |
| CPU time | 57.23 seconds |
| Started | Feb 08 06:14:28 PM UTC 25 |
| Finished | Feb 08 06:15:27 PM UTC 25 |
| Peak memory | 227852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4011790412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbde v_streaming_out.4011790412 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_timeout_missing_host_handshake.154262517 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 4248085158 ps |
| CPU time | 29.33 seconds |
| Started | Feb 08 06:14:14 PM UTC 25 |
| Finished | Feb 08 06:14:44 PM UTC 25 |
| Peak memory | 217612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154262517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_host_handshake.154262517 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_tx_rx_disruption.4149517810 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 580199065 ps |
| CPU time | 2.54 seconds |
| Started | Feb 08 06:14:28 PM UTC 25 |
| Finished | Feb 08 06:14:32 PM UTC 25 |
| Peak memory | 217308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 149517810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_tx_rx_disruption.4149517810 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/38.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/380.usbdev_tx_rx_disruption.3550325562 |
| Short name | T3506 |
| Test name | |
| Test status | |
| Simulation time | 457115386 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:19:46 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 550325562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 380.usbdev_tx_rx_disruption.3550325562 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/380.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/381.usbdev_tx_rx_disruption.2190714966 |
| Short name | T3463 |
| Test name | |
| Test status | |
| Simulation time | 477951769 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:19:48 PM UTC 25 |
| Finished | Feb 08 06:19:54 PM UTC 25 |
| Peak memory | 214724 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 190714966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 381.usbdev_tx_rx_disruption.2190714966 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/381.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/382.usbdev_tx_rx_disruption.3517838572 |
| Short name | T3464 |
| Test name | |
| Test status | |
| Simulation time | 527161251 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:19:48 PM UTC 25 |
| Finished | Feb 08 06:19:54 PM UTC 25 |
| Peak memory | 214808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 517838572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 382.usbdev_tx_rx_disruption.3517838572 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/382.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/383.usbdev_tx_rx_disruption.731962080 |
| Short name | T3485 |
| Test name | |
| Test status | |
| Simulation time | 601291324 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:19:50 PM UTC 25 |
| Finished | Feb 08 06:20:03 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 31962080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 383.usbdev_tx_rx_disruption.731962080 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/383.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/384.usbdev_tx_rx_disruption.2661215316 |
| Short name | T3484 |
| Test name | |
| Test status | |
| Simulation time | 532387606 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:19:50 PM UTC 25 |
| Finished | Feb 08 06:20:03 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 661215316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 384.usbdev_tx_rx_disruption.2661215316 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/384.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/385.usbdev_tx_rx_disruption.1473036897 |
| Short name | T3482 |
| Test name | |
| Test status | |
| Simulation time | 478269518 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:19:50 PM UTC 25 |
| Finished | Feb 08 06:20:03 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 473036897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 385.usbdev_tx_rx_disruption.1473036897 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/385.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/386.usbdev_tx_rx_disruption.2550307398 |
| Short name | T3460 |
| Test name | |
| Test status | |
| Simulation time | 528268278 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:19:50 PM UTC 25 |
| Finished | Feb 08 06:19:53 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 550307398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 386.usbdev_tx_rx_disruption.2550307398 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/386.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/387.usbdev_tx_rx_disruption.970818892 |
| Short name | T3459 |
| Test name | |
| Test status | |
| Simulation time | 553044942 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:19:50 PM UTC 25 |
| Finished | Feb 08 06:19:53 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 70818892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 387.usbdev_tx_rx_disruption.970818892 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/387.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/388.usbdev_tx_rx_disruption.1816248611 |
| Short name | T3461 |
| Test name | |
| Test status | |
| Simulation time | 512750283 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:19:50 PM UTC 25 |
| Finished | Feb 08 06:19:53 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 816248611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 388.usbdev_tx_rx_disruption.1816248611 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/388.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/389.usbdev_tx_rx_disruption.1052377219 |
| Short name | T3530 |
| Test name | |
| Test status | |
| Simulation time | 512082701 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:19:54 PM UTC 25 |
| Finished | Feb 08 06:20:11 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 052377219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 389.usbdev_tx_rx_disruption.1052377219 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/389.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_alert_test.552488523 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 54687987 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:14:45 PM UTC 25 |
| Finished | Feb 08 06:14:47 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552488523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 39.usbdev_alert_test.552488523 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_aon_wake_disconnect.1865678489 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 9300291508 ps |
| CPU time | 11.74 seconds |
| Started | Feb 08 06:14:28 PM UTC 25 |
| Finished | Feb 08 06:14:41 PM UTC 25 |
| Peak memory | 217380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865678489 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.1865678489 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_aon_wake_reset.807254683 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 14033597353 ps |
| CPU time | 23.96 seconds |
| Started | Feb 08 06:14:29 PM UTC 25 |
| Finished | Feb 08 06:14:55 PM UTC 25 |
| Peak memory | 227500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807254683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TE ST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.807254683 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_aon_wake_resume.3336147245 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 24865350408 ps |
| CPU time | 40.36 seconds |
| Started | Feb 08 06:14:30 PM UTC 25 |
| Finished | Feb 08 06:15:11 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336147245 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.3336147245 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_av_buffer.1833024597 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 226314662 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:14:30 PM UTC 25 |
| Finished | Feb 08 06:14:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1833024597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbde v_av_buffer.1833024597 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_bitstuff_err.404602483 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 146737721 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 06:14:30 PM UTC 25 |
| Finished | Feb 08 06:14:32 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=404602483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usb dev_bitstuff_err.404602483 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_data_toggle_clear.2705789797 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 312927930 ps |
| CPU time | 2.09 seconds |
| Started | Feb 08 06:14:30 PM UTC 25 |
| Finished | Feb 08 06:14:33 PM UTC 25 |
| Peak memory | 217104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2705789797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.2705789797 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_data_toggle_restore.2931092045 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 538651631 ps |
| CPU time | 2.65 seconds |
| Started | Feb 08 06:14:30 PM UTC 25 |
| Finished | Feb 08 06:14:33 PM UTC 25 |
| Peak memory | 217164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931092045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.2931092045 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_device_address.2869308912 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 26114600304 ps |
| CPU time | 46.42 seconds |
| Started | Feb 08 06:14:30 PM UTC 25 |
| Finished | Feb 08 06:15:18 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2869308912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39. usbdev_device_address.2869308912 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_device_timeout.23132754 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 199422434 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:14:31 PM UTC 25 |
| Finished | Feb 08 06:14:34 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23132754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UV M_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.23132754 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_disable_endpoint.1312435061 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 704804723 ps |
| CPU time | 2.19 seconds |
| Started | Feb 08 06:14:31 PM UTC 25 |
| Finished | Feb 08 06:14:35 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1312435061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.usbdev_disable_endpoint.1312435061 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_disconnected.3039156496 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 159267050 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 06:14:31 PM UTC 25 |
| Finished | Feb 08 06:14:34 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3039156496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.us bdev_disconnected.3039156496 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_enable.1459597224 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 46407498 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:14:31 PM UTC 25 |
| Finished | Feb 08 06:14:34 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1459597224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_e nable.1459597224 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_endpoint_access.2107738159 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 907296304 ps |
| CPU time | 3.3 seconds |
| Started | Feb 08 06:14:33 PM UTC 25 |
| Finished | Feb 08 06:14:37 PM UTC 25 |
| Peak memory | 217516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2107738159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39 .usbdev_endpoint_access.2107738159 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_endpoint_types.3045693275 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 197623204 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:14:33 PM UTC 25 |
| Finished | Feb 08 06:14:35 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045693275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 39.usbdev_endpoint_types.3045693275 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_fifo_rst.1283183320 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 247748929 ps |
| CPU time | 1.72 seconds |
| Started | Feb 08 06:14:33 PM UTC 25 |
| Finished | Feb 08 06:14:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1283183320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev _fifo_rst.1283183320 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_in_iso.1988970851 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 164394257 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:14:33 PM UTC 25 |
| Finished | Feb 08 06:14:35 PM UTC 25 |
| Peak memory | 215068 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988970851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 39.usbdev_in_iso.1988970851 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_in_stall.218878685 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 142375939 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:14:33 PM UTC 25 |
| Finished | Feb 08 06:14:35 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=218878685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_ in_stall.218878685 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_in_trans.3710248662 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 257206351 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:14:34 PM UTC 25 |
| Finished | Feb 08 06:14:37 PM UTC 25 |
| Peak memory | 214916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3710248662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev _in_trans.3710248662 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_invalid_sync.2034598841 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 5148992730 ps |
| CPU time | 42.12 seconds |
| Started | Feb 08 06:14:33 PM UTC 25 |
| Finished | Feb 08 06:15:16 PM UTC 25 |
| Peak memory | 234484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034598841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.2034598841 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_iso_retraction.3088002127 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 8296370844 ps |
| CPU time | 116.36 seconds |
| Started | Feb 08 06:14:34 PM UTC 25 |
| Finished | Feb 08 06:16:33 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088002127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 39.usbdev_iso_retraction.3088002127 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_link_in_err.3667855467 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 224321726 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:14:34 PM UTC 25 |
| Finished | Feb 08 06:14:37 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3667855467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usb dev_link_in_err.3667855467 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_link_resume.134400772 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 30216553179 ps |
| CPU time | 70.84 seconds |
| Started | Feb 08 06:14:34 PM UTC 25 |
| Finished | Feb 08 06:15:47 PM UTC 25 |
| Peak memory | 217384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=134400772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbd ev_link_resume.134400772 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_link_suspend.1574224678 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 9831088997 ps |
| CPU time | 16.39 seconds |
| Started | Feb 08 06:14:36 PM UTC 25 |
| Finished | Feb 08 06:14:54 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1574224678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.us bdev_link_suspend.1574224678 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_low_speed_traffic.362437974 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 2364016297 ps |
| CPU time | 19.56 seconds |
| Started | Feb 08 06:14:36 PM UTC 25 |
| Finished | Feb 08 06:14:57 PM UTC 25 |
| Peak memory | 229704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362437974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed _traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 39.usbdev_low_speed_traffic.362437974 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_max_inter_pkt_delay.1429901759 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 2080114376 ps |
| CPU time | 54.76 seconds |
| Started | Feb 08 06:14:36 PM UTC 25 |
| Finished | Feb 08 06:15:32 PM UTC 25 |
| Peak memory | 227728 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429901759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.1429901759 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_max_length_in_transaction.3218347957 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 260433375 ps |
| CPU time | 1.88 seconds |
| Started | Feb 08 06:14:36 PM UTC 25 |
| Finished | Feb 08 06:14:39 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218347957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 39.usbdev_max_length_in_transaction.3218347957 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_max_length_out_transaction.1212253590 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 192153497 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:14:36 PM UTC 25 |
| Finished | Feb 08 06:14:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1212253590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1212253590 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_min_inter_pkt_delay.1921381798 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 2821239427 ps |
| CPU time | 89.66 seconds |
| Started | Feb 08 06:14:36 PM UTC 25 |
| Finished | Feb 08 06:16:08 PM UTC 25 |
| Peak memory | 227664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921381798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.1921381798 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_min_length_in_transaction.2702906437 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 161789217 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:14:36 PM UTC 25 |
| Finished | Feb 08 06:14:39 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702906437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 39.usbdev_min_length_in_transaction.2702906437 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_min_length_out_transaction.459534254 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 185653136 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:14:36 PM UTC 25 |
| Finished | Feb 08 06:14:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=459534254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 39.usbdev_min_length_out_transaction.459534254 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_out_iso.2232672345 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 163157138 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:14:37 PM UTC 25 |
| Finished | Feb 08 06:14:40 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2232672345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_ out_iso.2232672345 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_out_stall.3372459743 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 184305691 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 06:14:37 PM UTC 25 |
| Finished | Feb 08 06:14:40 PM UTC 25 |
| Peak memory | 214832 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3372459743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbde v_out_stall.3372459743 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_out_trans_nak.2969251981 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 218232595 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:14:38 PM UTC 25 |
| Finished | Feb 08 06:14:40 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2969251981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.u sbdev_out_trans_nak.2969251981 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_pending_in_trans.3986562904 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 177551125 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:14:38 PM UTC 25 |
| Finished | Feb 08 06:14:40 PM UTC 25 |
| Peak memory | 214940 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3986562904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.usbdev_pending_in_trans.3986562904 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_phy_config_pinflip.106580820 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 221129117 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:14:39 PM UTC 25 |
| Finished | Feb 08 06:14:41 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=106580820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 39.usbdev_phy_config_pinflip.106580820 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_phy_config_usb_ref_disable.3961584859 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 143570537 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 06:14:40 PM UTC 25 |
| Finished | Feb 08 06:14:43 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3961584859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3961584859 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_phy_pins_sense.2245147247 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 43026649 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 06:14:40 PM UTC 25 |
| Finished | Feb 08 06:14:42 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2245147247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39. usbdev_phy_pins_sense.2245147247 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_pkt_buffer.1571870882 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 7883816156 ps |
| CPU time | 26.71 seconds |
| Started | Feb 08 06:14:40 PM UTC 25 |
| Finished | Feb 08 06:15:08 PM UTC 25 |
| Peak memory | 227892 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1571870882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbd ev_pkt_buffer.1571870882 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_pkt_received.80939136 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 210845401 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:14:40 PM UTC 25 |
| Finished | Feb 08 06:14:43 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=80939136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbd ev_pkt_received.80939136 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_pkt_sent.4249378872 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 222735112 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:14:40 PM UTC 25 |
| Finished | Feb 08 06:14:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4249378872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev _pkt_sent.4249378872 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_random_length_in_transaction.3386814617 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 263948472 ps |
| CPU time | 1.91 seconds |
| Started | Feb 08 06:14:42 PM UTC 25 |
| Finished | Feb 08 06:14:45 PM UTC 25 |
| Peak memory | 214996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3386814617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.u sbdev_random_length_in_transaction.3386814617 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_random_length_out_transaction.42765325 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 220344789 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:14:42 PM UTC 25 |
| Finished | Feb 08 06:14:44 PM UTC 25 |
| Peak memory | 214984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=42765325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.42765325 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_rx_crc_err.1247390075 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 159189238 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:14:42 PM UTC 25 |
| Finished | Feb 08 06:14:44 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1247390075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbd ev_rx_crc_err.1247390075 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_rx_full.2972711012 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 398843255 ps |
| CPU time | 1.79 seconds |
| Started | Feb 08 06:14:42 PM UTC 25 |
| Finished | Feb 08 06:14:45 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2972711012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_ rx_full.2972711012 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_setup_stage.2583157960 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 146314862 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:14:42 PM UTC 25 |
| Finished | Feb 08 06:14:44 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2583157960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usb dev_setup_stage.2583157960 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_setup_trans_ignored.1403970038 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 154285673 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:14:43 PM UTC 25 |
| Finished | Feb 08 06:14:46 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1403970038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 39.usbdev_setup_trans_ignored.1403970038 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_smoke.375781725 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 252831324 ps |
| CPU time | 1.8 seconds |
| Started | Feb 08 06:14:43 PM UTC 25 |
| Finished | Feb 08 06:14:46 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=375781725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smo ke.375781725 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_spurious_pids_ignored.3552752121 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 2620077775 ps |
| CPU time | 26.99 seconds |
| Started | Feb 08 06:14:43 PM UTC 25 |
| Finished | Feb 08 06:15:12 PM UTC 25 |
| Peak memory | 229644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552752121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 39.usbdev_spurious_pids_ignored.3552752121 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_stall_priority_over_nak.1865421505 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 185044773 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:14:43 PM UTC 25 |
| Finished | Feb 08 06:14:46 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1865421505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 39.usbdev_stall_priority_over_nak.1865421505 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_stall_trans.1399220848 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 149068941 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:14:43 PM UTC 25 |
| Finished | Feb 08 06:14:46 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1399220848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usb dev_stall_trans.1399220848 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_stream_len_max.154509068 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 1144415100 ps |
| CPU time | 5.21 seconds |
| Started | Feb 08 06:14:43 PM UTC 25 |
| Finished | Feb 08 06:14:50 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=154509068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.u sbdev_stream_len_max.154509068 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_streaming_out.65158617 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 3403471926 ps |
| CPU time | 97.07 seconds |
| Started | Feb 08 06:14:43 PM UTC 25 |
| Finished | Feb 08 06:16:23 PM UTC 25 |
| Peak memory | 227856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=65158617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_ streaming_out.65158617 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_timeout_missing_host_handshake.1931643510 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 1999079951 ps |
| CPU time | 18.01 seconds |
| Started | Feb 08 06:14:31 PM UTC 25 |
| Finished | Feb 08 06:14:51 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931643510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_host_handshake.1931643510 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_tx_rx_disruption.3676381612 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 465998507 ps |
| CPU time | 2.34 seconds |
| Started | Feb 08 06:14:45 PM UTC 25 |
| Finished | Feb 08 06:14:48 PM UTC 25 |
| Peak memory | 216576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 676381612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_tx_rx_disruption.3676381612 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/39.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/390.usbdev_tx_rx_disruption.23142068 |
| Short name | T3536 |
| Test name | |
| Test status | |
| Simulation time | 605596767 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:19:54 PM UTC 25 |
| Finished | Feb 08 06:20:11 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 3142068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 390.usbdev_tx_rx_disruption.23142068 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/390.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/391.usbdev_tx_rx_disruption.1461011187 |
| Short name | T3539 |
| Test name | |
| Test status | |
| Simulation time | 675813507 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 06:19:54 PM UTC 25 |
| Finished | Feb 08 06:20:12 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 461011187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 391.usbdev_tx_rx_disruption.1461011187 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/391.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/392.usbdev_tx_rx_disruption.3555109462 |
| Short name | T3508 |
| Test name | |
| Test status | |
| Simulation time | 481192684 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:19:55 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 555109462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 392.usbdev_tx_rx_disruption.3555109462 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/392.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/393.usbdev_tx_rx_disruption.1224111586 |
| Short name | T3512 |
| Test name | |
| Test status | |
| Simulation time | 521333228 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:19:55 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 224111586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 393.usbdev_tx_rx_disruption.1224111586 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/393.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/394.usbdev_tx_rx_disruption.3320214465 |
| Short name | T3516 |
| Test name | |
| Test status | |
| Simulation time | 630975683 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:19:55 PM UTC 25 |
| Finished | Feb 08 06:20:10 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 320214465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 394.usbdev_tx_rx_disruption.3320214465 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/394.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/395.usbdev_tx_rx_disruption.1526747820 |
| Short name | T3513 |
| Test name | |
| Test status | |
| Simulation time | 504330999 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:19:55 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 526747820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 395.usbdev_tx_rx_disruption.1526747820 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/395.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/396.usbdev_tx_rx_disruption.3886742594 |
| Short name | T3509 |
| Test name | |
| Test status | |
| Simulation time | 462570031 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:19:55 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 886742594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 396.usbdev_tx_rx_disruption.3886742594 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/396.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/397.usbdev_tx_rx_disruption.1672513189 |
| Short name | T3507 |
| Test name | |
| Test status | |
| Simulation time | 556290309 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:19:55 PM UTC 25 |
| Finished | Feb 08 06:20:09 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 672513189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 397.usbdev_tx_rx_disruption.1672513189 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/397.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/398.usbdev_tx_rx_disruption.839420899 |
| Short name | T3518 |
| Test name | |
| Test status | |
| Simulation time | 597163612 ps |
| CPU time | 1.74 seconds |
| Started | Feb 08 06:19:56 PM UTC 25 |
| Finished | Feb 08 06:20:10 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 39420899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 398.usbdev_tx_rx_disruption.839420899 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/398.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/399.usbdev_tx_rx_disruption.1579846031 |
| Short name | T3525 |
| Test name | |
| Test status | |
| Simulation time | 574389584 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:20:00 PM UTC 25 |
| Finished | Feb 08 06:20:11 PM UTC 25 |
| Peak memory | 214740 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 579846031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 399.usbdev_tx_rx_disruption.1579846031 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/399.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_alert_test.3793670538 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 42387856 ps |
| CPU time | 1.02 seconds |
| Started | Feb 08 05:59:41 PM UTC 25 |
| Finished | Feb 08 05:59:43 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793670538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 4.usbdev_alert_test.3793670538 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_aon_wake_disconnect.3453987084 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 5014915590 ps |
| CPU time | 9.3 seconds |
| Started | Feb 08 05:58:36 PM UTC 25 |
| Finished | Feb 08 05:58:46 PM UTC 25 |
| Peak memory | 227660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453987084 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.3453987084 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_aon_wake_reset.1546334250 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 14750093583 ps |
| CPU time | 34.05 seconds |
| Started | Feb 08 05:58:36 PM UTC 25 |
| Finished | Feb 08 05:59:11 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546334250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.1546334250 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_aon_wake_resume.2090420140 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 29601506169 ps |
| CPU time | 37.44 seconds |
| Started | Feb 08 05:58:36 PM UTC 25 |
| Finished | Feb 08 05:59:14 PM UTC 25 |
| Peak memory | 217440 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090420140 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.2090420140 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_av_buffer.3850447738 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 153503871 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 05:58:38 PM UTC 25 |
| Finished | Feb 08 05:58:40 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3850447738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev _av_buffer.3850447738 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_av_empty.3204257983 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 163523141 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 05:58:38 PM UTC 25 |
| Finished | Feb 08 05:58:41 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3204257983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ av_empty.3204257983 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_av_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_av_overflow.633651851 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 146359062 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 05:58:39 PM UTC 25 |
| Finished | Feb 08 05:58:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=633651851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbde v_av_overflow.633651851 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_av_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_bitstuff_err.843775918 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 169252163 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 05:58:39 PM UTC 25 |
| Finished | Feb 08 05:58:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=843775918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbd ev_bitstuff_err.843775918 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_data_toggle_clear.2913597376 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 270592348 ps |
| CPU time | 2.11 seconds |
| Started | Feb 08 05:58:41 PM UTC 25 |
| Finished | Feb 08 05:58:45 PM UTC 25 |
| Peak memory | 217112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2913597376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.2913597376 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_data_toggle_restore.2024744535 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 680611948 ps |
| CPU time | 3.36 seconds |
| Started | Feb 08 05:58:41 PM UTC 25 |
| Finished | Feb 08 05:58:46 PM UTC 25 |
| Peak memory | 217112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024744535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.2024744535 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_device_address.950537220 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 43966059844 ps |
| CPU time | 99.96 seconds |
| Started | Feb 08 05:58:42 PM UTC 25 |
| Finished | Feb 08 06:00:24 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=950537220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.us bdev_device_address.950537220 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_device_timeout.3251745680 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 699486384 ps |
| CPU time | 20.63 seconds |
| Started | Feb 08 05:58:43 PM UTC 25 |
| Finished | Feb 08 05:59:05 PM UTC 25 |
| Peak memory | 217404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251745680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.3251745680 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_disable_endpoint.101976255 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 610384517 ps |
| CPU time | 2.21 seconds |
| Started | Feb 08 05:58:44 PM UTC 25 |
| Finished | Feb 08 05:58:48 PM UTC 25 |
| Peak memory | 217276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=101976255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4. usbdev_disable_endpoint.101976255 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_disconnected.3004087806 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 141204903 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 05:58:44 PM UTC 25 |
| Finished | Feb 08 05:58:47 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3004087806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usb dev_disconnected.3004087806 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_enable.1955619984 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 47055140 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 05:58:45 PM UTC 25 |
| Finished | Feb 08 05:58:48 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1955619984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_en able.1955619984 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_endpoint_access.1506025993 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 932251745 ps |
| CPU time | 3.6 seconds |
| Started | Feb 08 05:58:48 PM UTC 25 |
| Finished | Feb 08 05:58:52 PM UTC 25 |
| Peak memory | 217308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1506025993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4. usbdev_endpoint_access.1506025993 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_endpoint_types.1148188053 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 335697148 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 05:58:48 PM UTC 25 |
| Finished | Feb 08 05:58:50 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148188053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 4.usbdev_endpoint_types.1148188053 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_fifo_rst.2200540321 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 172792807 ps |
| CPU time | 2.19 seconds |
| Started | Feb 08 05:58:48 PM UTC 25 |
| Finished | Feb 08 05:58:51 PM UTC 25 |
| Peak memory | 217344 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2200540321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ fifo_rst.2200540321 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_freq_hiclk.3049033865 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 95181638752 ps |
| CPU time | 198.47 seconds |
| Started | Feb 08 05:58:49 PM UTC 25 |
| Finished | Feb 08 06:02:11 PM UTC 25 |
| Peak memory | 217424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049033865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phas e_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 4.usbdev_freq_hiclk.3049033865 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_freq_hiclk/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_freq_hiclk_max.2971184066 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 94349859476 ps |
| CPU time | 197.38 seconds |
| Started | Feb 08 05:58:49 PM UTC 25 |
| Finished | Feb 08 06:02:10 PM UTC 25 |
| Peak memory | 217424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_track ing=1 +reset_recovery=1 +usb_freq_delta=+120000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2971184066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hi clk_max.2971184066 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_freq_hiclk_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_freq_loclk.909910120 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 103143818226 ps |
| CPU time | 261.8 seconds |
| Started | Feb 08 05:58:49 PM UTC 25 |
| Finished | Feb 08 06:03:15 PM UTC 25 |
| Peak memory | 217532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909910120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase _delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 4.usbdev_freq_loclk.909910120 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_freq_loclk/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_freq_loclk_max.3491304996 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 105129970413 ps |
| CPU time | 185.63 seconds |
| Started | Feb 08 05:58:49 PM UTC 25 |
| Finished | Feb 08 06:01:58 PM UTC 25 |
| Peak memory | 217416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+1 20000 +reset_recovery=1 +usb_freq_delta=-120000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3491304996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_lo clk_max.3491304996 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_freq_loclk_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_freq_phase.1190098172 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 116137857433 ps |
| CPU time | 239.08 seconds |
| Started | Feb 08 05:58:51 PM UTC 25 |
| Finished | Feb 08 06:02:53 PM UTC 25 |
| Peak memory | 217468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1190098172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 .usbdev_freq_phase.1190098172 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_freq_phase/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_in_iso.3617747299 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 195047074 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 05:58:52 PM UTC 25 |
| Finished | Feb 08 05:58:55 PM UTC 25 |
| Peak memory | 227748 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617747299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 4.usbdev_in_iso.3617747299 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_in_stall.2354994095 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 150204225 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 05:58:53 PM UTC 25 |
| Finished | Feb 08 05:58:56 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2354994095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ in_stall.2354994095 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_in_trans.3334355562 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 179260753 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 05:58:55 PM UTC 25 |
| Finished | Feb 08 05:58:58 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3334355562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ in_trans.3334355562 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_invalid_sync.3852824274 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 5219607908 ps |
| CPU time | 176.29 seconds |
| Started | Feb 08 05:58:51 PM UTC 25 |
| Finished | Feb 08 06:01:50 PM UTC 25 |
| Peak memory | 229712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852824274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.3852824274 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_iso_retraction.2905139045 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 7582213525 ps |
| CPU time | 64.99 seconds |
| Started | Feb 08 05:58:56 PM UTC 25 |
| Finished | Feb 08 06:00:03 PM UTC 25 |
| Peak memory | 217416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905139045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 4.usbdev_iso_retraction.2905139045 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_link_in_err.752889374 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 208858597 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 05:58:58 PM UTC 25 |
| Finished | Feb 08 05:59:01 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=752889374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbde v_link_in_err.752889374 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_link_resume.2420501181 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 7635916852 ps |
| CPU time | 29.53 seconds |
| Started | Feb 08 05:59:02 PM UTC 25 |
| Finished | Feb 08 05:59:32 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2420501181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbd ev_link_resume.2420501181 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_link_suspend.2857213277 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 8702235324 ps |
| CPU time | 26.93 seconds |
| Started | Feb 08 05:59:04 PM UTC 25 |
| Finished | Feb 08 05:59:32 PM UTC 25 |
| Peak memory | 217452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2857213277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usb dev_link_suspend.2857213277 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_low_speed_traffic.3095063272 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 3020540194 ps |
| CPU time | 86.11 seconds |
| Started | Feb 08 05:59:06 PM UTC 25 |
| Finished | Feb 08 06:00:34 PM UTC 25 |
| Peak memory | 229712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095063272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 4.usbdev_low_speed_traffic.3095063272 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_max_inter_pkt_delay.1827990362 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 1970062119 ps |
| CPU time | 20.28 seconds |
| Started | Feb 08 05:59:08 PM UTC 25 |
| Finished | Feb 08 05:59:30 PM UTC 25 |
| Peak memory | 229684 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827990362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.1827990362 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_max_length_in_transaction.2560819797 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 283623141 ps |
| CPU time | 1.97 seconds |
| Started | Feb 08 05:59:08 PM UTC 25 |
| Finished | Feb 08 05:59:11 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560819797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 4.usbdev_max_length_in_transaction.2560819797 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_max_length_out_transaction.3210526922 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 223963879 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 05:59:08 PM UTC 25 |
| Finished | Feb 08 05:59:11 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3210526922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.3210526922 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_max_non_iso_usb_traffic.221420509 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 2775993059 ps |
| CPU time | 26.31 seconds |
| Started | Feb 08 05:59:09 PM UTC 25 |
| Finished | Feb 08 05:59:37 PM UTC 25 |
| Peak memory | 229760 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=221420509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 4.usbdev_max_non_iso_usb_traffic.221420509 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_max_usb_traffic.703811410 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 2332809664 ps |
| CPU time | 22.24 seconds |
| Started | Feb 08 05:59:12 PM UTC 25 |
| Finished | Feb 08 05:59:35 PM UTC 25 |
| Peak memory | 229768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703811410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_t raffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 4.usbdev_max_usb_traffic.703811410 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_min_inter_pkt_delay.2165132023 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 2896128984 ps |
| CPU time | 23.95 seconds |
| Started | Feb 08 05:59:12 PM UTC 25 |
| Finished | Feb 08 05:59:37 PM UTC 25 |
| Peak memory | 229700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165132023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.2165132023 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_min_length_in_transaction.1504980373 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 153047379 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 05:59:12 PM UTC 25 |
| Finished | Feb 08 05:59:14 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504980373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 4.usbdev_min_length_in_transaction.1504980373 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_min_length_out_transaction.81956413 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 149270296 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 05:59:12 PM UTC 25 |
| Finished | Feb 08 05:59:14 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=81956413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 4.usbdev_min_length_out_transaction.81956413 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_nak_trans.1610528658 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 214988415 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 05:59:12 PM UTC 25 |
| Finished | Feb 08 05:59:15 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1610528658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev _nak_trans.1610528658 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_out_iso.2831273871 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 241547279 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 05:59:15 PM UTC 25 |
| Finished | Feb 08 05:59:18 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2831273871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_o ut_iso.2831273871 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_out_stall.3514876537 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 185232858 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 05:59:15 PM UTC 25 |
| Finished | Feb 08 05:59:18 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3514876537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev _out_stall.3514876537 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_out_trans_nak.3615522436 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 159200540 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 05:59:15 PM UTC 25 |
| Finished | Feb 08 05:59:18 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3615522436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.us bdev_out_trans_nak.3615522436 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_pending_in_trans.2613708839 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 145097408 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 05:59:15 PM UTC 25 |
| Finished | Feb 08 05:59:18 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2613708839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 .usbdev_pending_in_trans.2613708839 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_phy_config_pinflip.2096406873 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 199447670 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 05:59:19 PM UTC 25 |
| Finished | Feb 08 05:59:22 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096406873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 4.usbdev_phy_config_pinflip.2096406873 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_phy_config_rand_bus_type.2451721347 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 222827339 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 05:59:19 PM UTC 25 |
| Finished | Feb 08 05:59:22 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2451721347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 4.usbdev_phy_config_rand_bus_type.2451721347 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_phy_config_rand_bus_type/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_phy_config_usb_ref_disable.2120660240 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 141457465 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 05:59:19 PM UTC 25 |
| Finished | Feb 08 05:59:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2120660240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2120660240 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_phy_pins_sense.2533605673 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 36328505 ps |
| CPU time | 1 seconds |
| Started | Feb 08 05:59:19 PM UTC 25 |
| Finished | Feb 08 05:59:21 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2533605673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.u sbdev_phy_pins_sense.2533605673 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_pkt_buffer.3331457217 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 15849792795 ps |
| CPU time | 60.7 seconds |
| Started | Feb 08 05:59:22 PM UTC 25 |
| Finished | Feb 08 06:00:25 PM UTC 25 |
| Peak memory | 227880 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3331457217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbde v_pkt_buffer.3331457217 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_pkt_received.754512226 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 167037596 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 05:59:22 PM UTC 25 |
| Finished | Feb 08 05:59:25 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=754512226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbd ev_pkt_received.754512226 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_pkt_sent.2039110488 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 219400985 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 05:59:22 PM UTC 25 |
| Finished | Feb 08 05:59:25 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2039110488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ pkt_sent.2039110488 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_rand_bus_disconnects.3969899505 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 2712774448 ps |
| CPU time | 34.47 seconds |
| Started | Feb 08 05:59:26 PM UTC 25 |
| Finished | Feb 08 06:00:02 PM UTC 25 |
| Peak memory | 229768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969899505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_ TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.3969899505 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_rand_bus_disconnects/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_rand_bus_resets.2527081559 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 3345377383 ps |
| CPU time | 78.85 seconds |
| Started | Feb 08 05:59:26 PM UTC 25 |
| Finished | Feb 08 06:00:47 PM UTC 25 |
| Peak memory | 229828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527081559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 4.usbdev_rand_bus_resets.2527081559 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_rand_bus_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_rand_suspends.2604519376 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 9591636985 ps |
| CPU time | 163.44 seconds |
| Started | Feb 08 05:59:26 PM UTC 25 |
| Finished | Feb 08 06:02:12 PM UTC 25 |
| Peak memory | 229968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604519376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_ TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.2604519376 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_rand_suspends/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_random_length_in_transaction.1960653506 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 182090536 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 05:59:22 PM UTC 25 |
| Finished | Feb 08 05:59:25 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1960653506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.us bdev_random_length_in_transaction.1960653506 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_random_length_out_transaction.3181804942 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 166943877 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 05:59:26 PM UTC 25 |
| Finished | Feb 08 05:59:28 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3181804942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 4.usbdev_random_length_out_transaction.3181804942 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_resume_link_active.249500302 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 20179348861 ps |
| CPU time | 31.05 seconds |
| Started | Feb 08 05:59:30 PM UTC 25 |
| Finished | Feb 08 06:00:02 PM UTC 25 |
| Peak memory | 217208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=249500302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_resume_link_active.249500302 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_resume_link_active/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_rx_crc_err.3873743961 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 160803889 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 05:59:30 PM UTC 25 |
| Finished | Feb 08 05:59:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3873743961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbde v_rx_crc_err.3873743961 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_rx_full.2000557734 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 368110618 ps |
| CPU time | 2.13 seconds |
| Started | Feb 08 05:59:31 PM UTC 25 |
| Finished | Feb 08 05:59:34 PM UTC 25 |
| Peak memory | 217108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2000557734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_r x_full.2000557734 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_rx_pid_err.3989898080 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 199639197 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 05:59:33 PM UTC 25 |
| Finished | Feb 08 05:59:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3989898080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbde v_rx_pid_err.3989898080 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_rx_pid_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_sec_cm.3195434814 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 919878409 ps |
| CPU time | 2.98 seconds |
| Started | Feb 08 05:59:41 PM UTC 25 |
| Finished | Feb 08 05:59:45 PM UTC 25 |
| Peak memory | 251548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195434814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 4.usbdev_sec_cm.3195434814 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_setup_priority.3789600651 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 338444389 ps |
| CPU time | 1.92 seconds |
| Started | Feb 08 05:59:33 PM UTC 25 |
| Finished | Feb 08 05:59:36 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3789600651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.u sbdev_setup_priority.3789600651 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_setup_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_setup_priority_over_stall_response.1093290244 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 203292259 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 05:59:33 PM UTC 25 |
| Finished | Feb 08 05:59:36 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1093290244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_respons e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 4.usbdev_setup_priority_over_stall_response.1093290244 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_setup_priority_over_stall_response/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_setup_stage.1666381145 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 178118997 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 05:59:35 PM UTC 25 |
| Finished | Feb 08 05:59:38 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1666381145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbd ev_setup_stage.1666381145 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_setup_trans_ignored.839869164 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 145180144 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 05:59:37 PM UTC 25 |
| Finished | Feb 08 05:59:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=839869164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.839869164 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_smoke.1753535828 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 240461745 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 05:59:37 PM UTC 25 |
| Finished | Feb 08 05:59:40 PM UTC 25 |
| Peak memory | 215084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1753535828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smo ke.1753535828 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_spurious_pids_ignored.2060584005 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 3713072288 ps |
| CPU time | 33.27 seconds |
| Started | Feb 08 05:59:37 PM UTC 25 |
| Finished | Feb 08 06:00:12 PM UTC 25 |
| Peak memory | 234336 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060584005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 4.usbdev_spurious_pids_ignored.2060584005 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_stall_priority_over_nak.3367705785 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 194395717 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 05:59:37 PM UTC 25 |
| Finished | Feb 08 05:59:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3367705785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 4.usbdev_stall_priority_over_nak.3367705785 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_stall_trans.1637260074 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 159181444 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 05:59:37 PM UTC 25 |
| Finished | Feb 08 05:59:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1637260074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbd ev_stall_trans.1637260074 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_stream_len_max.1959481784 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 572972418 ps |
| CPU time | 2.45 seconds |
| Started | Feb 08 05:59:38 PM UTC 25 |
| Finished | Feb 08 05:59:42 PM UTC 25 |
| Peak memory | 217088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1959481784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.u sbdev_stream_len_max.1959481784 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_streaming_out.1118710654 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 1740552628 ps |
| CPU time | 57.81 seconds |
| Started | Feb 08 05:59:38 PM UTC 25 |
| Finished | Feb 08 06:00:38 PM UTC 25 |
| Peak memory | 234368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1118710654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev _streaming_out.1118710654 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_stress_usb_traffic.2403405752 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 9133390306 ps |
| CPU time | 107.04 seconds |
| Started | Feb 08 05:59:40 PM UTC 25 |
| Finished | Feb 08 06:01:29 PM UTC 25 |
| Peak memory | 229640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403405752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM _TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.2403405752 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_stress_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_timeout_missing_host_handshake.992601057 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 3565814060 ps |
| CPU time | 23.05 seconds |
| Started | Feb 08 05:58:43 PM UTC 25 |
| Finished | Feb 08 05:59:07 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992601057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_host_handshake.992601057 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/4.usbdev_tx_rx_disruption.26454234 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 455249380 ps |
| CPU time | 2.74 seconds |
| Started | Feb 08 05:59:41 PM UTC 25 |
| Finished | Feb 08 05:59:45 PM UTC 25 |
| Peak memory | 217180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 6454234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_tx_rx_disruption.26454234 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/4.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_alert_test.4070681384 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 51969316 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 06:15:05 PM UTC 25 |
| Finished | Feb 08 06:15:07 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070681384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 40.usbdev_alert_test.4070681384 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_aon_wake_disconnect.2443106640 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 5943417091 ps |
| CPU time | 17.02 seconds |
| Started | Feb 08 06:14:45 PM UTC 25 |
| Finished | Feb 08 06:15:04 PM UTC 25 |
| Peak memory | 227844 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443106640 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.2443106640 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_aon_wake_reset.3313952346 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 21179032573 ps |
| CPU time | 31.75 seconds |
| Started | Feb 08 06:14:45 PM UTC 25 |
| Finished | Feb 08 06:15:18 PM UTC 25 |
| Peak memory | 217384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313952346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.3313952346 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_aon_wake_resume.3758412185 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 29187528499 ps |
| CPU time | 49.73 seconds |
| Started | Feb 08 06:14:45 PM UTC 25 |
| Finished | Feb 08 06:15:37 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758412185 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.3758412185 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_av_buffer.3714255160 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 157907071 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:14:47 PM UTC 25 |
| Finished | Feb 08 06:14:50 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3714255160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbde v_av_buffer.3714255160 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_bitstuff_err.859208036 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 146188832 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:14:47 PM UTC 25 |
| Finished | Feb 08 06:14:49 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=859208036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usb dev_bitstuff_err.859208036 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_data_toggle_clear.1371461265 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 461365818 ps |
| CPU time | 2.96 seconds |
| Started | Feb 08 06:14:47 PM UTC 25 |
| Finished | Feb 08 06:14:51 PM UTC 25 |
| Peak memory | 217180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1371461265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.1371461265 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_data_toggle_restore.2724618513 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 510870460 ps |
| CPU time | 2.65 seconds |
| Started | Feb 08 06:14:47 PM UTC 25 |
| Finished | Feb 08 06:14:51 PM UTC 25 |
| Peak memory | 217108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724618513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2724618513 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_device_address.3719105496 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 23076004584 ps |
| CPU time | 43.09 seconds |
| Started | Feb 08 06:14:47 PM UTC 25 |
| Finished | Feb 08 06:15:32 PM UTC 25 |
| Peak memory | 216636 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3719105496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40. usbdev_device_address.3719105496 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_device_timeout.2259219906 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 5691699809 ps |
| CPU time | 36.91 seconds |
| Started | Feb 08 06:14:47 PM UTC 25 |
| Finished | Feb 08 06:15:26 PM UTC 25 |
| Peak memory | 217404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259219906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.2259219906 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_disable_endpoint.325620811 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 986473963 ps |
| CPU time | 3.45 seconds |
| Started | Feb 08 06:14:48 PM UTC 25 |
| Finished | Feb 08 06:14:53 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=325620811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40 .usbdev_disable_endpoint.325620811 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_disconnected.3736393702 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 149107445 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:14:48 PM UTC 25 |
| Finished | Feb 08 06:14:51 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3736393702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.us bdev_disconnected.3736393702 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_enable.3419133202 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 61656531 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 06:14:50 PM UTC 25 |
| Finished | Feb 08 06:14:52 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3419133202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_e nable.3419133202 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_endpoint_access.2919510253 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 847216150 ps |
| CPU time | 4.41 seconds |
| Started | Feb 08 06:14:51 PM UTC 25 |
| Finished | Feb 08 06:14:56 PM UTC 25 |
| Peak memory | 217508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2919510253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40 .usbdev_endpoint_access.2919510253 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_fifo_rst.482337738 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 464741515 ps |
| CPU time | 3.72 seconds |
| Started | Feb 08 06:14:51 PM UTC 25 |
| Finished | Feb 08 06:14:56 PM UTC 25 |
| Peak memory | 217360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=482337738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_ fifo_rst.482337738 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_in_iso.779563044 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 264193476 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:14:52 PM UTC 25 |
| Finished | Feb 08 06:14:55 PM UTC 25 |
| Peak memory | 227816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779563044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 40.usbdev_in_iso.779563044 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_in_stall.4290697583 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 138874771 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:14:52 PM UTC 25 |
| Finished | Feb 08 06:14:55 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4290697583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev _in_stall.4290697583 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_in_trans.330541893 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 216844623 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:14:52 PM UTC 25 |
| Finished | Feb 08 06:14:55 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=330541893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_ in_trans.330541893 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_invalid_sync.2122831713 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 3840468940 ps |
| CPU time | 28.71 seconds |
| Started | Feb 08 06:14:52 PM UTC 25 |
| Finished | Feb 08 06:15:22 PM UTC 25 |
| Peak memory | 227732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122831713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.2122831713 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_iso_retraction.301890710 |
| Short name | T2962 |
| Test name | |
| Test status | |
| Simulation time | 10778830703 ps |
| CPU time | 139.42 seconds |
| Started | Feb 08 06:14:52 PM UTC 25 |
| Finished | Feb 08 06:17:14 PM UTC 25 |
| Peak memory | 219132 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301890710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retra ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 40.usbdev_iso_retraction.301890710 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_link_in_err.3121812328 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 243142024 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 06:14:54 PM UTC 25 |
| Finished | Feb 08 06:14:56 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3121812328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usb dev_link_in_err.3121812328 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_link_resume.1072100565 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 25207726061 ps |
| CPU time | 33.79 seconds |
| Started | Feb 08 06:14:54 PM UTC 25 |
| Finished | Feb 08 06:15:29 PM UTC 25 |
| Peak memory | 227784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1072100565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usb dev_link_resume.1072100565 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_link_suspend.383561661 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 8636323028 ps |
| CPU time | 13.43 seconds |
| Started | Feb 08 06:14:56 PM UTC 25 |
| Finished | Feb 08 06:15:11 PM UTC 25 |
| Peak memory | 217456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=383561661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usb dev_link_suspend.383561661 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_low_speed_traffic.2022002767 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 4134231985 ps |
| CPU time | 42.3 seconds |
| Started | Feb 08 06:14:56 PM UTC 25 |
| Finished | Feb 08 06:15:40 PM UTC 25 |
| Peak memory | 229816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022002767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 40.usbdev_low_speed_traffic.2022002767 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_max_inter_pkt_delay.2596966987 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 3077175579 ps |
| CPU time | 28.18 seconds |
| Started | Feb 08 06:14:56 PM UTC 25 |
| Finished | Feb 08 06:15:26 PM UTC 25 |
| Peak memory | 229656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596966987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.2596966987 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_max_length_in_transaction.1096234475 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 239121814 ps |
| CPU time | 1.84 seconds |
| Started | Feb 08 06:14:56 PM UTC 25 |
| Finished | Feb 08 06:14:59 PM UTC 25 |
| Peak memory | 216372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096234475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 40.usbdev_max_length_in_transaction.1096234475 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_max_length_out_transaction.1669331376 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 198901948 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:14:56 PM UTC 25 |
| Finished | Feb 08 06:14:59 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1669331376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1669331376 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_min_inter_pkt_delay.2992329872 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 3927857339 ps |
| CPU time | 106.81 seconds |
| Started | Feb 08 06:14:56 PM UTC 25 |
| Finished | Feb 08 06:16:46 PM UTC 25 |
| Peak memory | 226848 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992329872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.2992329872 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_min_length_in_transaction.842039298 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 163616623 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:14:56 PM UTC 25 |
| Finished | Feb 08 06:14:59 PM UTC 25 |
| Peak memory | 215156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842039298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 40.usbdev_min_length_in_transaction.842039298 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_min_length_out_transaction.2050693981 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 166066627 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:14:56 PM UTC 25 |
| Finished | Feb 08 06:14:59 PM UTC 25 |
| Peak memory | 215048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2050693981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2050693981 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_nak_trans.3251546060 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 215085879 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:14:56 PM UTC 25 |
| Finished | Feb 08 06:14:59 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3251546060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbde v_nak_trans.3251546060 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_out_iso.2236493519 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 216477096 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:14:58 PM UTC 25 |
| Finished | Feb 08 06:15:01 PM UTC 25 |
| Peak memory | 215084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2236493519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_ out_iso.2236493519 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_out_stall.189777077 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 142995129 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:14:58 PM UTC 25 |
| Finished | Feb 08 06:15:00 PM UTC 25 |
| Peak memory | 215080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=189777077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev _out_stall.189777077 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_out_trans_nak.1553873001 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 192700669 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:14:58 PM UTC 25 |
| Finished | Feb 08 06:15:01 PM UTC 25 |
| Peak memory | 215076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1553873001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.u sbdev_out_trans_nak.1553873001 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_pending_in_trans.1697573631 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 154374393 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:14:58 PM UTC 25 |
| Finished | Feb 08 06:15:01 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1697573631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.usbdev_pending_in_trans.1697573631 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_phy_config_pinflip.428339350 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 197454391 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:14:58 PM UTC 25 |
| Finished | Feb 08 06:15:01 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=428339350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 40.usbdev_phy_config_pinflip.428339350 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_phy_config_usb_ref_disable.3136468777 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 141073509 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:14:58 PM UTC 25 |
| Finished | Feb 08 06:15:01 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3136468777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.3136468777 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_phy_pins_sense.1087717371 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 93518655 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 06:15:00 PM UTC 25 |
| Finished | Feb 08 06:15:03 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1087717371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40. usbdev_phy_pins_sense.1087717371 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_pkt_buffer.16117719 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 14929667088 ps |
| CPU time | 45.32 seconds |
| Started | Feb 08 06:15:00 PM UTC 25 |
| Finished | Feb 08 06:15:47 PM UTC 25 |
| Peak memory | 227692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=16117719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev _pkt_buffer.16117719 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_pkt_received.891677848 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 194011866 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:15:00 PM UTC 25 |
| Finished | Feb 08 06:15:03 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=891677848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usb dev_pkt_received.891677848 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_pkt_sent.2591392478 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 256613408 ps |
| CPU time | 1.84 seconds |
| Started | Feb 08 06:15:00 PM UTC 25 |
| Finished | Feb 08 06:15:04 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2591392478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev _pkt_sent.2591392478 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_random_length_in_transaction.856336714 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 180721573 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:15:00 PM UTC 25 |
| Finished | Feb 08 06:15:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=856336714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.us bdev_random_length_in_transaction.856336714 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_random_length_out_transaction.537298343 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 229999123 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:15:02 PM UTC 25 |
| Finished | Feb 08 06:15:05 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=537298343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 40.usbdev_random_length_out_transaction.537298343 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_rx_crc_err.3727400637 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 175989234 ps |
| CPU time | 1.12 seconds |
| Started | Feb 08 06:15:02 PM UTC 25 |
| Finished | Feb 08 06:15:04 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3727400637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbd ev_rx_crc_err.3727400637 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_rx_full.939959236 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 253335359 ps |
| CPU time | 1.78 seconds |
| Started | Feb 08 06:15:02 PM UTC 25 |
| Finished | Feb 08 06:15:05 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=939959236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_r x_full.939959236 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_setup_stage.3135908044 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 171191689 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:15:02 PM UTC 25 |
| Finished | Feb 08 06:15:05 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3135908044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usb dev_setup_stage.3135908044 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_setup_trans_ignored.3378135953 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 158374829 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 06:15:02 PM UTC 25 |
| Finished | Feb 08 06:15:05 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3378135953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 40.usbdev_setup_trans_ignored.3378135953 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_smoke.11054494 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 214577341 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:15:02 PM UTC 25 |
| Finished | Feb 08 06:15:05 PM UTC 25 |
| Peak memory | 215008 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=11054494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smok e.11054494 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_spurious_pids_ignored.3407449553 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 3487494488 ps |
| CPU time | 34.41 seconds |
| Started | Feb 08 06:15:02 PM UTC 25 |
| Finished | Feb 08 06:15:38 PM UTC 25 |
| Peak memory | 234280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407449553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 40.usbdev_spurious_pids_ignored.3407449553 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_stall_priority_over_nak.1685428525 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 202381777 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:15:03 PM UTC 25 |
| Finished | Feb 08 06:15:06 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1685428525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 40.usbdev_stall_priority_over_nak.1685428525 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_stall_trans.691830776 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 212988456 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:15:03 PM UTC 25 |
| Finished | Feb 08 06:15:06 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=691830776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbd ev_stall_trans.691830776 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_stream_len_max.788756493 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 1323595048 ps |
| CPU time | 5.53 seconds |
| Started | Feb 08 06:15:05 PM UTC 25 |
| Finished | Feb 08 06:15:12 PM UTC 25 |
| Peak memory | 217416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=788756493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.u sbdev_stream_len_max.788756493 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_streaming_out.236597353 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 2119531240 ps |
| CPU time | 16.12 seconds |
| Started | Feb 08 06:15:05 PM UTC 25 |
| Finished | Feb 08 06:15:22 PM UTC 25 |
| Peak memory | 234420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=236597353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev _streaming_out.236597353 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_timeout_missing_host_handshake.3311819258 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 5700657765 ps |
| CPU time | 38.19 seconds |
| Started | Feb 08 06:14:48 PM UTC 25 |
| Finished | Feb 08 06:15:28 PM UTC 25 |
| Peak memory | 217348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311819258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_host_handshake.3311819258 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_tx_rx_disruption.1420194679 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 467817054 ps |
| CPU time | 2.4 seconds |
| Started | Feb 08 06:15:05 PM UTC 25 |
| Finished | Feb 08 06:15:08 PM UTC 25 |
| Peak memory | 217116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 420194679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_tx_rx_disruption.1420194679 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/40.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/400.usbdev_tx_rx_disruption.3038932097 |
| Short name | T3528 |
| Test name | |
| Test status | |
| Simulation time | 618843277 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:20:00 PM UTC 25 |
| Finished | Feb 08 06:20:11 PM UTC 25 |
| Peak memory | 214664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 038932097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 400.usbdev_tx_rx_disruption.3038932097 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/400.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/401.usbdev_tx_rx_disruption.2066368783 |
| Short name | T3529 |
| Test name | |
| Test status | |
| Simulation time | 471769387 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:20:00 PM UTC 25 |
| Finished | Feb 08 06:20:11 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 066368783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 401.usbdev_tx_rx_disruption.2066368783 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/401.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/402.usbdev_tx_rx_disruption.2519829483 |
| Short name | T3526 |
| Test name | |
| Test status | |
| Simulation time | 582199346 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:20:00 PM UTC 25 |
| Finished | Feb 08 06:20:11 PM UTC 25 |
| Peak memory | 214864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 519829483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 402.usbdev_tx_rx_disruption.2519829483 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/402.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/403.usbdev_tx_rx_disruption.3624361816 |
| Short name | T3524 |
| Test name | |
| Test status | |
| Simulation time | 452200107 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:20:00 PM UTC 25 |
| Finished | Feb 08 06:20:11 PM UTC 25 |
| Peak memory | 214964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 624361816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 403.usbdev_tx_rx_disruption.3624361816 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/403.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/404.usbdev_tx_rx_disruption.2100115798 |
| Short name | T3531 |
| Test name | |
| Test status | |
| Simulation time | 540367544 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:20:00 PM UTC 25 |
| Finished | Feb 08 06:20:11 PM UTC 25 |
| Peak memory | 214968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 100115798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 404.usbdev_tx_rx_disruption.2100115798 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/404.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/405.usbdev_tx_rx_disruption.2871268409 |
| Short name | T3538 |
| Test name | |
| Test status | |
| Simulation time | 544841649 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 06:20:00 PM UTC 25 |
| Finished | Feb 08 06:20:12 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 871268409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 405.usbdev_tx_rx_disruption.2871268409 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/405.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/406.usbdev_tx_rx_disruption.796116894 |
| Short name | T3537 |
| Test name | |
| Test status | |
| Simulation time | 593274706 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:20:00 PM UTC 25 |
| Finished | Feb 08 06:20:11 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 96116894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 406.usbdev_tx_rx_disruption.796116894 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/406.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/407.usbdev_tx_rx_disruption.451370141 |
| Short name | T3527 |
| Test name | |
| Test status | |
| Simulation time | 496494784 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:20:00 PM UTC 25 |
| Finished | Feb 08 06:20:11 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 51370141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 407.usbdev_tx_rx_disruption.451370141 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/407.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/408.usbdev_tx_rx_disruption.2053521981 |
| Short name | T3535 |
| Test name | |
| Test status | |
| Simulation time | 604062981 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:20:00 PM UTC 25 |
| Finished | Feb 08 06:20:11 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 053521981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 408.usbdev_tx_rx_disruption.2053521981 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/408.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/409.usbdev_tx_rx_disruption.2524846845 |
| Short name | T3532 |
| Test name | |
| Test status | |
| Simulation time | 499134067 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:20:00 PM UTC 25 |
| Finished | Feb 08 06:20:11 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 524846845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 409.usbdev_tx_rx_disruption.2524846845 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/409.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_alert_test.55574783 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 62276316 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 06:15:25 PM UTC 25 |
| Finished | Feb 08 06:15:27 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55574783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 41.usbdev_alert_test.55574783 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_aon_wake_disconnect.1077961518 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 4803327608 ps |
| CPU time | 14.58 seconds |
| Started | Feb 08 06:15:07 PM UTC 25 |
| Finished | Feb 08 06:15:23 PM UTC 25 |
| Peak memory | 227480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077961518 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.1077961518 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_aon_wake_reset.1346712536 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 15928732133 ps |
| CPU time | 25.23 seconds |
| Started | Feb 08 06:15:07 PM UTC 25 |
| Finished | Feb 08 06:15:34 PM UTC 25 |
| Peak memory | 227552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346712536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.1346712536 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_aon_wake_resume.3188666868 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 29571397141 ps |
| CPU time | 49.12 seconds |
| Started | Feb 08 06:15:07 PM UTC 25 |
| Finished | Feb 08 06:15:58 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188666868 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.3188666868 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_av_buffer.3874901969 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 156003325 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:15:07 PM UTC 25 |
| Finished | Feb 08 06:15:10 PM UTC 25 |
| Peak memory | 214864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3874901969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbde v_av_buffer.3874901969 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_bitstuff_err.1889792897 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 145938823 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:15:07 PM UTC 25 |
| Finished | Feb 08 06:15:10 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1889792897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.us bdev_bitstuff_err.1889792897 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_data_toggle_clear.821669809 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 235926482 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:15:07 PM UTC 25 |
| Finished | Feb 08 06:15:10 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=821669809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.usbdev_data_toggle_clear.821669809 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_data_toggle_restore.4116861873 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 949381903 ps |
| CPU time | 2.9 seconds |
| Started | Feb 08 06:15:07 PM UTC 25 |
| Finished | Feb 08 06:15:12 PM UTC 25 |
| Peak memory | 217424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116861873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.4116861873 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_device_address.1873729291 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 30353091970 ps |
| CPU time | 61.07 seconds |
| Started | Feb 08 06:15:07 PM UTC 25 |
| Finished | Feb 08 06:16:10 PM UTC 25 |
| Peak memory | 217600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1873729291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41. usbdev_device_address.1873729291 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_device_timeout.1891703507 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 9102332840 ps |
| CPU time | 60.69 seconds |
| Started | Feb 08 06:15:09 PM UTC 25 |
| Finished | Feb 08 06:16:12 PM UTC 25 |
| Peak memory | 217532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891703507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.1891703507 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_disable_endpoint.860560407 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 528153516 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:15:09 PM UTC 25 |
| Finished | Feb 08 06:15:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=860560407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41 .usbdev_disable_endpoint.860560407 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_disconnected.3524447902 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 152822966 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 06:15:09 PM UTC 25 |
| Finished | Feb 08 06:15:12 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3524447902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.us bdev_disconnected.3524447902 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_enable.3420238541 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 36344815 ps |
| CPU time | 1.05 seconds |
| Started | Feb 08 06:15:09 PM UTC 25 |
| Finished | Feb 08 06:15:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3420238541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_e nable.3420238541 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_endpoint_access.2078314488 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 998627243 ps |
| CPU time | 4.33 seconds |
| Started | Feb 08 06:15:09 PM UTC 25 |
| Finished | Feb 08 06:15:15 PM UTC 25 |
| Peak memory | 217320 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2078314488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41 .usbdev_endpoint_access.2078314488 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_endpoint_types.4184231072 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 738721547 ps |
| CPU time | 1.92 seconds |
| Started | Feb 08 06:15:11 PM UTC 25 |
| Finished | Feb 08 06:15:14 PM UTC 25 |
| Peak memory | 215004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184231072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 41.usbdev_endpoint_types.4184231072 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_fifo_rst.597194520 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 230192988 ps |
| CPU time | 2.41 seconds |
| Started | Feb 08 06:15:11 PM UTC 25 |
| Finished | Feb 08 06:15:15 PM UTC 25 |
| Peak memory | 217524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=597194520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_ fifo_rst.597194520 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_in_iso.2065128278 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 214976460 ps |
| CPU time | 1.96 seconds |
| Started | Feb 08 06:15:13 PM UTC 25 |
| Finished | Feb 08 06:15:16 PM UTC 25 |
| Peak memory | 227756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065128278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 41.usbdev_in_iso.2065128278 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_in_stall.335147779 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 151188948 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:15:13 PM UTC 25 |
| Finished | Feb 08 06:15:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=335147779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_ in_stall.335147779 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_in_trans.1095443621 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 238730578 ps |
| CPU time | 1.72 seconds |
| Started | Feb 08 06:15:13 PM UTC 25 |
| Finished | Feb 08 06:15:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1095443621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev _in_trans.1095443621 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_invalid_sync.631353000 |
| Short name | T2927 |
| Test name | |
| Test status | |
| Simulation time | 4915354499 ps |
| CPU time | 135.06 seconds |
| Started | Feb 08 06:15:11 PM UTC 25 |
| Finished | Feb 08 06:17:29 PM UTC 25 |
| Peak memory | 229820 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631353000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.631353000 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_iso_retraction.722565931 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 5796674886 ps |
| CPU time | 40.7 seconds |
| Started | Feb 08 06:15:13 PM UTC 25 |
| Finished | Feb 08 06:15:55 PM UTC 25 |
| Peak memory | 217408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722565931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retra ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 41.usbdev_iso_retraction.722565931 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_link_in_err.662649827 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 168011104 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:15:13 PM UTC 25 |
| Finished | Feb 08 06:15:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=662649827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbd ev_link_in_err.662649827 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_link_resume.810755665 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 24194694149 ps |
| CPU time | 45.95 seconds |
| Started | Feb 08 06:15:13 PM UTC 25 |
| Finished | Feb 08 06:16:01 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=810755665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbd ev_link_resume.810755665 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_link_suspend.2656742535 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 11354931406 ps |
| CPU time | 17.14 seconds |
| Started | Feb 08 06:15:13 PM UTC 25 |
| Finished | Feb 08 06:15:32 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2656742535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.us bdev_link_suspend.2656742535 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_low_speed_traffic.3314311693 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 3817360551 ps |
| CPU time | 31.14 seconds |
| Started | Feb 08 06:15:13 PM UTC 25 |
| Finished | Feb 08 06:15:46 PM UTC 25 |
| Peak memory | 229780 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314311693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 41.usbdev_low_speed_traffic.3314311693 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_max_inter_pkt_delay.2349922387 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 2006821097 ps |
| CPU time | 56.14 seconds |
| Started | Feb 08 06:15:13 PM UTC 25 |
| Finished | Feb 08 06:16:11 PM UTC 25 |
| Peak memory | 227592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349922387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.2349922387 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_max_length_in_transaction.2270019963 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 262651799 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:15:14 PM UTC 25 |
| Finished | Feb 08 06:15:17 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270019963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 41.usbdev_max_length_in_transaction.2270019963 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_max_length_out_transaction.1873160244 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 192051304 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:15:16 PM UTC 25 |
| Finished | Feb 08 06:15:18 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1873160244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.1873160244 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_min_inter_pkt_delay.1234433264 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 2669112264 ps |
| CPU time | 78.75 seconds |
| Started | Feb 08 06:15:17 PM UTC 25 |
| Finished | Feb 08 06:16:38 PM UTC 25 |
| Peak memory | 227856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234433264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.1234433264 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_min_length_in_transaction.990903780 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 159708542 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:15:17 PM UTC 25 |
| Finished | Feb 08 06:15:20 PM UTC 25 |
| Peak memory | 215156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990903780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 41.usbdev_min_length_in_transaction.990903780 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_min_length_out_transaction.2024627201 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 154602170 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:15:17 PM UTC 25 |
| Finished | Feb 08 06:15:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2024627201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.2024627201 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_nak_trans.178633933 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 215379241 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:15:17 PM UTC 25 |
| Finished | Feb 08 06:15:20 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=178633933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev _nak_trans.178633933 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_out_iso.2740318547 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 150584719 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:15:17 PM UTC 25 |
| Finished | Feb 08 06:15:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2740318547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_ out_iso.2740318547 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_out_stall.3440565245 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 154083177 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:15:19 PM UTC 25 |
| Finished | Feb 08 06:15:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3440565245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbde v_out_stall.3440565245 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_out_trans_nak.1324503104 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 190535462 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:15:19 PM UTC 25 |
| Finished | Feb 08 06:15:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1324503104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.u sbdev_out_trans_nak.1324503104 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_pending_in_trans.15763443 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 147170952 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:15:19 PM UTC 25 |
| Finished | Feb 08 06:15:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=15763443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41. usbdev_pending_in_trans.15763443 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_phy_config_pinflip.3956575738 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 299537751 ps |
| CPU time | 1.84 seconds |
| Started | Feb 08 06:15:19 PM UTC 25 |
| Finished | Feb 08 06:15:23 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956575738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 41.usbdev_phy_config_pinflip.3956575738 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_phy_config_usb_ref_disable.2253661287 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 144393741 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:15:19 PM UTC 25 |
| Finished | Feb 08 06:15:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2253661287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.2253661287 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_phy_pins_sense.2732239482 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 40154212 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 06:15:20 PM UTC 25 |
| Finished | Feb 08 06:15:23 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2732239482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41. usbdev_phy_pins_sense.2732239482 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_pkt_buffer.482548664 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 18686202069 ps |
| CPU time | 47.68 seconds |
| Started | Feb 08 06:15:21 PM UTC 25 |
| Finished | Feb 08 06:16:10 PM UTC 25 |
| Peak memory | 227664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=482548664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbde v_pkt_buffer.482548664 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_pkt_received.293655918 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 185751478 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:15:21 PM UTC 25 |
| Finished | Feb 08 06:15:24 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=293655918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usb dev_pkt_received.293655918 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_pkt_sent.598958155 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 186416419 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:15:21 PM UTC 25 |
| Finished | Feb 08 06:15:23 PM UTC 25 |
| Peak memory | 215092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=598958155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_ pkt_sent.598958155 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_random_length_in_transaction.1048278892 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 189238690 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 06:15:21 PM UTC 25 |
| Finished | Feb 08 06:15:23 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1048278892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.u sbdev_random_length_in_transaction.1048278892 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_random_length_out_transaction.1192964045 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 168614392 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:15:22 PM UTC 25 |
| Finished | Feb 08 06:15:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1192964045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 41.usbdev_random_length_out_transaction.1192964045 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_rx_crc_err.1284730813 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 154863617 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:15:23 PM UTC 25 |
| Finished | Feb 08 06:15:26 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1284730813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbd ev_rx_crc_err.1284730813 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_rx_full.261597342 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 342264782 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:15:24 PM UTC 25 |
| Finished | Feb 08 06:15:26 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=261597342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_r x_full.261597342 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_setup_stage.2184964292 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 147821462 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:15:24 PM UTC 25 |
| Finished | Feb 08 06:15:26 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2184964292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usb dev_setup_stage.2184964292 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_setup_trans_ignored.179940590 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 173155656 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:15:24 PM UTC 25 |
| Finished | Feb 08 06:15:26 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=179940590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.179940590 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_smoke.4231376631 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 210301185 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:15:24 PM UTC 25 |
| Finished | Feb 08 06:15:26 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4231376631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_sm oke.4231376631 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_spurious_pids_ignored.391606737 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 2244264610 ps |
| CPU time | 22.14 seconds |
| Started | Feb 08 06:15:24 PM UTC 25 |
| Finished | Feb 08 06:15:47 PM UTC 25 |
| Peak memory | 229700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391606737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 41.usbdev_spurious_pids_ignored.391606737 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_stall_priority_over_nak.382876299 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 174875341 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:15:24 PM UTC 25 |
| Finished | Feb 08 06:15:26 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=382876299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 41.usbdev_stall_priority_over_nak.382876299 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_stall_trans.206052864 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 183762008 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:15:24 PM UTC 25 |
| Finished | Feb 08 06:15:27 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=206052864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbd ev_stall_trans.206052864 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_stream_len_max.2918758238 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 252028541 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:15:25 PM UTC 25 |
| Finished | Feb 08 06:15:28 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2918758238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41. usbdev_stream_len_max.2918758238 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_streaming_out.930243763 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 1992398009 ps |
| CPU time | 21.81 seconds |
| Started | Feb 08 06:15:25 PM UTC 25 |
| Finished | Feb 08 06:15:48 PM UTC 25 |
| Peak memory | 234244 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=930243763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev _streaming_out.930243763 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_timeout_missing_host_handshake.1889699205 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 1422933546 ps |
| CPU time | 33.48 seconds |
| Started | Feb 08 06:15:09 PM UTC 25 |
| Finished | Feb 08 06:15:44 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889699205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing_host_handshake.1889699205 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_tx_rx_disruption.471181349 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 627220152 ps |
| CPU time | 2.58 seconds |
| Started | Feb 08 06:15:25 PM UTC 25 |
| Finished | Feb 08 06:15:29 PM UTC 25 |
| Peak memory | 217124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 71181349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_tx_rx_disruption.471181349 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/41.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/410.usbdev_tx_rx_disruption.275530236 |
| Short name | T3534 |
| Test name | |
| Test status | |
| Simulation time | 474729206 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:20:00 PM UTC 25 |
| Finished | Feb 08 06:20:11 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 75530236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 410.usbdev_tx_rx_disruption.275530236 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/410.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/411.usbdev_tx_rx_disruption.2623828148 |
| Short name | T3533 |
| Test name | |
| Test status | |
| Simulation time | 592558810 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:20:00 PM UTC 25 |
| Finished | Feb 08 06:20:11 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 623828148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 411.usbdev_tx_rx_disruption.2623828148 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/411.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/412.usbdev_tx_rx_disruption.2661353622 |
| Short name | T3519 |
| Test name | |
| Test status | |
| Simulation time | 621222944 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:20:04 PM UTC 25 |
| Finished | Feb 08 06:20:10 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 661353622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 412.usbdev_tx_rx_disruption.2661353622 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/412.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/413.usbdev_tx_rx_disruption.2548667758 |
| Short name | T3521 |
| Test name | |
| Test status | |
| Simulation time | 631266148 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:20:04 PM UTC 25 |
| Finished | Feb 08 06:20:10 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 548667758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 413.usbdev_tx_rx_disruption.2548667758 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/413.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/414.usbdev_tx_rx_disruption.233470217 |
| Short name | T3523 |
| Test name | |
| Test status | |
| Simulation time | 620533875 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:20:04 PM UTC 25 |
| Finished | Feb 08 06:20:11 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 33470217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 414.usbdev_tx_rx_disruption.233470217 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/414.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/415.usbdev_tx_rx_disruption.1533759327 |
| Short name | T3520 |
| Test name | |
| Test status | |
| Simulation time | 521463997 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:20:04 PM UTC 25 |
| Finished | Feb 08 06:20:10 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 533759327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 415.usbdev_tx_rx_disruption.1533759327 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/415.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/416.usbdev_tx_rx_disruption.1614619677 |
| Short name | T3522 |
| Test name | |
| Test status | |
| Simulation time | 515615042 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:20:04 PM UTC 25 |
| Finished | Feb 08 06:20:11 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 614619677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 416.usbdev_tx_rx_disruption.1614619677 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/416.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/417.usbdev_tx_rx_disruption.955257313 |
| Short name | T3547 |
| Test name | |
| Test status | |
| Simulation time | 680784382 ps |
| CPU time | 1.8 seconds |
| Started | Feb 08 06:20:10 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 55257313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 417.usbdev_tx_rx_disruption.955257313 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/417.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/418.usbdev_tx_rx_disruption.1005518076 |
| Short name | T3540 |
| Test name | |
| Test status | |
| Simulation time | 431869024 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:13 PM UTC 25 |
| Peak memory | 215936 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 005518076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 418.usbdev_tx_rx_disruption.1005518076 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/418.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/419.usbdev_tx_rx_disruption.564951202 |
| Short name | T3543 |
| Test name | |
| Test status | |
| Simulation time | 534919880 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:13 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 64951202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 419.usbdev_tx_rx_disruption.564951202 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/419.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_alert_test.713976296 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 56842970 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:15:45 PM UTC 25 |
| Finished | Feb 08 06:15:47 PM UTC 25 |
| Peak memory | 214928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713976296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 42.usbdev_alert_test.713976296 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_aon_wake_disconnect.1613098145 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 4616614410 ps |
| CPU time | 7.28 seconds |
| Started | Feb 08 06:15:27 PM UTC 25 |
| Finished | Feb 08 06:15:35 PM UTC 25 |
| Peak memory | 227404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613098145 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.1613098145 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_aon_wake_reset.3267963008 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 13853811104 ps |
| CPU time | 17.92 seconds |
| Started | Feb 08 06:15:27 PM UTC 25 |
| Finished | Feb 08 06:15:46 PM UTC 25 |
| Peak memory | 227308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267963008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3267963008 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_aon_wake_resume.2304419676 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 29766215064 ps |
| CPU time | 50.75 seconds |
| Started | Feb 08 06:15:27 PM UTC 25 |
| Finished | Feb 08 06:16:19 PM UTC 25 |
| Peak memory | 217576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304419676 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.2304419676 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_av_buffer.1153104711 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 159342481 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:15:27 PM UTC 25 |
| Finished | Feb 08 06:15:30 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1153104711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbde v_av_buffer.1153104711 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_bitstuff_err.2953081051 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 140039794 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 06:15:27 PM UTC 25 |
| Finished | Feb 08 06:15:29 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2953081051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.us bdev_bitstuff_err.2953081051 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_data_toggle_clear.1079425815 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 158236179 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:15:27 PM UTC 25 |
| Finished | Feb 08 06:15:30 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1079425815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.1079425815 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_data_toggle_restore.1571950388 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 781106111 ps |
| CPU time | 4.24 seconds |
| Started | Feb 08 06:15:27 PM UTC 25 |
| Finished | Feb 08 06:15:33 PM UTC 25 |
| Peak memory | 217108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571950388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1571950388 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_device_address.3399418658 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 38791856140 ps |
| CPU time | 81.08 seconds |
| Started | Feb 08 06:15:27 PM UTC 25 |
| Finished | Feb 08 06:16:50 PM UTC 25 |
| Peak memory | 217424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3399418658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42. usbdev_device_address.3399418658 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_device_timeout.1090102812 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 4891174938 ps |
| CPU time | 35.3 seconds |
| Started | Feb 08 06:15:27 PM UTC 25 |
| Finished | Feb 08 06:16:04 PM UTC 25 |
| Peak memory | 217528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090102812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.1090102812 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_disable_endpoint.4056942252 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 760873005 ps |
| CPU time | 2.97 seconds |
| Started | Feb 08 06:15:29 PM UTC 25 |
| Finished | Feb 08 06:15:33 PM UTC 25 |
| Peak memory | 217088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4056942252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.usbdev_disable_endpoint.4056942252 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_disconnected.1680129794 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 149997518 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:15:29 PM UTC 25 |
| Finished | Feb 08 06:15:31 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1680129794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.us bdev_disconnected.1680129794 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_enable.310187921 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 35373508 ps |
| CPU time | 0.96 seconds |
| Started | Feb 08 06:15:29 PM UTC 25 |
| Finished | Feb 08 06:15:31 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=310187921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_en able.310187921 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_endpoint_access.541388234 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 1030268522 ps |
| CPU time | 4.22 seconds |
| Started | Feb 08 06:15:30 PM UTC 25 |
| Finished | Feb 08 06:15:35 PM UTC 25 |
| Peak memory | 217204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=541388234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42. usbdev_endpoint_access.541388234 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_endpoint_types.582839815 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 213246683 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:15:30 PM UTC 25 |
| Finished | Feb 08 06:15:33 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582839815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 42.usbdev_endpoint_types.582839815 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_fifo_rst.971847414 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 303837661 ps |
| CPU time | 2.86 seconds |
| Started | Feb 08 06:15:30 PM UTC 25 |
| Finished | Feb 08 06:15:34 PM UTC 25 |
| Peak memory | 217300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=971847414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_ fifo_rst.971847414 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_in_iso.3368422734 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 216668352 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 06:15:31 PM UTC 25 |
| Finished | Feb 08 06:15:34 PM UTC 25 |
| Peak memory | 227756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368422734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 42.usbdev_in_iso.3368422734 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_in_stall.2527941237 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 151048051 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:15:31 PM UTC 25 |
| Finished | Feb 08 06:15:34 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2527941237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev _in_stall.2527941237 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_in_trans.2919300086 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 194646686 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:15:33 PM UTC 25 |
| Finished | Feb 08 06:15:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2919300086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev _in_trans.2919300086 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_invalid_sync.1326061681 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 4329738276 ps |
| CPU time | 45.56 seconds |
| Started | Feb 08 06:15:31 PM UTC 25 |
| Finished | Feb 08 06:16:18 PM UTC 25 |
| Peak memory | 227644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326061681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.1326061681 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_iso_retraction.3445718510 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 8661811891 ps |
| CPU time | 64.6 seconds |
| Started | Feb 08 06:15:33 PM UTC 25 |
| Finished | Feb 08 06:16:40 PM UTC 25 |
| Peak memory | 217548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445718510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 42.usbdev_iso_retraction.3445718510 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_link_in_err.1649862981 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 225301496 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:15:33 PM UTC 25 |
| Finished | Feb 08 06:15:36 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1649862981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usb dev_link_in_err.1649862981 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_link_resume.405462583 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 32415439865 ps |
| CPU time | 72.87 seconds |
| Started | Feb 08 06:15:33 PM UTC 25 |
| Finished | Feb 08 06:16:48 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=405462583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbd ev_link_resume.405462583 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_link_suspend.1724704215 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 5747202895 ps |
| CPU time | 12.41 seconds |
| Started | Feb 08 06:15:33 PM UTC 25 |
| Finished | Feb 08 06:15:47 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1724704215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.us bdev_link_suspend.1724704215 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_low_speed_traffic.2224765319 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 3741929685 ps |
| CPU time | 39.89 seconds |
| Started | Feb 08 06:15:35 PM UTC 25 |
| Finished | Feb 08 06:16:16 PM UTC 25 |
| Peak memory | 234456 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224765319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 42.usbdev_low_speed_traffic.2224765319 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_max_inter_pkt_delay.1528043110 |
| Short name | T2914 |
| Test name | |
| Test status | |
| Simulation time | 2704838269 ps |
| CPU time | 79.41 seconds |
| Started | Feb 08 06:15:35 PM UTC 25 |
| Finished | Feb 08 06:16:56 PM UTC 25 |
| Peak memory | 234476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528043110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.1528043110 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_max_length_in_transaction.3672651480 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 247098600 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:15:35 PM UTC 25 |
| Finished | Feb 08 06:15:37 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672651480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 42.usbdev_max_length_in_transaction.3672651480 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_max_length_out_transaction.522559867 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 193561299 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:15:35 PM UTC 25 |
| Finished | Feb 08 06:15:38 PM UTC 25 |
| Peak memory | 216632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=522559867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 42.usbdev_max_length_out_transaction.522559867 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_min_inter_pkt_delay.2980630615 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 2357611435 ps |
| CPU time | 25.68 seconds |
| Started | Feb 08 06:15:35 PM UTC 25 |
| Finished | Feb 08 06:16:02 PM UTC 25 |
| Peak memory | 229720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980630615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.2980630615 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_min_length_in_transaction.641076486 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 184351312 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:15:35 PM UTC 25 |
| Finished | Feb 08 06:15:37 PM UTC 25 |
| Peak memory | 215156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641076486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 42.usbdev_min_length_in_transaction.641076486 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_min_length_out_transaction.2216303554 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 158848641 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:15:35 PM UTC 25 |
| Finished | Feb 08 06:15:38 PM UTC 25 |
| Peak memory | 216556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2216303554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.2216303554 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_nak_trans.3671494418 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 214765804 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 06:15:36 PM UTC 25 |
| Finished | Feb 08 06:15:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3671494418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbde v_nak_trans.3671494418 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_out_iso.1810185280 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 161595661 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:15:36 PM UTC 25 |
| Finished | Feb 08 06:15:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1810185280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_ out_iso.1810185280 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_out_stall.713515312 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 162126308 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:15:36 PM UTC 25 |
| Finished | Feb 08 06:15:39 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=713515312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev _out_stall.713515312 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_out_trans_nak.785030522 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 181890070 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:15:36 PM UTC 25 |
| Finished | Feb 08 06:15:39 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=785030522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.us bdev_out_trans_nak.785030522 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_pending_in_trans.4192150942 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 163690901 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:15:38 PM UTC 25 |
| Finished | Feb 08 06:15:40 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4192150942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.usbdev_pending_in_trans.4192150942 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_phy_config_pinflip.790111228 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 193221970 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:15:38 PM UTC 25 |
| Finished | Feb 08 06:15:40 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=790111228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 42.usbdev_phy_config_pinflip.790111228 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_phy_config_usb_ref_disable.1652722098 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 156209465 ps |
| CPU time | 1.23 seconds |
| Started | Feb 08 06:15:38 PM UTC 25 |
| Finished | Feb 08 06:15:40 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1652722098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.1652722098 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_phy_pins_sense.628060933 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 107580379 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:15:39 PM UTC 25 |
| Finished | Feb 08 06:15:42 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=628060933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.u sbdev_phy_pins_sense.628060933 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_pkt_buffer.2362898116 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 19035611285 ps |
| CPU time | 50.7 seconds |
| Started | Feb 08 06:15:39 PM UTC 25 |
| Finished | Feb 08 06:16:32 PM UTC 25 |
| Peak memory | 227744 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2362898116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbd ev_pkt_buffer.2362898116 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_pkt_received.3632238462 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 244484087 ps |
| CPU time | 0.99 seconds |
| Started | Feb 08 06:15:39 PM UTC 25 |
| Finished | Feb 08 06:15:41 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3632238462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.us bdev_pkt_received.3632238462 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_pkt_sent.1921649586 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 191786069 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:15:39 PM UTC 25 |
| Finished | Feb 08 06:15:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1921649586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev _pkt_sent.1921649586 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_random_length_in_transaction.3193265965 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 287025898 ps |
| CPU time | 1.87 seconds |
| Started | Feb 08 06:15:39 PM UTC 25 |
| Finished | Feb 08 06:15:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3193265965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.u sbdev_random_length_in_transaction.3193265965 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_random_length_out_transaction.3667321153 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 160346739 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 06:15:39 PM UTC 25 |
| Finished | Feb 08 06:15:42 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3667321153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 42.usbdev_random_length_out_transaction.3667321153 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_rx_crc_err.2436974243 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 205664012 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:15:39 PM UTC 25 |
| Finished | Feb 08 06:15:42 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2436974243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbd ev_rx_crc_err.2436974243 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_rx_full.2362724089 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 339606433 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:15:40 PM UTC 25 |
| Finished | Feb 08 06:15:43 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2362724089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_ rx_full.2362724089 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_setup_stage.2844101049 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 152575489 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:15:42 PM UTC 25 |
| Finished | Feb 08 06:15:44 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2844101049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usb dev_setup_stage.2844101049 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_setup_trans_ignored.731245117 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 151101007 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 06:15:42 PM UTC 25 |
| Finished | Feb 08 06:15:44 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=731245117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.731245117 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_smoke.381349045 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 270526317 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:15:42 PM UTC 25 |
| Finished | Feb 08 06:15:44 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=381349045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smo ke.381349045 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_spurious_pids_ignored.3931883639 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 2770491495 ps |
| CPU time | 23.49 seconds |
| Started | Feb 08 06:15:42 PM UTC 25 |
| Finished | Feb 08 06:16:07 PM UTC 25 |
| Peak memory | 229896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931883639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 42.usbdev_spurious_pids_ignored.3931883639 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_stall_priority_over_nak.3997948645 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 175686242 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:15:42 PM UTC 25 |
| Finished | Feb 08 06:15:45 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3997948645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 42.usbdev_stall_priority_over_nak.3997948645 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_stall_trans.3423849383 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 182816073 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:15:43 PM UTC 25 |
| Finished | Feb 08 06:15:46 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3423849383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usb dev_stall_trans.3423849383 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_stream_len_max.3081283017 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 1295242938 ps |
| CPU time | 4.22 seconds |
| Started | Feb 08 06:15:43 PM UTC 25 |
| Finished | Feb 08 06:15:49 PM UTC 25 |
| Peak memory | 217360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3081283017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42. usbdev_stream_len_max.3081283017 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_streaming_out.800554414 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 1719239906 ps |
| CPU time | 51.03 seconds |
| Started | Feb 08 06:15:43 PM UTC 25 |
| Finished | Feb 08 06:16:36 PM UTC 25 |
| Peak memory | 229720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=800554414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev _streaming_out.800554414 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_timeout_missing_host_handshake.1220221188 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 4981733802 ps |
| CPU time | 34.46 seconds |
| Started | Feb 08 06:15:29 PM UTC 25 |
| Finished | Feb 08 06:16:05 PM UTC 25 |
| Peak memory | 217412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220221188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing_host_handshake.1220221188 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_tx_rx_disruption.89663302 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 466468899 ps |
| CPU time | 2.63 seconds |
| Started | Feb 08 06:15:43 PM UTC 25 |
| Finished | Feb 08 06:15:47 PM UTC 25 |
| Peak memory | 217316 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 9663302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_tx_rx_disruption.89663302 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/42.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/420.usbdev_tx_rx_disruption.459607951 |
| Short name | T3541 |
| Test name | |
| Test status | |
| Simulation time | 509481732 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:13 PM UTC 25 |
| Peak memory | 216344 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 59607951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 420.usbdev_tx_rx_disruption.459607951 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/420.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/421.usbdev_tx_rx_disruption.2869605383 |
| Short name | T3546 |
| Test name | |
| Test status | |
| Simulation time | 547358230 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 869605383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 421.usbdev_tx_rx_disruption.2869605383 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/421.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/422.usbdev_tx_rx_disruption.3410341264 |
| Short name | T3545 |
| Test name | |
| Test status | |
| Simulation time | 508795024 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 410341264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 422.usbdev_tx_rx_disruption.3410341264 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/422.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/423.usbdev_tx_rx_disruption.3296271914 |
| Short name | T3559 |
| Test name | |
| Test status | |
| Simulation time | 604273638 ps |
| CPU time | 2.06 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 217188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 296271914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 423.usbdev_tx_rx_disruption.3296271914 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/423.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/424.usbdev_tx_rx_disruption.3226418933 |
| Short name | T3549 |
| Test name | |
| Test status | |
| Simulation time | 566743433 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 226418933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 424.usbdev_tx_rx_disruption.3226418933 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/424.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/425.usbdev_tx_rx_disruption.3308067118 |
| Short name | T3544 |
| Test name | |
| Test status | |
| Simulation time | 482167696 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 308067118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 425.usbdev_tx_rx_disruption.3308067118 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/425.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/426.usbdev_tx_rx_disruption.3306890721 |
| Short name | T3542 |
| Test name | |
| Test status | |
| Simulation time | 425514620 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:13 PM UTC 25 |
| Peak memory | 215048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 306890721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 426.usbdev_tx_rx_disruption.3306890721 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/426.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/427.usbdev_tx_rx_disruption.2718707148 |
| Short name | T3567 |
| Test name | |
| Test status | |
| Simulation time | 641772789 ps |
| CPU time | 2.17 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 217124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 718707148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 427.usbdev_tx_rx_disruption.2718707148 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/427.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/428.usbdev_tx_rx_disruption.2291878125 |
| Short name | T3548 |
| Test name | |
| Test status | |
| Simulation time | 588585720 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 291878125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 428.usbdev_tx_rx_disruption.2291878125 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/428.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/429.usbdev_tx_rx_disruption.2005843381 |
| Short name | T3550 |
| Test name | |
| Test status | |
| Simulation time | 554385001 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 005843381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 429.usbdev_tx_rx_disruption.2005843381 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/429.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_alert_test.2028020345 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 41237789 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 06:16:05 PM UTC 25 |
| Finished | Feb 08 06:16:07 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028020345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 43.usbdev_alert_test.2028020345 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_aon_wake_disconnect.1272803288 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 6821329073 ps |
| CPU time | 16.24 seconds |
| Started | Feb 08 06:15:45 PM UTC 25 |
| Finished | Feb 08 06:16:02 PM UTC 25 |
| Peak memory | 227680 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272803288 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.1272803288 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_aon_wake_reset.226410480 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 18588412172 ps |
| CPU time | 27.42 seconds |
| Started | Feb 08 06:15:45 PM UTC 25 |
| Finished | Feb 08 06:16:14 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226410480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TE ST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.226410480 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_aon_wake_resume.2093073926 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 29392232003 ps |
| CPU time | 52.51 seconds |
| Started | Feb 08 06:15:45 PM UTC 25 |
| Finished | Feb 08 06:16:39 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093073926 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.2093073926 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_av_buffer.1624420783 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 149491363 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:15:46 PM UTC 25 |
| Finished | Feb 08 06:15:49 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1624420783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbde v_av_buffer.1624420783 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_bitstuff_err.407828033 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 156640280 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:15:46 PM UTC 25 |
| Finished | Feb 08 06:15:49 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=407828033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usb dev_bitstuff_err.407828033 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_data_toggle_clear.4176695837 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 396397451 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:15:46 PM UTC 25 |
| Finished | Feb 08 06:15:49 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4176695837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.4176695837 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_data_toggle_restore.1147820867 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 327735716 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:15:46 PM UTC 25 |
| Finished | Feb 08 06:15:49 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147820867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.1147820867 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_device_address.3068582242 |
| Short name | T2924 |
| Test name | |
| Test status | |
| Simulation time | 40136165875 ps |
| CPU time | 69.14 seconds |
| Started | Feb 08 06:15:46 PM UTC 25 |
| Finished | Feb 08 06:16:57 PM UTC 25 |
| Peak memory | 217488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3068582242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43. usbdev_device_address.3068582242 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_device_timeout.1187277082 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 878556664 ps |
| CPU time | 19.51 seconds |
| Started | Feb 08 06:15:48 PM UTC 25 |
| Finished | Feb 08 06:16:09 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187277082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.1187277082 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_disable_endpoint.2624243869 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 693048213 ps |
| CPU time | 3.25 seconds |
| Started | Feb 08 06:15:48 PM UTC 25 |
| Finished | Feb 08 06:15:53 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2624243869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.usbdev_disable_endpoint.2624243869 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_disconnected.3411345586 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 179252424 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:15:48 PM UTC 25 |
| Finished | Feb 08 06:15:51 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3411345586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.us bdev_disconnected.3411345586 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_enable.171720998 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 43006477 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 06:15:48 PM UTC 25 |
| Finished | Feb 08 06:15:51 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=171720998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_en able.171720998 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_endpoint_access.1168251024 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 1019238389 ps |
| CPU time | 3.31 seconds |
| Started | Feb 08 06:15:48 PM UTC 25 |
| Finished | Feb 08 06:15:53 PM UTC 25 |
| Peak memory | 217580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1168251024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43 .usbdev_endpoint_access.1168251024 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_endpoint_types.3183377010 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 299013043 ps |
| CPU time | 1.91 seconds |
| Started | Feb 08 06:15:48 PM UTC 25 |
| Finished | Feb 08 06:15:52 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183377010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 43.usbdev_endpoint_types.3183377010 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_fifo_rst.1423411478 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 365506712 ps |
| CPU time | 3.78 seconds |
| Started | Feb 08 06:15:48 PM UTC 25 |
| Finished | Feb 08 06:15:53 PM UTC 25 |
| Peak memory | 217288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1423411478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev _fifo_rst.1423411478 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_in_iso.96461272 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 271777163 ps |
| CPU time | 1.85 seconds |
| Started | Feb 08 06:15:50 PM UTC 25 |
| Finished | Feb 08 06:15:53 PM UTC 25 |
| Peak memory | 227812 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96461272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 43.usbdev_in_iso.96461272 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_in_stall.4263199147 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 181924017 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:15:50 PM UTC 25 |
| Finished | Feb 08 06:15:53 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4263199147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev _in_stall.4263199147 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_in_trans.2955072108 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 204016278 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:15:50 PM UTC 25 |
| Finished | Feb 08 06:15:53 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2955072108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev _in_trans.2955072108 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_invalid_sync.1316970254 |
| Short name | T3072 |
| Test name | |
| Test status | |
| Simulation time | 4389028981 ps |
| CPU time | 122.98 seconds |
| Started | Feb 08 06:15:50 PM UTC 25 |
| Finished | Feb 08 06:17:55 PM UTC 25 |
| Peak memory | 234520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316970254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.1316970254 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_iso_retraction.3520879411 |
| Short name | T3005 |
| Test name | |
| Test status | |
| Simulation time | 14277362730 ps |
| CPU time | 100.02 seconds |
| Started | Feb 08 06:15:50 PM UTC 25 |
| Finished | Feb 08 06:17:32 PM UTC 25 |
| Peak memory | 217412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520879411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 43.usbdev_iso_retraction.3520879411 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_link_in_err.1278725671 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 252806894 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:15:50 PM UTC 25 |
| Finished | Feb 08 06:15:53 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1278725671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usb dev_link_in_err.1278725671 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_link_resume.4130740670 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 6052667629 ps |
| CPU time | 11.43 seconds |
| Started | Feb 08 06:15:50 PM UTC 25 |
| Finished | Feb 08 06:16:03 PM UTC 25 |
| Peak memory | 217424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4130740670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usb dev_link_resume.4130740670 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_link_suspend.158026556 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 5866924403 ps |
| CPU time | 17.16 seconds |
| Started | Feb 08 06:15:51 PM UTC 25 |
| Finished | Feb 08 06:16:10 PM UTC 25 |
| Peak memory | 227664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=158026556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usb dev_link_suspend.158026556 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_low_speed_traffic.2567856433 |
| Short name | T3099 |
| Test name | |
| Test status | |
| Simulation time | 4555303972 ps |
| CPU time | 127.3 seconds |
| Started | Feb 08 06:15:52 PM UTC 25 |
| Finished | Feb 08 06:18:02 PM UTC 25 |
| Peak memory | 229792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567856433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 43.usbdev_low_speed_traffic.2567856433 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_max_inter_pkt_delay.3039222366 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 2057834231 ps |
| CPU time | 56.62 seconds |
| Started | Feb 08 06:15:52 PM UTC 25 |
| Finished | Feb 08 06:16:51 PM UTC 25 |
| Peak memory | 227720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039222366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.3039222366 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_max_length_in_transaction.2539272964 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 276049371 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 06:15:54 PM UTC 25 |
| Finished | Feb 08 06:15:57 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539272964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 43.usbdev_max_length_in_transaction.2539272964 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_max_length_out_transaction.4190489716 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 233071466 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:15:54 PM UTC 25 |
| Finished | Feb 08 06:15:57 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4190489716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.4190489716 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_min_inter_pkt_delay.3441613783 |
| Short name | T2999 |
| Test name | |
| Test status | |
| Simulation time | 3577838482 ps |
| CPU time | 94.04 seconds |
| Started | Feb 08 06:15:54 PM UTC 25 |
| Finished | Feb 08 06:17:30 PM UTC 25 |
| Peak memory | 227912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441613783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.3441613783 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_min_length_in_transaction.3185554164 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 230489839 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:15:54 PM UTC 25 |
| Finished | Feb 08 06:15:56 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185554164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 43.usbdev_min_length_in_transaction.3185554164 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_min_length_out_transaction.8839005 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 156818875 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:15:54 PM UTC 25 |
| Finished | Feb 08 06:15:57 PM UTC 25 |
| Peak memory | 215044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=8839005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 43.usbdev_min_length_out_transaction.8839005 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_nak_trans.3569791987 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 167563118 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:15:54 PM UTC 25 |
| Finished | Feb 08 06:15:57 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3569791987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbde v_nak_trans.3569791987 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_out_iso.1852804608 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 195041713 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:15:55 PM UTC 25 |
| Finished | Feb 08 06:15:58 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1852804608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_ out_iso.1852804608 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_out_stall.215087048 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 173647108 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:15:56 PM UTC 25 |
| Finished | Feb 08 06:15:59 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=215087048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev _out_stall.215087048 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_out_trans_nak.3009375612 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 155441562 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:15:58 PM UTC 25 |
| Finished | Feb 08 06:16:00 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3009375612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.u sbdev_out_trans_nak.3009375612 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_pending_in_trans.2368636772 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 161535989 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:15:58 PM UTC 25 |
| Finished | Feb 08 06:16:00 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2368636772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.usbdev_pending_in_trans.2368636772 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_phy_config_pinflip.226919263 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 182802284 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:15:58 PM UTC 25 |
| Finished | Feb 08 06:16:01 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=226919263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 43.usbdev_phy_config_pinflip.226919263 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_phy_config_usb_ref_disable.1238839533 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 158956358 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:15:58 PM UTC 25 |
| Finished | Feb 08 06:16:00 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1238839533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.1238839533 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_phy_pins_sense.469308553 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 35193438 ps |
| CPU time | 1 seconds |
| Started | Feb 08 06:15:58 PM UTC 25 |
| Finished | Feb 08 06:16:00 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=469308553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.u sbdev_phy_pins_sense.469308553 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_pkt_buffer.1129588118 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 14588327916 ps |
| CPU time | 49.58 seconds |
| Started | Feb 08 06:15:59 PM UTC 25 |
| Finished | Feb 08 06:16:50 PM UTC 25 |
| Peak memory | 227692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1129588118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbd ev_pkt_buffer.1129588118 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_pkt_received.3739754577 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 192855883 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:15:59 PM UTC 25 |
| Finished | Feb 08 06:16:02 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3739754577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.us bdev_pkt_received.3739754577 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_pkt_sent.2873302757 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 177383045 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:15:59 PM UTC 25 |
| Finished | Feb 08 06:16:02 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2873302757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev _pkt_sent.2873302757 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_random_length_in_transaction.2265849077 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 194223311 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:15:59 PM UTC 25 |
| Finished | Feb 08 06:16:02 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2265849077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.u sbdev_random_length_in_transaction.2265849077 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_random_length_out_transaction.2569470095 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 181833466 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:16:02 PM UTC 25 |
| Finished | Feb 08 06:16:04 PM UTC 25 |
| Peak memory | 215016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2569470095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 43.usbdev_random_length_out_transaction.2569470095 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_rx_crc_err.1102113480 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 144287796 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:16:02 PM UTC 25 |
| Finished | Feb 08 06:16:04 PM UTC 25 |
| Peak memory | 214976 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1102113480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbd ev_rx_crc_err.1102113480 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_rx_full.3755568590 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 373896363 ps |
| CPU time | 1.84 seconds |
| Started | Feb 08 06:16:02 PM UTC 25 |
| Finished | Feb 08 06:16:05 PM UTC 25 |
| Peak memory | 215084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3755568590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_ rx_full.3755568590 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_setup_stage.4256488951 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 153140304 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:16:02 PM UTC 25 |
| Finished | Feb 08 06:16:04 PM UTC 25 |
| Peak memory | 215060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4256488951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usb dev_setup_stage.4256488951 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_setup_trans_ignored.722022468 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 156493975 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:16:02 PM UTC 25 |
| Finished | Feb 08 06:16:04 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=722022468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.722022468 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_smoke.3975100338 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 278034798 ps |
| CPU time | 1.77 seconds |
| Started | Feb 08 06:16:02 PM UTC 25 |
| Finished | Feb 08 06:16:05 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3975100338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_sm oke.3975100338 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_spurious_pids_ignored.3459551464 |
| Short name | T3024 |
| Test name | |
| Test status | |
| Simulation time | 2772318119 ps |
| CPU time | 93.11 seconds |
| Started | Feb 08 06:16:03 PM UTC 25 |
| Finished | Feb 08 06:17:39 PM UTC 25 |
| Peak memory | 229772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459551464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 43.usbdev_spurious_pids_ignored.3459551464 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_stall_priority_over_nak.984650115 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 164118005 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 06:16:03 PM UTC 25 |
| Finished | Feb 08 06:16:06 PM UTC 25 |
| Peak memory | 214900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=984650115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 43.usbdev_stall_priority_over_nak.984650115 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_stall_trans.1880617495 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 187896768 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 06:16:03 PM UTC 25 |
| Finished | Feb 08 06:16:06 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1880617495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usb dev_stall_trans.1880617495 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_stream_len_max.3521613370 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 451722031 ps |
| CPU time | 1.71 seconds |
| Started | Feb 08 06:16:04 PM UTC 25 |
| Finished | Feb 08 06:16:06 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3521613370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43. usbdev_stream_len_max.3521613370 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_streaming_out.3557642176 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 3337594325 ps |
| CPU time | 30.01 seconds |
| Started | Feb 08 06:16:03 PM UTC 25 |
| Finished | Feb 08 06:16:35 PM UTC 25 |
| Peak memory | 229956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3557642176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbde v_streaming_out.3557642176 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_timeout_missing_host_handshake.2961937400 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 2235019198 ps |
| CPU time | 16.6 seconds |
| Started | Feb 08 06:15:48 PM UTC 25 |
| Finished | Feb 08 06:16:06 PM UTC 25 |
| Peak memory | 217604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961937400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing_host_handshake.2961937400 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_tx_rx_disruption.2271237671 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 533340711 ps |
| CPU time | 2.13 seconds |
| Started | Feb 08 06:16:04 PM UTC 25 |
| Finished | Feb 08 06:16:07 PM UTC 25 |
| Peak memory | 217180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 271237671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_tx_rx_disruption.2271237671 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/43.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/430.usbdev_tx_rx_disruption.1831065320 |
| Short name | T3557 |
| Test name | |
| Test status | |
| Simulation time | 651326815 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 831065320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 430.usbdev_tx_rx_disruption.1831065320 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/430.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/431.usbdev_tx_rx_disruption.266012411 |
| Short name | T3552 |
| Test name | |
| Test status | |
| Simulation time | 557737471 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 66012411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 431.usbdev_tx_rx_disruption.266012411 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/431.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/432.usbdev_tx_rx_disruption.2173560028 |
| Short name | T3562 |
| Test name | |
| Test status | |
| Simulation time | 623709882 ps |
| CPU time | 1.74 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 173560028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 432.usbdev_tx_rx_disruption.2173560028 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/432.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/433.usbdev_tx_rx_disruption.2462858387 |
| Short name | T3551 |
| Test name | |
| Test status | |
| Simulation time | 473702629 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 462858387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 433.usbdev_tx_rx_disruption.2462858387 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/433.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/434.usbdev_tx_rx_disruption.2924350418 |
| Short name | T3555 |
| Test name | |
| Test status | |
| Simulation time | 533115464 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 924350418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 434.usbdev_tx_rx_disruption.2924350418 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/434.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/435.usbdev_tx_rx_disruption.3188333043 |
| Short name | T3553 |
| Test name | |
| Test status | |
| Simulation time | 441587348 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 188333043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 435.usbdev_tx_rx_disruption.3188333043 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/435.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/436.usbdev_tx_rx_disruption.3776560955 |
| Short name | T3556 |
| Test name | |
| Test status | |
| Simulation time | 507391234 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 776560955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 436.usbdev_tx_rx_disruption.3776560955 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/436.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/437.usbdev_tx_rx_disruption.3099401388 |
| Short name | T3558 |
| Test name | |
| Test status | |
| Simulation time | 618693405 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 099401388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 437.usbdev_tx_rx_disruption.3099401388 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/437.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/438.usbdev_tx_rx_disruption.3995903903 |
| Short name | T3561 |
| Test name | |
| Test status | |
| Simulation time | 638620111 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 995903903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 438.usbdev_tx_rx_disruption.3995903903 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/438.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/439.usbdev_tx_rx_disruption.3385483893 |
| Short name | T3554 |
| Test name | |
| Test status | |
| Simulation time | 547313693 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 385483893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 439.usbdev_tx_rx_disruption.3385483893 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/439.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_alert_test.3639022823 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 72125527 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 06:16:22 PM UTC 25 |
| Finished | Feb 08 06:16:24 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639022823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 44.usbdev_alert_test.3639022823 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_aon_wake_disconnect.2472564432 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 6408300566 ps |
| CPU time | 13.64 seconds |
| Started | Feb 08 06:16:05 PM UTC 25 |
| Finished | Feb 08 06:16:20 PM UTC 25 |
| Peak memory | 227652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472564432 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.2472564432 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_aon_wake_reset.3610826802 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 15443550814 ps |
| CPU time | 22.8 seconds |
| Started | Feb 08 06:16:05 PM UTC 25 |
| Finished | Feb 08 06:16:29 PM UTC 25 |
| Peak memory | 227784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610826802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.3610826802 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_aon_wake_resume.3325660234 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 26238782095 ps |
| CPU time | 39.45 seconds |
| Started | Feb 08 06:16:05 PM UTC 25 |
| Finished | Feb 08 06:16:46 PM UTC 25 |
| Peak memory | 227632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325660234 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.3325660234 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_av_buffer.2416715883 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 167908225 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:16:05 PM UTC 25 |
| Finished | Feb 08 06:16:07 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2416715883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbde v_av_buffer.2416715883 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_bitstuff_err.2475099409 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 160664374 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:16:06 PM UTC 25 |
| Finished | Feb 08 06:16:09 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2475099409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.us bdev_bitstuff_err.2475099409 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_data_toggle_clear.1811907192 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 424608001 ps |
| CPU time | 1.85 seconds |
| Started | Feb 08 06:16:07 PM UTC 25 |
| Finished | Feb 08 06:16:09 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1811907192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.1811907192 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_data_toggle_restore.3788486167 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 642890560 ps |
| CPU time | 2.13 seconds |
| Started | Feb 08 06:16:07 PM UTC 25 |
| Finished | Feb 08 06:16:10 PM UTC 25 |
| Peak memory | 217380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788486167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.3788486167 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_device_address.255256923 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 16747068208 ps |
| CPU time | 30.17 seconds |
| Started | Feb 08 06:16:07 PM UTC 25 |
| Finished | Feb 08 06:16:38 PM UTC 25 |
| Peak memory | 217380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=255256923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.u sbdev_device_address.255256923 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_device_timeout.3621724374 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 4777070060 ps |
| CPU time | 41.38 seconds |
| Started | Feb 08 06:16:07 PM UTC 25 |
| Finished | Feb 08 06:16:50 PM UTC 25 |
| Peak memory | 217520 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621724374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.3621724374 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_disable_endpoint.227937479 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 845703569 ps |
| CPU time | 3.66 seconds |
| Started | Feb 08 06:16:08 PM UTC 25 |
| Finished | Feb 08 06:16:13 PM UTC 25 |
| Peak memory | 216344 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=227937479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44 .usbdev_disable_endpoint.227937479 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_disconnected.345822619 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 139719513 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:16:08 PM UTC 25 |
| Finished | Feb 08 06:16:11 PM UTC 25 |
| Peak memory | 216148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=345822619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usb dev_disconnected.345822619 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_enable.2565858666 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 37236282 ps |
| CPU time | 0.96 seconds |
| Started | Feb 08 06:16:08 PM UTC 25 |
| Finished | Feb 08 06:16:10 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2565858666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_e nable.2565858666 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_endpoint_access.189701972 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 1013405463 ps |
| CPU time | 4.22 seconds |
| Started | Feb 08 06:16:08 PM UTC 25 |
| Finished | Feb 08 06:16:14 PM UTC 25 |
| Peak memory | 217384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=189701972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44. usbdev_endpoint_access.189701972 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_endpoint_types.2792668820 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 454325267 ps |
| CPU time | 2 seconds |
| Started | Feb 08 06:16:08 PM UTC 25 |
| Finished | Feb 08 06:16:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792668820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 44.usbdev_endpoint_types.2792668820 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_fifo_rst.1348545232 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 165596991 ps |
| CPU time | 2.22 seconds |
| Started | Feb 08 06:16:08 PM UTC 25 |
| Finished | Feb 08 06:16:12 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1348545232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev _fifo_rst.1348545232 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_in_iso.1685680764 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 152711247 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 06:16:10 PM UTC 25 |
| Finished | Feb 08 06:16:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685680764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 44.usbdev_in_iso.1685680764 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_in_stall.1859760673 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 142044289 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:16:10 PM UTC 25 |
| Finished | Feb 08 06:16:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1859760673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev _in_stall.1859760673 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_in_trans.619213815 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 173677103 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 06:16:12 PM UTC 25 |
| Finished | Feb 08 06:16:14 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=619213815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_ in_trans.619213815 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_invalid_sync.1993389850 |
| Short name | T2969 |
| Test name | |
| Test status | |
| Simulation time | 2470637794 ps |
| CPU time | 65.46 seconds |
| Started | Feb 08 06:16:10 PM UTC 25 |
| Finished | Feb 08 06:17:17 PM UTC 25 |
| Peak memory | 227852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993389850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.1993389850 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_iso_retraction.1830576600 |
| Short name | T3027 |
| Test name | |
| Test status | |
| Simulation time | 13203215824 ps |
| CPU time | 86.16 seconds |
| Started | Feb 08 06:16:12 PM UTC 25 |
| Finished | Feb 08 06:17:40 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830576600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 44.usbdev_iso_retraction.1830576600 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_link_in_err.230758158 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 152350841 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 06:16:12 PM UTC 25 |
| Finished | Feb 08 06:16:14 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=230758158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbd ev_link_in_err.230758158 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_link_resume.2758910524 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 9073079008 ps |
| CPU time | 14.68 seconds |
| Started | Feb 08 06:16:12 PM UTC 25 |
| Finished | Feb 08 06:16:28 PM UTC 25 |
| Peak memory | 217552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2758910524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usb dev_link_resume.2758910524 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_link_suspend.2410484817 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 3947688439 ps |
| CPU time | 8.02 seconds |
| Started | Feb 08 06:16:12 PM UTC 25 |
| Finished | Feb 08 06:16:22 PM UTC 25 |
| Peak memory | 227592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2410484817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.us bdev_link_suspend.2410484817 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_low_speed_traffic.1893938095 |
| Short name | T3125 |
| Test name | |
| Test status | |
| Simulation time | 4356418900 ps |
| CPU time | 115.81 seconds |
| Started | Feb 08 06:16:12 PM UTC 25 |
| Finished | Feb 08 06:18:10 PM UTC 25 |
| Peak memory | 229972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893938095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 44.usbdev_low_speed_traffic.1893938095 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_max_inter_pkt_delay.1408445788 |
| Short name | T2970 |
| Test name | |
| Test status | |
| Simulation time | 2342293774 ps |
| CPU time | 62.87 seconds |
| Started | Feb 08 06:16:12 PM UTC 25 |
| Finished | Feb 08 06:17:17 PM UTC 25 |
| Peak memory | 227720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408445788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.1408445788 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_max_length_in_transaction.2588649435 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 259059823 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:16:12 PM UTC 25 |
| Finished | Feb 08 06:16:15 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588649435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 44.usbdev_max_length_in_transaction.2588649435 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_max_length_out_transaction.1787550853 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 193570604 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:16:14 PM UTC 25 |
| Finished | Feb 08 06:16:17 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1787550853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1787550853 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_min_inter_pkt_delay.239384939 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 2570313432 ps |
| CPU time | 18.31 seconds |
| Started | Feb 08 06:16:14 PM UTC 25 |
| Finished | Feb 08 06:16:34 PM UTC 25 |
| Peak memory | 234428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239384939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usb dev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.239384939 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_min_length_in_transaction.3254531057 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 175289010 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:16:14 PM UTC 25 |
| Finished | Feb 08 06:16:16 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254531057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 44.usbdev_min_length_in_transaction.3254531057 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_min_length_out_transaction.1362515138 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 185173610 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:16:14 PM UTC 25 |
| Finished | Feb 08 06:16:17 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1362515138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1362515138 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_nak_trans.842214462 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 226804268 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:16:14 PM UTC 25 |
| Finished | Feb 08 06:16:17 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=842214462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev _nak_trans.842214462 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_out_iso.151482462 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 192264034 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 06:16:14 PM UTC 25 |
| Finished | Feb 08 06:16:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=151482462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_o ut_iso.151482462 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_out_stall.4242112938 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 245799628 ps |
| CPU time | 1.71 seconds |
| Started | Feb 08 06:16:15 PM UTC 25 |
| Finished | Feb 08 06:16:18 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4242112938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbde v_out_stall.4242112938 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_out_trans_nak.1172474780 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 203500529 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:16:15 PM UTC 25 |
| Finished | Feb 08 06:16:18 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1172474780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.u sbdev_out_trans_nak.1172474780 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_pending_in_trans.1499863062 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 141974989 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:16:15 PM UTC 25 |
| Finished | Feb 08 06:16:18 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1499863062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.usbdev_pending_in_trans.1499863062 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_phy_config_pinflip.2026111644 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 263352469 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 06:16:15 PM UTC 25 |
| Finished | Feb 08 06:16:18 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026111644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 44.usbdev_phy_config_pinflip.2026111644 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_phy_config_usb_ref_disable.2642351481 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 137318379 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:16:17 PM UTC 25 |
| Finished | Feb 08 06:16:19 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2642351481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.2642351481 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_phy_pins_sense.346372797 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 47095583 ps |
| CPU time | 0.79 seconds |
| Started | Feb 08 06:16:18 PM UTC 25 |
| Finished | Feb 08 06:16:20 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=346372797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.u sbdev_phy_pins_sense.346372797 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_pkt_buffer.508800785 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 8521271052 ps |
| CPU time | 24.11 seconds |
| Started | Feb 08 06:16:18 PM UTC 25 |
| Finished | Feb 08 06:16:44 PM UTC 25 |
| Peak memory | 227688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=508800785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbde v_pkt_buffer.508800785 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_pkt_received.807198528 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 179272631 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:16:18 PM UTC 25 |
| Finished | Feb 08 06:16:21 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=807198528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usb dev_pkt_received.807198528 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_pkt_sent.3798625731 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 180119351 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:16:18 PM UTC 25 |
| Finished | Feb 08 06:16:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3798625731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev _pkt_sent.3798625731 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_random_length_in_transaction.1206091822 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 169106872 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:16:18 PM UTC 25 |
| Finished | Feb 08 06:16:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1206091822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.u sbdev_random_length_in_transaction.1206091822 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_random_length_out_transaction.3512493156 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 205286024 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:16:18 PM UTC 25 |
| Finished | Feb 08 06:16:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3512493156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 44.usbdev_random_length_out_transaction.3512493156 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_rx_crc_err.629814522 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 148242565 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:16:20 PM UTC 25 |
| Finished | Feb 08 06:16:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=629814522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbde v_rx_crc_err.629814522 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_rx_full.742160604 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 331265326 ps |
| CPU time | 2.01 seconds |
| Started | Feb 08 06:16:20 PM UTC 25 |
| Finished | Feb 08 06:16:23 PM UTC 25 |
| Peak memory | 217304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=742160604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_r x_full.742160604 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_setup_stage.2090053409 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 223999012 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:16:20 PM UTC 25 |
| Finished | Feb 08 06:16:23 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2090053409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usb dev_setup_stage.2090053409 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_setup_trans_ignored.1339021938 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 147362488 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:16:20 PM UTC 25 |
| Finished | Feb 08 06:16:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1339021938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 44.usbdev_setup_trans_ignored.1339021938 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_smoke.4040120074 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 210258186 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:16:20 PM UTC 25 |
| Finished | Feb 08 06:16:23 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4040120074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_sm oke.4040120074 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_spurious_pids_ignored.3759343736 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 2481769734 ps |
| CPU time | 29.18 seconds |
| Started | Feb 08 06:16:20 PM UTC 25 |
| Finished | Feb 08 06:16:51 PM UTC 25 |
| Peak memory | 229652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759343736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 44.usbdev_spurious_pids_ignored.3759343736 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_stall_priority_over_nak.79480916 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 199921257 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:16:20 PM UTC 25 |
| Finished | Feb 08 06:16:23 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=79480916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 44.usbdev_stall_priority_over_nak.79480916 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_stall_trans.14039347 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 178664230 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 06:16:22 PM UTC 25 |
| Finished | Feb 08 06:16:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=14039347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbde v_stall_trans.14039347 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_stream_len_max.2683582521 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 198412094 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:16:22 PM UTC 25 |
| Finished | Feb 08 06:16:25 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2683582521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44. usbdev_stream_len_max.2683582521 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_streaming_out.2362896077 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 2515689974 ps |
| CPU time | 27.68 seconds |
| Started | Feb 08 06:16:22 PM UTC 25 |
| Finished | Feb 08 06:16:51 PM UTC 25 |
| Peak memory | 229716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2362896077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbde v_streaming_out.2362896077 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_timeout_missing_host_handshake.1157117016 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 1430217876 ps |
| CPU time | 35.25 seconds |
| Started | Feb 08 06:16:08 PM UTC 25 |
| Finished | Feb 08 06:16:45 PM UTC 25 |
| Peak memory | 217548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157117016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing_host_handshake.1157117016 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_tx_rx_disruption.2928819390 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 495826368 ps |
| CPU time | 2.1 seconds |
| Started | Feb 08 06:16:22 PM UTC 25 |
| Finished | Feb 08 06:16:25 PM UTC 25 |
| Peak memory | 217116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 928819390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_tx_rx_disruption.2928819390 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/44.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/440.usbdev_tx_rx_disruption.1200872115 |
| Short name | T3566 |
| Test name | |
| Test status | |
| Simulation time | 501311025 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 200872115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 440.usbdev_tx_rx_disruption.1200872115 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/440.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/441.usbdev_tx_rx_disruption.1456105810 |
| Short name | T3560 |
| Test name | |
| Test status | |
| Simulation time | 513354998 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 456105810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 441.usbdev_tx_rx_disruption.1456105810 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/441.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/442.usbdev_tx_rx_disruption.2785493076 |
| Short name | T3565 |
| Test name | |
| Test status | |
| Simulation time | 543688035 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 785493076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 442.usbdev_tx_rx_disruption.2785493076 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/442.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/443.usbdev_tx_rx_disruption.878895247 |
| Short name | T3564 |
| Test name | |
| Test status | |
| Simulation time | 641469534 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 78895247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 443.usbdev_tx_rx_disruption.878895247 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/443.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/444.usbdev_tx_rx_disruption.4211782252 |
| Short name | T3593 |
| Test name | |
| Test status | |
| Simulation time | 567306204 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:24 PM UTC 25 |
| Peak memory | 216704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 211782252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 444.usbdev_tx_rx_disruption.4211782252 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/444.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/445.usbdev_tx_rx_disruption.1897121483 |
| Short name | T3563 |
| Test name | |
| Test status | |
| Simulation time | 525901794 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:20:11 PM UTC 25 |
| Finished | Feb 08 06:20:14 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 897121483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 445.usbdev_tx_rx_disruption.1897121483 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/445.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/446.usbdev_tx_rx_disruption.3607714160 |
| Short name | T3608 |
| Test name | |
| Test status | |
| Simulation time | 722352845 ps |
| CPU time | 1.88 seconds |
| Started | Feb 08 06:20:13 PM UTC 25 |
| Finished | Feb 08 06:20:30 PM UTC 25 |
| Peak memory | 215060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 607714160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 446.usbdev_tx_rx_disruption.3607714160 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/446.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/447.usbdev_tx_rx_disruption.667300481 |
| Short name | T3613 |
| Test name | |
| Test status | |
| Simulation time | 485888740 ps |
| CPU time | 1.84 seconds |
| Started | Feb 08 06:20:13 PM UTC 25 |
| Finished | Feb 08 06:20:30 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6 67300481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 447.usbdev_tx_rx_disruption.667300481 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/447.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/448.usbdev_tx_rx_disruption.2356305139 |
| Short name | T3600 |
| Test name | |
| Test status | |
| Simulation time | 471859301 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:20:13 PM UTC 25 |
| Finished | Feb 08 06:20:26 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 356305139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 448.usbdev_tx_rx_disruption.2356305139 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/448.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/449.usbdev_tx_rx_disruption.2603202676 |
| Short name | T3607 |
| Test name | |
| Test status | |
| Simulation time | 467694057 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:20:13 PM UTC 25 |
| Finished | Feb 08 06:20:30 PM UTC 25 |
| Peak memory | 215088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 603202676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 449.usbdev_tx_rx_disruption.2603202676 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/449.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_alert_test.2216621891 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 86387789 ps |
| CPU time | 0.98 seconds |
| Started | Feb 08 06:16:43 PM UTC 25 |
| Finished | Feb 08 06:16:45 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216621891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 45.usbdev_alert_test.2216621891 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_aon_wake_disconnect.2255221129 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 4573679445 ps |
| CPU time | 9.57 seconds |
| Started | Feb 08 06:16:22 PM UTC 25 |
| Finished | Feb 08 06:16:33 PM UTC 25 |
| Peak memory | 227524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255221129 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.2255221129 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_aon_wake_reset.3600615865 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 14687997480 ps |
| CPU time | 22.94 seconds |
| Started | Feb 08 06:16:22 PM UTC 25 |
| Finished | Feb 08 06:16:46 PM UTC 25 |
| Peak memory | 227592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600615865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.3600615865 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_aon_wake_resume.3659347387 |
| Short name | T2958 |
| Test name | |
| Test status | |
| Simulation time | 29110847226 ps |
| CPU time | 48.26 seconds |
| Started | Feb 08 06:16:24 PM UTC 25 |
| Finished | Feb 08 06:17:14 PM UTC 25 |
| Peak memory | 217160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659347387 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.3659347387 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_av_buffer.451907518 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 167570192 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:16:24 PM UTC 25 |
| Finished | Feb 08 06:16:26 PM UTC 25 |
| Peak memory | 214908 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=451907518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev _av_buffer.451907518 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_bitstuff_err.4244456133 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 185884585 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:16:24 PM UTC 25 |
| Finished | Feb 08 06:16:26 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4244456133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.us bdev_bitstuff_err.4244456133 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_data_toggle_clear.21947432 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 432314035 ps |
| CPU time | 2.56 seconds |
| Started | Feb 08 06:16:24 PM UTC 25 |
| Finished | Feb 08 06:16:28 PM UTC 25 |
| Peak memory | 217176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=21947432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45 .usbdev_data_toggle_clear.21947432 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_data_toggle_restore.2692598533 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 961206652 ps |
| CPU time | 4.64 seconds |
| Started | Feb 08 06:16:24 PM UTC 25 |
| Finished | Feb 08 06:16:30 PM UTC 25 |
| Peak memory | 217444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692598533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.2692598533 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_device_address.1454281193 |
| Short name | T3020 |
| Test name | |
| Test status | |
| Simulation time | 34550290796 ps |
| CPU time | 71.83 seconds |
| Started | Feb 08 06:16:24 PM UTC 25 |
| Finished | Feb 08 06:17:38 PM UTC 25 |
| Peak memory | 217408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1454281193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45. usbdev_device_address.1454281193 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_device_timeout.3944019021 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 2216340997 ps |
| CPU time | 16.51 seconds |
| Started | Feb 08 06:16:24 PM UTC 25 |
| Finished | Feb 08 06:16:42 PM UTC 25 |
| Peak memory | 217404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944019021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.3944019021 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_disable_endpoint.451706833 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 727573762 ps |
| CPU time | 3.52 seconds |
| Started | Feb 08 06:16:25 PM UTC 25 |
| Finished | Feb 08 06:16:30 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=451706833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45 .usbdev_disable_endpoint.451706833 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_disconnected.48876675 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 153164311 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:16:26 PM UTC 25 |
| Finished | Feb 08 06:16:28 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=48876675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbd ev_disconnected.48876675 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_enable.18952648 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 117594679 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:16:26 PM UTC 25 |
| Finished | Feb 08 06:16:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=18952648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_ena ble.18952648 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_endpoint_access.1301891246 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 741085205 ps |
| CPU time | 4.04 seconds |
| Started | Feb 08 06:16:26 PM UTC 25 |
| Finished | Feb 08 06:16:31 PM UTC 25 |
| Peak memory | 217580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1301891246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45 .usbdev_endpoint_access.1301891246 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_endpoint_types.944765664 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 190553696 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:16:27 PM UTC 25 |
| Finished | Feb 08 06:16:30 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944765664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 45.usbdev_endpoint_types.944765664 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_fifo_rst.1397820724 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 190975674 ps |
| CPU time | 3.58 seconds |
| Started | Feb 08 06:16:27 PM UTC 25 |
| Finished | Feb 08 06:16:32 PM UTC 25 |
| Peak memory | 217396 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1397820724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev _fifo_rst.1397820724 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_in_iso.2862952838 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 274272297 ps |
| CPU time | 2.23 seconds |
| Started | Feb 08 06:16:28 PM UTC 25 |
| Finished | Feb 08 06:16:31 PM UTC 25 |
| Peak memory | 227820 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862952838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 45.usbdev_in_iso.2862952838 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_in_stall.3920809307 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 165693443 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:16:29 PM UTC 25 |
| Finished | Feb 08 06:16:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3920809307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev _in_stall.3920809307 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_in_trans.4026088233 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 274029600 ps |
| CPU time | 1.9 seconds |
| Started | Feb 08 06:16:29 PM UTC 25 |
| Finished | Feb 08 06:16:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4026088233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev _in_trans.4026088233 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_invalid_sync.2170201539 |
| Short name | T2949 |
| Test name | |
| Test status | |
| Simulation time | 4122204608 ps |
| CPU time | 40.46 seconds |
| Started | Feb 08 06:16:27 PM UTC 25 |
| Finished | Feb 08 06:17:09 PM UTC 25 |
| Peak memory | 229900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170201539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.2170201539 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_iso_retraction.166521240 |
| Short name | T3078 |
| Test name | |
| Test status | |
| Simulation time | 6412127595 ps |
| CPU time | 86.03 seconds |
| Started | Feb 08 06:16:29 PM UTC 25 |
| Finished | Feb 08 06:17:57 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166521240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retra ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 45.usbdev_iso_retraction.166521240 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_link_in_err.3353323247 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 204465456 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:16:31 PM UTC 25 |
| Finished | Feb 08 06:16:33 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3353323247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usb dev_link_in_err.3353323247 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_link_resume.2286409478 |
| Short name | T2908 |
| Test name | |
| Test status | |
| Simulation time | 8556337297 ps |
| CPU time | 20.22 seconds |
| Started | Feb 08 06:16:31 PM UTC 25 |
| Finished | Feb 08 06:16:52 PM UTC 25 |
| Peak memory | 217616 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2286409478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usb dev_link_resume.2286409478 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_link_suspend.3857747312 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 4985672643 ps |
| CPU time | 15.59 seconds |
| Started | Feb 08 06:16:31 PM UTC 25 |
| Finished | Feb 08 06:16:48 PM UTC 25 |
| Peak memory | 227784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3857747312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.us bdev_link_suspend.3857747312 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_low_speed_traffic.1422316796 |
| Short name | T3249 |
| Test name | |
| Test status | |
| Simulation time | 4446997191 ps |
| CPU time | 120.94 seconds |
| Started | Feb 08 06:16:31 PM UTC 25 |
| Finished | Feb 08 06:18:34 PM UTC 25 |
| Peak memory | 229864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422316796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 45.usbdev_low_speed_traffic.1422316796 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_max_inter_pkt_delay.596958261 |
| Short name | T2907 |
| Test name | |
| Test status | |
| Simulation time | 2373273932 ps |
| CPU time | 19.04 seconds |
| Started | Feb 08 06:16:32 PM UTC 25 |
| Finished | Feb 08 06:16:52 PM UTC 25 |
| Peak memory | 217700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596958261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.596958261 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_max_length_in_transaction.2940237258 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 269797218 ps |
| CPU time | 1.79 seconds |
| Started | Feb 08 06:16:32 PM UTC 25 |
| Finished | Feb 08 06:16:35 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940237258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 45.usbdev_max_length_in_transaction.2940237258 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_max_length_out_transaction.815886182 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 239124298 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:16:34 PM UTC 25 |
| Finished | Feb 08 06:16:36 PM UTC 25 |
| Peak memory | 214872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=815886182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 45.usbdev_max_length_out_transaction.815886182 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_min_inter_pkt_delay.1944897078 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 2129772805 ps |
| CPU time | 16.58 seconds |
| Started | Feb 08 06:16:34 PM UTC 25 |
| Finished | Feb 08 06:16:52 PM UTC 25 |
| Peak memory | 227436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944897078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.1944897078 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_min_length_in_transaction.2241240055 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 181900287 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:16:34 PM UTC 25 |
| Finished | Feb 08 06:16:36 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241240055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 45.usbdev_min_length_in_transaction.2241240055 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_min_length_out_transaction.888802199 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 154656112 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:16:34 PM UTC 25 |
| Finished | Feb 08 06:16:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=888802199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 45.usbdev_min_length_out_transaction.888802199 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_out_iso.2038271947 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 190940922 ps |
| CPU time | 1.21 seconds |
| Started | Feb 08 06:16:35 PM UTC 25 |
| Finished | Feb 08 06:16:38 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2038271947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_ out_iso.2038271947 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_out_stall.1269135881 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 158572781 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:16:35 PM UTC 25 |
| Finished | Feb 08 06:16:38 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1269135881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbde v_out_stall.1269135881 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_out_trans_nak.1887502018 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 161123172 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:16:35 PM UTC 25 |
| Finished | Feb 08 06:16:38 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1887502018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.u sbdev_out_trans_nak.1887502018 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_pending_in_trans.3546066931 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 161905678 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:16:35 PM UTC 25 |
| Finished | Feb 08 06:16:38 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3546066931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.usbdev_pending_in_trans.3546066931 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_phy_config_pinflip.2525480149 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 210945880 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:16:37 PM UTC 25 |
| Finished | Feb 08 06:16:39 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525480149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 45.usbdev_phy_config_pinflip.2525480149 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_phy_config_usb_ref_disable.2794476696 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 141075498 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:16:37 PM UTC 25 |
| Finished | Feb 08 06:16:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2794476696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.2794476696 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_phy_pins_sense.941370483 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 90800105 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:16:38 PM UTC 25 |
| Finished | Feb 08 06:16:40 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=941370483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.u sbdev_phy_pins_sense.941370483 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_pkt_buffer.2240556923 |
| Short name | T2985 |
| Test name | |
| Test status | |
| Simulation time | 13686548251 ps |
| CPU time | 43 seconds |
| Started | Feb 08 06:16:38 PM UTC 25 |
| Finished | Feb 08 06:17:23 PM UTC 25 |
| Peak memory | 227684 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2240556923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbd ev_pkt_buffer.2240556923 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_pkt_received.3547023077 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 190257046 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:16:38 PM UTC 25 |
| Finished | Feb 08 06:16:41 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3547023077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.us bdev_pkt_received.3547023077 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_pkt_sent.769017724 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 248098872 ps |
| CPU time | 1.85 seconds |
| Started | Feb 08 06:16:38 PM UTC 25 |
| Finished | Feb 08 06:16:41 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=769017724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_ pkt_sent.769017724 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_random_length_in_transaction.1318585535 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 160980803 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:16:38 PM UTC 25 |
| Finished | Feb 08 06:16:41 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1318585535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.u sbdev_random_length_in_transaction.1318585535 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_random_length_out_transaction.4104266958 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 190551977 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:16:40 PM UTC 25 |
| Finished | Feb 08 06:16:43 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4104266958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 45.usbdev_random_length_out_transaction.4104266958 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_rx_crc_err.3913043803 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 147190501 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:16:40 PM UTC 25 |
| Finished | Feb 08 06:16:42 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3913043803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbd ev_rx_crc_err.3913043803 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_rx_full.3990918106 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 402108064 ps |
| CPU time | 2.49 seconds |
| Started | Feb 08 06:16:40 PM UTC 25 |
| Finished | Feb 08 06:16:44 PM UTC 25 |
| Peak memory | 217176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3990918106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_ rx_full.3990918106 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_setup_stage.539461744 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 199893029 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:16:40 PM UTC 25 |
| Finished | Feb 08 06:16:43 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=539461744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbd ev_setup_stage.539461744 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_setup_trans_ignored.3203055132 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 174828358 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:16:40 PM UTC 25 |
| Finished | Feb 08 06:16:43 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3203055132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 45.usbdev_setup_trans_ignored.3203055132 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_smoke.2168957859 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 234887146 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:16:40 PM UTC 25 |
| Finished | Feb 08 06:16:43 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2168957859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_sm oke.2168957859 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_spurious_pids_ignored.2867887883 |
| Short name | T3049 |
| Test name | |
| Test status | |
| Simulation time | 2521002655 ps |
| CPU time | 65.74 seconds |
| Started | Feb 08 06:16:40 PM UTC 25 |
| Finished | Feb 08 06:17:48 PM UTC 25 |
| Peak memory | 229772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867887883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 45.usbdev_spurious_pids_ignored.2867887883 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_stall_priority_over_nak.3374579352 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 185926204 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:16:40 PM UTC 25 |
| Finished | Feb 08 06:16:43 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3374579352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 45.usbdev_stall_priority_over_nak.3374579352 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_stall_trans.2570203363 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 178118463 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:16:42 PM UTC 25 |
| Finished | Feb 08 06:16:44 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2570203363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usb dev_stall_trans.2570203363 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_stream_len_max.2884599214 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 798312999 ps |
| CPU time | 2.4 seconds |
| Started | Feb 08 06:16:42 PM UTC 25 |
| Finished | Feb 08 06:16:45 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2884599214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45. usbdev_stream_len_max.2884599214 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_streaming_out.2769678019 |
| Short name | T3073 |
| Test name | |
| Test status | |
| Simulation time | 2722779132 ps |
| CPU time | 72.44 seconds |
| Started | Feb 08 06:16:42 PM UTC 25 |
| Finished | Feb 08 06:17:56 PM UTC 25 |
| Peak memory | 227852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2769678019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbde v_streaming_out.2769678019 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_timeout_missing_host_handshake.526864158 |
| Short name | T2961 |
| Test name | |
| Test status | |
| Simulation time | 1983143362 ps |
| CPU time | 47.28 seconds |
| Started | Feb 08 06:16:25 PM UTC 25 |
| Finished | Feb 08 06:17:14 PM UTC 25 |
| Peak memory | 217412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526864158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing_host_handshake.526864158 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_tx_rx_disruption.1791510058 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 529092532 ps |
| CPU time | 2.55 seconds |
| Started | Feb 08 06:16:42 PM UTC 25 |
| Finished | Feb 08 06:16:46 PM UTC 25 |
| Peak memory | 217116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 791510058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_tx_rx_disruption.1791510058 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/45.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/450.usbdev_tx_rx_disruption.2460153153 |
| Short name | T3620 |
| Test name | |
| Test status | |
| Simulation time | 567784786 ps |
| CPU time | 2.05 seconds |
| Started | Feb 08 06:20:13 PM UTC 25 |
| Finished | Feb 08 06:20:30 PM UTC 25 |
| Peak memory | 217188 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 460153153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 450.usbdev_tx_rx_disruption.2460153153 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/450.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/451.usbdev_tx_rx_disruption.106236553 |
| Short name | T3616 |
| Test name | |
| Test status | |
| Simulation time | 551854606 ps |
| CPU time | 1.78 seconds |
| Started | Feb 08 06:20:13 PM UTC 25 |
| Finished | Feb 08 06:20:30 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 06236553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 451.usbdev_tx_rx_disruption.106236553 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/451.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/452.usbdev_tx_rx_disruption.4137368833 |
| Short name | T3609 |
| Test name | |
| Test status | |
| Simulation time | 519815734 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:20:13 PM UTC 25 |
| Finished | Feb 08 06:20:30 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 137368833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 452.usbdev_tx_rx_disruption.4137368833 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/452.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/453.usbdev_tx_rx_disruption.2818549278 |
| Short name | T3614 |
| Test name | |
| Test status | |
| Simulation time | 507232757 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:20:13 PM UTC 25 |
| Finished | Feb 08 06:20:30 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 818549278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 453.usbdev_tx_rx_disruption.2818549278 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/453.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/454.usbdev_tx_rx_disruption.363186607 |
| Short name | T3612 |
| Test name | |
| Test status | |
| Simulation time | 460908337 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:20:13 PM UTC 25 |
| Finished | Feb 08 06:20:30 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 63186607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 454.usbdev_tx_rx_disruption.363186607 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/454.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/455.usbdev_tx_rx_disruption.2044901092 |
| Short name | T3610 |
| Test name | |
| Test status | |
| Simulation time | 454134520 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:20:13 PM UTC 25 |
| Finished | Feb 08 06:20:30 PM UTC 25 |
| Peak memory | 215088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 044901092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 455.usbdev_tx_rx_disruption.2044901092 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/455.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/456.usbdev_tx_rx_disruption.4129134056 |
| Short name | T3618 |
| Test name | |
| Test status | |
| Simulation time | 668775784 ps |
| CPU time | 1.84 seconds |
| Started | Feb 08 06:20:13 PM UTC 25 |
| Finished | Feb 08 06:20:30 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 129134056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 456.usbdev_tx_rx_disruption.4129134056 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/456.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/457.usbdev_tx_rx_disruption.2068978931 |
| Short name | T3617 |
| Test name | |
| Test status | |
| Simulation time | 564520079 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:20:13 PM UTC 25 |
| Finished | Feb 08 06:20:30 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 068978931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 457.usbdev_tx_rx_disruption.2068978931 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/457.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/458.usbdev_tx_rx_disruption.1221724075 |
| Short name | T3621 |
| Test name | |
| Test status | |
| Simulation time | 651752616 ps |
| CPU time | 2.12 seconds |
| Started | Feb 08 06:20:13 PM UTC 25 |
| Finished | Feb 08 06:20:31 PM UTC 25 |
| Peak memory | 217124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 221724075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 458.usbdev_tx_rx_disruption.1221724075 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/458.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/459.usbdev_tx_rx_disruption.1176861146 |
| Short name | T3615 |
| Test name | |
| Test status | |
| Simulation time | 472076297 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:20:14 PM UTC 25 |
| Finished | Feb 08 06:20:30 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 176861146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 459.usbdev_tx_rx_disruption.1176861146 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/459.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_alert_test.1088202911 |
| Short name | T2931 |
| Test name | |
| Test status | |
| Simulation time | 38021388 ps |
| CPU time | 1.05 seconds |
| Started | Feb 08 06:16:59 PM UTC 25 |
| Finished | Feb 08 06:17:01 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088202911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 46.usbdev_alert_test.1088202911 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_aon_wake_disconnect.2409430216 |
| Short name | T2937 |
| Test name | |
| Test status | |
| Simulation time | 11343705516 ps |
| CPU time | 18.51 seconds |
| Started | Feb 08 06:16:43 PM UTC 25 |
| Finished | Feb 08 06:17:03 PM UTC 25 |
| Peak memory | 217444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409430216 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.2409430216 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_aon_wake_reset.1508253119 |
| Short name | T2956 |
| Test name | |
| Test status | |
| Simulation time | 19566146103 ps |
| CPU time | 28.42 seconds |
| Started | Feb 08 06:16:43 PM UTC 25 |
| Finished | Feb 08 06:17:13 PM UTC 25 |
| Peak memory | 217384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508253119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.1508253119 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_aon_wake_resume.1934988321 |
| Short name | T3000 |
| Test name | |
| Test status | |
| Simulation time | 30059349857 ps |
| CPU time | 43.87 seconds |
| Started | Feb 08 06:16:45 PM UTC 25 |
| Finished | Feb 08 06:17:30 PM UTC 25 |
| Peak memory | 217384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934988321 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.1934988321 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_av_buffer.2131029491 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 158736006 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:16:45 PM UTC 25 |
| Finished | Feb 08 06:16:48 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2131029491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbde v_av_buffer.2131029491 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_bitstuff_err.760728532 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 159080968 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 06:16:45 PM UTC 25 |
| Finished | Feb 08 06:16:47 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=760728532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usb dev_bitstuff_err.760728532 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_data_toggle_clear.378872970 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 566495520 ps |
| CPU time | 1.99 seconds |
| Started | Feb 08 06:16:45 PM UTC 25 |
| Finished | Feb 08 06:16:48 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=378872970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.usbdev_data_toggle_clear.378872970 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_data_toggle_restore.3089315169 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 973689775 ps |
| CPU time | 3.41 seconds |
| Started | Feb 08 06:16:45 PM UTC 25 |
| Finished | Feb 08 06:16:50 PM UTC 25 |
| Peak memory | 217644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089315169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.3089315169 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_device_address.2832462126 |
| Short name | T3096 |
| Test name | |
| Test status | |
| Simulation time | 35873552057 ps |
| CPU time | 74.73 seconds |
| Started | Feb 08 06:16:45 PM UTC 25 |
| Finished | Feb 08 06:18:02 PM UTC 25 |
| Peak memory | 217496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2832462126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46. usbdev_device_address.2832462126 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_device_timeout.3551925667 |
| Short name | T2994 |
| Test name | |
| Test status | |
| Simulation time | 4755870379 ps |
| CPU time | 40.86 seconds |
| Started | Feb 08 06:16:45 PM UTC 25 |
| Finished | Feb 08 06:17:28 PM UTC 25 |
| Peak memory | 217404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551925667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.3551925667 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_disable_endpoint.3349096767 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 776079248 ps |
| CPU time | 2.85 seconds |
| Started | Feb 08 06:16:46 PM UTC 25 |
| Finished | Feb 08 06:16:51 PM UTC 25 |
| Peak memory | 217280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3349096767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.usbdev_disable_endpoint.3349096767 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_disconnected.1260321306 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 137489696 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:16:46 PM UTC 25 |
| Finished | Feb 08 06:16:49 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1260321306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.us bdev_disconnected.1260321306 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_enable.4142862702 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 129811887 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:16:46 PM UTC 25 |
| Finished | Feb 08 06:16:49 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4142862702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_e nable.4142862702 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_endpoint_access.1203777410 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 772659177 ps |
| CPU time | 2.53 seconds |
| Started | Feb 08 06:16:47 PM UTC 25 |
| Finished | Feb 08 06:16:50 PM UTC 25 |
| Peak memory | 217624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1203777410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46 .usbdev_endpoint_access.1203777410 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_fifo_rst.4246777621 |
| Short name | T2910 |
| Test name | |
| Test status | |
| Simulation time | 354046407 ps |
| CPU time | 3.36 seconds |
| Started | Feb 08 06:16:48 PM UTC 25 |
| Finished | Feb 08 06:16:52 PM UTC 25 |
| Peak memory | 217544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4246777621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev _fifo_rst.4246777621 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_in_iso.2339505392 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 233583856 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:16:48 PM UTC 25 |
| Finished | Feb 08 06:16:51 PM UTC 25 |
| Peak memory | 215084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339505392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 46.usbdev_in_iso.2339505392 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_in_stall.648582557 |
| Short name | T2905 |
| Test name | |
| Test status | |
| Simulation time | 150205017 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:16:49 PM UTC 25 |
| Finished | Feb 08 06:16:52 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=648582557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_ in_stall.648582557 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_in_trans.2588857961 |
| Short name | T2909 |
| Test name | |
| Test status | |
| Simulation time | 275111895 ps |
| CPU time | 1.81 seconds |
| Started | Feb 08 06:16:49 PM UTC 25 |
| Finished | Feb 08 06:16:52 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2588857961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev _in_trans.2588857961 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_invalid_sync.2635484888 |
| Short name | T2991 |
| Test name | |
| Test status | |
| Simulation time | 3514992285 ps |
| CPU time | 35.87 seconds |
| Started | Feb 08 06:16:48 PM UTC 25 |
| Finished | Feb 08 06:17:25 PM UTC 25 |
| Peak memory | 227644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635484888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.2635484888 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_iso_retraction.889153288 |
| Short name | T3117 |
| Test name | |
| Test status | |
| Simulation time | 10575061924 ps |
| CPU time | 76.49 seconds |
| Started | Feb 08 06:16:49 PM UTC 25 |
| Finished | Feb 08 06:18:08 PM UTC 25 |
| Peak memory | 217292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889153288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retra ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 46.usbdev_iso_retraction.889153288 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_link_in_err.678000166 |
| Short name | T2906 |
| Test name | |
| Test status | |
| Simulation time | 235630887 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:16:49 PM UTC 25 |
| Finished | Feb 08 06:16:52 PM UTC 25 |
| Peak memory | 215020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=678000166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbd ev_link_in_err.678000166 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_link_resume.966085140 |
| Short name | T3019 |
| Test name | |
| Test status | |
| Simulation time | 24141607229 ps |
| CPU time | 45.37 seconds |
| Started | Feb 08 06:16:51 PM UTC 25 |
| Finished | Feb 08 06:17:38 PM UTC 25 |
| Peak memory | 217416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=966085140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbd ev_link_resume.966085140 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_link_suspend.998109308 |
| Short name | T2941 |
| Test name | |
| Test status | |
| Simulation time | 5493154932 ps |
| CPU time | 13.03 seconds |
| Started | Feb 08 06:16:51 PM UTC 25 |
| Finished | Feb 08 06:17:05 PM UTC 25 |
| Peak memory | 227792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=998109308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usb dev_link_suspend.998109308 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_low_speed_traffic.3349205487 |
| Short name | T3151 |
| Test name | |
| Test status | |
| Simulation time | 3177151420 ps |
| CPU time | 84.69 seconds |
| Started | Feb 08 06:16:51 PM UTC 25 |
| Finished | Feb 08 06:18:17 PM UTC 25 |
| Peak memory | 229644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349205487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 46.usbdev_low_speed_traffic.3349205487 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_max_inter_pkt_delay.3647985381 |
| Short name | T3040 |
| Test name | |
| Test status | |
| Simulation time | 2018703266 ps |
| CPU time | 51.18 seconds |
| Started | Feb 08 06:16:51 PM UTC 25 |
| Finished | Feb 08 06:17:44 PM UTC 25 |
| Peak memory | 227592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647985381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.3647985381 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_max_length_in_transaction.1540177556 |
| Short name | T2911 |
| Test name | |
| Test status | |
| Simulation time | 241438680 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:16:51 PM UTC 25 |
| Finished | Feb 08 06:16:54 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540177556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 46.usbdev_max_length_in_transaction.1540177556 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_max_length_out_transaction.1779307 |
| Short name | T2916 |
| Test name | |
| Test status | |
| Simulation time | 187264303 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:16:54 PM UTC 25 |
| Finished | Feb 08 06:16:56 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1779307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 46.usbdev_max_length_out_transaction.1779307 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_min_inter_pkt_delay.1186846915 |
| Short name | T3142 |
| Test name | |
| Test status | |
| Simulation time | 2845740732 ps |
| CPU time | 80.92 seconds |
| Started | Feb 08 06:16:54 PM UTC 25 |
| Finished | Feb 08 06:18:16 PM UTC 25 |
| Peak memory | 227856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186846915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.1186846915 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_min_length_in_transaction.2478682902 |
| Short name | T2915 |
| Test name | |
| Test status | |
| Simulation time | 166547366 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:16:54 PM UTC 25 |
| Finished | Feb 08 06:16:56 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478682902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 46.usbdev_min_length_in_transaction.2478682902 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_min_length_out_transaction.3595389909 |
| Short name | T2912 |
| Test name | |
| Test status | |
| Simulation time | 145959137 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 06:16:54 PM UTC 25 |
| Finished | Feb 08 06:16:56 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3595389909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3595389909 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_nak_trans.4272820440 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 218005048 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:16:54 PM UTC 25 |
| Finished | Feb 08 06:16:56 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4272820440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbde v_nak_trans.4272820440 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_out_iso.1340543360 |
| Short name | T2919 |
| Test name | |
| Test status | |
| Simulation time | 158482080 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:16:54 PM UTC 25 |
| Finished | Feb 08 06:16:56 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1340543360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_ out_iso.1340543360 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_out_stall.2580980747 |
| Short name | T2913 |
| Test name | |
| Test status | |
| Simulation time | 178495657 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:16:54 PM UTC 25 |
| Finished | Feb 08 06:16:56 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2580980747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbde v_out_stall.2580980747 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_out_trans_nak.3569150567 |
| Short name | T2918 |
| Test name | |
| Test status | |
| Simulation time | 188574334 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 06:16:54 PM UTC 25 |
| Finished | Feb 08 06:16:56 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3569150567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.u sbdev_out_trans_nak.3569150567 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_pending_in_trans.3605039185 |
| Short name | T2920 |
| Test name | |
| Test status | |
| Simulation time | 146964598 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:16:54 PM UTC 25 |
| Finished | Feb 08 06:16:56 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3605039185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.usbdev_pending_in_trans.3605039185 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_phy_config_pinflip.2934192693 |
| Short name | T2923 |
| Test name | |
| Test status | |
| Simulation time | 231628368 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:16:54 PM UTC 25 |
| Finished | Feb 08 06:16:57 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934192693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 46.usbdev_phy_config_pinflip.2934192693 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_phy_config_usb_ref_disable.46616607 |
| Short name | T2921 |
| Test name | |
| Test status | |
| Simulation time | 169741597 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:16:54 PM UTC 25 |
| Finished | Feb 08 06:16:57 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=46616607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 46.usbdev_phy_config_usb_ref_disable.46616607 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_phy_pins_sense.2063310054 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 82483976 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:16:54 PM UTC 25 |
| Finished | Feb 08 06:16:56 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2063310054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46. usbdev_phy_pins_sense.2063310054 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_pkt_buffer.1065759319 |
| Short name | T3043 |
| Test name | |
| Test status | |
| Simulation time | 18145284452 ps |
| CPU time | 49.94 seconds |
| Started | Feb 08 06:16:54 PM UTC 25 |
| Finished | Feb 08 06:17:46 PM UTC 25 |
| Peak memory | 234496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1065759319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbd ev_pkt_buffer.1065759319 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_pkt_received.567276292 |
| Short name | T2922 |
| Test name | |
| Test status | |
| Simulation time | 186400405 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:16:54 PM UTC 25 |
| Finished | Feb 08 06:16:57 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=567276292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usb dev_pkt_received.567276292 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_pkt_sent.2163134538 |
| Short name | T2917 |
| Test name | |
| Test status | |
| Simulation time | 198184039 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 06:16:54 PM UTC 25 |
| Finished | Feb 08 06:16:56 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2163134538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev _pkt_sent.2163134538 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_random_length_in_transaction.4263288416 |
| Short name | T2925 |
| Test name | |
| Test status | |
| Simulation time | 218167296 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:16:55 PM UTC 25 |
| Finished | Feb 08 06:16:58 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4263288416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.u sbdev_random_length_in_transaction.4263288416 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_random_length_out_transaction.3967474505 |
| Short name | T2929 |
| Test name | |
| Test status | |
| Simulation time | 166251958 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:16:58 PM UTC 25 |
| Finished | Feb 08 06:17:01 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3967474505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 46.usbdev_random_length_out_transaction.3967474505 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_rx_crc_err.3791237024 |
| Short name | T2928 |
| Test name | |
| Test status | |
| Simulation time | 157282107 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:16:58 PM UTC 25 |
| Finished | Feb 08 06:17:01 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3791237024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbd ev_rx_crc_err.3791237024 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_rx_full.3437037799 |
| Short name | T2935 |
| Test name | |
| Test status | |
| Simulation time | 373627402 ps |
| CPU time | 2.41 seconds |
| Started | Feb 08 06:16:58 PM UTC 25 |
| Finished | Feb 08 06:17:02 PM UTC 25 |
| Peak memory | 217176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3437037799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_ rx_full.3437037799 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_setup_stage.3048095693 |
| Short name | T2930 |
| Test name | |
| Test status | |
| Simulation time | 170457555 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:16:58 PM UTC 25 |
| Finished | Feb 08 06:17:01 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3048095693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usb dev_setup_stage.3048095693 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_setup_trans_ignored.1989071173 |
| Short name | T2926 |
| Test name | |
| Test status | |
| Simulation time | 152928027 ps |
| CPU time | 1.21 seconds |
| Started | Feb 08 06:16:58 PM UTC 25 |
| Finished | Feb 08 06:17:01 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1989071173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 46.usbdev_setup_trans_ignored.1989071173 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_smoke.2629351335 |
| Short name | T2934 |
| Test name | |
| Test status | |
| Simulation time | 231878737 ps |
| CPU time | 1.85 seconds |
| Started | Feb 08 06:16:58 PM UTC 25 |
| Finished | Feb 08 06:17:01 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2629351335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_sm oke.2629351335 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_spurious_pids_ignored.3919391092 |
| Short name | T3133 |
| Test name | |
| Test status | |
| Simulation time | 2482394787 ps |
| CPU time | 72.37 seconds |
| Started | Feb 08 06:16:58 PM UTC 25 |
| Finished | Feb 08 06:18:13 PM UTC 25 |
| Peak memory | 229768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919391092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 46.usbdev_spurious_pids_ignored.3919391092 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_stall_priority_over_nak.468900057 |
| Short name | T2932 |
| Test name | |
| Test status | |
| Simulation time | 149085924 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:16:58 PM UTC 25 |
| Finished | Feb 08 06:17:01 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=468900057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 46.usbdev_stall_priority_over_nak.468900057 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_stall_trans.2839037039 |
| Short name | T2933 |
| Test name | |
| Test status | |
| Simulation time | 188056752 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:16:58 PM UTC 25 |
| Finished | Feb 08 06:17:01 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2839037039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usb dev_stall_trans.2839037039 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_stream_len_max.1413515944 |
| Short name | T2936 |
| Test name | |
| Test status | |
| Simulation time | 871413193 ps |
| CPU time | 2.78 seconds |
| Started | Feb 08 06:16:59 PM UTC 25 |
| Finished | Feb 08 06:17:03 PM UTC 25 |
| Peak memory | 217424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1413515944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46. usbdev_stream_len_max.1413515944 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_streaming_out.3034413953 |
| Short name | T3147 |
| Test name | |
| Test status | |
| Simulation time | 2594084357 ps |
| CPU time | 76.72 seconds |
| Started | Feb 08 06:16:58 PM UTC 25 |
| Finished | Feb 08 06:18:17 PM UTC 25 |
| Peak memory | 229900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3034413953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbde v_streaming_out.3034413953 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_timeout_missing_host_handshake.1377953283 |
| Short name | T2954 |
| Test name | |
| Test status | |
| Simulation time | 2940189180 ps |
| CPU time | 25.8 seconds |
| Started | Feb 08 06:16:45 PM UTC 25 |
| Finished | Feb 08 06:17:12 PM UTC 25 |
| Peak memory | 217476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377953283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing_host_handshake.1377953283 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_tx_rx_disruption.2587062784 |
| Short name | T2938 |
| Test name | |
| Test status | |
| Simulation time | 648026066 ps |
| CPU time | 3.31 seconds |
| Started | Feb 08 06:16:59 PM UTC 25 |
| Finished | Feb 08 06:17:03 PM UTC 25 |
| Peak memory | 217180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 587062784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_tx_rx_disruption.2587062784 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/46.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/460.usbdev_tx_rx_disruption.3561822535 |
| Short name | T3619 |
| Test name | |
| Test status | |
| Simulation time | 585770396 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:20:14 PM UTC 25 |
| Finished | Feb 08 06:20:30 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 561822535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 460.usbdev_tx_rx_disruption.3561822535 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/460.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/461.usbdev_tx_rx_disruption.2631335243 |
| Short name | T3582 |
| Test name | |
| Test status | |
| Simulation time | 447528698 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:20:14 PM UTC 25 |
| Finished | Feb 08 06:20:23 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 631335243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 461.usbdev_tx_rx_disruption.2631335243 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/461.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/462.usbdev_tx_rx_disruption.417908007 |
| Short name | T3583 |
| Test name | |
| Test status | |
| Simulation time | 567821103 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:20:14 PM UTC 25 |
| Finished | Feb 08 06:20:23 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 17908007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 462.usbdev_tx_rx_disruption.417908007 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/462.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/463.usbdev_tx_rx_disruption.1702431368 |
| Short name | T3588 |
| Test name | |
| Test status | |
| Simulation time | 659601499 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 06:20:14 PM UTC 25 |
| Finished | Feb 08 06:20:24 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 702431368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 463.usbdev_tx_rx_disruption.1702431368 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/463.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/464.usbdev_tx_rx_disruption.2454688115 |
| Short name | T3584 |
| Test name | |
| Test status | |
| Simulation time | 520276905 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:20:14 PM UTC 25 |
| Finished | Feb 08 06:20:24 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 454688115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 464.usbdev_tx_rx_disruption.2454688115 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/464.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/465.usbdev_tx_rx_disruption.2320293966 |
| Short name | T3586 |
| Test name | |
| Test status | |
| Simulation time | 635708243 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:20:14 PM UTC 25 |
| Finished | Feb 08 06:20:24 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 320293966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 465.usbdev_tx_rx_disruption.2320293966 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/465.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/466.usbdev_tx_rx_disruption.878873315 |
| Short name | T3587 |
| Test name | |
| Test status | |
| Simulation time | 711278591 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:20:14 PM UTC 25 |
| Finished | Feb 08 06:20:24 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 78873315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 466.usbdev_tx_rx_disruption.878873315 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/466.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/467.usbdev_tx_rx_disruption.4061708287 |
| Short name | T3585 |
| Test name | |
| Test status | |
| Simulation time | 616995169 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:20:14 PM UTC 25 |
| Finished | Feb 08 06:20:24 PM UTC 25 |
| Peak memory | 215088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 061708287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 467.usbdev_tx_rx_disruption.4061708287 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/467.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/468.usbdev_tx_rx_disruption.3355001116 |
| Short name | T3589 |
| Test name | |
| Test status | |
| Simulation time | 638078854 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:20:14 PM UTC 25 |
| Finished | Feb 08 06:20:24 PM UTC 25 |
| Peak memory | 215092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 355001116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 468.usbdev_tx_rx_disruption.3355001116 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/468.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/469.usbdev_tx_rx_disruption.784611835 |
| Short name | T3590 |
| Test name | |
| Test status | |
| Simulation time | 441389368 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:20:14 PM UTC 25 |
| Finished | Feb 08 06:20:24 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 84611835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 469.usbdev_tx_rx_disruption.784611835 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/469.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_alert_test.2548268668 |
| Short name | T2988 |
| Test name | |
| Test status | |
| Simulation time | 53428357 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 06:17:22 PM UTC 25 |
| Finished | Feb 08 06:17:25 PM UTC 25 |
| Peak memory | 215044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548268668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 47.usbdev_alert_test.2548268668 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_aon_wake_disconnect.1725817073 |
| Short name | T2973 |
| Test name | |
| Test status | |
| Simulation time | 4654072146 ps |
| CPU time | 16.55 seconds |
| Started | Feb 08 06:17:00 PM UTC 25 |
| Finished | Feb 08 06:17:18 PM UTC 25 |
| Peak memory | 227652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725817073 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.1725817073 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_aon_wake_reset.1253664540 |
| Short name | T3001 |
| Test name | |
| Test status | |
| Simulation time | 15459298942 ps |
| CPU time | 28.48 seconds |
| Started | Feb 08 06:17:00 PM UTC 25 |
| Finished | Feb 08 06:17:30 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253664540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.1253664540 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_aon_wake_resume.1592571474 |
| Short name | T3059 |
| Test name | |
| Test status | |
| Simulation time | 30907385920 ps |
| CPU time | 47.05 seconds |
| Started | Feb 08 06:17:02 PM UTC 25 |
| Finished | Feb 08 06:17:51 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592571474 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.1592571474 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_av_buffer.3729524347 |
| Short name | T2940 |
| Test name | |
| Test status | |
| Simulation time | 143403130 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:17:02 PM UTC 25 |
| Finished | Feb 08 06:17:05 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3729524347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbde v_av_buffer.3729524347 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_bitstuff_err.3392303107 |
| Short name | T2939 |
| Test name | |
| Test status | |
| Simulation time | 149653465 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:17:02 PM UTC 25 |
| Finished | Feb 08 06:17:04 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3392303107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.us bdev_bitstuff_err.3392303107 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_data_toggle_clear.2921112813 |
| Short name | T2942 |
| Test name | |
| Test status | |
| Simulation time | 397479243 ps |
| CPU time | 2.08 seconds |
| Started | Feb 08 06:17:02 PM UTC 25 |
| Finished | Feb 08 06:17:05 PM UTC 25 |
| Peak memory | 217180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2921112813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.2921112813 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_data_toggle_restore.1876982037 |
| Short name | T2943 |
| Test name | |
| Test status | |
| Simulation time | 476352438 ps |
| CPU time | 2.55 seconds |
| Started | Feb 08 06:17:02 PM UTC 25 |
| Finished | Feb 08 06:17:06 PM UTC 25 |
| Peak memory | 217300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876982037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.1876982037 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_device_address.2151676069 |
| Short name | T3119 |
| Test name | |
| Test status | |
| Simulation time | 30811567689 ps |
| CPU time | 64.7 seconds |
| Started | Feb 08 06:17:02 PM UTC 25 |
| Finished | Feb 08 06:18:09 PM UTC 25 |
| Peak memory | 217416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2151676069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47. usbdev_device_address.2151676069 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_device_timeout.3223693872 |
| Short name | T2987 |
| Test name | |
| Test status | |
| Simulation time | 884453031 ps |
| CPU time | 20.44 seconds |
| Started | Feb 08 06:17:02 PM UTC 25 |
| Finished | Feb 08 06:17:24 PM UTC 25 |
| Peak memory | 217348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223693872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.3223693872 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_disable_endpoint.2094363950 |
| Short name | T2946 |
| Test name | |
| Test status | |
| Simulation time | 586736056 ps |
| CPU time | 2.94 seconds |
| Started | Feb 08 06:17:02 PM UTC 25 |
| Finished | Feb 08 06:17:06 PM UTC 25 |
| Peak memory | 217088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2094363950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.usbdev_disable_endpoint.2094363950 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_disconnected.1178421379 |
| Short name | T2945 |
| Test name | |
| Test status | |
| Simulation time | 205681798 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:17:04 PM UTC 25 |
| Finished | Feb 08 06:17:06 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1178421379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.us bdev_disconnected.1178421379 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_enable.715174112 |
| Short name | T2944 |
| Test name | |
| Test status | |
| Simulation time | 119172294 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:17:04 PM UTC 25 |
| Finished | Feb 08 06:17:06 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=715174112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_en able.715174112 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_endpoint_access.754638071 |
| Short name | T2950 |
| Test name | |
| Test status | |
| Simulation time | 874258673 ps |
| CPU time | 4.24 seconds |
| Started | Feb 08 06:17:04 PM UTC 25 |
| Finished | Feb 08 06:17:09 PM UTC 25 |
| Peak memory | 217384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=754638071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47. usbdev_endpoint_access.754638071 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_endpoint_types.2423306058 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 400590871 ps |
| CPU time | 2.19 seconds |
| Started | Feb 08 06:17:04 PM UTC 25 |
| Finished | Feb 08 06:17:07 PM UTC 25 |
| Peak memory | 217148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423306058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 47.usbdev_endpoint_types.2423306058 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_fifo_rst.1905904219 |
| Short name | T2948 |
| Test name | |
| Test status | |
| Simulation time | 372662318 ps |
| CPU time | 2.91 seconds |
| Started | Feb 08 06:17:05 PM UTC 25 |
| Finished | Feb 08 06:17:09 PM UTC 25 |
| Peak memory | 217288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1905904219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev _fifo_rst.1905904219 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_in_iso.2881464398 |
| Short name | T2951 |
| Test name | |
| Test status | |
| Simulation time | 250018729 ps |
| CPU time | 1.98 seconds |
| Started | Feb 08 06:17:06 PM UTC 25 |
| Finished | Feb 08 06:17:09 PM UTC 25 |
| Peak memory | 227756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881464398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 47.usbdev_in_iso.2881464398 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_in_stall.2850251453 |
| Short name | T2947 |
| Test name | |
| Test status | |
| Simulation time | 141540827 ps |
| CPU time | 1.17 seconds |
| Started | Feb 08 06:17:06 PM UTC 25 |
| Finished | Feb 08 06:17:08 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2850251453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev _in_stall.2850251453 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_in_trans.2836520246 |
| Short name | T2953 |
| Test name | |
| Test status | |
| Simulation time | 212902874 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:17:07 PM UTC 25 |
| Finished | Feb 08 06:17:10 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2836520246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev _in_trans.2836520246 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_invalid_sync.4072922542 |
| Short name | T3047 |
| Test name | |
| Test status | |
| Simulation time | 5040622651 ps |
| CPU time | 39.96 seconds |
| Started | Feb 08 06:17:06 PM UTC 25 |
| Finished | Feb 08 06:17:48 PM UTC 25 |
| Peak memory | 229772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072922542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.4072922542 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_iso_retraction.433932686 |
| Short name | T3126 |
| Test name | |
| Test status | |
| Simulation time | 7834168233 ps |
| CPU time | 61.77 seconds |
| Started | Feb 08 06:17:08 PM UTC 25 |
| Finished | Feb 08 06:18:11 PM UTC 25 |
| Peak memory | 216924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433932686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retra ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 47.usbdev_iso_retraction.433932686 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_link_in_err.1443036214 |
| Short name | T2952 |
| Test name | |
| Test status | |
| Simulation time | 199165502 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:17:08 PM UTC 25 |
| Finished | Feb 08 06:17:10 PM UTC 25 |
| Peak memory | 214732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1443036214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usb dev_link_in_err.1443036214 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_link_resume.3854676686 |
| Short name | T2997 |
| Test name | |
| Test status | |
| Simulation time | 11956269138 ps |
| CPU time | 19.51 seconds |
| Started | Feb 08 06:17:08 PM UTC 25 |
| Finished | Feb 08 06:17:28 PM UTC 25 |
| Peak memory | 217584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3854676686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usb dev_link_resume.3854676686 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_link_suspend.1669266485 |
| Short name | T3007 |
| Test name | |
| Test status | |
| Simulation time | 11083485924 ps |
| CPU time | 23.8 seconds |
| Started | Feb 08 06:17:08 PM UTC 25 |
| Finished | Feb 08 06:17:33 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1669266485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.us bdev_link_suspend.1669266485 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_low_speed_traffic.2033599262 |
| Short name | T3231 |
| Test name | |
| Test status | |
| Simulation time | 2990719355 ps |
| CPU time | 81.98 seconds |
| Started | Feb 08 06:17:09 PM UTC 25 |
| Finished | Feb 08 06:18:33 PM UTC 25 |
| Peak memory | 227660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033599262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 47.usbdev_low_speed_traffic.2033599262 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_max_inter_pkt_delay.764893 |
| Short name | T3118 |
| Test name | |
| Test status | |
| Simulation time | 1923907775 ps |
| CPU time | 56.23 seconds |
| Started | Feb 08 06:17:10 PM UTC 25 |
| Finished | Feb 08 06:18:08 PM UTC 25 |
| Peak memory | 227592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbd ev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.764893 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_max_length_in_transaction.727687041 |
| Short name | T2955 |
| Test name | |
| Test status | |
| Simulation time | 304915121 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:17:10 PM UTC 25 |
| Finished | Feb 08 06:17:12 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727687041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 47.usbdev_max_length_in_transaction.727687041 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_max_length_out_transaction.3674275519 |
| Short name | T2957 |
| Test name | |
| Test status | |
| Simulation time | 232320671 ps |
| CPU time | 1.72 seconds |
| Started | Feb 08 06:17:10 PM UTC 25 |
| Finished | Feb 08 06:17:13 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3674275519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.3674275519 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_min_inter_pkt_delay.940289476 |
| Short name | T3015 |
| Test name | |
| Test status | |
| Simulation time | 2994403260 ps |
| CPU time | 24.98 seconds |
| Started | Feb 08 06:17:10 PM UTC 25 |
| Finished | Feb 08 06:17:37 PM UTC 25 |
| Peak memory | 229700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940289476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usb dev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.940289476 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_min_length_in_transaction.497131437 |
| Short name | T2959 |
| Test name | |
| Test status | |
| Simulation time | 151936716 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:17:11 PM UTC 25 |
| Finished | Feb 08 06:17:14 PM UTC 25 |
| Peak memory | 215156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497131437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 47.usbdev_min_length_in_transaction.497131437 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_min_length_out_transaction.2552432252 |
| Short name | T2960 |
| Test name | |
| Test status | |
| Simulation time | 149019044 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:17:11 PM UTC 25 |
| Finished | Feb 08 06:17:14 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2552432252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.2552432252 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_nak_trans.2343139912 |
| Short name | T2964 |
| Test name | |
| Test status | |
| Simulation time | 186843513 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:17:13 PM UTC 25 |
| Finished | Feb 08 06:17:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2343139912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbde v_nak_trans.2343139912 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_out_iso.1882079278 |
| Short name | T2965 |
| Test name | |
| Test status | |
| Simulation time | 171011316 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:17:13 PM UTC 25 |
| Finished | Feb 08 06:17:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1882079278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_ out_iso.1882079278 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_out_stall.143048417 |
| Short name | T2963 |
| Test name | |
| Test status | |
| Simulation time | 181376594 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:17:13 PM UTC 25 |
| Finished | Feb 08 06:17:15 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=143048417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev _out_stall.143048417 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_out_trans_nak.3249699266 |
| Short name | T2971 |
| Test name | |
| Test status | |
| Simulation time | 214615627 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:17:14 PM UTC 25 |
| Finished | Feb 08 06:17:17 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3249699266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.u sbdev_out_trans_nak.3249699266 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_pending_in_trans.823487935 |
| Short name | T2968 |
| Test name | |
| Test status | |
| Simulation time | 155197408 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:17:14 PM UTC 25 |
| Finished | Feb 08 06:17:17 PM UTC 25 |
| Peak memory | 215084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=823487935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47 .usbdev_pending_in_trans.823487935 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_phy_config_pinflip.1734925915 |
| Short name | T2967 |
| Test name | |
| Test status | |
| Simulation time | 217659727 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:17:14 PM UTC 25 |
| Finished | Feb 08 06:17:17 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734925915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 47.usbdev_phy_config_pinflip.1734925915 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_phy_config_usb_ref_disable.3926670146 |
| Short name | T2972 |
| Test name | |
| Test status | |
| Simulation time | 211648293 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:17:14 PM UTC 25 |
| Finished | Feb 08 06:17:17 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3926670146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.3926670146 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_phy_pins_sense.4279146175 |
| Short name | T2966 |
| Test name | |
| Test status | |
| Simulation time | 38608968 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:17:14 PM UTC 25 |
| Finished | Feb 08 06:17:17 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4279146175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47. usbdev_phy_pins_sense.4279146175 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_pkt_buffer.2554839066 |
| Short name | T3124 |
| Test name | |
| Test status | |
| Simulation time | 21795631426 ps |
| CPU time | 52.61 seconds |
| Started | Feb 08 06:17:16 PM UTC 25 |
| Finished | Feb 08 06:18:10 PM UTC 25 |
| Peak memory | 234600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2554839066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbd ev_pkt_buffer.2554839066 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_pkt_received.173580829 |
| Short name | T2974 |
| Test name | |
| Test status | |
| Simulation time | 202238774 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:17:16 PM UTC 25 |
| Finished | Feb 08 06:17:18 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=173580829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usb dev_pkt_received.173580829 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_pkt_sent.2221942660 |
| Short name | T2975 |
| Test name | |
| Test status | |
| Simulation time | 212086458 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:17:16 PM UTC 25 |
| Finished | Feb 08 06:17:18 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2221942660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev _pkt_sent.2221942660 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_random_length_in_transaction.964322187 |
| Short name | T2977 |
| Test name | |
| Test status | |
| Simulation time | 202412219 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:17:17 PM UTC 25 |
| Finished | Feb 08 06:17:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=964322187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.us bdev_random_length_in_transaction.964322187 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_random_length_out_transaction.1059841119 |
| Short name | T2976 |
| Test name | |
| Test status | |
| Simulation time | 160174680 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:17:17 PM UTC 25 |
| Finished | Feb 08 06:17:19 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1059841119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 47.usbdev_random_length_out_transaction.1059841119 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_rx_crc_err.1308356597 |
| Short name | T2979 |
| Test name | |
| Test status | |
| Simulation time | 188252151 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:17:18 PM UTC 25 |
| Finished | Feb 08 06:17:21 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1308356597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbd ev_rx_crc_err.1308356597 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_rx_full.1934145114 |
| Short name | T2981 |
| Test name | |
| Test status | |
| Simulation time | 359118952 ps |
| CPU time | 1.67 seconds |
| Started | Feb 08 06:17:18 PM UTC 25 |
| Finished | Feb 08 06:17:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1934145114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_ rx_full.1934145114 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_setup_stage.4291241697 |
| Short name | T2978 |
| Test name | |
| Test status | |
| Simulation time | 159406501 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 06:17:18 PM UTC 25 |
| Finished | Feb 08 06:17:21 PM UTC 25 |
| Peak memory | 214964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4291241697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usb dev_setup_stage.4291241697 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_setup_trans_ignored.3680836994 |
| Short name | T2980 |
| Test name | |
| Test status | |
| Simulation time | 184538696 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:17:18 PM UTC 25 |
| Finished | Feb 08 06:17:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3680836994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 47.usbdev_setup_trans_ignored.3680836994 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_smoke.2416270336 |
| Short name | T2983 |
| Test name | |
| Test status | |
| Simulation time | 239296263 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:17:18 PM UTC 25 |
| Finished | Feb 08 06:17:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2416270336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_sm oke.2416270336 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_spurious_pids_ignored.124858576 |
| Short name | T3062 |
| Test name | |
| Test status | |
| Simulation time | 3720825644 ps |
| CPU time | 32.06 seconds |
| Started | Feb 08 06:17:19 PM UTC 25 |
| Finished | Feb 08 06:17:52 PM UTC 25 |
| Peak memory | 227588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124858576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 47.usbdev_spurious_pids_ignored.124858576 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_stall_priority_over_nak.1386271511 |
| Short name | T2982 |
| Test name | |
| Test status | |
| Simulation time | 175895038 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:17:19 PM UTC 25 |
| Finished | Feb 08 06:17:21 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1386271511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 47.usbdev_stall_priority_over_nak.1386271511 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_stall_trans.3254621344 |
| Short name | T2984 |
| Test name | |
| Test status | |
| Simulation time | 160293460 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 06:17:20 PM UTC 25 |
| Finished | Feb 08 06:17:22 PM UTC 25 |
| Peak memory | 215084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3254621344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usb dev_stall_trans.3254621344 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_stream_len_max.743680163 |
| Short name | T2992 |
| Test name | |
| Test status | |
| Simulation time | 899750035 ps |
| CPU time | 4.26 seconds |
| Started | Feb 08 06:17:20 PM UTC 25 |
| Finished | Feb 08 06:17:25 PM UTC 25 |
| Peak memory | 217480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=743680163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.u sbdev_stream_len_max.743680163 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_streaming_out.1145625539 |
| Short name | T3031 |
| Test name | |
| Test status | |
| Simulation time | 2281205128 ps |
| CPU time | 20.82 seconds |
| Started | Feb 08 06:17:20 PM UTC 25 |
| Finished | Feb 08 06:17:42 PM UTC 25 |
| Peak memory | 227664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1145625539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbde v_streaming_out.1145625539 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_timeout_missing_host_handshake.1154035367 |
| Short name | T3057 |
| Test name | |
| Test status | |
| Simulation time | 4810875108 ps |
| CPU time | 46.4 seconds |
| Started | Feb 08 06:17:02 PM UTC 25 |
| Finished | Feb 08 06:17:50 PM UTC 25 |
| Peak memory | 217348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154035367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_host_handshake.1154035367 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_tx_rx_disruption.2776048243 |
| Short name | T2986 |
| Test name | |
| Test status | |
| Simulation time | 577597612 ps |
| CPU time | 2.92 seconds |
| Started | Feb 08 06:17:20 PM UTC 25 |
| Finished | Feb 08 06:17:24 PM UTC 25 |
| Peak memory | 217116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 776048243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_tx_rx_disruption.2776048243 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/47.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/470.usbdev_tx_rx_disruption.1594888006 |
| Short name | T3568 |
| Test name | |
| Test status | |
| Simulation time | 577950473 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:18 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 594888006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 470.usbdev_tx_rx_disruption.1594888006 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/470.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/471.usbdev_tx_rx_disruption.1987411362 |
| Short name | T3571 |
| Test name | |
| Test status | |
| Simulation time | 575890649 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:19 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 987411362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 471.usbdev_tx_rx_disruption.1987411362 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/471.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/472.usbdev_tx_rx_disruption.4265473936 |
| Short name | T3569 |
| Test name | |
| Test status | |
| Simulation time | 450924323 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:19 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 265473936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 472.usbdev_tx_rx_disruption.4265473936 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/472.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/473.usbdev_tx_rx_disruption.2159889255 |
| Short name | T3573 |
| Test name | |
| Test status | |
| Simulation time | 528432404 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:19 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 159889255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 473.usbdev_tx_rx_disruption.2159889255 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/473.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/475.usbdev_tx_rx_disruption.2098914831 |
| Short name | T3570 |
| Test name | |
| Test status | |
| Simulation time | 468075608 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:19 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 098914831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 475.usbdev_tx_rx_disruption.2098914831 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/475.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/476.usbdev_tx_rx_disruption.1989802088 |
| Short name | T3574 |
| Test name | |
| Test status | |
| Simulation time | 527175548 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:19 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 989802088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 476.usbdev_tx_rx_disruption.1989802088 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/476.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/477.usbdev_tx_rx_disruption.4191102003 |
| Short name | T3572 |
| Test name | |
| Test status | |
| Simulation time | 465881986 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:19 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 191102003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 477.usbdev_tx_rx_disruption.4191102003 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/477.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/478.usbdev_tx_rx_disruption.753883775 |
| Short name | T3577 |
| Test name | |
| Test status | |
| Simulation time | 637941409 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:19 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 53883775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 478.usbdev_tx_rx_disruption.753883775 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/478.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/479.usbdev_tx_rx_disruption.2482097908 |
| Short name | T3576 |
| Test name | |
| Test status | |
| Simulation time | 577117175 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:19 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 482097908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 479.usbdev_tx_rx_disruption.2482097908 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/479.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_alert_test.4064955723 |
| Short name | T3044 |
| Test name | |
| Test status | |
| Simulation time | 56427047 ps |
| CPU time | 1.05 seconds |
| Started | Feb 08 06:17:44 PM UTC 25 |
| Finished | Feb 08 06:17:46 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064955723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 48.usbdev_alert_test.4064955723 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_aon_wake_disconnect.481615284 |
| Short name | T3035 |
| Test name | |
| Test status | |
| Simulation time | 11211127868 ps |
| CPU time | 19.34 seconds |
| Started | Feb 08 06:17:22 PM UTC 25 |
| Finished | Feb 08 06:17:43 PM UTC 25 |
| Peak memory | 217220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481615284 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.481615284 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_aon_wake_reset.904016675 |
| Short name | T3068 |
| Test name | |
| Test status | |
| Simulation time | 18778709269 ps |
| CPU time | 30.49 seconds |
| Started | Feb 08 06:17:23 PM UTC 25 |
| Finished | Feb 08 06:17:54 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904016675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TE ST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.904016675 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_aon_wake_resume.2180003631 |
| Short name | T3106 |
| Test name | |
| Test status | |
| Simulation time | 25853785720 ps |
| CPU time | 40.14 seconds |
| Started | Feb 08 06:17:23 PM UTC 25 |
| Finished | Feb 08 06:18:04 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180003631 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.2180003631 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_av_buffer.673053667 |
| Short name | T2990 |
| Test name | |
| Test status | |
| Simulation time | 222963626 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:17:23 PM UTC 25 |
| Finished | Feb 08 06:17:25 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=673053667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev _av_buffer.673053667 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_bitstuff_err.3809869266 |
| Short name | T2989 |
| Test name | |
| Test status | |
| Simulation time | 168766135 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:17:23 PM UTC 25 |
| Finished | Feb 08 06:17:25 PM UTC 25 |
| Peak memory | 214964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3809869266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.us bdev_bitstuff_err.3809869266 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_data_toggle_clear.1168229405 |
| Short name | T2993 |
| Test name | |
| Test status | |
| Simulation time | 293012870 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:17:24 PM UTC 25 |
| Finished | Feb 08 06:17:27 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1168229405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.1168229405 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_data_toggle_restore.785885838 |
| Short name | T3002 |
| Test name | |
| Test status | |
| Simulation time | 1043044251 ps |
| CPU time | 5.02 seconds |
| Started | Feb 08 06:17:24 PM UTC 25 |
| Finished | Feb 08 06:17:30 PM UTC 25 |
| Peak memory | 217300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785885838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_t oggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.785885838 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_device_address.4016999795 |
| Short name | T3329 |
| Test name | |
| Test status | |
| Simulation time | 51002350741 ps |
| CPU time | 97.46 seconds |
| Started | Feb 08 06:17:24 PM UTC 25 |
| Finished | Feb 08 06:19:04 PM UTC 25 |
| Peak memory | 217640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4016999795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48. usbdev_device_address.4016999795 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_device_timeout.3111645680 |
| Short name | T3088 |
| Test name | |
| Test status | |
| Simulation time | 4375131912 ps |
| CPU time | 33.49 seconds |
| Started | Feb 08 06:17:26 PM UTC 25 |
| Finished | Feb 08 06:18:01 PM UTC 25 |
| Peak memory | 217476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111645680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.3111645680 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_disable_endpoint.2879895438 |
| Short name | T2998 |
| Test name | |
| Test status | |
| Simulation time | 851694332 ps |
| CPU time | 2.8 seconds |
| Started | Feb 08 06:17:26 PM UTC 25 |
| Finished | Feb 08 06:17:30 PM UTC 25 |
| Peak memory | 217088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2879895438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.usbdev_disable_endpoint.2879895438 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_disconnected.3232750907 |
| Short name | T2995 |
| Test name | |
| Test status | |
| Simulation time | 153017437 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 06:17:26 PM UTC 25 |
| Finished | Feb 08 06:17:28 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3232750907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.us bdev_disconnected.3232750907 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_enable.126812758 |
| Short name | T2996 |
| Test name | |
| Test status | |
| Simulation time | 36034627 ps |
| CPU time | 1.05 seconds |
| Started | Feb 08 06:17:26 PM UTC 25 |
| Finished | Feb 08 06:17:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=126812758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_en able.126812758 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_endpoint_access.3352860178 |
| Short name | T3003 |
| Test name | |
| Test status | |
| Simulation time | 815215231 ps |
| CPU time | 2.92 seconds |
| Started | Feb 08 06:17:27 PM UTC 25 |
| Finished | Feb 08 06:17:31 PM UTC 25 |
| Peak memory | 217324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3352860178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48 .usbdev_endpoint_access.3352860178 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_fifo_rst.1659488384 |
| Short name | T3009 |
| Test name | |
| Test status | |
| Simulation time | 306494960 ps |
| CPU time | 3.36 seconds |
| Started | Feb 08 06:17:28 PM UTC 25 |
| Finished | Feb 08 06:17:33 PM UTC 25 |
| Peak memory | 217508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1659488384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev _fifo_rst.1659488384 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_in_iso.245649894 |
| Short name | T3008 |
| Test name | |
| Test status | |
| Simulation time | 209717154 ps |
| CPU time | 1.93 seconds |
| Started | Feb 08 06:17:30 PM UTC 25 |
| Finished | Feb 08 06:17:33 PM UTC 25 |
| Peak memory | 227816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245649894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 48.usbdev_in_iso.245649894 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_in_stall.2757818504 |
| Short name | T3004 |
| Test name | |
| Test status | |
| Simulation time | 157763218 ps |
| CPU time | 0.98 seconds |
| Started | Feb 08 06:17:30 PM UTC 25 |
| Finished | Feb 08 06:17:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2757818504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev _in_stall.2757818504 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_in_trans.3808367222 |
| Short name | T3006 |
| Test name | |
| Test status | |
| Simulation time | 173291831 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:17:30 PM UTC 25 |
| Finished | Feb 08 06:17:32 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3808367222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev _in_trans.3808367222 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_invalid_sync.1039083969 |
| Short name | T3056 |
| Test name | |
| Test status | |
| Simulation time | 2525196009 ps |
| CPU time | 20.51 seconds |
| Started | Feb 08 06:17:28 PM UTC 25 |
| Finished | Feb 08 06:17:50 PM UTC 25 |
| Peak memory | 234376 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039083969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.1039083969 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_iso_retraction.2700326603 |
| Short name | T3315 |
| Test name | |
| Test status | |
| Simulation time | 11653233688 ps |
| CPU time | 82.17 seconds |
| Started | Feb 08 06:17:30 PM UTC 25 |
| Finished | Feb 08 06:18:54 PM UTC 25 |
| Peak memory | 217548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700326603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 48.usbdev_iso_retraction.2700326603 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_link_in_err.2936233957 |
| Short name | T3010 |
| Test name | |
| Test status | |
| Simulation time | 214782510 ps |
| CPU time | 1.82 seconds |
| Started | Feb 08 06:17:31 PM UTC 25 |
| Finished | Feb 08 06:17:34 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2936233957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usb dev_link_in_err.2936233957 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_link_resume.3706618870 |
| Short name | T3053 |
| Test name | |
| Test status | |
| Simulation time | 7368988548 ps |
| CPU time | 15.94 seconds |
| Started | Feb 08 06:17:31 PM UTC 25 |
| Finished | Feb 08 06:17:49 PM UTC 25 |
| Peak memory | 217048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3706618870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usb dev_link_resume.3706618870 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_link_suspend.774997122 |
| Short name | T3048 |
| Test name | |
| Test status | |
| Simulation time | 8462889251 ps |
| CPU time | 14.97 seconds |
| Started | Feb 08 06:17:31 PM UTC 25 |
| Finished | Feb 08 06:17:48 PM UTC 25 |
| Peak memory | 217180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=774997122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usb dev_link_suspend.774997122 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_low_speed_traffic.3610880837 |
| Short name | T3087 |
| Test name | |
| Test status | |
| Simulation time | 3051188082 ps |
| CPU time | 27.78 seconds |
| Started | Feb 08 06:17:31 PM UTC 25 |
| Finished | Feb 08 06:18:01 PM UTC 25 |
| Peak memory | 234500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610880837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 48.usbdev_low_speed_traffic.3610880837 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_max_inter_pkt_delay.728381724 |
| Short name | T3291 |
| Test name | |
| Test status | |
| Simulation time | 2911661059 ps |
| CPU time | 74.57 seconds |
| Started | Feb 08 06:17:31 PM UTC 25 |
| Finished | Feb 08 06:18:48 PM UTC 25 |
| Peak memory | 229756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728381724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.728381724 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_max_length_in_transaction.2084369158 |
| Short name | T3011 |
| Test name | |
| Test status | |
| Simulation time | 239369502 ps |
| CPU time | 1.74 seconds |
| Started | Feb 08 06:17:31 PM UTC 25 |
| Finished | Feb 08 06:17:34 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084369158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 48.usbdev_max_length_in_transaction.2084369158 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_max_length_out_transaction.1501744192 |
| Short name | T3013 |
| Test name | |
| Test status | |
| Simulation time | 208445034 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:17:33 PM UTC 25 |
| Finished | Feb 08 06:17:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1501744192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.1501744192 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_min_inter_pkt_delay.3379897988 |
| Short name | T3234 |
| Test name | |
| Test status | |
| Simulation time | 2145070059 ps |
| CPU time | 58.17 seconds |
| Started | Feb 08 06:17:33 PM UTC 25 |
| Finished | Feb 08 06:18:33 PM UTC 25 |
| Peak memory | 229648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379897988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.3379897988 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_min_length_in_transaction.2118919006 |
| Short name | T3012 |
| Test name | |
| Test status | |
| Simulation time | 164806962 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 06:17:33 PM UTC 25 |
| Finished | Feb 08 06:17:35 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118919006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 48.usbdev_min_length_in_transaction.2118919006 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_min_length_out_transaction.1174441806 |
| Short name | T3014 |
| Test name | |
| Test status | |
| Simulation time | 157744822 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:17:33 PM UTC 25 |
| Finished | Feb 08 06:17:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1174441806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1174441806 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_nak_trans.301803311 |
| Short name | T3017 |
| Test name | |
| Test status | |
| Simulation time | 232442259 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:17:34 PM UTC 25 |
| Finished | Feb 08 06:17:37 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=301803311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev _nak_trans.301803311 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_out_iso.745632840 |
| Short name | T3018 |
| Test name | |
| Test status | |
| Simulation time | 188493583 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:17:34 PM UTC 25 |
| Finished | Feb 08 06:17:37 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=745632840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_o ut_iso.745632840 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_out_stall.289063939 |
| Short name | T3016 |
| Test name | |
| Test status | |
| Simulation time | 218447121 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:17:34 PM UTC 25 |
| Finished | Feb 08 06:17:37 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=289063939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev _out_stall.289063939 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_out_trans_nak.1492259533 |
| Short name | T3022 |
| Test name | |
| Test status | |
| Simulation time | 171156276 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:17:36 PM UTC 25 |
| Finished | Feb 08 06:17:38 PM UTC 25 |
| Peak memory | 214928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1492259533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.u sbdev_out_trans_nak.1492259533 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_pending_in_trans.3744448175 |
| Short name | T3021 |
| Test name | |
| Test status | |
| Simulation time | 146262854 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:17:36 PM UTC 25 |
| Finished | Feb 08 06:17:38 PM UTC 25 |
| Peak memory | 214884 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3744448175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.usbdev_pending_in_trans.3744448175 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_phy_config_pinflip.2654772908 |
| Short name | T3023 |
| Test name | |
| Test status | |
| Simulation time | 215521086 ps |
| CPU time | 1.67 seconds |
| Started | Feb 08 06:17:36 PM UTC 25 |
| Finished | Feb 08 06:17:39 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654772908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 48.usbdev_phy_config_pinflip.2654772908 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_phy_config_usb_ref_disable.1861251029 |
| Short name | T3026 |
| Test name | |
| Test status | |
| Simulation time | 139165289 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:17:37 PM UTC 25 |
| Finished | Feb 08 06:17:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1861251029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.1861251029 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_phy_pins_sense.439445487 |
| Short name | T3025 |
| Test name | |
| Test status | |
| Simulation time | 40868190 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:17:37 PM UTC 25 |
| Finished | Feb 08 06:17:39 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=439445487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.u sbdev_phy_pins_sense.439445487 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_pkt_buffer.3873082418 |
| Short name | T3094 |
| Test name | |
| Test status | |
| Simulation time | 7389560039 ps |
| CPU time | 22.05 seconds |
| Started | Feb 08 06:17:38 PM UTC 25 |
| Finished | Feb 08 06:18:02 PM UTC 25 |
| Peak memory | 227756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3873082418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbd ev_pkt_buffer.3873082418 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_pkt_received.3049545395 |
| Short name | T3028 |
| Test name | |
| Test status | |
| Simulation time | 211974342 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:17:38 PM UTC 25 |
| Finished | Feb 08 06:17:41 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3049545395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.us bdev_pkt_received.3049545395 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_pkt_sent.757237980 |
| Short name | T3029 |
| Test name | |
| Test status | |
| Simulation time | 182078245 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:17:38 PM UTC 25 |
| Finished | Feb 08 06:17:41 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=757237980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_ pkt_sent.757237980 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_random_length_in_transaction.3899268609 |
| Short name | T3030 |
| Test name | |
| Test status | |
| Simulation time | 177708233 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:17:38 PM UTC 25 |
| Finished | Feb 08 06:17:41 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3899268609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.u sbdev_random_length_in_transaction.3899268609 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_random_length_out_transaction.3827569248 |
| Short name | T3036 |
| Test name | |
| Test status | |
| Simulation time | 191089306 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:17:40 PM UTC 25 |
| Finished | Feb 08 06:17:43 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3827569248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 48.usbdev_random_length_out_transaction.3827569248 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_rx_crc_err.819759977 |
| Short name | T3032 |
| Test name | |
| Test status | |
| Simulation time | 239699869 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:17:40 PM UTC 25 |
| Finished | Feb 08 06:17:43 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=819759977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbde v_rx_crc_err.819759977 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_rx_full.3943788753 |
| Short name | T3039 |
| Test name | |
| Test status | |
| Simulation time | 245603503 ps |
| CPU time | 1.85 seconds |
| Started | Feb 08 06:17:40 PM UTC 25 |
| Finished | Feb 08 06:17:44 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3943788753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_ rx_full.3943788753 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_setup_stage.3548864376 |
| Short name | T3033 |
| Test name | |
| Test status | |
| Simulation time | 154104563 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:17:41 PM UTC 25 |
| Finished | Feb 08 06:17:43 PM UTC 25 |
| Peak memory | 214128 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3548864376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usb dev_setup_stage.3548864376 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_setup_trans_ignored.1771562576 |
| Short name | T3034 |
| Test name | |
| Test status | |
| Simulation time | 146860098 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:17:41 PM UTC 25 |
| Finished | Feb 08 06:17:43 PM UTC 25 |
| Peak memory | 216096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1771562576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 48.usbdev_setup_trans_ignored.1771562576 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_smoke.3569914585 |
| Short name | T3037 |
| Test name | |
| Test status | |
| Simulation time | 211845155 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:17:41 PM UTC 25 |
| Finished | Feb 08 06:17:43 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3569914585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_sm oke.3569914585 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_spurious_pids_ignored.4065324985 |
| Short name | T3134 |
| Test name | |
| Test status | |
| Simulation time | 3872241357 ps |
| CPU time | 31.08 seconds |
| Started | Feb 08 06:17:41 PM UTC 25 |
| Finished | Feb 08 06:18:13 PM UTC 25 |
| Peak memory | 227372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065324985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 48.usbdev_spurious_pids_ignored.4065324985 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_stall_priority_over_nak.546643731 |
| Short name | T3038 |
| Test name | |
| Test status | |
| Simulation time | 230495429 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:17:41 PM UTC 25 |
| Finished | Feb 08 06:17:43 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=546643731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 48.usbdev_stall_priority_over_nak.546643731 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_stall_trans.405099317 |
| Short name | T3041 |
| Test name | |
| Test status | |
| Simulation time | 180739410 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:17:42 PM UTC 25 |
| Finished | Feb 08 06:17:45 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=405099317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbd ev_stall_trans.405099317 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_stream_len_max.4128755520 |
| Short name | T3045 |
| Test name | |
| Test status | |
| Simulation time | 805005155 ps |
| CPU time | 2.82 seconds |
| Started | Feb 08 06:17:42 PM UTC 25 |
| Finished | Feb 08 06:17:46 PM UTC 25 |
| Peak memory | 217080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4128755520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48. usbdev_stream_len_max.4128755520 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_streaming_out.2674103687 |
| Short name | T3313 |
| Test name | |
| Test status | |
| Simulation time | 2643901146 ps |
| CPU time | 69.9 seconds |
| Started | Feb 08 06:17:42 PM UTC 25 |
| Finished | Feb 08 06:18:54 PM UTC 25 |
| Peak memory | 227700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2674103687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbde v_streaming_out.2674103687 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_timeout_missing_host_handshake.1643186200 |
| Short name | T3103 |
| Test name | |
| Test status | |
| Simulation time | 4371380888 ps |
| CPU time | 36.15 seconds |
| Started | Feb 08 06:17:26 PM UTC 25 |
| Finished | Feb 08 06:18:03 PM UTC 25 |
| Peak memory | 217412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643186200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_host_handshake.1643186200 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_tx_rx_disruption.3630563642 |
| Short name | T3046 |
| Test name | |
| Test status | |
| Simulation time | 498553664 ps |
| CPU time | 2.79 seconds |
| Started | Feb 08 06:17:42 PM UTC 25 |
| Finished | Feb 08 06:17:46 PM UTC 25 |
| Peak memory | 217308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 630563642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_tx_rx_disruption.3630563642 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/48.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/480.usbdev_tx_rx_disruption.1433634275 |
| Short name | T3575 |
| Test name | |
| Test status | |
| Simulation time | 448814098 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:19 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 433634275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 480.usbdev_tx_rx_disruption.1433634275 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/480.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/481.usbdev_tx_rx_disruption.3558677516 |
| Short name | T3579 |
| Test name | |
| Test status | |
| Simulation time | 505356897 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:19 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 558677516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 481.usbdev_tx_rx_disruption.3558677516 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/481.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/482.usbdev_tx_rx_disruption.519068642 |
| Short name | T3580 |
| Test name | |
| Test status | |
| Simulation time | 560218480 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:19 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 19068642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 482.usbdev_tx_rx_disruption.519068642 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/482.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/483.usbdev_tx_rx_disruption.3792741372 |
| Short name | T3581 |
| Test name | |
| Test status | |
| Simulation time | 535936133 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:19 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 792741372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 483.usbdev_tx_rx_disruption.3792741372 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/483.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/484.usbdev_tx_rx_disruption.4110114862 |
| Short name | T3595 |
| Test name | |
| Test status | |
| Simulation time | 487861478 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:26 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 110114862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 484.usbdev_tx_rx_disruption.4110114862 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/484.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/485.usbdev_tx_rx_disruption.896911453 |
| Short name | T3578 |
| Test name | |
| Test status | |
| Simulation time | 506196005 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:19 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 96911453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 485.usbdev_tx_rx_disruption.896911453 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/485.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/486.usbdev_tx_rx_disruption.79725688 |
| Short name | T3602 |
| Test name | |
| Test status | |
| Simulation time | 610799480 ps |
| CPU time | 1.67 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:26 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 9725688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 486.usbdev_tx_rx_disruption.79725688 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/486.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/487.usbdev_tx_rx_disruption.2950696928 |
| Short name | T3596 |
| Test name | |
| Test status | |
| Simulation time | 561718444 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:26 PM UTC 25 |
| Peak memory | 215012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 950696928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 487.usbdev_tx_rx_disruption.2950696928 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/487.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/488.usbdev_tx_rx_disruption.879372813 |
| Short name | T3597 |
| Test name | |
| Test status | |
| Simulation time | 578110850 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:26 PM UTC 25 |
| Peak memory | 215044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 79372813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 488.usbdev_tx_rx_disruption.879372813 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/488.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/489.usbdev_tx_rx_disruption.1879921369 |
| Short name | T3601 |
| Test name | |
| Test status | |
| Simulation time | 569639175 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:26 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 879921369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 489.usbdev_tx_rx_disruption.1879921369 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/489.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_alert_test.2179595624 |
| Short name | T3102 |
| Test name | |
| Test status | |
| Simulation time | 69967021 ps |
| CPU time | 0.91 seconds |
| Started | Feb 08 06:18:00 PM UTC 25 |
| Finished | Feb 08 06:18:02 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179595624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 49.usbdev_alert_test.2179595624 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_aon_wake_disconnect.776105213 |
| Short name | T3069 |
| Test name | |
| Test status | |
| Simulation time | 3818928540 ps |
| CPU time | 9.74 seconds |
| Started | Feb 08 06:17:44 PM UTC 25 |
| Finished | Feb 08 06:17:55 PM UTC 25 |
| Peak memory | 227844 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776105213 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.776105213 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_aon_wake_reset.2682569813 |
| Short name | T3101 |
| Test name | |
| Test status | |
| Simulation time | 14172669115 ps |
| CPU time | 17.39 seconds |
| Started | Feb 08 06:17:44 PM UTC 25 |
| Finished | Feb 08 06:18:02 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682569813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.2682569813 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_aon_wake_resume.625138114 |
| Short name | T3216 |
| Test name | |
| Test status | |
| Simulation time | 26266270778 ps |
| CPU time | 43.27 seconds |
| Started | Feb 08 06:17:45 PM UTC 25 |
| Finished | Feb 08 06:18:30 PM UTC 25 |
| Peak memory | 227584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625138114 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.625138114 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_av_buffer.2488047330 |
| Short name | T3052 |
| Test name | |
| Test status | |
| Simulation time | 183112699 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:17:45 PM UTC 25 |
| Finished | Feb 08 06:17:48 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2488047330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbde v_av_buffer.2488047330 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_bitstuff_err.1080879462 |
| Short name | T3051 |
| Test name | |
| Test status | |
| Simulation time | 180967319 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:17:45 PM UTC 25 |
| Finished | Feb 08 06:17:48 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1080879462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.us bdev_bitstuff_err.1080879462 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_data_toggle_clear.3522490063 |
| Short name | T3050 |
| Test name | |
| Test status | |
| Simulation time | 141873568 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:17:45 PM UTC 25 |
| Finished | Feb 08 06:17:48 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3522490063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.3522490063 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_data_toggle_restore.915611871 |
| Short name | T3058 |
| Test name | |
| Test status | |
| Simulation time | 1158324044 ps |
| CPU time | 3.92 seconds |
| Started | Feb 08 06:17:45 PM UTC 25 |
| Finished | Feb 08 06:17:51 PM UTC 25 |
| Peak memory | 217388 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915611871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_t oggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.915611871 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_device_address.3800494690 |
| Short name | T3257 |
| Test name | |
| Test status | |
| Simulation time | 22358077178 ps |
| CPU time | 48.04 seconds |
| Started | Feb 08 06:17:46 PM UTC 25 |
| Finished | Feb 08 06:18:35 PM UTC 25 |
| Peak memory | 217604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3800494690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49. usbdev_device_address.3800494690 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_device_timeout.3970314671 |
| Short name | T3232 |
| Test name | |
| Test status | |
| Simulation time | 1952353320 ps |
| CPU time | 45.52 seconds |
| Started | Feb 08 06:17:46 PM UTC 25 |
| Finished | Feb 08 06:18:33 PM UTC 25 |
| Peak memory | 217392 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970314671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.3970314671 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_disable_endpoint.1870704939 |
| Short name | T3060 |
| Test name | |
| Test status | |
| Simulation time | 797219403 ps |
| CPU time | 2.73 seconds |
| Started | Feb 08 06:17:47 PM UTC 25 |
| Finished | Feb 08 06:17:51 PM UTC 25 |
| Peak memory | 217076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1870704939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.usbdev_disable_endpoint.1870704939 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_disconnected.1658963543 |
| Short name | T3055 |
| Test name | |
| Test status | |
| Simulation time | 141142887 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:17:48 PM UTC 25 |
| Finished | Feb 08 06:17:50 PM UTC 25 |
| Peak memory | 215120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1658963543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.us bdev_disconnected.1658963543 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_enable.2628056598 |
| Short name | T3054 |
| Test name | |
| Test status | |
| Simulation time | 43923199 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 06:17:48 PM UTC 25 |
| Finished | Feb 08 06:17:50 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2628056598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_e nable.2628056598 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_endpoint_access.3602185832 |
| Short name | T3065 |
| Test name | |
| Test status | |
| Simulation time | 843524741 ps |
| CPU time | 3.39 seconds |
| Started | Feb 08 06:17:48 PM UTC 25 |
| Finished | Feb 08 06:17:52 PM UTC 25 |
| Peak memory | 217372 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3602185832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49 .usbdev_endpoint_access.3602185832 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_endpoint_types.2632422052 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 284221380 ps |
| CPU time | 1.81 seconds |
| Started | Feb 08 06:17:49 PM UTC 25 |
| Finished | Feb 08 06:17:52 PM UTC 25 |
| Peak memory | 215036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632422052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 49.usbdev_endpoint_types.2632422052 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_fifo_rst.2974614058 |
| Short name | T3067 |
| Test name | |
| Test status | |
| Simulation time | 184577861 ps |
| CPU time | 2.89 seconds |
| Started | Feb 08 06:17:49 PM UTC 25 |
| Finished | Feb 08 06:17:53 PM UTC 25 |
| Peak memory | 217500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2974614058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev _fifo_rst.2974614058 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_in_iso.2177079759 |
| Short name | T3063 |
| Test name | |
| Test status | |
| Simulation time | 180502762 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:17:49 PM UTC 25 |
| Finished | Feb 08 06:17:52 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177079759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 49.usbdev_in_iso.2177079759 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_in_stall.2412934393 |
| Short name | T3061 |
| Test name | |
| Test status | |
| Simulation time | 147878039 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:17:49 PM UTC 25 |
| Finished | Feb 08 06:17:52 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2412934393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev _in_stall.2412934393 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_in_trans.2974953860 |
| Short name | T3064 |
| Test name | |
| Test status | |
| Simulation time | 179470932 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:17:49 PM UTC 25 |
| Finished | Feb 08 06:17:52 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2974953860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev _in_trans.2974953860 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_invalid_sync.3101003775 |
| Short name | T3364 |
| Test name | |
| Test status | |
| Simulation time | 3303076885 ps |
| CPU time | 83.04 seconds |
| Started | Feb 08 06:17:49 PM UTC 25 |
| Finished | Feb 08 06:19:14 PM UTC 25 |
| Peak memory | 227868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101003775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.3101003775 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_iso_retraction.3111397616 |
| Short name | T3193 |
| Test name | |
| Test status | |
| Simulation time | 4738259476 ps |
| CPU time | 34.67 seconds |
| Started | Feb 08 06:17:49 PM UTC 25 |
| Finished | Feb 08 06:18:26 PM UTC 25 |
| Peak memory | 217416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111397616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 49.usbdev_iso_retraction.3111397616 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_link_in_err.2171463031 |
| Short name | T3066 |
| Test name | |
| Test status | |
| Simulation time | 208607107 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:17:51 PM UTC 25 |
| Finished | Feb 08 06:17:53 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2171463031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usb dev_link_in_err.2171463031 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_link_resume.298621749 |
| Short name | T3227 |
| Test name | |
| Test status | |
| Simulation time | 25039226798 ps |
| CPU time | 39.85 seconds |
| Started | Feb 08 06:17:51 PM UTC 25 |
| Finished | Feb 08 06:18:32 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=298621749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbd ev_link_resume.298621749 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_link_suspend.622229105 |
| Short name | T3089 |
| Test name | |
| Test status | |
| Simulation time | 3813900539 ps |
| CPU time | 7.7 seconds |
| Started | Feb 08 06:17:52 PM UTC 25 |
| Finished | Feb 08 06:18:01 PM UTC 25 |
| Peak memory | 227792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=622229105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usb dev_link_suspend.622229105 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_low_speed_traffic.3184602844 |
| Short name | T3153 |
| Test name | |
| Test status | |
| Simulation time | 2722979029 ps |
| CPU time | 24.89 seconds |
| Started | Feb 08 06:17:52 PM UTC 25 |
| Finished | Feb 08 06:18:18 PM UTC 25 |
| Peak memory | 229708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184602844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 49.usbdev_low_speed_traffic.3184602844 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_max_inter_pkt_delay.1306402378 |
| Short name | T3290 |
| Test name | |
| Test status | |
| Simulation time | 2127300603 ps |
| CPU time | 53.55 seconds |
| Started | Feb 08 06:17:52 PM UTC 25 |
| Finished | Feb 08 06:18:47 PM UTC 25 |
| Peak memory | 234488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306402378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.1306402378 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_max_length_in_transaction.3295451924 |
| Short name | T3071 |
| Test name | |
| Test status | |
| Simulation time | 253800419 ps |
| CPU time | 1.89 seconds |
| Started | Feb 08 06:17:52 PM UTC 25 |
| Finished | Feb 08 06:17:55 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295451924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 49.usbdev_max_length_in_transaction.3295451924 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_max_length_out_transaction.165741878 |
| Short name | T3070 |
| Test name | |
| Test status | |
| Simulation time | 198606526 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:17:52 PM UTC 25 |
| Finished | Feb 08 06:17:55 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=165741878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 49.usbdev_max_length_out_transaction.165741878 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_min_inter_pkt_delay.1422681054 |
| Short name | T3181 |
| Test name | |
| Test status | |
| Simulation time | 2774949555 ps |
| CPU time | 28.67 seconds |
| Started | Feb 08 06:17:54 PM UTC 25 |
| Finished | Feb 08 06:18:24 PM UTC 25 |
| Peak memory | 227708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422681054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.1422681054 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_min_length_in_transaction.3559918240 |
| Short name | T3074 |
| Test name | |
| Test status | |
| Simulation time | 153950002 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:17:54 PM UTC 25 |
| Finished | Feb 08 06:17:56 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559918240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 49.usbdev_min_length_in_transaction.3559918240 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_min_length_out_transaction.3490241575 |
| Short name | T3077 |
| Test name | |
| Test status | |
| Simulation time | 226207496 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:17:54 PM UTC 25 |
| Finished | Feb 08 06:17:57 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3490241575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3490241575 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_nak_trans.3863216590 |
| Short name | T3042 |
| Test name | |
| Test status | |
| Simulation time | 216305240 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 06:17:54 PM UTC 25 |
| Finished | Feb 08 06:17:56 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3863216590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbde v_nak_trans.3863216590 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_out_iso.3043589495 |
| Short name | T3076 |
| Test name | |
| Test status | |
| Simulation time | 187324739 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:17:54 PM UTC 25 |
| Finished | Feb 08 06:17:57 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3043589495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_ out_iso.3043589495 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_out_stall.867895720 |
| Short name | T3075 |
| Test name | |
| Test status | |
| Simulation time | 187208492 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:17:54 PM UTC 25 |
| Finished | Feb 08 06:17:57 PM UTC 25 |
| Peak memory | 215088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=867895720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev _out_stall.867895720 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_out_trans_nak.2799233553 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 152765077 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:17:54 PM UTC 25 |
| Finished | Feb 08 06:17:56 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2799233553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.u sbdev_out_trans_nak.2799233553 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_pending_in_trans.1032341912 |
| Short name | T3080 |
| Test name | |
| Test status | |
| Simulation time | 217431033 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:17:55 PM UTC 25 |
| Finished | Feb 08 06:17:58 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1032341912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.usbdev_pending_in_trans.1032341912 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_phy_config_pinflip.4203579997 |
| Short name | T3082 |
| Test name | |
| Test status | |
| Simulation time | 238121948 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:17:55 PM UTC 25 |
| Finished | Feb 08 06:17:58 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203579997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 49.usbdev_phy_config_pinflip.4203579997 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_phy_config_usb_ref_disable.3847494141 |
| Short name | T3081 |
| Test name | |
| Test status | |
| Simulation time | 162726608 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:17:55 PM UTC 25 |
| Finished | Feb 08 06:17:58 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3847494141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3847494141 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_phy_pins_sense.2666250009 |
| Short name | T3079 |
| Test name | |
| Test status | |
| Simulation time | 41514069 ps |
| CPU time | 0.98 seconds |
| Started | Feb 08 06:17:55 PM UTC 25 |
| Finished | Feb 08 06:17:57 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2666250009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49. usbdev_phy_pins_sense.2666250009 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_pkt_buffer.1660465423 |
| Short name | T3165 |
| Test name | |
| Test status | |
| Simulation time | 8867091409 ps |
| CPU time | 22.05 seconds |
| Started | Feb 08 06:17:57 PM UTC 25 |
| Finished | Feb 08 06:18:20 PM UTC 25 |
| Peak memory | 227684 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1660465423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbd ev_pkt_buffer.1660465423 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_pkt_received.3638692466 |
| Short name | T3084 |
| Test name | |
| Test status | |
| Simulation time | 191452322 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:17:57 PM UTC 25 |
| Finished | Feb 08 06:18:00 PM UTC 25 |
| Peak memory | 216816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3638692466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.us bdev_pkt_received.3638692466 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_pkt_sent.601394665 |
| Short name | T3083 |
| Test name | |
| Test status | |
| Simulation time | 234824087 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:17:57 PM UTC 25 |
| Finished | Feb 08 06:17:59 PM UTC 25 |
| Peak memory | 214560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=601394665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_ pkt_sent.601394665 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_random_length_in_transaction.3343648650 |
| Short name | T3086 |
| Test name | |
| Test status | |
| Simulation time | 192143122 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:17:57 PM UTC 25 |
| Finished | Feb 08 06:18:00 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3343648650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.u sbdev_random_length_in_transaction.3343648650 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_random_length_out_transaction.80297305 |
| Short name | T3085 |
| Test name | |
| Test status | |
| Simulation time | 181065516 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:17:57 PM UTC 25 |
| Finished | Feb 08 06:18:00 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=80297305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.80297305 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_rx_crc_err.1674939112 |
| Short name | T3090 |
| Test name | |
| Test status | |
| Simulation time | 177853172 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:17:59 PM UTC 25 |
| Finished | Feb 08 06:18:01 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1674939112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbd ev_rx_crc_err.1674939112 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_rx_full.1887144921 |
| Short name | T3097 |
| Test name | |
| Test status | |
| Simulation time | 385184055 ps |
| CPU time | 2 seconds |
| Started | Feb 08 06:17:59 PM UTC 25 |
| Finished | Feb 08 06:18:02 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1887144921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_ rx_full.1887144921 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_setup_stage.3262203382 |
| Short name | T3091 |
| Test name | |
| Test status | |
| Simulation time | 200402724 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:17:59 PM UTC 25 |
| Finished | Feb 08 06:18:01 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3262203382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usb dev_setup_stage.3262203382 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_setup_trans_ignored.1889179809 |
| Short name | T3092 |
| Test name | |
| Test status | |
| Simulation time | 197263647 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:17:59 PM UTC 25 |
| Finished | Feb 08 06:18:01 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1889179809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 49.usbdev_setup_trans_ignored.1889179809 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_smoke.507892591 |
| Short name | T3093 |
| Test name | |
| Test status | |
| Simulation time | 201098945 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:17:59 PM UTC 25 |
| Finished | Feb 08 06:18:02 PM UTC 25 |
| Peak memory | 215056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=507892591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smo ke.507892591 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_spurious_pids_ignored.77266569 |
| Short name | T3176 |
| Test name | |
| Test status | |
| Simulation time | 3085304681 ps |
| CPU time | 22.52 seconds |
| Started | Feb 08 06:17:59 PM UTC 25 |
| Finished | Feb 08 06:18:23 PM UTC 25 |
| Peak memory | 229672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77266569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 49.usbdev_spurious_pids_ignored.77266569 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_stall_priority_over_nak.2563048774 |
| Short name | T3095 |
| Test name | |
| Test status | |
| Simulation time | 199740849 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:17:59 PM UTC 25 |
| Finished | Feb 08 06:18:02 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2563048774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 49.usbdev_stall_priority_over_nak.2563048774 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_stall_trans.3718542566 |
| Short name | T3098 |
| Test name | |
| Test status | |
| Simulation time | 213381639 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:17:59 PM UTC 25 |
| Finished | Feb 08 06:18:02 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3718542566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usb dev_stall_trans.3718542566 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_stream_len_max.2578227900 |
| Short name | T3105 |
| Test name | |
| Test status | |
| Simulation time | 814004984 ps |
| CPU time | 2.46 seconds |
| Started | Feb 08 06:18:00 PM UTC 25 |
| Finished | Feb 08 06:18:04 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2578227900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49. usbdev_stream_len_max.2578227900 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_streaming_out.68838795 |
| Short name | T3376 |
| Test name | |
| Test status | |
| Simulation time | 3205087534 ps |
| CPU time | 80.08 seconds |
| Started | Feb 08 06:17:59 PM UTC 25 |
| Finished | Feb 08 06:19:21 PM UTC 25 |
| Peak memory | 227880 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=68838795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_ streaming_out.68838795 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_timeout_missing_host_handshake.3389996143 |
| Short name | T3100 |
| Test name | |
| Test status | |
| Simulation time | 1540341460 ps |
| CPU time | 13.49 seconds |
| Started | Feb 08 06:17:47 PM UTC 25 |
| Finished | Feb 08 06:18:02 PM UTC 25 |
| Peak memory | 217356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389996143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing_host_handshake.3389996143 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_tx_rx_disruption.4216391428 |
| Short name | T3104 |
| Test name | |
| Test status | |
| Simulation time | 495893599 ps |
| CPU time | 1.9 seconds |
| Started | Feb 08 06:18:00 PM UTC 25 |
| Finished | Feb 08 06:18:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 216391428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_tx_rx_disruption.4216391428 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/49.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/490.usbdev_tx_rx_disruption.973960396 |
| Short name | T3594 |
| Test name | |
| Test status | |
| Simulation time | 479381194 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:26 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 73960396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 490.usbdev_tx_rx_disruption.973960396 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/490.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/491.usbdev_tx_rx_disruption.2141383656 |
| Short name | T3603 |
| Test name | |
| Test status | |
| Simulation time | 572921216 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:26 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 141383656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 491.usbdev_tx_rx_disruption.2141383656 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/491.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/492.usbdev_tx_rx_disruption.3902888256 |
| Short name | T3605 |
| Test name | |
| Test status | |
| Simulation time | 513422025 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:29 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 902888256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 492.usbdev_tx_rx_disruption.3902888256 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/492.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/493.usbdev_tx_rx_disruption.3739790204 |
| Short name | T3598 |
| Test name | |
| Test status | |
| Simulation time | 557706421 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:26 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 739790204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 493.usbdev_tx_rx_disruption.3739790204 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/493.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/494.usbdev_tx_rx_disruption.4190007180 |
| Short name | T3599 |
| Test name | |
| Test status | |
| Simulation time | 498505627 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:26 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 190007180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 494.usbdev_tx_rx_disruption.4190007180 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/494.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/495.usbdev_tx_rx_disruption.3777534634 |
| Short name | T3606 |
| Test name | |
| Test status | |
| Simulation time | 658517110 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:30 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 777534634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 495.usbdev_tx_rx_disruption.3777534634 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/495.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/496.usbdev_tx_rx_disruption.355555123 |
| Short name | T3604 |
| Test name | |
| Test status | |
| Simulation time | 491165455 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:29 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 55555123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 496.usbdev_tx_rx_disruption.355555123 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/496.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/497.usbdev_tx_rx_disruption.243305819 |
| Short name | T3611 |
| Test name | |
| Test status | |
| Simulation time | 613788231 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 06:20:16 PM UTC 25 |
| Finished | Feb 08 06:20:30 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 43305819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 497.usbdev_tx_rx_disruption.243305819 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/497.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/498.usbdev_tx_rx_disruption.390572364 |
| Short name | T3592 |
| Test name | |
| Test status | |
| Simulation time | 621387259 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:20:20 PM UTC 25 |
| Finished | Feb 08 06:20:24 PM UTC 25 |
| Peak memory | 215168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 90572364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 498.usbdev_tx_rx_disruption.390572364 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/498.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/499.usbdev_tx_rx_disruption.16070811 |
| Short name | T3591 |
| Test name | |
| Test status | |
| Simulation time | 568795434 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:20:20 PM UTC 25 |
| Finished | Feb 08 06:20:24 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 6070811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 499.usbdev_tx_rx_disruption.16070811 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/499.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_alert_test.351090394 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 42639598 ps |
| CPU time | 1 seconds |
| Started | Feb 08 06:00:43 PM UTC 25 |
| Finished | Feb 08 06:00:45 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351090394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 5.usbdev_alert_test.351090394 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_aon_wake_disconnect.548447571 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 9270413640 ps |
| CPU time | 23.92 seconds |
| Started | Feb 08 05:59:43 PM UTC 25 |
| Finished | Feb 08 06:00:08 PM UTC 25 |
| Peak memory | 217380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548447571 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.548447571 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_aon_wake_reset.3593525491 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 14574539881 ps |
| CPU time | 27 seconds |
| Started | Feb 08 05:59:43 PM UTC 25 |
| Finished | Feb 08 06:00:11 PM UTC 25 |
| Peak memory | 227592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593525491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.3593525491 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_aon_wake_resume.3616991635 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 24923308933 ps |
| CPU time | 43.31 seconds |
| Started | Feb 08 05:59:44 PM UTC 25 |
| Finished | Feb 08 06:00:29 PM UTC 25 |
| Peak memory | 227648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616991635 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.3616991635 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_av_buffer.1929790917 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 168511164 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 05:59:46 PM UTC 25 |
| Finished | Feb 08 05:59:48 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1929790917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev _av_buffer.1929790917 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_bitstuff_err.221986616 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 191597615 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 05:59:46 PM UTC 25 |
| Finished | Feb 08 05:59:48 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=221986616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbd ev_bitstuff_err.221986616 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_data_toggle_clear.531678020 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 505564074 ps |
| CPU time | 2.96 seconds |
| Started | Feb 08 05:59:49 PM UTC 25 |
| Finished | Feb 08 05:59:53 PM UTC 25 |
| Peak memory | 217180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=531678020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5 .usbdev_data_toggle_clear.531678020 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_data_toggle_restore.3331216075 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 879777336 ps |
| CPU time | 4.15 seconds |
| Started | Feb 08 05:59:49 PM UTC 25 |
| Finished | Feb 08 05:59:54 PM UTC 25 |
| Peak memory | 217392 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331216075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.3331216075 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_device_address.3668066388 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 14198954021 ps |
| CPU time | 30.04 seconds |
| Started | Feb 08 05:59:54 PM UTC 25 |
| Finished | Feb 08 06:00:25 PM UTC 25 |
| Peak memory | 217680 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3668066388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.u sbdev_device_address.3668066388 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_device_timeout.3191584215 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 2919749565 ps |
| CPU time | 23.89 seconds |
| Started | Feb 08 05:59:54 PM UTC 25 |
| Finished | Feb 08 06:00:19 PM UTC 25 |
| Peak memory | 217400 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191584215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.3191584215 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_disable_endpoint.2393779345 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 895184567 ps |
| CPU time | 4.29 seconds |
| Started | Feb 08 06:00:01 PM UTC 25 |
| Finished | Feb 08 06:00:23 PM UTC 25 |
| Peak memory | 217344 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2393779345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5 .usbdev_disable_endpoint.2393779345 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_disconnected.1242656706 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 155850202 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:00:03 PM UTC 25 |
| Finished | Feb 08 06:00:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1242656706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usb dev_disconnected.1242656706 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_enable.3241536968 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 60651644 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:00:20 PM UTC 25 |
| Finished | Feb 08 06:00:23 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3241536968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_en able.3241536968 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_endpoint_access.2921596374 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 872408368 ps |
| CPU time | 3.55 seconds |
| Started | Feb 08 06:00:20 PM UTC 25 |
| Finished | Feb 08 06:00:26 PM UTC 25 |
| Peak memory | 217508 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2921596374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5. usbdev_endpoint_access.2921596374 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_fifo_rst.955346430 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 271545656 ps |
| CPU time | 2.85 seconds |
| Started | Feb 08 06:00:20 PM UTC 25 |
| Finished | Feb 08 06:00:25 PM UTC 25 |
| Peak memory | 217480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=955346430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_f ifo_rst.955346430 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_in_iso.3090326963 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 227067141 ps |
| CPU time | 1.9 seconds |
| Started | Feb 08 06:00:20 PM UTC 25 |
| Finished | Feb 08 06:00:24 PM UTC 25 |
| Peak memory | 227744 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090326963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 5.usbdev_in_iso.3090326963 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_in_stall.2605948756 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 151824057 ps |
| CPU time | 1.3 seconds |
| Started | Feb 08 06:00:20 PM UTC 25 |
| Finished | Feb 08 06:00:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2605948756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ in_stall.2605948756 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_in_trans.2905993869 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 286922945 ps |
| CPU time | 1.74 seconds |
| Started | Feb 08 06:00:20 PM UTC 25 |
| Finished | Feb 08 06:00:24 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2905993869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ in_trans.2905993869 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_invalid_sync.3962537321 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 4753577748 ps |
| CPU time | 53.31 seconds |
| Started | Feb 08 06:00:20 PM UTC 25 |
| Finished | Feb 08 06:01:16 PM UTC 25 |
| Peak memory | 234432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962537321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.3962537321 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_iso_retraction.3524476872 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 11598288258 ps |
| CPU time | 139 seconds |
| Started | Feb 08 06:00:20 PM UTC 25 |
| Finished | Feb 08 06:02:43 PM UTC 25 |
| Peak memory | 217544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524476872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 5.usbdev_iso_retraction.3524476872 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_link_in_err.379577457 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 170107809 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:00:20 PM UTC 25 |
| Finished | Feb 08 06:00:24 PM UTC 25 |
| Peak memory | 215000 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=379577457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbde v_link_in_err.379577457 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_link_resume.877127210 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 30921401867 ps |
| CPU time | 59.2 seconds |
| Started | Feb 08 06:00:22 PM UTC 25 |
| Finished | Feb 08 06:01:23 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=877127210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbde v_link_resume.877127210 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_link_suspend.4244238370 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 3453134760 ps |
| CPU time | 7.1 seconds |
| Started | Feb 08 06:00:22 PM UTC 25 |
| Finished | Feb 08 06:00:31 PM UTC 25 |
| Peak memory | 217572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4244238370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usb dev_link_suspend.4244238370 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_low_speed_traffic.1877912809 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 3773052046 ps |
| CPU time | 111.26 seconds |
| Started | Feb 08 06:00:27 PM UTC 25 |
| Finished | Feb 08 06:02:21 PM UTC 25 |
| Peak memory | 229772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877912809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 5.usbdev_low_speed_traffic.1877912809 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_max_inter_pkt_delay.3795006387 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 1961052551 ps |
| CPU time | 50.38 seconds |
| Started | Feb 08 06:00:27 PM UTC 25 |
| Finished | Feb 08 06:01:19 PM UTC 25 |
| Peak memory | 227776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795006387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.3795006387 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_max_length_in_transaction.2921345066 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 234767405 ps |
| CPU time | 1.71 seconds |
| Started | Feb 08 06:00:27 PM UTC 25 |
| Finished | Feb 08 06:00:30 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921345066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 5.usbdev_max_length_in_transaction.2921345066 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_max_length_out_transaction.1052396855 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 203375899 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:00:27 PM UTC 25 |
| Finished | Feb 08 06:00:30 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1052396855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.1052396855 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_max_non_iso_usb_traffic.3799891536 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 1829708987 ps |
| CPU time | 14.1 seconds |
| Started | Feb 08 06:00:27 PM UTC 25 |
| Finished | Feb 08 06:00:42 PM UTC 25 |
| Peak memory | 217304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3799891536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 5.usbdev_max_non_iso_usb_traffic.3799891536 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_max_usb_traffic.4259537295 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 2877852527 ps |
| CPU time | 29.16 seconds |
| Started | Feb 08 06:00:27 PM UTC 25 |
| Finished | Feb 08 06:00:58 PM UTC 25 |
| Peak memory | 217484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259537295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_ traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 5.usbdev_max_usb_traffic.4259537295 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_min_inter_pkt_delay.796488775 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 2464201494 ps |
| CPU time | 67.22 seconds |
| Started | Feb 08 06:00:27 PM UTC 25 |
| Finished | Feb 08 06:01:36 PM UTC 25 |
| Peak memory | 229772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796488775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usb dev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.796488775 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_min_length_in_transaction.3437991255 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 167777937 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:00:27 PM UTC 25 |
| Finished | Feb 08 06:00:30 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437991255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.usbdev_min_length_in_transaction.3437991255 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_min_length_out_transaction.3594116670 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 148610343 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:00:27 PM UTC 25 |
| Finished | Feb 08 06:00:30 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3594116670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.3594116670 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_nak_trans.4164838025 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 202328371 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:00:27 PM UTC 25 |
| Finished | Feb 08 06:00:30 PM UTC 25 |
| Peak memory | 215152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4164838025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev _nak_trans.4164838025 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_out_iso.4279175996 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 180264525 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:00:27 PM UTC 25 |
| Finished | Feb 08 06:00:30 PM UTC 25 |
| Peak memory | 215072 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4279175996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_o ut_iso.4279175996 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_out_stall.1767355238 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 171173510 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:00:27 PM UTC 25 |
| Finished | Feb 08 06:00:30 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1767355238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev _out_stall.1767355238 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_out_trans_nak.3718021863 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 145876041 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:00:27 PM UTC 25 |
| Finished | Feb 08 06:00:30 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3718021863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.us bdev_out_trans_nak.3718021863 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_pending_in_trans.940390940 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 187827383 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:00:31 PM UTC 25 |
| Finished | Feb 08 06:00:34 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=940390940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5. usbdev_pending_in_trans.940390940 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_phy_config_pinflip.2258034460 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 268494494 ps |
| CPU time | 1.82 seconds |
| Started | Feb 08 06:00:31 PM UTC 25 |
| Finished | Feb 08 06:00:34 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258034460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 5.usbdev_phy_config_pinflip.2258034460 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_phy_config_usb_ref_disable.1145879006 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 140307751 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:00:31 PM UTC 25 |
| Finished | Feb 08 06:00:34 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1145879006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.1145879006 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_phy_pins_sense.939611170 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 39344175 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:00:31 PM UTC 25 |
| Finished | Feb 08 06:00:33 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=939611170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.us bdev_phy_pins_sense.939611170 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_pkt_buffer.2754419601 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 21059704686 ps |
| CPU time | 69.77 seconds |
| Started | Feb 08 06:00:31 PM UTC 25 |
| Finished | Feb 08 06:01:43 PM UTC 25 |
| Peak memory | 227872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2754419601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbde v_pkt_buffer.2754419601 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_pkt_received.1313618551 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 167744423 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:00:31 PM UTC 25 |
| Finished | Feb 08 06:00:34 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1313618551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usb dev_pkt_received.1313618551 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_pkt_sent.82469513 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 199152648 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:00:31 PM UTC 25 |
| Finished | Feb 08 06:00:34 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=82469513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pk t_sent.82469513 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_rand_bus_disconnects.3692660893 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 5648076310 ps |
| CPU time | 24.48 seconds |
| Started | Feb 08 06:00:32 PM UTC 25 |
| Finished | Feb 08 06:00:58 PM UTC 25 |
| Peak memory | 234468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692660893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_ TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.3692660893 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_rand_bus_disconnects/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_rand_suspends.2817124260 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 5694951718 ps |
| CPU time | 89.89 seconds |
| Started | Feb 08 06:00:35 PM UTC 25 |
| Finished | Feb 08 06:02:08 PM UTC 25 |
| Peak memory | 229968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817124260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_ TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.2817124260 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_rand_suspends/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_random_length_in_transaction.821979961 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 226025987 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 06:00:31 PM UTC 25 |
| Finished | Feb 08 06:00:34 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=821979961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usb dev_random_length_in_transaction.821979961 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_random_length_out_transaction.3333939672 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 206054367 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:00:31 PM UTC 25 |
| Finished | Feb 08 06:00:34 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3333939672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.usbdev_random_length_out_transaction.3333939672 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_resume_link_active.1595354935 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 20165784879 ps |
| CPU time | 32.67 seconds |
| Started | Feb 08 06:00:35 PM UTC 25 |
| Finished | Feb 08 06:01:10 PM UTC 25 |
| Peak memory | 217332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1595354935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_resume_link_active.1595354935 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_resume_link_active/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_rx_crc_err.3218636042 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 148011372 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:00:35 PM UTC 25 |
| Finished | Feb 08 06:00:38 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3218636042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbde v_rx_crc_err.3218636042 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_rx_full.1431894152 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 345706239 ps |
| CPU time | 2.26 seconds |
| Started | Feb 08 06:00:35 PM UTC 25 |
| Finished | Feb 08 06:00:39 PM UTC 25 |
| Peak memory | 217268 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1431894152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_r x_full.1431894152 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_setup_stage.380314483 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 147776823 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:00:35 PM UTC 25 |
| Finished | Feb 08 06:00:38 PM UTC 25 |
| Peak memory | 214960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=380314483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbde v_setup_stage.380314483 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_setup_trans_ignored.4087415104 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 149604442 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:00:35 PM UTC 25 |
| Finished | Feb 08 06:00:38 PM UTC 25 |
| Peak memory | 215076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4087415104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.usbdev_setup_trans_ignored.4087415104 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_smoke.812675260 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 213763297 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:00:35 PM UTC 25 |
| Finished | Feb 08 06:00:39 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=812675260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smok e.812675260 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_spurious_pids_ignored.3238027056 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 3198356505 ps |
| CPU time | 44.79 seconds |
| Started | Feb 08 06:00:35 PM UTC 25 |
| Finished | Feb 08 06:01:22 PM UTC 25 |
| Peak memory | 227776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238027056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 5.usbdev_spurious_pids_ignored.3238027056 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_stall_priority_over_nak.946672142 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 172372247 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:00:39 PM UTC 25 |
| Finished | Feb 08 06:00:41 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=946672142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 5.usbdev_stall_priority_over_nak.946672142 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_stall_trans.3451815907 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 184290682 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:00:40 PM UTC 25 |
| Finished | Feb 08 06:00:44 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3451815907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbd ev_stall_trans.3451815907 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_stream_len_max.3405729898 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 711201605 ps |
| CPU time | 3.37 seconds |
| Started | Feb 08 06:00:40 PM UTC 25 |
| Finished | Feb 08 06:00:46 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3405729898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.u sbdev_stream_len_max.3405729898 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_streaming_out.1993816801 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 3083167268 ps |
| CPU time | 85.56 seconds |
| Started | Feb 08 06:00:40 PM UTC 25 |
| Finished | Feb 08 06:02:09 PM UTC 25 |
| Peak memory | 227856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1993816801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev _streaming_out.1993816801 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/5.usbdev_timeout_missing_host_handshake.64908752 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 1078857828 ps |
| CPU time | 12.58 seconds |
| Started | Feb 08 05:59:55 PM UTC 25 |
| Finished | Feb 08 06:00:09 PM UTC 25 |
| Peak memory | 217408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64908752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UV M_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_host_handshake.64908752 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/5.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/50.usbdev_endpoint_types.2707629514 |
| Short name | T3109 |
| Test name | |
| Test status | |
| Simulation time | 232109051 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 06:18:02 PM UTC 25 |
| Finished | Feb 08 06:18:05 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707629514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 50.usbdev_endpoint_types.2707629514 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/50.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/50.usbdev_tx_rx_disruption.3066682166 |
| Short name | T3108 |
| Test name | |
| Test status | |
| Simulation time | 485181690 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 06:18:02 PM UTC 25 |
| Finished | Feb 08 06:18:04 PM UTC 25 |
| Peak memory | 215012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 066682166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.usbdev_tx_rx_disruption.3066682166 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/50.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/51.usbdev_endpoint_types.3041182653 |
| Short name | T3107 |
| Test name | |
| Test status | |
| Simulation time | 219733889 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:18:02 PM UTC 25 |
| Finished | Feb 08 06:18:04 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041182653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 51.usbdev_endpoint_types.3041182653 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/51.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/51.usbdev_tx_rx_disruption.3444029244 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 563318179 ps |
| CPU time | 2.04 seconds |
| Started | Feb 08 06:18:02 PM UTC 25 |
| Finished | Feb 08 06:18:05 PM UTC 25 |
| Peak memory | 217180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 444029244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.usbdev_tx_rx_disruption.3444029244 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/51.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/52.usbdev_endpoint_types.2908038769 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 463225211 ps |
| CPU time | 1.68 seconds |
| Started | Feb 08 06:18:02 PM UTC 25 |
| Finished | Feb 08 06:18:05 PM UTC 25 |
| Peak memory | 215036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908038769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 52.usbdev_endpoint_types.2908038769 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/52.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/52.usbdev_tx_rx_disruption.4271021418 |
| Short name | T3110 |
| Test name | |
| Test status | |
| Simulation time | 437127290 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:18:04 PM UTC 25 |
| Finished | Feb 08 06:18:07 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 271021418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.usbdev_tx_rx_disruption.4271021418 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/52.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/53.usbdev_endpoint_types.3360739260 |
| Short name | T3112 |
| Test name | |
| Test status | |
| Simulation time | 527676775 ps |
| CPU time | 2.13 seconds |
| Started | Feb 08 06:18:04 PM UTC 25 |
| Finished | Feb 08 06:18:07 PM UTC 25 |
| Peak memory | 217340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360739260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 53.usbdev_endpoint_types.3360739260 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/53.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/53.usbdev_tx_rx_disruption.4108322468 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 513361188 ps |
| CPU time | 1.86 seconds |
| Started | Feb 08 06:18:04 PM UTC 25 |
| Finished | Feb 08 06:18:07 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 108322468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.usbdev_tx_rx_disruption.4108322468 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/53.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/54.usbdev_endpoint_types.2775472567 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 299899321 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:18:04 PM UTC 25 |
| Finished | Feb 08 06:18:07 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775472567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 54.usbdev_endpoint_types.2775472567 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/54.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/54.usbdev_tx_rx_disruption.1489783053 |
| Short name | T3111 |
| Test name | |
| Test status | |
| Simulation time | 482017476 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 06:18:04 PM UTC 25 |
| Finished | Feb 08 06:18:07 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 489783053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.usbdev_tx_rx_disruption.1489783053 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/54.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/55.usbdev_endpoint_types.1720041581 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 425166156 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:18:04 PM UTC 25 |
| Finished | Feb 08 06:18:07 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720041581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 55.usbdev_endpoint_types.1720041581 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/55.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/55.usbdev_tx_rx_disruption.3347417325 |
| Short name | T3113 |
| Test name | |
| Test status | |
| Simulation time | 440564216 ps |
| CPU time | 1.89 seconds |
| Started | Feb 08 06:18:04 PM UTC 25 |
| Finished | Feb 08 06:18:07 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 347417325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.usbdev_tx_rx_disruption.3347417325 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/55.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/56.usbdev_endpoint_types.4031975535 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 351651683 ps |
| CPU time | 2.04 seconds |
| Started | Feb 08 06:18:04 PM UTC 25 |
| Finished | Feb 08 06:18:08 PM UTC 25 |
| Peak memory | 217340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031975535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 56.usbdev_endpoint_types.4031975535 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/56.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/56.usbdev_tx_rx_disruption.914411096 |
| Short name | T3114 |
| Test name | |
| Test status | |
| Simulation time | 726571933 ps |
| CPU time | 2.03 seconds |
| Started | Feb 08 06:18:04 PM UTC 25 |
| Finished | Feb 08 06:18:08 PM UTC 25 |
| Peak memory | 217176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 14411096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.usbdev_tx_rx_disruption.914411096 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/56.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/57.usbdev_endpoint_types.1358344221 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 413809685 ps |
| CPU time | 2.03 seconds |
| Started | Feb 08 06:18:04 PM UTC 25 |
| Finished | Feb 08 06:18:07 PM UTC 25 |
| Peak memory | 217148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358344221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 57.usbdev_endpoint_types.1358344221 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/57.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/57.usbdev_tx_rx_disruption.767931759 |
| Short name | T3116 |
| Test name | |
| Test status | |
| Simulation time | 535064207 ps |
| CPU time | 2.23 seconds |
| Started | Feb 08 06:18:04 PM UTC 25 |
| Finished | Feb 08 06:18:08 PM UTC 25 |
| Peak memory | 217124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 67931759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.usbdev_tx_rx_disruption.767931759 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/57.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/58.usbdev_endpoint_types.3331939405 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 447583657 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 06:18:04 PM UTC 25 |
| Finished | Feb 08 06:18:07 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331939405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 58.usbdev_endpoint_types.3331939405 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/58.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/58.usbdev_tx_rx_disruption.889951229 |
| Short name | T3115 |
| Test name | |
| Test status | |
| Simulation time | 573879246 ps |
| CPU time | 1.91 seconds |
| Started | Feb 08 06:18:04 PM UTC 25 |
| Finished | Feb 08 06:18:08 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 89951229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.usbdev_tx_rx_disruption.889951229 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/58.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/59.usbdev_endpoint_types.3400751199 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 214949525 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:18:06 PM UTC 25 |
| Finished | Feb 08 06:18:08 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400751199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 59.usbdev_endpoint_types.3400751199 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/59.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/59.usbdev_tx_rx_disruption.1171326384 |
| Short name | T3120 |
| Test name | |
| Test status | |
| Simulation time | 646177737 ps |
| CPU time | 1.77 seconds |
| Started | Feb 08 06:18:06 PM UTC 25 |
| Finished | Feb 08 06:18:09 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 171326384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.usbdev_tx_rx_disruption.1171326384 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/59.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_alert_test.728987841 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 40811638 ps |
| CPU time | 0.95 seconds |
| Started | Feb 08 06:01:39 PM UTC 25 |
| Finished | Feb 08 06:01:41 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728987841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 6.usbdev_alert_test.728987841 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_aon_wake_disconnect.1374217137 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 5668040020 ps |
| CPU time | 10.21 seconds |
| Started | Feb 08 06:00:45 PM UTC 25 |
| Finished | Feb 08 06:00:56 PM UTC 25 |
| Peak memory | 227660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374217137 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.1374217137 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_aon_wake_reset.3664261645 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 13657133588 ps |
| CPU time | 32.32 seconds |
| Started | Feb 08 06:00:45 PM UTC 25 |
| Finished | Feb 08 06:01:18 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664261645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.3664261645 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_aon_wake_resume.3857306986 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 30097095410 ps |
| CPU time | 41.69 seconds |
| Started | Feb 08 06:00:45 PM UTC 25 |
| Finished | Feb 08 06:01:28 PM UTC 25 |
| Peak memory | 217632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857306986 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.3857306986 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_av_buffer.2064925419 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 195045049 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:00:46 PM UTC 25 |
| Finished | Feb 08 06:00:48 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2064925419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev _av_buffer.2064925419 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_bitstuff_err.2388205309 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 204437838 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:00:46 PM UTC 25 |
| Finished | Feb 08 06:00:48 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2388205309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usb dev_bitstuff_err.2388205309 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_data_toggle_clear.3487431130 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 359037858 ps |
| CPU time | 2.16 seconds |
| Started | Feb 08 06:00:47 PM UTC 25 |
| Finished | Feb 08 06:00:50 PM UTC 25 |
| Peak memory | 217368 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3487431130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.3487431130 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_data_toggle_restore.3954468135 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 527458675 ps |
| CPU time | 2.91 seconds |
| Started | Feb 08 06:00:48 PM UTC 25 |
| Finished | Feb 08 06:00:52 PM UTC 25 |
| Peak memory | 217176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954468135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.3954468135 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_device_timeout.796492213 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 1520443528 ps |
| CPU time | 13.77 seconds |
| Started | Feb 08 06:00:49 PM UTC 25 |
| Finished | Feb 08 06:01:04 PM UTC 25 |
| Peak memory | 217600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796492213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.796492213 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_disable_endpoint.1734460394 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 630820422 ps |
| CPU time | 2.95 seconds |
| Started | Feb 08 06:00:51 PM UTC 25 |
| Finished | Feb 08 06:00:55 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1734460394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6 .usbdev_disable_endpoint.1734460394 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_disconnected.2286819792 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 144144715 ps |
| CPU time | 1.12 seconds |
| Started | Feb 08 06:00:53 PM UTC 25 |
| Finished | Feb 08 06:00:55 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2286819792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usb dev_disconnected.2286819792 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_enable.3851296147 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 82935275 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:00:55 PM UTC 25 |
| Finished | Feb 08 06:00:57 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3851296147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_en able.3851296147 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_endpoint_access.105719449 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 882482175 ps |
| CPU time | 2.67 seconds |
| Started | Feb 08 06:00:56 PM UTC 25 |
| Finished | Feb 08 06:00:59 PM UTC 25 |
| Peak memory | 217320 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=105719449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.u sbdev_endpoint_access.105719449 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_endpoint_types.2962477163 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 160636434 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:00:57 PM UTC 25 |
| Finished | Feb 08 06:00:59 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962477163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 6.usbdev_endpoint_types.2962477163 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_fifo_rst.1394326351 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 211487061 ps |
| CPU time | 2.51 seconds |
| Started | Feb 08 06:00:57 PM UTC 25 |
| Finished | Feb 08 06:01:01 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1394326351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ fifo_rst.1394326351 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_in_iso.3994128544 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 156823181 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:00:59 PM UTC 25 |
| Finished | Feb 08 06:01:02 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994128544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 6.usbdev_in_iso.3994128544 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_in_stall.484763391 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 166740002 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:00:59 PM UTC 25 |
| Finished | Feb 08 06:01:02 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=484763391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_i n_stall.484763391 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_in_trans.217837447 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 188975184 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:01:00 PM UTC 25 |
| Finished | Feb 08 06:01:03 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=217837447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_i n_trans.217837447 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_invalid_sync.2583293192 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 2810645275 ps |
| CPU time | 19.68 seconds |
| Started | Feb 08 06:00:58 PM UTC 25 |
| Finished | Feb 08 06:01:19 PM UTC 25 |
| Peak memory | 234568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583293192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.2583293192 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_iso_retraction.1979792559 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 5385393445 ps |
| CPU time | 42.54 seconds |
| Started | Feb 08 06:01:01 PM UTC 25 |
| Finished | Feb 08 06:01:45 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979792559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 6.usbdev_iso_retraction.1979792559 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_link_in_err.560233400 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 244570840 ps |
| CPU time | 1.84 seconds |
| Started | Feb 08 06:01:02 PM UTC 25 |
| Finished | Feb 08 06:01:05 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=560233400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbde v_link_in_err.560233400 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_link_resume.826971720 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 32907068906 ps |
| CPU time | 63.03 seconds |
| Started | Feb 08 06:01:03 PM UTC 25 |
| Finished | Feb 08 06:02:08 PM UTC 25 |
| Peak memory | 217448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=826971720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbde v_link_resume.826971720 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_link_suspend.1795486650 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 10431853396 ps |
| CPU time | 30.72 seconds |
| Started | Feb 08 06:01:03 PM UTC 25 |
| Finished | Feb 08 06:01:35 PM UTC 25 |
| Peak memory | 217580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1795486650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usb dev_link_suspend.1795486650 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_low_speed_traffic.159096441 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 3986894222 ps |
| CPU time | 114.26 seconds |
| Started | Feb 08 06:01:04 PM UTC 25 |
| Finished | Feb 08 06:03:01 PM UTC 25 |
| Peak memory | 227660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159096441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed _traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 6.usbdev_low_speed_traffic.159096441 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_max_inter_pkt_delay.1419611992 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 2083635894 ps |
| CPU time | 59.37 seconds |
| Started | Feb 08 06:01:05 PM UTC 25 |
| Finished | Feb 08 06:02:06 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419611992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.1419611992 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_max_length_in_transaction.1873401908 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 240762383 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:01:05 PM UTC 25 |
| Finished | Feb 08 06:01:08 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873401908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 6.usbdev_max_length_in_transaction.1873401908 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_max_length_out_transaction.491317190 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 197699654 ps |
| CPU time | 1.23 seconds |
| Started | Feb 08 06:01:08 PM UTC 25 |
| Finished | Feb 08 06:01:11 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=491317190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 6.usbdev_max_length_out_transaction.491317190 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_max_non_iso_usb_traffic.1327141201 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 2618179494 ps |
| CPU time | 22.3 seconds |
| Started | Feb 08 06:01:10 PM UTC 25 |
| Finished | Feb 08 06:01:34 PM UTC 25 |
| Peak memory | 229752 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1327141201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 6.usbdev_max_non_iso_usb_traffic.1327141201 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_max_usb_traffic.2697722378 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 2512315853 ps |
| CPU time | 33.34 seconds |
| Started | Feb 08 06:01:11 PM UTC 25 |
| Finished | Feb 08 06:01:45 PM UTC 25 |
| Peak memory | 229900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697722378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_ traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 6.usbdev_max_usb_traffic.2697722378 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_min_inter_pkt_delay.620926589 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 2759464620 ps |
| CPU time | 28.12 seconds |
| Started | Feb 08 06:01:12 PM UTC 25 |
| Finished | Feb 08 06:01:41 PM UTC 25 |
| Peak memory | 227688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620926589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usb dev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.620926589 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_min_length_in_transaction.1247965276 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 194372694 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:01:17 PM UTC 25 |
| Finished | Feb 08 06:01:19 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247965276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.usbdev_min_length_in_transaction.1247965276 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_min_length_out_transaction.4222243013 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 146822509 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:01:19 PM UTC 25 |
| Finished | Feb 08 06:01:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4222243013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.4222243013 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_nak_trans.1290362621 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 171486054 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:01:20 PM UTC 25 |
| Finished | Feb 08 06:01:23 PM UTC 25 |
| Peak memory | 215060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1290362621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev _nak_trans.1290362621 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_out_iso.4193249960 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 245550712 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:01:20 PM UTC 25 |
| Finished | Feb 08 06:01:23 PM UTC 25 |
| Peak memory | 215052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4193249960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_o ut_iso.4193249960 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_out_stall.1361682093 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 199802464 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:01:21 PM UTC 25 |
| Finished | Feb 08 06:01:23 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1361682093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev _out_stall.1361682093 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_out_trans_nak.649810503 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 181590627 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:01:24 PM UTC 25 |
| Finished | Feb 08 06:01:26 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=649810503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usb dev_out_trans_nak.649810503 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_pending_in_trans.586202237 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 165925162 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:01:24 PM UTC 25 |
| Finished | Feb 08 06:01:26 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=586202237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6. usbdev_pending_in_trans.586202237 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_phy_config_pinflip.2403099363 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 184871013 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:01:24 PM UTC 25 |
| Finished | Feb 08 06:01:26 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403099363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 6.usbdev_phy_config_pinflip.2403099363 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_phy_config_usb_ref_disable.2784617353 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 186724859 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:01:24 PM UTC 25 |
| Finished | Feb 08 06:01:26 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2784617353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2784617353 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_phy_pins_sense.177228772 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 35043055 ps |
| CPU time | 0.87 seconds |
| Started | Feb 08 06:01:24 PM UTC 25 |
| Finished | Feb 08 06:01:26 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=177228772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.us bdev_phy_pins_sense.177228772 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_pkt_buffer.2983566687 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 6870171318 ps |
| CPU time | 25.98 seconds |
| Started | Feb 08 06:01:24 PM UTC 25 |
| Finished | Feb 08 06:01:51 PM UTC 25 |
| Peak memory | 231848 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2983566687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbde v_pkt_buffer.2983566687 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_pkt_received.2953665282 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 182633804 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:01:25 PM UTC 25 |
| Finished | Feb 08 06:01:28 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2953665282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usb dev_pkt_received.2953665282 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_pkt_sent.1437845214 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 271332045 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:01:27 PM UTC 25 |
| Finished | Feb 08 06:01:30 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1437845214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ pkt_sent.1437845214 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_rand_bus_disconnects.777979364 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 5137447029 ps |
| CPU time | 22.37 seconds |
| Started | Feb 08 06:01:27 PM UTC 25 |
| Finished | Feb 08 06:01:51 PM UTC 25 |
| Peak memory | 234488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777979364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.777979364 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_rand_bus_disconnects/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_rand_bus_resets.2995177383 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 7772470965 ps |
| CPU time | 202.64 seconds |
| Started | Feb 08 06:01:27 PM UTC 25 |
| Finished | Feb 08 06:04:53 PM UTC 25 |
| Peak memory | 229776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995177383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 6.usbdev_rand_bus_resets.2995177383 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_rand_bus_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_rand_suspends.707910704 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 9598316794 ps |
| CPU time | 180.45 seconds |
| Started | Feb 08 06:01:29 PM UTC 25 |
| Finished | Feb 08 06:04:32 PM UTC 25 |
| Peak memory | 229760 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707910704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.707910704 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_rand_suspends/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_random_length_in_transaction.2959873929 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 207346608 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:01:27 PM UTC 25 |
| Finished | Feb 08 06:01:30 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2959873929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.us bdev_random_length_in_transaction.2959873929 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_random_length_out_transaction.1890270668 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 187094996 ps |
| CPU time | 1.59 seconds |
| Started | Feb 08 06:01:27 PM UTC 25 |
| Finished | Feb 08 06:01:30 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1890270668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.usbdev_random_length_out_transaction.1890270668 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_resume_link_active.909238950 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 20193295021 ps |
| CPU time | 36.81 seconds |
| Started | Feb 08 06:01:29 PM UTC 25 |
| Finished | Feb 08 06:02:07 PM UTC 25 |
| Peak memory | 217208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=909238950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_resume_link_active.909238950 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_resume_link_active/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_rx_crc_err.964355150 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 133209884 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:01:30 PM UTC 25 |
| Finished | Feb 08 06:01:32 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=964355150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev _rx_crc_err.964355150 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_rx_full.3321117367 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 255404998 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:01:31 PM UTC 25 |
| Finished | Feb 08 06:01:34 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3321117367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_r x_full.3321117367 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_setup_stage.3074304072 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 183517443 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:01:31 PM UTC 25 |
| Finished | Feb 08 06:01:34 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3074304072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbd ev_setup_stage.3074304072 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_setup_trans_ignored.689426479 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 160741367 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:01:31 PM UTC 25 |
| Finished | Feb 08 06:01:33 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=689426479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.689426479 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_smoke.1646214186 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 212120681 ps |
| CPU time | 1.76 seconds |
| Started | Feb 08 06:01:33 PM UTC 25 |
| Finished | Feb 08 06:01:36 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1646214186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smo ke.1646214186 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_spurious_pids_ignored.680037990 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 1909034162 ps |
| CPU time | 56.18 seconds |
| Started | Feb 08 06:01:34 PM UTC 25 |
| Finished | Feb 08 06:02:32 PM UTC 25 |
| Peak memory | 229468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680037990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 6.usbdev_spurious_pids_ignored.680037990 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_stall_priority_over_nak.1357503881 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 168101231 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:01:34 PM UTC 25 |
| Finished | Feb 08 06:01:37 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1357503881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 6.usbdev_stall_priority_over_nak.1357503881 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_stall_trans.3528270172 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 171508194 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:01:35 PM UTC 25 |
| Finished | Feb 08 06:01:37 PM UTC 25 |
| Peak memory | 214988 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3528270172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbd ev_stall_trans.3528270172 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_stream_len_max.960362986 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 948505807 ps |
| CPU time | 2.81 seconds |
| Started | Feb 08 06:01:39 PM UTC 25 |
| Finished | Feb 08 06:01:42 PM UTC 25 |
| Peak memory | 217356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=960362986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.us bdev_stream_len_max.960362986 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_streaming_out.2853654833 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 2945102748 ps |
| CPU time | 88.36 seconds |
| Started | Feb 08 06:01:39 PM UTC 25 |
| Finished | Feb 08 06:03:09 PM UTC 25 |
| Peak memory | 229712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2853654833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev _streaming_out.2853654833 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_timeout_missing_host_handshake.778624251 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 1527842044 ps |
| CPU time | 17.34 seconds |
| Started | Feb 08 06:00:51 PM UTC 25 |
| Finished | Feb 08 06:01:10 PM UTC 25 |
| Peak memory | 217468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778624251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_host_handshake.778624251 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/6.usbdev_tx_rx_disruption.2525784891 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 572200381 ps |
| CPU time | 2.64 seconds |
| Started | Feb 08 06:01:39 PM UTC 25 |
| Finished | Feb 08 06:01:42 PM UTC 25 |
| Peak memory | 217116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 525784891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_tx_rx_disruption.2525784891 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/6.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/60.usbdev_tx_rx_disruption.28186306 |
| Short name | T3121 |
| Test name | |
| Test status | |
| Simulation time | 478690804 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:18:06 PM UTC 25 |
| Finished | Feb 08 06:18:09 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 8186306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.usbdev_tx_rx_disruption.28186306 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/60.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/61.usbdev_endpoint_types.1984864540 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 513140506 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:18:06 PM UTC 25 |
| Finished | Feb 08 06:18:09 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984864540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 61.usbdev_endpoint_types.1984864540 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/61.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/61.usbdev_tx_rx_disruption.2092853696 |
| Short name | T3122 |
| Test name | |
| Test status | |
| Simulation time | 563947475 ps |
| CPU time | 1.83 seconds |
| Started | Feb 08 06:18:06 PM UTC 25 |
| Finished | Feb 08 06:18:09 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 092853696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.usbdev_tx_rx_disruption.2092853696 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/61.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/62.usbdev_endpoint_types.3613901908 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 184333768 ps |
| CPU time | 1.02 seconds |
| Started | Feb 08 06:18:06 PM UTC 25 |
| Finished | Feb 08 06:18:08 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613901908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 62.usbdev_endpoint_types.3613901908 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/62.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/62.usbdev_tx_rx_disruption.4220716517 |
| Short name | T3123 |
| Test name | |
| Test status | |
| Simulation time | 488111543 ps |
| CPU time | 2.02 seconds |
| Started | Feb 08 06:18:06 PM UTC 25 |
| Finished | Feb 08 06:18:09 PM UTC 25 |
| Peak memory | 217180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 220716517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.usbdev_tx_rx_disruption.4220716517 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/62.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/63.usbdev_endpoint_types.1690479722 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 262798628 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:18:07 PM UTC 25 |
| Finished | Feb 08 06:18:10 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690479722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 63.usbdev_endpoint_types.1690479722 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/63.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/63.usbdev_tx_rx_disruption.3245336008 |
| Short name | T3127 |
| Test name | |
| Test status | |
| Simulation time | 433162025 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:18:09 PM UTC 25 |
| Finished | Feb 08 06:18:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 245336008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.usbdev_tx_rx_disruption.3245336008 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/63.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/64.usbdev_endpoint_types.2089402156 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 652803792 ps |
| CPU time | 1.71 seconds |
| Started | Feb 08 06:18:09 PM UTC 25 |
| Finished | Feb 08 06:18:12 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089402156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 64.usbdev_endpoint_types.2089402156 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/64.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/64.usbdev_tx_rx_disruption.897128683 |
| Short name | T3128 |
| Test name | |
| Test status | |
| Simulation time | 474636942 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:18:09 PM UTC 25 |
| Finished | Feb 08 06:18:12 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 97128683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.usbdev_tx_rx_disruption.897128683 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/64.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/65.usbdev_tx_rx_disruption.354609508 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 468776299 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:18:09 PM UTC 25 |
| Finished | Feb 08 06:18:12 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 54609508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.usbdev_tx_rx_disruption.354609508 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/65.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/66.usbdev_endpoint_types.2456494963 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 350982093 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:18:09 PM UTC 25 |
| Finished | Feb 08 06:18:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456494963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 66.usbdev_endpoint_types.2456494963 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/66.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/66.usbdev_tx_rx_disruption.3533691984 |
| Short name | T3131 |
| Test name | |
| Test status | |
| Simulation time | 709431527 ps |
| CPU time | 1.87 seconds |
| Started | Feb 08 06:18:09 PM UTC 25 |
| Finished | Feb 08 06:18:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 533691984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.usbdev_tx_rx_disruption.3533691984 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/66.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/67.usbdev_endpoint_types.427025748 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 321767774 ps |
| CPU time | 1.78 seconds |
| Started | Feb 08 06:18:09 PM UTC 25 |
| Finished | Feb 08 06:18:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427025748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 67.usbdev_endpoint_types.427025748 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/67.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/67.usbdev_tx_rx_disruption.3291912412 |
| Short name | T3129 |
| Test name | |
| Test status | |
| Simulation time | 591771742 ps |
| CPU time | 1.77 seconds |
| Started | Feb 08 06:18:09 PM UTC 25 |
| Finished | Feb 08 06:18:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 291912412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.usbdev_tx_rx_disruption.3291912412 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/67.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/68.usbdev_tx_rx_disruption.2168681994 |
| Short name | T3130 |
| Test name | |
| Test status | |
| Simulation time | 518359027 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:18:09 PM UTC 25 |
| Finished | Feb 08 06:18:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 168681994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.usbdev_tx_rx_disruption.2168681994 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/68.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/69.usbdev_endpoint_types.3621543898 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 528397660 ps |
| CPU time | 1.81 seconds |
| Started | Feb 08 06:18:09 PM UTC 25 |
| Finished | Feb 08 06:18:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621543898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 69.usbdev_endpoint_types.3621543898 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/69.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/69.usbdev_tx_rx_disruption.4280998340 |
| Short name | T3132 |
| Test name | |
| Test status | |
| Simulation time | 554331011 ps |
| CPU time | 1.84 seconds |
| Started | Feb 08 06:18:09 PM UTC 25 |
| Finished | Feb 08 06:18:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 280998340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.usbdev_tx_rx_disruption.4280998340 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/69.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_alert_test.2459103642 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 49497076 ps |
| CPU time | 0.94 seconds |
| Started | Feb 08 06:02:12 PM UTC 25 |
| Finished | Feb 08 06:02:14 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459103642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 7.usbdev_alert_test.2459103642 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_aon_wake_disconnect.101978038 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 5389028740 ps |
| CPU time | 10.7 seconds |
| Started | Feb 08 06:01:39 PM UTC 25 |
| Finished | Feb 08 06:01:51 PM UTC 25 |
| Peak memory | 227844 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101978038 -assert nopostproc +UVM_TEST NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.101978038 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_aon_wake_reset.1738177287 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 13795182036 ps |
| CPU time | 21.7 seconds |
| Started | Feb 08 06:01:39 PM UTC 25 |
| Finished | Feb 08 06:02:02 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738177287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.1738177287 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_aon_wake_resume.3533327064 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 23539133712 ps |
| CPU time | 62.24 seconds |
| Started | Feb 08 06:01:39 PM UTC 25 |
| Finished | Feb 08 06:02:43 PM UTC 25 |
| Peak memory | 227776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533327064 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.3533327064 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_av_buffer.2342056282 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 168375384 ps |
| CPU time | 1.54 seconds |
| Started | Feb 08 06:01:40 PM UTC 25 |
| Finished | Feb 08 06:01:43 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2342056282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev _av_buffer.2342056282 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_bitstuff_err.528270604 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 142771158 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 06:01:42 PM UTC 25 |
| Finished | Feb 08 06:01:44 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=528270604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbd ev_bitstuff_err.528270604 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_data_toggle_clear.1655603000 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 387068521 ps |
| CPU time | 2.36 seconds |
| Started | Feb 08 06:01:42 PM UTC 25 |
| Finished | Feb 08 06:01:46 PM UTC 25 |
| Peak memory | 217176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1655603000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.1655603000 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_data_toggle_restore.3079828093 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 361563584 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 06:01:42 PM UTC 25 |
| Finished | Feb 08 06:01:45 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079828093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.3079828093 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_device_address.538656484 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 22318756879 ps |
| CPU time | 56.45 seconds |
| Started | Feb 08 06:01:42 PM UTC 25 |
| Finished | Feb 08 06:02:40 PM UTC 25 |
| Peak memory | 217604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=538656484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.us bdev_device_address.538656484 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_device_timeout.2120991791 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 1064456268 ps |
| CPU time | 10.63 seconds |
| Started | Feb 08 06:01:43 PM UTC 25 |
| Finished | Feb 08 06:01:55 PM UTC 25 |
| Peak memory | 217460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120991791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.2120991791 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_disable_endpoint.1332399458 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 640423844 ps |
| CPU time | 2.26 seconds |
| Started | Feb 08 06:01:45 PM UTC 25 |
| Finished | Feb 08 06:01:49 PM UTC 25 |
| Peak memory | 217024 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1332399458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7 .usbdev_disable_endpoint.1332399458 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_enable.351817027 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 33139118 ps |
| CPU time | 0.93 seconds |
| Started | Feb 08 06:01:45 PM UTC 25 |
| Finished | Feb 08 06:01:47 PM UTC 25 |
| Peak memory | 214356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=351817027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ena ble.351817027 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_endpoint_access.505959335 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 760045335 ps |
| CPU time | 2.93 seconds |
| Started | Feb 08 06:01:45 PM UTC 25 |
| Finished | Feb 08 06:01:50 PM UTC 25 |
| Peak memory | 217276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=505959335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.u sbdev_endpoint_access.505959335 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_endpoint_types.1934581299 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 407823681 ps |
| CPU time | 2.01 seconds |
| Started | Feb 08 06:01:46 PM UTC 25 |
| Finished | Feb 08 06:01:49 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934581299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 7.usbdev_endpoint_types.1934581299 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_fifo_rst.3659266731 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 192710646 ps |
| CPU time | 2.83 seconds |
| Started | Feb 08 06:01:46 PM UTC 25 |
| Finished | Feb 08 06:01:50 PM UTC 25 |
| Peak memory | 217272 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3659266731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ fifo_rst.3659266731 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_in_iso.621890963 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 221356108 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 06:01:47 PM UTC 25 |
| Finished | Feb 08 06:01:50 PM UTC 25 |
| Peak memory | 227732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621890963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 7.usbdev_in_iso.621890963 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_in_stall.3032659852 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 150449066 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 06:01:48 PM UTC 25 |
| Finished | Feb 08 06:01:50 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3032659852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ in_stall.3032659852 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_in_trans.3828642709 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 273376231 ps |
| CPU time | 1.78 seconds |
| Started | Feb 08 06:01:49 PM UTC 25 |
| Finished | Feb 08 06:01:52 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3828642709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ in_trans.3828642709 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_invalid_sync.1407544655 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 5630713430 ps |
| CPU time | 59.93 seconds |
| Started | Feb 08 06:01:47 PM UTC 25 |
| Finished | Feb 08 06:02:48 PM UTC 25 |
| Peak memory | 234292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407544655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.1407544655 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_iso_retraction.1814641066 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 3812596107 ps |
| CPU time | 56.04 seconds |
| Started | Feb 08 06:01:49 PM UTC 25 |
| Finished | Feb 08 06:02:47 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814641066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 7.usbdev_iso_retraction.1814641066 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_link_in_err.1859397900 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 229677889 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:01:51 PM UTC 25 |
| Finished | Feb 08 06:01:53 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1859397900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbd ev_link_in_err.1859397900 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_link_resume.2357919129 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 28563513154 ps |
| CPU time | 65.83 seconds |
| Started | Feb 08 06:01:51 PM UTC 25 |
| Finished | Feb 08 06:02:58 PM UTC 25 |
| Peak memory | 227592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2357919129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbd ev_link_resume.2357919129 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_link_suspend.1575822751 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 5634565707 ps |
| CPU time | 19.69 seconds |
| Started | Feb 08 06:01:51 PM UTC 25 |
| Finished | Feb 08 06:02:12 PM UTC 25 |
| Peak memory | 227852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1575822751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usb dev_link_suspend.1575822751 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_low_speed_traffic.3632335821 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 4951518927 ps |
| CPU time | 40.12 seconds |
| Started | Feb 08 06:01:51 PM UTC 25 |
| Finished | Feb 08 06:02:32 PM UTC 25 |
| Peak memory | 227700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632335821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 7.usbdev_low_speed_traffic.3632335821 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_max_inter_pkt_delay.3933576842 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 2052908942 ps |
| CPU time | 15.54 seconds |
| Started | Feb 08 06:01:52 PM UTC 25 |
| Finished | Feb 08 06:02:09 PM UTC 25 |
| Peak memory | 234300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933576842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.3933576842 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_max_length_in_transaction.1920470116 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 248782423 ps |
| CPU time | 1.69 seconds |
| Started | Feb 08 06:01:52 PM UTC 25 |
| Finished | Feb 08 06:01:55 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920470116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 7.usbdev_max_length_in_transaction.1920470116 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_max_length_out_transaction.1662109124 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 192658155 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:01:52 PM UTC 25 |
| Finished | Feb 08 06:01:55 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1662109124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.1662109124 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_max_non_iso_usb_traffic.285987260 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 2112825853 ps |
| CPU time | 24.77 seconds |
| Started | Feb 08 06:01:52 PM UTC 25 |
| Finished | Feb 08 06:02:19 PM UTC 25 |
| Peak memory | 229824 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=285987260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 7.usbdev_max_non_iso_usb_traffic.285987260 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_max_usb_traffic.1764967450 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 3909179316 ps |
| CPU time | 31.67 seconds |
| Started | Feb 08 06:01:53 PM UTC 25 |
| Finished | Feb 08 06:02:26 PM UTC 25 |
| Peak memory | 229900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764967450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_ traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 7.usbdev_max_usb_traffic.1764967450 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_min_inter_pkt_delay.1979533232 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 2726232039 ps |
| CPU time | 30.81 seconds |
| Started | Feb 08 06:01:54 PM UTC 25 |
| Finished | Feb 08 06:02:26 PM UTC 25 |
| Peak memory | 229816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979533232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.1979533232 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_min_length_in_transaction.1043472013 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 229173533 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:01:54 PM UTC 25 |
| Finished | Feb 08 06:01:57 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043472013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.usbdev_min_length_in_transaction.1043472013 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_min_length_out_transaction.873347560 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 140563661 ps |
| CPU time | 1.19 seconds |
| Started | Feb 08 06:01:54 PM UTC 25 |
| Finished | Feb 08 06:01:56 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=873347560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 7.usbdev_min_length_out_transaction.873347560 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_nak_trans.620511340 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 192278537 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:01:56 PM UTC 25 |
| Finished | Feb 08 06:01:59 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=620511340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ nak_trans.620511340 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_out_iso.2276621887 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 186293048 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:01:56 PM UTC 25 |
| Finished | Feb 08 06:01:59 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2276621887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_o ut_iso.2276621887 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_out_stall.3976757022 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 166801146 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:01:56 PM UTC 25 |
| Finished | Feb 08 06:01:59 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3976757022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev _out_stall.3976757022 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_out_trans_nak.3183328538 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 224076541 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:01:58 PM UTC 25 |
| Finished | Feb 08 06:02:00 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3183328538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.us bdev_out_trans_nak.3183328538 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_pending_in_trans.520312855 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 151650203 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:01:58 PM UTC 25 |
| Finished | Feb 08 06:02:00 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=520312855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7. usbdev_pending_in_trans.520312855 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_phy_config_pinflip.251765189 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 182782608 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:01:59 PM UTC 25 |
| Finished | Feb 08 06:02:02 PM UTC 25 |
| Peak memory | 215092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=251765189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.usbdev_phy_config_pinflip.251765189 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_phy_config_usb_ref_disable.1871450785 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 146184228 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:01:59 PM UTC 25 |
| Finished | Feb 08 06:02:02 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1871450785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.1871450785 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_phy_pins_sense.1706010419 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 47904818 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:01:59 PM UTC 25 |
| Finished | Feb 08 06:02:02 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1706010419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.u sbdev_phy_pins_sense.1706010419 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_pkt_buffer.1594293468 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 9590039552 ps |
| CPU time | 35.84 seconds |
| Started | Feb 08 06:02:01 PM UTC 25 |
| Finished | Feb 08 06:02:38 PM UTC 25 |
| Peak memory | 227616 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1594293468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbde v_pkt_buffer.1594293468 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_pkt_received.773726132 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 177889877 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:02:01 PM UTC 25 |
| Finished | Feb 08 06:02:03 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=773726132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbd ev_pkt_received.773726132 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_pkt_sent.1939696728 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 187258921 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:02:02 PM UTC 25 |
| Finished | Feb 08 06:02:04 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1939696728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ pkt_sent.1939696728 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_rand_bus_disconnects.3730699367 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 5625912146 ps |
| CPU time | 25.92 seconds |
| Started | Feb 08 06:02:03 PM UTC 25 |
| Finished | Feb 08 06:02:30 PM UTC 25 |
| Peak memory | 234428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730699367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_ TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.3730699367 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_rand_bus_disconnects/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_rand_bus_resets.1961387424 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 3422103386 ps |
| CPU time | 30.91 seconds |
| Started | Feb 08 06:02:03 PM UTC 25 |
| Finished | Feb 08 06:02:35 PM UTC 25 |
| Peak memory | 229760 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961387424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 7.usbdev_rand_bus_resets.1961387424 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_rand_bus_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_rand_suspends.1254686612 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 9426575636 ps |
| CPU time | 57.54 seconds |
| Started | Feb 08 06:02:04 PM UTC 25 |
| Finished | Feb 08 06:03:03 PM UTC 25 |
| Peak memory | 234572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254686612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_ TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.1254686612 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_rand_suspends/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_random_length_in_transaction.1654324305 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 189440373 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:02:03 PM UTC 25 |
| Finished | Feb 08 06:02:06 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1654324305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.us bdev_random_length_in_transaction.1654324305 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_random_length_out_transaction.2016030869 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 161221637 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 06:02:03 PM UTC 25 |
| Finished | Feb 08 06:02:06 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2016030869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.usbdev_random_length_out_transaction.2016030869 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_resume_link_active.1073677891 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 20170787724 ps |
| CPU time | 33.84 seconds |
| Started | Feb 08 06:02:06 PM UTC 25 |
| Finished | Feb 08 06:02:41 PM UTC 25 |
| Peak memory | 217212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1073677891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_resume_link_active.1073677891 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_resume_link_active/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_rx_crc_err.378651539 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 151578500 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 06:02:06 PM UTC 25 |
| Finished | Feb 08 06:02:08 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=378651539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev _rx_crc_err.378651539 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_rx_full.1555258773 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 425305347 ps |
| CPU time | 2.42 seconds |
| Started | Feb 08 06:02:07 PM UTC 25 |
| Finished | Feb 08 06:02:10 PM UTC 25 |
| Peak memory | 217172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1555258773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_r x_full.1555258773 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_setup_stage.3865407222 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 149763202 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 06:02:07 PM UTC 25 |
| Finished | Feb 08 06:02:09 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3865407222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbd ev_setup_stage.3865407222 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_setup_trans_ignored.2041226551 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 153394802 ps |
| CPU time | 1.33 seconds |
| Started | Feb 08 06:02:07 PM UTC 25 |
| Finished | Feb 08 06:02:09 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2041226551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.usbdev_setup_trans_ignored.2041226551 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_smoke.2694748999 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 228012001 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 06:02:08 PM UTC 25 |
| Finished | Feb 08 06:02:11 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2694748999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smo ke.2694748999 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_spurious_pids_ignored.1672010535 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 2559607693 ps |
| CPU time | 18.59 seconds |
| Started | Feb 08 06:02:08 PM UTC 25 |
| Finished | Feb 08 06:02:28 PM UTC 25 |
| Peak memory | 234560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672010535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 7.usbdev_spurious_pids_ignored.1672010535 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_stall_priority_over_nak.1038264961 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 234549776 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:02:08 PM UTC 25 |
| Finished | Feb 08 06:02:11 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1038264961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 7.usbdev_stall_priority_over_nak.1038264961 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_stall_trans.3973011868 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 155493017 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:02:10 PM UTC 25 |
| Finished | Feb 08 06:02:12 PM UTC 25 |
| Peak memory | 215048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3973011868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbd ev_stall_trans.3973011868 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_stream_len_max.3392787007 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 313900614 ps |
| CPU time | 1.97 seconds |
| Started | Feb 08 06:02:10 PM UTC 25 |
| Finished | Feb 08 06:02:13 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3392787007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.u sbdev_stream_len_max.3392787007 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_streaming_out.1553502527 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 2314744229 ps |
| CPU time | 65.84 seconds |
| Started | Feb 08 06:02:10 PM UTC 25 |
| Finished | Feb 08 06:03:17 PM UTC 25 |
| Peak memory | 227636 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1553502527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev _streaming_out.1553502527 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_timeout_missing_host_handshake.1249198759 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 7693251481 ps |
| CPU time | 47.9 seconds |
| Started | Feb 08 06:01:43 PM UTC 25 |
| Finished | Feb 08 06:02:33 PM UTC 25 |
| Peak memory | 217360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249198759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_host_handshake.1249198759 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/7.usbdev_tx_rx_disruption.1181038398 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 597236917 ps |
| CPU time | 2.72 seconds |
| Started | Feb 08 06:02:12 PM UTC 25 |
| Finished | Feb 08 06:02:15 PM UTC 25 |
| Peak memory | 217116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 181038398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_tx_rx_disruption.1181038398 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/7.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/70.usbdev_endpoint_types.2014398534 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 558379085 ps |
| CPU time | 2.03 seconds |
| Started | Feb 08 06:18:09 PM UTC 25 |
| Finished | Feb 08 06:18:13 PM UTC 25 |
| Peak memory | 217276 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014398534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 70.usbdev_endpoint_types.2014398534 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/70.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/70.usbdev_tx_rx_disruption.972855774 |
| Short name | T3139 |
| Test name | |
| Test status | |
| Simulation time | 658306201 ps |
| CPU time | 2.09 seconds |
| Started | Feb 08 06:18:12 PM UTC 25 |
| Finished | Feb 08 06:18:15 PM UTC 25 |
| Peak memory | 216788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 72855774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.usbdev_tx_rx_disruption.972855774 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/70.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/71.usbdev_endpoint_types.957861759 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 523358657 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 06:18:12 PM UTC 25 |
| Finished | Feb 08 06:18:15 PM UTC 25 |
| Peak memory | 214752 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957861759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 71.usbdev_endpoint_types.957861759 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/71.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/71.usbdev_tx_rx_disruption.1221425293 |
| Short name | T3136 |
| Test name | |
| Test status | |
| Simulation time | 470601990 ps |
| CPU time | 1.67 seconds |
| Started | Feb 08 06:18:12 PM UTC 25 |
| Finished | Feb 08 06:18:15 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 221425293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.usbdev_tx_rx_disruption.1221425293 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/71.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/72.usbdev_endpoint_types.2845109177 |
| Short name | T3135 |
| Test name | |
| Test status | |
| Simulation time | 258162642 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 06:18:12 PM UTC 25 |
| Finished | Feb 08 06:18:14 PM UTC 25 |
| Peak memory | 215088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845109177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 72.usbdev_endpoint_types.2845109177 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/72.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/72.usbdev_tx_rx_disruption.258735181 |
| Short name | T3137 |
| Test name | |
| Test status | |
| Simulation time | 492957684 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 06:18:12 PM UTC 25 |
| Finished | Feb 08 06:18:15 PM UTC 25 |
| Peak memory | 216604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 58735181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.usbdev_tx_rx_disruption.258735181 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/72.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/73.usbdev_endpoint_types.3931011645 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 257234252 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:18:12 PM UTC 25 |
| Finished | Feb 08 06:18:15 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931011645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 73.usbdev_endpoint_types.3931011645 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/73.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/73.usbdev_tx_rx_disruption.1581420351 |
| Short name | T3140 |
| Test name | |
| Test status | |
| Simulation time | 636789182 ps |
| CPU time | 1.95 seconds |
| Started | Feb 08 06:18:12 PM UTC 25 |
| Finished | Feb 08 06:18:15 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 581420351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.usbdev_tx_rx_disruption.1581420351 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/73.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/74.usbdev_endpoint_types.3609905549 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 409517883 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:18:12 PM UTC 25 |
| Finished | Feb 08 06:18:15 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609905549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 74.usbdev_endpoint_types.3609905549 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/74.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/74.usbdev_tx_rx_disruption.1893070933 |
| Short name | T3138 |
| Test name | |
| Test status | |
| Simulation time | 447333084 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:18:12 PM UTC 25 |
| Finished | Feb 08 06:18:15 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 893070933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.usbdev_tx_rx_disruption.1893070933 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/74.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/75.usbdev_endpoint_types.2619384863 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 424369133 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 06:18:12 PM UTC 25 |
| Finished | Feb 08 06:18:15 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619384863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 75.usbdev_endpoint_types.2619384863 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/75.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/75.usbdev_tx_rx_disruption.3529517714 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 436297563 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 06:18:12 PM UTC 25 |
| Finished | Feb 08 06:18:15 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 529517714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.usbdev_tx_rx_disruption.3529517714 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/75.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/76.usbdev_endpoint_types.3148471859 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 190522948 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 06:18:14 PM UTC 25 |
| Finished | Feb 08 06:18:16 PM UTC 25 |
| Peak memory | 214924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148471859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 76.usbdev_endpoint_types.3148471859 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/76.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/76.usbdev_tx_rx_disruption.482757152 |
| Short name | T3146 |
| Test name | |
| Test status | |
| Simulation time | 463074372 ps |
| CPU time | 1.98 seconds |
| Started | Feb 08 06:18:14 PM UTC 25 |
| Finished | Feb 08 06:18:17 PM UTC 25 |
| Peak memory | 214900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 82757152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.usbdev_tx_rx_disruption.482757152 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/76.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/77.usbdev_endpoint_types.1083532162 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 479346234 ps |
| CPU time | 1.72 seconds |
| Started | Feb 08 06:18:14 PM UTC 25 |
| Finished | Feb 08 06:18:17 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083532162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 77.usbdev_endpoint_types.1083532162 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/77.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/77.usbdev_tx_rx_disruption.2897235518 |
| Short name | T3144 |
| Test name | |
| Test status | |
| Simulation time | 502787115 ps |
| CPU time | 1.76 seconds |
| Started | Feb 08 06:18:14 PM UTC 25 |
| Finished | Feb 08 06:18:17 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 897235518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.usbdev_tx_rx_disruption.2897235518 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/77.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/78.usbdev_endpoint_types.3275757563 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 363678373 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:18:14 PM UTC 25 |
| Finished | Feb 08 06:18:17 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275757563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 78.usbdev_endpoint_types.3275757563 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/78.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/78.usbdev_tx_rx_disruption.2730782186 |
| Short name | T3145 |
| Test name | |
| Test status | |
| Simulation time | 463194953 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:18:14 PM UTC 25 |
| Finished | Feb 08 06:18:17 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 730782186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.usbdev_tx_rx_disruption.2730782186 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/78.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/79.usbdev_endpoint_types.1112653191 |
| Short name | T3141 |
| Test name | |
| Test status | |
| Simulation time | 195207626 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:18:14 PM UTC 25 |
| Finished | Feb 08 06:18:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112653191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 79.usbdev_endpoint_types.1112653191 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/79.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/79.usbdev_tx_rx_disruption.3208813070 |
| Short name | T3143 |
| Test name | |
| Test status | |
| Simulation time | 427432695 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:18:14 PM UTC 25 |
| Finished | Feb 08 06:18:17 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 208813070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.usbdev_tx_rx_disruption.3208813070 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/79.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_alert_test.3295344549 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 49657034 ps |
| CPU time | 0.96 seconds |
| Started | Feb 08 06:02:46 PM UTC 25 |
| Finished | Feb 08 06:02:48 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295344549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 8.usbdev_alert_test.3295344549 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_aon_wake_disconnect.1795892266 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 9137359532 ps |
| CPU time | 19.03 seconds |
| Started | Feb 08 06:02:12 PM UTC 25 |
| Finished | Feb 08 06:02:32 PM UTC 25 |
| Peak memory | 217516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795892266 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.1795892266 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_aon_wake_reset.2214056564 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 15150733869 ps |
| CPU time | 27.72 seconds |
| Started | Feb 08 06:02:12 PM UTC 25 |
| Finished | Feb 08 06:02:41 PM UTC 25 |
| Peak memory | 227784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214056564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.2214056564 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_aon_wake_resume.3271724132 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 23891090454 ps |
| CPU time | 36.61 seconds |
| Started | Feb 08 06:02:14 PM UTC 25 |
| Finished | Feb 08 06:02:52 PM UTC 25 |
| Peak memory | 227712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271724132 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.3271724132 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_av_buffer.2103510453 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 164359148 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:02:14 PM UTC 25 |
| Finished | Feb 08 06:02:16 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2103510453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev _av_buffer.2103510453 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_bitstuff_err.1134627340 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 143978752 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:02:14 PM UTC 25 |
| Finished | Feb 08 06:02:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1134627340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usb dev_bitstuff_err.1134627340 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_data_toggle_clear.1996260453 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 473459797 ps |
| CPU time | 2.51 seconds |
| Started | Feb 08 06:02:14 PM UTC 25 |
| Finished | Feb 08 06:02:17 PM UTC 25 |
| Peak memory | 217112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1996260453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.1996260453 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_data_toggle_restore.1969556966 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 1177337803 ps |
| CPU time | 5.65 seconds |
| Started | Feb 08 06:02:14 PM UTC 25 |
| Finished | Feb 08 06:02:21 PM UTC 25 |
| Peak memory | 217576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969556966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.1969556966 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_device_address.3723990513 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 15470283175 ps |
| CPU time | 32.64 seconds |
| Started | Feb 08 06:02:14 PM UTC 25 |
| Finished | Feb 08 06:02:48 PM UTC 25 |
| Peak memory | 217496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3723990513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.u sbdev_device_address.3723990513 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_device_timeout.4214822479 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 1412331261 ps |
| CPU time | 35.81 seconds |
| Started | Feb 08 06:02:15 PM UTC 25 |
| Finished | Feb 08 06:02:52 PM UTC 25 |
| Peak memory | 217280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214822479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.4214822479 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_disable_endpoint.846688336 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 741716511 ps |
| CPU time | 3 seconds |
| Started | Feb 08 06:02:16 PM UTC 25 |
| Finished | Feb 08 06:02:20 PM UTC 25 |
| Peak memory | 217084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=846688336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8. usbdev_disable_endpoint.846688336 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_disconnected.3135879235 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 206639846 ps |
| CPU time | 1.57 seconds |
| Started | Feb 08 06:02:17 PM UTC 25 |
| Finished | Feb 08 06:02:20 PM UTC 25 |
| Peak memory | 215016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3135879235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usb dev_disconnected.3135879235 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_enable.833425429 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 37152648 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:02:17 PM UTC 25 |
| Finished | Feb 08 06:02:20 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=833425429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ena ble.833425429 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_endpoint_access.481429310 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 1087978913 ps |
| CPU time | 4.61 seconds |
| Started | Feb 08 06:02:19 PM UTC 25 |
| Finished | Feb 08 06:02:24 PM UTC 25 |
| Peak memory | 217384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=481429310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.u sbdev_endpoint_access.481429310 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_endpoint_types.572888155 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 371443026 ps |
| CPU time | 2.42 seconds |
| Started | Feb 08 06:02:20 PM UTC 25 |
| Finished | Feb 08 06:02:23 PM UTC 25 |
| Peak memory | 217080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572888155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 8.usbdev_endpoint_types.572888155 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_fifo_rst.2401671744 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 245430885 ps |
| CPU time | 2.7 seconds |
| Started | Feb 08 06:02:21 PM UTC 25 |
| Finished | Feb 08 06:02:25 PM UTC 25 |
| Peak memory | 217536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2401671744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ fifo_rst.2401671744 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_in_iso.2453309063 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 235937410 ps |
| CPU time | 2.09 seconds |
| Started | Feb 08 06:02:21 PM UTC 25 |
| Finished | Feb 08 06:02:24 PM UTC 25 |
| Peak memory | 227620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453309063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 8.usbdev_in_iso.2453309063 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_in_stall.1240975838 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 158834867 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:02:22 PM UTC 25 |
| Finished | Feb 08 06:02:25 PM UTC 25 |
| Peak memory | 214928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1240975838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ in_stall.1240975838 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_in_trans.621499961 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 239553857 ps |
| CPU time | 1.51 seconds |
| Started | Feb 08 06:02:22 PM UTC 25 |
| Finished | Feb 08 06:02:25 PM UTC 25 |
| Peak memory | 214900 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=621499961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_i n_trans.621499961 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_invalid_sync.10724150 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 2297259828 ps |
| CPU time | 67.24 seconds |
| Started | Feb 08 06:02:21 PM UTC 25 |
| Finished | Feb 08 06:03:30 PM UTC 25 |
| Peak memory | 229708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10724150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 8.usbdev_invalid_sync.10724150 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_iso_retraction.3439306726 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 5405274034 ps |
| CPU time | 63.86 seconds |
| Started | Feb 08 06:02:23 PM UTC 25 |
| Finished | Feb 08 06:03:29 PM UTC 25 |
| Peak memory | 217416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439306726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 8.usbdev_iso_retraction.3439306726 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_link_in_err.2948307711 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 173779364 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:02:25 PM UTC 25 |
| Finished | Feb 08 06:02:27 PM UTC 25 |
| Peak memory | 215024 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2948307711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbd ev_link_in_err.2948307711 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_link_resume.1567976796 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 12988116414 ps |
| CPU time | 26.78 seconds |
| Started | Feb 08 06:02:25 PM UTC 25 |
| Finished | Feb 08 06:02:53 PM UTC 25 |
| Peak memory | 217392 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1567976796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbd ev_link_resume.1567976796 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_link_suspend.1574912949 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 3270797080 ps |
| CPU time | 11.18 seconds |
| Started | Feb 08 06:02:26 PM UTC 25 |
| Finished | Feb 08 06:02:38 PM UTC 25 |
| Peak memory | 227596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1574912949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usb dev_link_suspend.1574912949 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_low_speed_traffic.2391551971 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 3356462476 ps |
| CPU time | 85.83 seconds |
| Started | Feb 08 06:02:26 PM UTC 25 |
| Finished | Feb 08 06:03:54 PM UTC 25 |
| Peak memory | 234228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391551971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 8.usbdev_low_speed_traffic.2391551971 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_max_inter_pkt_delay.718370548 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 2396273195 ps |
| CPU time | 80.83 seconds |
| Started | Feb 08 06:02:26 PM UTC 25 |
| Finished | Feb 08 06:03:49 PM UTC 25 |
| Peak memory | 227720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718370548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.718370548 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_max_length_in_transaction.1819776811 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 234072950 ps |
| CPU time | 1.64 seconds |
| Started | Feb 08 06:02:26 PM UTC 25 |
| Finished | Feb 08 06:02:29 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819776811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 8.usbdev_max_length_in_transaction.1819776811 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_max_length_out_transaction.165723866 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 213593877 ps |
| CPU time | 1.31 seconds |
| Started | Feb 08 06:02:28 PM UTC 25 |
| Finished | Feb 08 06:02:30 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=165723866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 8.usbdev_max_length_out_transaction.165723866 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_max_non_iso_usb_traffic.2785695042 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 1685981660 ps |
| CPU time | 49.86 seconds |
| Started | Feb 08 06:02:28 PM UTC 25 |
| Finished | Feb 08 06:03:19 PM UTC 25 |
| Peak memory | 234428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2785695042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 8.usbdev_max_non_iso_usb_traffic.2785695042 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_max_usb_traffic.3764877839 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 3394531883 ps |
| CPU time | 36.78 seconds |
| Started | Feb 08 06:02:28 PM UTC 25 |
| Finished | Feb 08 06:03:06 PM UTC 25 |
| Peak memory | 234428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764877839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_ traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 8.usbdev_max_usb_traffic.3764877839 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_min_inter_pkt_delay.3580842369 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 3633117731 ps |
| CPU time | 30.67 seconds |
| Started | Feb 08 06:02:29 PM UTC 25 |
| Finished | Feb 08 06:03:01 PM UTC 25 |
| Peak memory | 229948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580842369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.3580842369 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_min_length_in_transaction.259232075 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 167863441 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:02:30 PM UTC 25 |
| Finished | Feb 08 06:02:32 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259232075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 8.usbdev_min_length_in_transaction.259232075 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_min_length_out_transaction.3369238988 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 159499819 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 06:02:31 PM UTC 25 |
| Finished | Feb 08 06:02:34 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3369238988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3369238988 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_nak_trans.993149247 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 228777826 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:02:31 PM UTC 25 |
| Finished | Feb 08 06:02:34 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=993149247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ nak_trans.993149247 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_out_iso.626358341 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 200717482 ps |
| CPU time | 1.6 seconds |
| Started | Feb 08 06:02:34 PM UTC 25 |
| Finished | Feb 08 06:02:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=626358341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ou t_iso.626358341 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_out_stall.905166483 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 150482432 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 06:02:34 PM UTC 25 |
| Finished | Feb 08 06:02:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=905166483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ out_stall.905166483 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_out_trans_nak.2111321649 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 158701026 ps |
| CPU time | 1.21 seconds |
| Started | Feb 08 06:02:34 PM UTC 25 |
| Finished | Feb 08 06:02:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2111321649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.us bdev_out_trans_nak.2111321649 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_pending_in_trans.359245830 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 159504120 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:02:34 PM UTC 25 |
| Finished | Feb 08 06:02:36 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=359245830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8. usbdev_pending_in_trans.359245830 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_phy_config_pinflip.1394431280 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 222151814 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:02:34 PM UTC 25 |
| Finished | Feb 08 06:02:37 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394431280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 8.usbdev_phy_config_pinflip.1394431280 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_phy_config_usb_ref_disable.71529693 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 162970527 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:02:35 PM UTC 25 |
| Finished | Feb 08 06:02:38 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=71529693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 8.usbdev_phy_config_usb_ref_disable.71529693 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_phy_pins_sense.344913813 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 112997675 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:02:35 PM UTC 25 |
| Finished | Feb 08 06:02:37 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=344913813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.us bdev_phy_pins_sense.344913813 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_pkt_buffer.1657730823 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 13989506889 ps |
| CPU time | 52.53 seconds |
| Started | Feb 08 06:02:36 PM UTC 25 |
| Finished | Feb 08 06:03:31 PM UTC 25 |
| Peak memory | 234472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1657730823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbde v_pkt_buffer.1657730823 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_pkt_received.1585405817 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 192887292 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:02:36 PM UTC 25 |
| Finished | Feb 08 06:02:39 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1585405817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usb dev_pkt_received.1585405817 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_pkt_sent.4061907791 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 232634331 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:02:38 PM UTC 25 |
| Finished | Feb 08 06:02:40 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4061907791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ pkt_sent.4061907791 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_rand_bus_disconnects.690048166 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 14149433974 ps |
| CPU time | 290.91 seconds |
| Started | Feb 08 06:02:38 PM UTC 25 |
| Finished | Feb 08 06:07:33 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690048166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_T EST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.690048166 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_rand_bus_disconnects/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_rand_bus_resets.198792622 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 6416163528 ps |
| CPU time | 32.65 seconds |
| Started | Feb 08 06:02:39 PM UTC 25 |
| Finished | Feb 08 06:03:13 PM UTC 25 |
| Peak memory | 227896 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198792622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 8.usbdev_rand_bus_resets.198792622 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_rand_bus_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_rand_suspends.2636689092 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 9391262375 ps |
| CPU time | 48.36 seconds |
| Started | Feb 08 06:02:39 PM UTC 25 |
| Finished | Feb 08 06:03:29 PM UTC 25 |
| Peak memory | 229588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636689092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_ TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.2636689092 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_rand_suspends/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_random_length_in_transaction.463738198 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 182745763 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:02:38 PM UTC 25 |
| Finished | Feb 08 06:02:40 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=463738198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usb dev_random_length_in_transaction.463738198 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_random_length_out_transaction.34964636 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 156383797 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:02:38 PM UTC 25 |
| Finished | Feb 08 06:02:40 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=34964636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.34964636 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_resume_link_active.3506162443 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 20224112089 ps |
| CPU time | 30.36 seconds |
| Started | Feb 08 06:02:39 PM UTC 25 |
| Finished | Feb 08 06:03:11 PM UTC 25 |
| Peak memory | 217148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3506162443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_resume_link_active.3506162443 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_resume_link_active/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_rx_crc_err.898677148 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 178550789 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:02:39 PM UTC 25 |
| Finished | Feb 08 06:02:42 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=898677148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev _rx_crc_err.898677148 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_rx_full.2009879657 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 321570637 ps |
| CPU time | 2.08 seconds |
| Started | Feb 08 06:02:39 PM UTC 25 |
| Finished | Feb 08 06:02:43 PM UTC 25 |
| Peak memory | 217172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2009879657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_r x_full.2009879657 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_setup_stage.829282648 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 154105126 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:02:42 PM UTC 25 |
| Finished | Feb 08 06:02:44 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=829282648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbde v_setup_stage.829282648 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_setup_trans_ignored.4283658911 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 172651730 ps |
| CPU time | 1.2 seconds |
| Started | Feb 08 06:02:42 PM UTC 25 |
| Finished | Feb 08 06:02:44 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4283658911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 8.usbdev_setup_trans_ignored.4283658911 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_smoke.809165002 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 280922539 ps |
| CPU time | 1.47 seconds |
| Started | Feb 08 06:02:42 PM UTC 25 |
| Finished | Feb 08 06:02:45 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=809165002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smok e.809165002 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_spurious_pids_ignored.2367726871 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 2449705906 ps |
| CPU time | 24.34 seconds |
| Started | Feb 08 06:02:42 PM UTC 25 |
| Finished | Feb 08 06:03:08 PM UTC 25 |
| Peak memory | 229944 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367726871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 8.usbdev_spurious_pids_ignored.2367726871 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_stall_priority_over_nak.1095626313 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 159058072 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:02:42 PM UTC 25 |
| Finished | Feb 08 06:02:44 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1095626313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 8.usbdev_stall_priority_over_nak.1095626313 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_stall_trans.397196802 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 158096265 ps |
| CPU time | 1.4 seconds |
| Started | Feb 08 06:02:42 PM UTC 25 |
| Finished | Feb 08 06:02:45 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=397196802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbde v_stall_trans.397196802 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_stream_len_max.2744571653 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 428960611 ps |
| CPU time | 2.63 seconds |
| Started | Feb 08 06:02:43 PM UTC 25 |
| Finished | Feb 08 06:02:47 PM UTC 25 |
| Peak memory | 217152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2744571653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.u sbdev_stream_len_max.2744571653 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_streaming_out.2608316071 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 2190896315 ps |
| CPU time | 65.03 seconds |
| Started | Feb 08 06:02:43 PM UTC 25 |
| Finished | Feb 08 06:03:50 PM UTC 25 |
| Peak memory | 227600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2608316071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev _streaming_out.2608316071 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_timeout_missing_host_handshake.2257465326 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 289948337 ps |
| CPU time | 6.07 seconds |
| Started | Feb 08 06:02:15 PM UTC 25 |
| Finished | Feb 08 06:02:22 PM UTC 25 |
| Peak memory | 217404 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257465326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_host_handshake.2257465326 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_tx_rx_disruption.1169004028 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 481026729 ps |
| CPU time | 2.18 seconds |
| Started | Feb 08 06:02:45 PM UTC 25 |
| Finished | Feb 08 06:02:48 PM UTC 25 |
| Peak memory | 217180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 169004028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_tx_rx_disruption.1169004028 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/8.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/80.usbdev_endpoint_types.570872689 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 799860282 ps |
| CPU time | 2.56 seconds |
| Started | Feb 08 06:18:14 PM UTC 25 |
| Finished | Feb 08 06:18:18 PM UTC 25 |
| Peak memory | 217272 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570872689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 80.usbdev_endpoint_types.570872689 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/80.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/80.usbdev_tx_rx_disruption.3078706348 |
| Short name | T3148 |
| Test name | |
| Test status | |
| Simulation time | 581270720 ps |
| CPU time | 1.9 seconds |
| Started | Feb 08 06:18:14 PM UTC 25 |
| Finished | Feb 08 06:18:17 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 078706348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.usbdev_tx_rx_disruption.3078706348 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/80.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/81.usbdev_endpoint_types.3934758961 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 422219820 ps |
| CPU time | 1.48 seconds |
| Started | Feb 08 06:18:14 PM UTC 25 |
| Finished | Feb 08 06:18:17 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934758961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 81.usbdev_endpoint_types.3934758961 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/81.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/81.usbdev_tx_rx_disruption.3883527186 |
| Short name | T3149 |
| Test name | |
| Test status | |
| Simulation time | 495530207 ps |
| CPU time | 1.86 seconds |
| Started | Feb 08 06:18:14 PM UTC 25 |
| Finished | Feb 08 06:18:17 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 883527186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.usbdev_tx_rx_disruption.3883527186 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/81.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/82.usbdev_tx_rx_disruption.2299703635 |
| Short name | T3150 |
| Test name | |
| Test status | |
| Simulation time | 532080046 ps |
| CPU time | 1.8 seconds |
| Started | Feb 08 06:18:14 PM UTC 25 |
| Finished | Feb 08 06:18:17 PM UTC 25 |
| Peak memory | 215076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 299703635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.usbdev_tx_rx_disruption.2299703635 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/82.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/83.usbdev_endpoint_types.3160685491 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 698913461 ps |
| CPU time | 1.89 seconds |
| Started | Feb 08 06:18:14 PM UTC 25 |
| Finished | Feb 08 06:18:18 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160685491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 83.usbdev_endpoint_types.3160685491 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/83.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/83.usbdev_tx_rx_disruption.1435831419 |
| Short name | T3152 |
| Test name | |
| Test status | |
| Simulation time | 606787821 ps |
| CPU time | 2.02 seconds |
| Started | Feb 08 06:18:14 PM UTC 25 |
| Finished | Feb 08 06:18:18 PM UTC 25 |
| Peak memory | 217196 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 435831419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.usbdev_tx_rx_disruption.1435831419 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/83.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/84.usbdev_endpoint_types.1295335490 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 685334743 ps |
| CPU time | 2.12 seconds |
| Started | Feb 08 06:18:14 PM UTC 25 |
| Finished | Feb 08 06:18:18 PM UTC 25 |
| Peak memory | 217340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295335490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 84.usbdev_endpoint_types.1295335490 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/84.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/84.usbdev_tx_rx_disruption.3004621153 |
| Short name | T3161 |
| Test name | |
| Test status | |
| Simulation time | 541082249 ps |
| CPU time | 2.09 seconds |
| Started | Feb 08 06:18:16 PM UTC 25 |
| Finished | Feb 08 06:18:19 PM UTC 25 |
| Peak memory | 217116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 004621153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.usbdev_tx_rx_disruption.3004621153 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/84.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/85.usbdev_tx_rx_disruption.2614778097 |
| Short name | T3156 |
| Test name | |
| Test status | |
| Simulation time | 590697866 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:18:16 PM UTC 25 |
| Finished | Feb 08 06:18:19 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 614778097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.usbdev_tx_rx_disruption.2614778097 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/85.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/86.usbdev_endpoint_types.2747437596 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 613486062 ps |
| CPU time | 1.75 seconds |
| Started | Feb 08 06:18:16 PM UTC 25 |
| Finished | Feb 08 06:18:19 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747437596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 86.usbdev_endpoint_types.2747437596 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/86.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/86.usbdev_tx_rx_disruption.1597223902 |
| Short name | T3157 |
| Test name | |
| Test status | |
| Simulation time | 494014330 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:18:16 PM UTC 25 |
| Finished | Feb 08 06:18:19 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 597223902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.usbdev_tx_rx_disruption.1597223902 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/86.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/87.usbdev_endpoint_types.3123000325 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 480508848 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 06:18:16 PM UTC 25 |
| Finished | Feb 08 06:18:19 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123000325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 87.usbdev_endpoint_types.3123000325 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/87.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/87.usbdev_tx_rx_disruption.4044743922 |
| Short name | T3160 |
| Test name | |
| Test status | |
| Simulation time | 667390271 ps |
| CPU time | 1.74 seconds |
| Started | Feb 08 06:18:16 PM UTC 25 |
| Finished | Feb 08 06:18:19 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 044743922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.usbdev_tx_rx_disruption.4044743922 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/87.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/88.usbdev_endpoint_types.1665430250 |
| Short name | T3155 |
| Test name | |
| Test status | |
| Simulation time | 246102114 ps |
| CPU time | 1.27 seconds |
| Started | Feb 08 06:18:16 PM UTC 25 |
| Finished | Feb 08 06:18:18 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665430250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 88.usbdev_endpoint_types.1665430250 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/88.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/88.usbdev_tx_rx_disruption.4285449842 |
| Short name | T3158 |
| Test name | |
| Test status | |
| Simulation time | 572972367 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:18:16 PM UTC 25 |
| Finished | Feb 08 06:18:19 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 285449842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.usbdev_tx_rx_disruption.4285449842 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/88.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/89.usbdev_endpoint_types.2398027763 |
| Short name | T3154 |
| Test name | |
| Test status | |
| Simulation time | 267780348 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 06:18:16 PM UTC 25 |
| Finished | Feb 08 06:18:18 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398027763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 89.usbdev_endpoint_types.2398027763 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/89.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/89.usbdev_tx_rx_disruption.4181831180 |
| Short name | T3159 |
| Test name | |
| Test status | |
| Simulation time | 438149448 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:18:16 PM UTC 25 |
| Finished | Feb 08 06:18:19 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 181831180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.usbdev_tx_rx_disruption.4181831180 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/89.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_alert_test.2159344700 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 79751838 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:03:17 PM UTC 25 |
| Finished | Feb 08 06:03:20 PM UTC 25 |
| Peak memory | 215032 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159344700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 9.usbdev_alert_test.2159344700 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_aon_wake_disconnect.2683388934 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 6302620773 ps |
| CPU time | 16.8 seconds |
| Started | Feb 08 06:02:46 PM UTC 25 |
| Finished | Feb 08 06:03:04 PM UTC 25 |
| Peak memory | 227788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683388934 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.2683388934 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_aon_wake_disconnect/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_aon_wake_reset.734634013 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 14912775150 ps |
| CPU time | 42.64 seconds |
| Started | Feb 08 06:02:46 PM UTC 25 |
| Finished | Feb 08 06:03:30 PM UTC 25 |
| Peak memory | 227652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734634013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TE ST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.734634013 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_aon_wake_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_aon_wake_resume.1000257541 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 23824130941 ps |
| CPU time | 45.03 seconds |
| Started | Feb 08 06:02:46 PM UTC 25 |
| Finished | Feb 08 06:03:33 PM UTC 25 |
| Peak memory | 227584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000257541 -assert nopostproc +UVM_TES TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.1000257541 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_aon_wake_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_av_buffer.3611221594 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 161617044 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:02:47 PM UTC 25 |
| Finished | Feb 08 06:02:50 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3611221594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev _av_buffer.3611221594 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_av_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_bitstuff_err.3021696292 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 142819815 ps |
| CPU time | 1.29 seconds |
| Started | Feb 08 06:02:47 PM UTC 25 |
| Finished | Feb 08 06:02:50 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3021696292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usb dev_bitstuff_err.3021696292 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_bitstuff_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_data_toggle_clear.2749169299 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 140336291 ps |
| CPU time | 1.37 seconds |
| Started | Feb 08 06:02:49 PM UTC 25 |
| Finished | Feb 08 06:02:52 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2749169299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.2749169299 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_data_toggle_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_data_toggle_restore.1238255791 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 293088121 ps |
| CPU time | 1.81 seconds |
| Started | Feb 08 06:02:49 PM UTC 25 |
| Finished | Feb 08 06:02:52 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238255791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_ toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.1238255791 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_data_toggle_restore/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_device_address.2482375318 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 14397449441 ps |
| CPU time | 34.35 seconds |
| Started | Feb 08 06:02:49 PM UTC 25 |
| Finished | Feb 08 06:03:25 PM UTC 25 |
| Peak memory | 217496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2482375318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.u sbdev_device_address.2482375318 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_device_address/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_device_timeout.155268108 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 364289122 ps |
| CPU time | 6.35 seconds |
| Started | Feb 08 06:02:49 PM UTC 25 |
| Finished | Feb 08 06:02:57 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155268108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +U VM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.155268108 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_device_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_disable_endpoint.495559605 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 553097627 ps |
| CPU time | 2.19 seconds |
| Started | Feb 08 06:02:51 PM UTC 25 |
| Finished | Feb 08 06:02:54 PM UTC 25 |
| Peak memory | 217076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=495559605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9. usbdev_disable_endpoint.495559605 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_disable_endpoint/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_disconnected.3636468349 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 142942487 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 06:02:51 PM UTC 25 |
| Finished | Feb 08 06:02:53 PM UTC 25 |
| Peak memory | 215040 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3636468349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usb dev_disconnected.3636468349 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_disconnected/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_enable.3929375574 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 34515252 ps |
| CPU time | 1.09 seconds |
| Started | Feb 08 06:02:51 PM UTC 25 |
| Finished | Feb 08 06:02:53 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3929375574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_en able.3929375574 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_endpoint_access.1622374140 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 849513445 ps |
| CPU time | 3.31 seconds |
| Started | Feb 08 06:02:53 PM UTC 25 |
| Finished | Feb 08 06:02:57 PM UTC 25 |
| Peak memory | 217500 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1622374140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9. usbdev_endpoint_access.1622374140 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_endpoint_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_endpoint_types.1776214855 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 648544990 ps |
| CPU time | 2.68 seconds |
| Started | Feb 08 06:02:53 PM UTC 25 |
| Finished | Feb 08 06:02:57 PM UTC 25 |
| Peak memory | 217144 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776214855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 9.usbdev_endpoint_types.1776214855 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_fifo_rst.1709799274 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 296390923 ps |
| CPU time | 3.21 seconds |
| Started | Feb 08 06:02:53 PM UTC 25 |
| Finished | Feb 08 06:02:57 PM UTC 25 |
| Peak memory | 217544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1709799274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ fifo_rst.1709799274 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_fifo_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_in_iso.3896606968 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 211741398 ps |
| CPU time | 1.56 seconds |
| Started | Feb 08 06:02:55 PM UTC 25 |
| Finished | Feb 08 06:02:58 PM UTC 25 |
| Peak memory | 214848 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896606968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 9.usbdev_in_iso.3896606968 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_in_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_in_stall.50987283 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 144061996 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:02:55 PM UTC 25 |
| Finished | Feb 08 06:02:58 PM UTC 25 |
| Peak memory | 214820 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=50987283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in _stall.50987283 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_in_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_in_trans.4046942139 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 251626539 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:02:55 PM UTC 25 |
| Finished | Feb 08 06:02:58 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4046942139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ in_trans.4046942139 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_invalid_sync.53117584 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 2963155069 ps |
| CPU time | 32.39 seconds |
| Started | Feb 08 06:02:53 PM UTC 25 |
| Finished | Feb 08 06:03:27 PM UTC 25 |
| Peak memory | 229892 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53117584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 9.usbdev_invalid_sync.53117584 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_invalid_sync/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_iso_retraction.2588748572 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 9293850743 ps |
| CPU time | 79.27 seconds |
| Started | Feb 08 06:02:55 PM UTC 25 |
| Finished | Feb 08 06:04:17 PM UTC 25 |
| Peak memory | 217416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588748572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retr action_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 9.usbdev_iso_retraction.2588748572 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_iso_retraction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_link_in_err.2669680204 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 189487218 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:02:55 PM UTC 25 |
| Finished | Feb 08 06:02:58 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2669680204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbd ev_link_in_err.2669680204 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_link_in_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_link_resume.249458087 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 24198701058 ps |
| CPU time | 52.68 seconds |
| Started | Feb 08 06:02:58 PM UTC 25 |
| Finished | Feb 08 06:03:52 PM UTC 25 |
| Peak memory | 227656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=249458087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbde v_link_resume.249458087 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_link_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_link_suspend.1676114716 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 6127044193 ps |
| CPU time | 14.08 seconds |
| Started | Feb 08 06:02:58 PM UTC 25 |
| Finished | Feb 08 06:03:13 PM UTC 25 |
| Peak memory | 227788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1676114716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usb dev_link_suspend.1676114716 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_link_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_low_speed_traffic.4041182304 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 5139854304 ps |
| CPU time | 153.41 seconds |
| Started | Feb 08 06:02:59 PM UTC 25 |
| Finished | Feb 08 06:05:35 PM UTC 25 |
| Peak memory | 227544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041182304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_spee d_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 9.usbdev_low_speed_traffic.4041182304 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_low_speed_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_max_inter_pkt_delay.3140543160 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 2506828091 ps |
| CPU time | 20.07 seconds |
| Started | Feb 08 06:02:59 PM UTC 25 |
| Finished | Feb 08 06:03:21 PM UTC 25 |
| Peak memory | 229792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140543160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.3140543160 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_max_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_max_length_in_transaction.1549916993 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 256829393 ps |
| CPU time | 1.84 seconds |
| Started | Feb 08 06:02:59 PM UTC 25 |
| Finished | Feb 08 06:03:02 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549916993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 9.usbdev_max_length_in_transaction.1549916993 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_max_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_max_length_out_transaction.872633251 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 200471580 ps |
| CPU time | 1.52 seconds |
| Started | Feb 08 06:02:59 PM UTC 25 |
| Finished | Feb 08 06:03:02 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=872633251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 9.usbdev_max_length_out_transaction.872633251 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_max_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_max_non_iso_usb_traffic.1097190015 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 1921467544 ps |
| CPU time | 15.07 seconds |
| Started | Feb 08 06:02:59 PM UTC 25 |
| Finished | Feb 08 06:03:16 PM UTC 25 |
| Peak memory | 217420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1097190015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 9.usbdev_max_non_iso_usb_traffic.1097190015 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_max_non_iso_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_max_usb_traffic.2219449539 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 3145012970 ps |
| CPU time | 92.92 seconds |
| Started | Feb 08 06:02:59 PM UTC 25 |
| Finished | Feb 08 06:04:34 PM UTC 25 |
| Peak memory | 234428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219449539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_ traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 9.usbdev_max_usb_traffic.2219449539 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_max_usb_traffic/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_min_inter_pkt_delay.3464883021 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 4390355811 ps |
| CPU time | 118.49 seconds |
| Started | Feb 08 06:02:59 PM UTC 25 |
| Finished | Feb 08 06:05:00 PM UTC 25 |
| Peak memory | 227660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464883021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=us bdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.3464883021 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_min_inter_pkt_delay/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_min_length_in_transaction.3298705482 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 158386929 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:03:02 PM UTC 25 |
| Finished | Feb 08 06:03:04 PM UTC 25 |
| Peak memory | 214832 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298705482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.usbdev_min_length_in_transaction.3298705482 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_min_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_min_length_out_transaction.857147171 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 156165951 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 06:03:02 PM UTC 25 |
| Finished | Feb 08 06:03:04 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=857147171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 9.usbdev_min_length_out_transaction.857147171 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_min_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_nak_trans.2153117384 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 248832488 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 06:03:02 PM UTC 25 |
| Finished | Feb 08 06:03:05 PM UTC 25 |
| Peak memory | 214980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2153117384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev _nak_trans.2153117384 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_nak_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_out_iso.1395374970 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 186637171 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:03:03 PM UTC 25 |
| Finished | Feb 08 06:03:06 PM UTC 25 |
| Peak memory | 215096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1395374970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_o ut_iso.1395374970 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_out_iso/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_out_stall.3663915013 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 183845310 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:03:03 PM UTC 25 |
| Finished | Feb 08 06:03:06 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3663915013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev _out_stall.3663915013 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_out_stall/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_out_trans_nak.2660255721 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 192043157 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 06:03:04 PM UTC 25 |
| Finished | Feb 08 06:03:07 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2660255721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.us bdev_out_trans_nak.2660255721 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_out_trans_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_pending_in_trans.3037376832 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 155401751 ps |
| CPU time | 1.25 seconds |
| Started | Feb 08 06:03:06 PM UTC 25 |
| Finished | Feb 08 06:03:08 PM UTC 25 |
| Peak memory | 215108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3037376832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9 .usbdev_pending_in_trans.3037376832 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_pending_in_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_phy_config_pinflip.469012667 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 182186819 ps |
| CPU time | 1.41 seconds |
| Started | Feb 08 06:03:06 PM UTC 25 |
| Finished | Feb 08 06:03:08 PM UTC 25 |
| Peak memory | 215068 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=469012667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.usbdev_phy_config_pinflip.469012667 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_phy_config_pinflip/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_phy_config_usb_ref_disable.2613157543 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 186720823 ps |
| CPU time | 1.49 seconds |
| Started | Feb 08 06:03:06 PM UTC 25 |
| Finished | Feb 08 06:03:08 PM UTC 25 |
| Peak memory | 215064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2613157543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.2613157543 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_phy_config_usb_ref_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_phy_pins_sense.2015080801 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 36725721 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 06:03:06 PM UTC 25 |
| Finished | Feb 08 06:03:08 PM UTC 25 |
| Peak memory | 215164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2015080801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.u sbdev_phy_pins_sense.2015080801 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_phy_pins_sense/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_pkt_buffer.1399612147 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 17332151311 ps |
| CPU time | 46.47 seconds |
| Started | Feb 08 06:03:07 PM UTC 25 |
| Finished | Feb 08 06:03:55 PM UTC 25 |
| Peak memory | 231984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1399612147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbde v_pkt_buffer.1399612147 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_pkt_buffer/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_pkt_received.4285387335 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 152011551 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:03:07 PM UTC 25 |
| Finished | Feb 08 06:03:10 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4285387335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usb dev_pkt_received.4285387335 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_pkt_received/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_pkt_sent.3060886860 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 290241868 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 06:03:07 PM UTC 25 |
| Finished | Feb 08 06:03:10 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3060886860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ pkt_sent.3060886860 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_pkt_sent/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_rand_bus_disconnects.1780032681 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 5843386891 ps |
| CPU time | 22.8 seconds |
| Started | Feb 08 06:03:08 PM UTC 25 |
| Finished | Feb 08 06:03:33 PM UTC 25 |
| Peak memory | 231864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780032681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_ TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.1780032681 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_rand_bus_disconnects/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_rand_bus_resets.887691612 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 5225324929 ps |
| CPU time | 27.09 seconds |
| Started | Feb 08 06:03:09 PM UTC 25 |
| Finished | Feb 08 06:03:37 PM UTC 25 |
| Peak memory | 229708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887691612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.usbdev_rand_bus_resets.887691612 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_rand_bus_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_rand_suspends.1530472955 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 5320697404 ps |
| CPU time | 51.07 seconds |
| Started | Feb 08 06:03:10 PM UTC 25 |
| Finished | Feb 08 06:04:03 PM UTC 25 |
| Peak memory | 229904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530472955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_ TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.1530472955 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_rand_suspends/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_random_length_in_transaction.3862863464 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 199541988 ps |
| CPU time | 1.26 seconds |
| Started | Feb 08 06:03:08 PM UTC 25 |
| Finished | Feb 08 06:03:11 PM UTC 25 |
| Peak memory | 215004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3862863464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.us bdev_random_length_in_transaction.3862863464 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_random_length_in_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_random_length_out_transaction.1731277206 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 170793180 ps |
| CPU time | 1.43 seconds |
| Started | Feb 08 06:03:08 PM UTC 25 |
| Finished | Feb 08 06:03:11 PM UTC 25 |
| Peak memory | 215024 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1731277206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.usbdev_random_length_out_transaction.1731277206 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_random_length_out_transaction/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_resume_link_active.816277948 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 20162000156 ps |
| CPU time | 57.06 seconds |
| Started | Feb 08 06:03:10 PM UTC 25 |
| Finished | Feb 08 06:04:09 PM UTC 25 |
| Peak memory | 217144 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=816277948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_resume_link_active.816277948 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_resume_link_active/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_rx_crc_err.3679283282 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 142403241 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:03:10 PM UTC 25 |
| Finished | Feb 08 06:03:12 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3679283282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbde v_rx_crc_err.3679283282 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_rx_crc_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_rx_full.871670658 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 432961731 ps |
| CPU time | 2.24 seconds |
| Started | Feb 08 06:03:11 PM UTC 25 |
| Finished | Feb 08 06:03:14 PM UTC 25 |
| Peak memory | 217308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=871670658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx _full.871670658 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_rx_full/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_setup_stage.2701730273 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 168681597 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 06:03:11 PM UTC 25 |
| Finished | Feb 08 06:03:14 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2701730273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbd ev_setup_stage.2701730273 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_setup_stage/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_setup_trans_ignored.574523089 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 175812652 ps |
| CPU time | 1.45 seconds |
| Started | Feb 08 06:03:12 PM UTC 25 |
| Finished | Feb 08 06:03:15 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=574523089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.574523089 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_setup_trans_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_smoke.900659118 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 220888097 ps |
| CPU time | 1.7 seconds |
| Started | Feb 08 06:03:12 PM UTC 25 |
| Finished | Feb 08 06:03:15 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=900659118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smok e.900659118 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_spurious_pids_ignored.1633195160 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 1717619529 ps |
| CPU time | 13.89 seconds |
| Started | Feb 08 06:03:12 PM UTC 25 |
| Finished | Feb 08 06:03:28 PM UTC 25 |
| Peak memory | 229760 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633195160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 9.usbdev_spurious_pids_ignored.1633195160 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_spurious_pids_ignored/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_stall_priority_over_nak.751190459 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 179824931 ps |
| CPU time | 1.32 seconds |
| Started | Feb 08 06:03:14 PM UTC 25 |
| Finished | Feb 08 06:03:16 PM UTC 25 |
| Peak memory | 215100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=751190459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 9.usbdev_stall_priority_over_nak.751190459 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_stall_priority_over_nak/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_stall_trans.3040675315 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 164210963 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 06:03:14 PM UTC 25 |
| Finished | Feb 08 06:03:16 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3040675315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbd ev_stall_trans.3040675315 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_stall_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_stream_len_max.3582461873 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 1329496470 ps |
| CPU time | 4.57 seconds |
| Started | Feb 08 06:03:15 PM UTC 25 |
| Finished | Feb 08 06:03:21 PM UTC 25 |
| Peak memory | 217296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3582461873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.u sbdev_stream_len_max.3582461873 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_stream_len_max/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_streaming_out.1632185546 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 2977641673 ps |
| CPU time | 23.6 seconds |
| Started | Feb 08 06:03:15 PM UTC 25 |
| Finished | Feb 08 06:03:40 PM UTC 25 |
| Peak memory | 229756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1632185546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev _streaming_out.1632185546 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_streaming_out/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_timeout_missing_host_handshake.3271410817 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 1072409971 ps |
| CPU time | 10.38 seconds |
| Started | Feb 08 06:02:49 PM UTC 25 |
| Finished | Feb 08 06:03:01 PM UTC 25 |
| Peak memory | 217352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271410817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test + UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_host_handshake.3271410817 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_timeout_missing_host_handshake/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/9.usbdev_tx_rx_disruption.3589399812 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 639006090 ps |
| CPU time | 2.62 seconds |
| Started | Feb 08 06:03:17 PM UTC 25 |
| Finished | Feb 08 06:03:21 PM UTC 25 |
| Peak memory | 216744 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 589399812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_tx_rx_disruption.3589399812 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/9.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/90.usbdev_endpoint_types.719764717 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 508638390 ps |
| CPU time | 1.42 seconds |
| Started | Feb 08 06:18:16 PM UTC 25 |
| Finished | Feb 08 06:18:19 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719764717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_ types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 90.usbdev_endpoint_types.719764717 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/90.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/90.usbdev_tx_rx_disruption.595392784 |
| Short name | T3170 |
| Test name | |
| Test status | |
| Simulation time | 521571569 ps |
| CPU time | 1.8 seconds |
| Started | Feb 08 06:18:17 PM UTC 25 |
| Finished | Feb 08 06:18:21 PM UTC 25 |
| Peak memory | 215084 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 95392784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.usbdev_tx_rx_disruption.595392784 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/90.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/91.usbdev_endpoint_types.1022707106 |
| Short name | T3162 |
| Test name | |
| Test status | |
| Simulation time | 364348029 ps |
| CPU time | 1.28 seconds |
| Started | Feb 08 06:18:17 PM UTC 25 |
| Finished | Feb 08 06:18:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022707106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 91.usbdev_endpoint_types.1022707106 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/91.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/91.usbdev_tx_rx_disruption.272233429 |
| Short name | T3168 |
| Test name | |
| Test status | |
| Simulation time | 663660857 ps |
| CPU time | 1.77 seconds |
| Started | Feb 08 06:18:17 PM UTC 25 |
| Finished | Feb 08 06:18:21 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 72233429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.usbdev_tx_rx_disruption.272233429 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/91.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/92.usbdev_tx_rx_disruption.2469276833 |
| Short name | T3166 |
| Test name | |
| Test status | |
| Simulation time | 391756554 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 06:18:17 PM UTC 25 |
| Finished | Feb 08 06:18:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 469276833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.usbdev_tx_rx_disruption.2469276833 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/92.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/93.usbdev_endpoint_types.2235970770 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 249322441 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 06:18:17 PM UTC 25 |
| Finished | Feb 08 06:18:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235970770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 93.usbdev_endpoint_types.2235970770 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/93.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/93.usbdev_tx_rx_disruption.3352363174 |
| Short name | T3169 |
| Test name | |
| Test status | |
| Simulation time | 517095761 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 06:18:17 PM UTC 25 |
| Finished | Feb 08 06:18:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 352363174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.usbdev_tx_rx_disruption.3352363174 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/93.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/94.usbdev_endpoint_types.1332593042 |
| Short name | T3163 |
| Test name | |
| Test status | |
| Simulation time | 172014795 ps |
| CPU time | 0.88 seconds |
| Started | Feb 08 06:18:18 PM UTC 25 |
| Finished | Feb 08 06:18:20 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332593042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 94.usbdev_endpoint_types.1332593042 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/94.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/94.usbdev_tx_rx_disruption.3696117994 |
| Short name | T3167 |
| Test name | |
| Test status | |
| Simulation time | 468671174 ps |
| CPU time | 1.53 seconds |
| Started | Feb 08 06:18:18 PM UTC 25 |
| Finished | Feb 08 06:18:21 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 696117994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.usbdev_tx_rx_disruption.3696117994 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/94.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/95.usbdev_endpoint_types.3891664340 |
| Short name | T3164 |
| Test name | |
| Test status | |
| Simulation time | 259746763 ps |
| CPU time | 0.96 seconds |
| Started | Feb 08 06:18:18 PM UTC 25 |
| Finished | Feb 08 06:18:20 PM UTC 25 |
| Peak memory | 215088 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891664340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 95.usbdev_endpoint_types.3891664340 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/95.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/95.usbdev_tx_rx_disruption.3112356549 |
| Short name | T3172 |
| Test name | |
| Test status | |
| Simulation time | 479634326 ps |
| CPU time | 1.77 seconds |
| Started | Feb 08 06:18:19 PM UTC 25 |
| Finished | Feb 08 06:18:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 112356549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.usbdev_tx_rx_disruption.3112356549 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/95.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/96.usbdev_endpoint_types.3269293418 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 223715392 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 06:18:19 PM UTC 25 |
| Finished | Feb 08 06:18:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269293418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 96.usbdev_endpoint_types.3269293418 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/96.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/96.usbdev_tx_rx_disruption.1774756111 |
| Short name | T3174 |
| Test name | |
| Test status | |
| Simulation time | 520444890 ps |
| CPU time | 1.87 seconds |
| Started | Feb 08 06:18:19 PM UTC 25 |
| Finished | Feb 08 06:18:23 PM UTC 25 |
| Peak memory | 215036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 774756111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.usbdev_tx_rx_disruption.1774756111 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/96.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/97.usbdev_tx_rx_disruption.2338804235 |
| Short name | T3173 |
| Test name | |
| Test status | |
| Simulation time | 502343718 ps |
| CPU time | 1.61 seconds |
| Started | Feb 08 06:18:19 PM UTC 25 |
| Finished | Feb 08 06:18:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 338804235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.usbdev_tx_rx_disruption.2338804235 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/97.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/98.usbdev_tx_rx_disruption.237686959 |
| Short name | T3171 |
| Test name | |
| Test status | |
| Simulation time | 464263548 ps |
| CPU time | 1.44 seconds |
| Started | Feb 08 06:18:19 PM UTC 25 |
| Finished | Feb 08 06:18:22 PM UTC 25 |
| Peak memory | 215112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 37686959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.usbdev_tx_rx_disruption.237686959 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/98.usbdev_tx_rx_disruption/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/99.usbdev_endpoint_types.3815226517 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 266785079 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 06:18:19 PM UTC 25 |
| Finished | Feb 08 06:18:22 PM UTC 25 |
| Peak memory | 215104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815226517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint _types_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 99.usbdev_endpoint_types.3815226517 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/99.usbdev_endpoint_types/latest |
| Test location | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/99.usbdev_tx_rx_disruption.2973572370 |
| Short name | T3178 |
| Test name | |
| Test status | |
| Simulation time | 560728715 ps |
| CPU time | 1.96 seconds |
| Started | Feb 08 06:18:20 PM UTC 25 |
| Finished | Feb 08 06:18:23 PM UTC 25 |
| Peak memory | 214944 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 + en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 973572370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.usbdev_tx_rx_disruption.2973572370 |
| Directory | /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/99.usbdev_tx_rx_disruption/latest |
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