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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.36 98.21 96.00 97.44 94.92 98.38 98.21 98.37


Total test records in report: 3808
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T3561 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/271.usbdev_tx_rx_disruption.3715001105 Oct 15 01:07:55 AM UTC 24 Oct 15 01:08:18 AM UTC 24 547504781 ps
T3562 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/265.usbdev_tx_rx_disruption.380482527 Oct 15 01:07:55 AM UTC 24 Oct 15 01:08:18 AM UTC 24 537321190 ps
T3563 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/272.usbdev_tx_rx_disruption.4042480761 Oct 15 01:07:55 AM UTC 24 Oct 15 01:08:18 AM UTC 24 489933716 ps
T3564 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/274.usbdev_tx_rx_disruption.320005235 Oct 15 01:07:55 AM UTC 24 Oct 15 01:08:18 AM UTC 24 499994929 ps
T3565 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/300.usbdev_tx_rx_disruption.1142538931 Oct 15 01:08:02 AM UTC 24 Oct 15 01:08:18 AM UTC 24 625403954 ps
T3566 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/270.usbdev_tx_rx_disruption.3494840699 Oct 15 01:07:55 AM UTC 24 Oct 15 01:08:18 AM UTC 24 640896792 ps
T3567 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/289.usbdev_tx_rx_disruption.2416725064 Oct 15 01:07:58 AM UTC 24 Oct 15 01:08:18 AM UTC 24 523930949 ps
T3568 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/275.usbdev_tx_rx_disruption.2346725255 Oct 15 01:07:55 AM UTC 24 Oct 15 01:08:18 AM UTC 24 606110364 ps
T3569 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/367.usbdev_tx_rx_disruption.3030592087 Oct 15 01:08:14 AM UTC 24 Oct 15 01:08:18 AM UTC 24 574255525 ps
T3570 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/287.usbdev_tx_rx_disruption.2493146243 Oct 15 01:07:58 AM UTC 24 Oct 15 01:08:18 AM UTC 24 596586708 ps
T3571 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/355.usbdev_tx_rx_disruption.2925791881 Oct 15 01:08:13 AM UTC 24 Oct 15 01:08:22 AM UTC 24 495887883 ps
T3572 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/359.usbdev_tx_rx_disruption.3932514638 Oct 15 01:08:13 AM UTC 24 Oct 15 01:08:22 AM UTC 24 494434819 ps
T3573 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/358.usbdev_tx_rx_disruption.90663104 Oct 15 01:08:13 AM UTC 24 Oct 15 01:08:22 AM UTC 24 539994774 ps
T3574 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/449.usbdev_tx_rx_disruption.4145585420 Oct 15 01:08:49 AM UTC 24 Oct 15 01:08:53 AM UTC 24 485796989 ps
T3575 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/356.usbdev_tx_rx_disruption.3504846325 Oct 15 01:08:13 AM UTC 24 Oct 15 01:08:22 AM UTC 24 631624612 ps
T3576 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/448.usbdev_tx_rx_disruption.809599176 Oct 15 01:08:49 AM UTC 24 Oct 15 01:08:53 AM UTC 24 477592365 ps
T3577 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/386.usbdev_tx_rx_disruption.1458533373 Oct 15 01:08:20 AM UTC 24 Oct 15 01:08:22 AM UTC 24 424476219 ps
T3578 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/382.usbdev_tx_rx_disruption.120618980 Oct 15 01:08:20 AM UTC 24 Oct 15 01:08:22 AM UTC 24 557298616 ps
T3579 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/383.usbdev_tx_rx_disruption.1918945366 Oct 15 01:08:20 AM UTC 24 Oct 15 01:08:22 AM UTC 24 556182597 ps
T3580 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/200.usbdev_tx_rx_disruption.1950496347 Oct 15 01:07:36 AM UTC 24 Oct 15 01:08:23 AM UTC 24 443771141 ps
T3581 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/333.usbdev_tx_rx_disruption.2341727664 Oct 15 01:08:10 AM UTC 24 Oct 15 01:08:23 AM UTC 24 523635950 ps
T3582 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/384.usbdev_tx_rx_disruption.2992814855 Oct 15 01:08:20 AM UTC 24 Oct 15 01:08:23 AM UTC 24 647588469 ps
T462 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/199.usbdev_endpoint_types.1823359771 Oct 15 01:07:36 AM UTC 24 Oct 15 01:08:23 AM UTC 24 618214866 ps
T3583 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/385.usbdev_tx_rx_disruption.3884004344 Oct 15 01:08:20 AM UTC 24 Oct 15 01:08:23 AM UTC 24 579872422 ps
T3584 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/334.usbdev_tx_rx_disruption.2519143825 Oct 15 01:08:10 AM UTC 24 Oct 15 01:08:23 AM UTC 24 604725408 ps
T3585 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/332.usbdev_tx_rx_disruption.3185954423 Oct 15 01:08:10 AM UTC 24 Oct 15 01:08:23 AM UTC 24 572788023 ps
T3586 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/335.usbdev_tx_rx_disruption.3500030540 Oct 15 01:08:10 AM UTC 24 Oct 15 01:08:23 AM UTC 24 604715405 ps
T3587 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/336.usbdev_tx_rx_disruption.3604498947 Oct 15 01:08:10 AM UTC 24 Oct 15 01:08:23 AM UTC 24 512179202 ps
T3588 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/337.usbdev_tx_rx_disruption.105288212 Oct 15 01:08:10 AM UTC 24 Oct 15 01:08:23 AM UTC 24 496686162 ps
T3589 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/338.usbdev_tx_rx_disruption.3595732483 Oct 15 01:08:10 AM UTC 24 Oct 15 01:08:23 AM UTC 24 489388436 ps
T3590 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/346.usbdev_tx_rx_disruption.2584105751 Oct 15 01:08:10 AM UTC 24 Oct 15 01:08:23 AM UTC 24 499589427 ps
T3591 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/344.usbdev_tx_rx_disruption.1137048001 Oct 15 01:08:10 AM UTC 24 Oct 15 01:08:23 AM UTC 24 527794939 ps
T3592 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/340.usbdev_tx_rx_disruption.262041594 Oct 15 01:08:10 AM UTC 24 Oct 15 01:08:23 AM UTC 24 559011412 ps
T3593 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/342.usbdev_tx_rx_disruption.1999844339 Oct 15 01:08:10 AM UTC 24 Oct 15 01:08:23 AM UTC 24 597994529 ps
T3594 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/347.usbdev_tx_rx_disruption.3513305409 Oct 15 01:08:10 AM UTC 24 Oct 15 01:08:23 AM UTC 24 638530072 ps
T3595 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/317.usbdev_tx_rx_disruption.3052357181 Oct 15 01:08:07 AM UTC 24 Oct 15 01:08:23 AM UTC 24 437398662 ps
T3596 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/363.usbdev_tx_rx_disruption.3849472216 Oct 15 01:08:13 AM UTC 24 Oct 15 01:08:23 AM UTC 24 638648000 ps
T3597 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/345.usbdev_tx_rx_disruption.2648139952 Oct 15 01:08:10 AM UTC 24 Oct 15 01:08:23 AM UTC 24 565900022 ps
T3598 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/361.usbdev_tx_rx_disruption.2798100748 Oct 15 01:08:13 AM UTC 24 Oct 15 01:08:23 AM UTC 24 465474410 ps
T3599 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/341.usbdev_tx_rx_disruption.937145785 Oct 15 01:08:10 AM UTC 24 Oct 15 01:08:23 AM UTC 24 494814073 ps
T3600 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/357.usbdev_tx_rx_disruption.1310517555 Oct 15 01:08:13 AM UTC 24 Oct 15 01:08:23 AM UTC 24 548654577 ps
T3601 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/343.usbdev_tx_rx_disruption.2261042813 Oct 15 01:08:10 AM UTC 24 Oct 15 01:08:23 AM UTC 24 611234782 ps
T3602 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/339.usbdev_tx_rx_disruption.595253941 Oct 15 01:08:10 AM UTC 24 Oct 15 01:08:23 AM UTC 24 636719976 ps
T3603 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/348.usbdev_tx_rx_disruption.3011856881 Oct 15 01:08:10 AM UTC 24 Oct 15 01:08:23 AM UTC 24 460867156 ps
T3604 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/360.usbdev_tx_rx_disruption.2757246452 Oct 15 01:08:13 AM UTC 24 Oct 15 01:08:23 AM UTC 24 603368164 ps
T3605 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/362.usbdev_tx_rx_disruption.3237485749 Oct 15 01:08:13 AM UTC 24 Oct 15 01:08:24 AM UTC 24 584693130 ps
T3606 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/350.usbdev_tx_rx_disruption.3187700510 Oct 15 01:08:10 AM UTC 24 Oct 15 01:08:24 AM UTC 24 659090484 ps
T3607 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/371.usbdev_tx_rx_disruption.4232800815 Oct 15 01:08:18 AM UTC 24 Oct 15 01:08:27 AM UTC 24 414144001 ps
T3608 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/372.usbdev_tx_rx_disruption.2430794901 Oct 15 01:08:18 AM UTC 24 Oct 15 01:08:27 AM UTC 24 439166987 ps
T3609 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/373.usbdev_tx_rx_disruption.91386146 Oct 15 01:08:18 AM UTC 24 Oct 15 01:08:27 AM UTC 24 586365654 ps
T3610 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/374.usbdev_tx_rx_disruption.3049422215 Oct 15 01:08:18 AM UTC 24 Oct 15 01:08:27 AM UTC 24 652422829 ps
T3611 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/399.usbdev_tx_rx_disruption.2728047123 Oct 15 01:08:25 AM UTC 24 Oct 15 01:08:28 AM UTC 24 485809133 ps
T3612 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/396.usbdev_tx_rx_disruption.3142034389 Oct 15 01:08:25 AM UTC 24 Oct 15 01:08:28 AM UTC 24 474046380 ps
T3613 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/397.usbdev_tx_rx_disruption.2219358949 Oct 15 01:08:25 AM UTC 24 Oct 15 01:08:28 AM UTC 24 482473042 ps
T3614 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/398.usbdev_tx_rx_disruption.320528526 Oct 15 01:08:25 AM UTC 24 Oct 15 01:08:28 AM UTC 24 556010211 ps
T3615 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/394.usbdev_tx_rx_disruption.3636859939 Oct 15 01:08:25 AM UTC 24 Oct 15 01:08:28 AM UTC 24 602685355 ps
T3616 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/395.usbdev_tx_rx_disruption.3662499319 Oct 15 01:08:25 AM UTC 24 Oct 15 01:08:28 AM UTC 24 586806755 ps
T3617 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/416.usbdev_tx_rx_disruption.326978974 Oct 15 01:08:26 AM UTC 24 Oct 15 01:08:32 AM UTC 24 551885155 ps
T3618 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/417.usbdev_tx_rx_disruption.2417177500 Oct 15 01:08:26 AM UTC 24 Oct 15 01:08:32 AM UTC 24 460741341 ps
T3619 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/415.usbdev_tx_rx_disruption.3697718049 Oct 15 01:08:26 AM UTC 24 Oct 15 01:08:32 AM UTC 24 464834798 ps
T3620 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/418.usbdev_tx_rx_disruption.2379228945 Oct 15 01:08:26 AM UTC 24 Oct 15 01:08:32 AM UTC 24 544266853 ps
T3621 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/413.usbdev_tx_rx_disruption.4282413012 Oct 15 01:08:26 AM UTC 24 Oct 15 01:08:32 AM UTC 24 618817008 ps
T3622 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/419.usbdev_tx_rx_disruption.2439442307 Oct 15 01:08:26 AM UTC 24 Oct 15 01:08:32 AM UTC 24 598372740 ps
T3623 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/420.usbdev_tx_rx_disruption.130754484 Oct 15 01:08:26 AM UTC 24 Oct 15 01:08:32 AM UTC 24 539375868 ps
T3624 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/428.usbdev_tx_rx_disruption.3959375497 Oct 15 01:08:29 AM UTC 24 Oct 15 01:08:32 AM UTC 24 529599173 ps
T3625 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/427.usbdev_tx_rx_disruption.2550267887 Oct 15 01:08:29 AM UTC 24 Oct 15 01:08:32 AM UTC 24 563502273 ps
T3626 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/429.usbdev_tx_rx_disruption.2794049697 Oct 15 01:08:29 AM UTC 24 Oct 15 01:08:32 AM UTC 24 498131670 ps
T3627 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/400.usbdev_tx_rx_disruption.3843971418 Oct 15 01:08:25 AM UTC 24 Oct 15 01:08:38 AM UTC 24 511390987 ps
T3628 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/442.usbdev_tx_rx_disruption.260783981 Oct 15 01:08:39 AM UTC 24 Oct 15 01:08:42 AM UTC 24 424625989 ps
T3629 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/430.usbdev_tx_rx_disruption.4049363731 Oct 15 01:08:30 AM UTC 24 Oct 15 01:08:42 AM UTC 24 492411000 ps
T3630 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/431.usbdev_tx_rx_disruption.267218940 Oct 15 01:08:30 AM UTC 24 Oct 15 01:08:42 AM UTC 24 584960132 ps
T3631 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/424.usbdev_tx_rx_disruption.4172958256 Oct 15 01:08:28 AM UTC 24 Oct 15 01:08:48 AM UTC 24 587770139 ps
T3632 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/425.usbdev_tx_rx_disruption.3961183254 Oct 15 01:08:28 AM UTC 24 Oct 15 01:08:48 AM UTC 24 498830756 ps
T3633 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/444.usbdev_tx_rx_disruption.572705490 Oct 15 01:08:43 AM UTC 24 Oct 15 01:08:48 AM UTC 24 460226849 ps
T3634 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/426.usbdev_tx_rx_disruption.3520126480 Oct 15 01:08:28 AM UTC 24 Oct 15 01:08:48 AM UTC 24 679320495 ps
T3635 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/421.usbdev_tx_rx_disruption.3454885782 Oct 15 01:08:26 AM UTC 24 Oct 15 01:08:52 AM UTC 24 476081135 ps
T3636 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/446.usbdev_tx_rx_disruption.4229404331 Oct 15 01:08:49 AM UTC 24 Oct 15 01:08:52 AM UTC 24 443055879 ps
T3637 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/389.usbdev_tx_rx_disruption.3381249885 Oct 15 01:08:23 AM UTC 24 Oct 15 01:08:53 AM UTC 24 471205314 ps
T3638 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/436.usbdev_tx_rx_disruption.79833717 Oct 15 01:08:33 AM UTC 24 Oct 15 01:08:53 AM UTC 24 376514723 ps
T3639 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/434.usbdev_tx_rx_disruption.3194979545 Oct 15 01:08:33 AM UTC 24 Oct 15 01:08:53 AM UTC 24 450570230 ps
T3640 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/447.usbdev_tx_rx_disruption.2058987676 Oct 15 01:08:49 AM UTC 24 Oct 15 01:08:53 AM UTC 24 573124975 ps
T3641 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/423.usbdev_tx_rx_disruption.2316580614 Oct 15 01:08:27 AM UTC 24 Oct 15 01:08:53 AM UTC 24 489831541 ps
T3642 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/387.usbdev_tx_rx_disruption.809132553 Oct 15 01:08:23 AM UTC 24 Oct 15 01:08:53 AM UTC 24 479567159 ps
T3643 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/388.usbdev_tx_rx_disruption.3689239876 Oct 15 01:08:23 AM UTC 24 Oct 15 01:08:53 AM UTC 24 535876058 ps
T3644 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/433.usbdev_tx_rx_disruption.4102256707 Oct 15 01:08:33 AM UTC 24 Oct 15 01:08:53 AM UTC 24 467022448 ps
T3645 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/432.usbdev_tx_rx_disruption.3662258470 Oct 15 01:08:33 AM UTC 24 Oct 15 01:08:53 AM UTC 24 449211447 ps
T3646 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/391.usbdev_tx_rx_disruption.1864487732 Oct 15 01:08:23 AM UTC 24 Oct 15 01:08:53 AM UTC 24 633031230 ps
T3647 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/390.usbdev_tx_rx_disruption.924547678 Oct 15 01:08:23 AM UTC 24 Oct 15 01:08:53 AM UTC 24 530679695 ps
T3648 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/392.usbdev_tx_rx_disruption.3431258830 Oct 15 01:08:23 AM UTC 24 Oct 15 01:08:53 AM UTC 24 480104345 ps
T3649 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/393.usbdev_tx_rx_disruption.2601084536 Oct 15 01:08:23 AM UTC 24 Oct 15 01:08:53 AM UTC 24 483906480 ps
T3650 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/438.usbdev_tx_rx_disruption.1232263679 Oct 15 01:08:33 AM UTC 24 Oct 15 01:08:53 AM UTC 24 579257091 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/422.usbdev_tx_rx_disruption.3138682144 Oct 15 01:08:27 AM UTC 24 Oct 15 01:08:53 AM UTC 24 555180646 ps
T3651 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/435.usbdev_tx_rx_disruption.2852276555 Oct 15 01:08:33 AM UTC 24 Oct 15 01:08:53 AM UTC 24 642861187 ps
T3652 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/441.usbdev_tx_rx_disruption.2611637487 Oct 15 01:08:33 AM UTC 24 Oct 15 01:08:53 AM UTC 24 530163166 ps
T3653 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/437.usbdev_tx_rx_disruption.2313380682 Oct 15 01:08:33 AM UTC 24 Oct 15 01:08:53 AM UTC 24 618516319 ps
T3654 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/440.usbdev_tx_rx_disruption.3546380996 Oct 15 01:08:33 AM UTC 24 Oct 15 01:08:53 AM UTC 24 579403929 ps
T3655 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/439.usbdev_tx_rx_disruption.587158688 Oct 15 01:08:33 AM UTC 24 Oct 15 01:08:53 AM UTC 24 568742458 ps
T3656 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/450.usbdev_tx_rx_disruption.722703197 Oct 15 01:08:52 AM UTC 24 Oct 15 01:08:55 AM UTC 24 424137702 ps
T3657 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/451.usbdev_tx_rx_disruption.2563975759 Oct 15 01:08:52 AM UTC 24 Oct 15 01:08:55 AM UTC 24 574701668 ps
T3658 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/443.usbdev_tx_rx_disruption.1268383330 Oct 15 01:08:43 AM UTC 24 Oct 15 01:08:55 AM UTC 24 500745549 ps
T3659 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/445.usbdev_tx_rx_disruption.3341443809 Oct 15 01:08:43 AM UTC 24 Oct 15 01:08:55 AM UTC 24 601067399 ps
T3660 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/458.usbdev_tx_rx_disruption.1135271210 Oct 15 01:08:55 AM UTC 24 Oct 15 01:08:57 AM UTC 24 433214466 ps
T3661 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/453.usbdev_tx_rx_disruption.1755136116 Oct 15 01:08:55 AM UTC 24 Oct 15 01:08:57 AM UTC 24 567232809 ps
T3662 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/457.usbdev_tx_rx_disruption.2545335336 Oct 15 01:08:55 AM UTC 24 Oct 15 01:08:57 AM UTC 24 498125394 ps
T3663 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/452.usbdev_tx_rx_disruption.1076198246 Oct 15 01:08:55 AM UTC 24 Oct 15 01:08:57 AM UTC 24 648836051 ps
T3664 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/454.usbdev_tx_rx_disruption.3448614634 Oct 15 01:08:55 AM UTC 24 Oct 15 01:08:57 AM UTC 24 661166975 ps
T3665 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/456.usbdev_tx_rx_disruption.3757625086 Oct 15 01:08:55 AM UTC 24 Oct 15 01:08:57 AM UTC 24 585963768 ps
T3666 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/461.usbdev_tx_rx_disruption.4005724388 Oct 15 01:08:55 AM UTC 24 Oct 15 01:08:58 AM UTC 24 475369042 ps
T3667 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/460.usbdev_tx_rx_disruption.416271378 Oct 15 01:08:55 AM UTC 24 Oct 15 01:08:58 AM UTC 24 493427878 ps
T3668 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/455.usbdev_tx_rx_disruption.3009335126 Oct 15 01:08:55 AM UTC 24 Oct 15 01:08:58 AM UTC 24 503040512 ps
T3669 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/463.usbdev_tx_rx_disruption.1465822633 Oct 15 01:08:55 AM UTC 24 Oct 15 01:08:58 AM UTC 24 572177181 ps
T3670 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/459.usbdev_tx_rx_disruption.1982131434 Oct 15 01:08:55 AM UTC 24 Oct 15 01:08:58 AM UTC 24 551885181 ps
T3671 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/464.usbdev_tx_rx_disruption.3888734349 Oct 15 01:08:55 AM UTC 24 Oct 15 01:08:58 AM UTC 24 502257927 ps
T3672 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/462.usbdev_tx_rx_disruption.364578163 Oct 15 01:08:55 AM UTC 24 Oct 15 01:08:58 AM UTC 24 529855208 ps
T3673 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/497.usbdev_tx_rx_disruption.3450756697 Oct 15 01:08:58 AM UTC 24 Oct 15 01:09:07 AM UTC 24 456802755 ps
T3674 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/496.usbdev_tx_rx_disruption.684398891 Oct 15 01:08:58 AM UTC 24 Oct 15 01:09:07 AM UTC 24 507399848 ps
T3675 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/498.usbdev_tx_rx_disruption.4284973938 Oct 15 01:08:58 AM UTC 24 Oct 15 01:09:17 AM UTC 24 605976257 ps
T3676 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/499.usbdev_tx_rx_disruption.2477956601 Oct 15 01:08:58 AM UTC 24 Oct 15 01:09:18 AM UTC 24 641056394 ps
T3677 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/487.usbdev_tx_rx_disruption.2201163043 Oct 15 01:08:56 AM UTC 24 Oct 15 01:09:25 AM UTC 24 442783339 ps
T3678 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/483.usbdev_tx_rx_disruption.1379876661 Oct 15 01:08:56 AM UTC 24 Oct 15 01:09:25 AM UTC 24 467856323 ps
T3679 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/482.usbdev_tx_rx_disruption.2281925474 Oct 15 01:08:56 AM UTC 24 Oct 15 01:09:25 AM UTC 24 503193887 ps
T3680 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/486.usbdev_tx_rx_disruption.673317207 Oct 15 01:08:56 AM UTC 24 Oct 15 01:09:26 AM UTC 24 640426334 ps
T3681 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/484.usbdev_tx_rx_disruption.2928843867 Oct 15 01:08:56 AM UTC 24 Oct 15 01:09:26 AM UTC 24 640323253 ps
T3682 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/491.usbdev_tx_rx_disruption.3298813179 Oct 15 01:08:56 AM UTC 24 Oct 15 01:09:26 AM UTC 24 600952941 ps
T3683 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/489.usbdev_tx_rx_disruption.3575182960 Oct 15 01:08:56 AM UTC 24 Oct 15 01:09:26 AM UTC 24 526947739 ps
T3684 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/485.usbdev_tx_rx_disruption.1452904928 Oct 15 01:08:56 AM UTC 24 Oct 15 01:09:26 AM UTC 24 567376030 ps
T3685 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/488.usbdev_tx_rx_disruption.3652357112 Oct 15 01:08:56 AM UTC 24 Oct 15 01:09:26 AM UTC 24 623829856 ps
T3686 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/492.usbdev_tx_rx_disruption.139540976 Oct 15 01:08:56 AM UTC 24 Oct 15 01:09:26 AM UTC 24 523421663 ps
T3687 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/493.usbdev_tx_rx_disruption.3226479614 Oct 15 01:08:56 AM UTC 24 Oct 15 01:09:26 AM UTC 24 640911802 ps
T3688 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/490.usbdev_tx_rx_disruption.3222089206 Oct 15 01:08:56 AM UTC 24 Oct 15 01:09:26 AM UTC 24 633569495 ps
T3689 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/495.usbdev_tx_rx_disruption.3064468392 Oct 15 01:08:56 AM UTC 24 Oct 15 01:09:26 AM UTC 24 606651002 ps
T463 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/184.usbdev_endpoint_types.198079378 Oct 15 01:07:26 AM UTC 24 Oct 15 01:09:26 AM UTC 24 495437924 ps
T3690 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/default/494.usbdev_tx_rx_disruption.1360132828 Oct 15 01:08:56 AM UTC 24 Oct 15 01:09:26 AM UTC 24 663992736 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_intr_test.174716824 Oct 15 01:08:58 AM UTC 24 Oct 15 01:09:01 AM UTC 24 48057798 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_hw_reset.4078369607 Oct 15 01:09:00 AM UTC 24 Oct 15 01:09:01 AM UTC 24 68250849 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_rw.1148682342 Oct 15 01:09:00 AM UTC 24 Oct 15 01:09:01 AM UTC 24 92509364 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1040658439 Oct 15 01:08:58 AM UTC 24 Oct 15 01:09:01 AM UTC 24 190726338 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_errors.4249347741 Oct 15 01:09:00 AM UTC 24 Oct 15 01:09:02 AM UTC 24 102841852 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3615141846 Oct 15 01:09:00 AM UTC 24 Oct 15 01:09:02 AM UTC 24 196419797 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3787479936 Oct 15 01:08:58 AM UTC 24 Oct 15 01:09:02 AM UTC 24 161280791 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_intg_err.3260534545 Oct 15 01:08:58 AM UTC 24 Oct 15 01:09:02 AM UTC 24 312641146 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1199784017 Oct 15 01:09:00 AM UTC 24 Oct 15 01:09:03 AM UTC 24 182487335 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_partial_access.483860518 Oct 15 01:09:00 AM UTC 24 Oct 15 01:09:03 AM UTC 24 134794641 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_aliasing.3591266318 Oct 15 01:09:00 AM UTC 24 Oct 15 01:09:03 AM UTC 24 239274894 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_bit_bash.336958293 Oct 15 01:09:00 AM UTC 24 Oct 15 01:09:04 AM UTC 24 367158197 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_intg_err.585722132 Oct 15 01:09:00 AM UTC 24 Oct 15 01:09:05 AM UTC 24 603203336 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_csr_rw.2256066004 Oct 15 01:09:24 AM UTC 24 Oct 15 01:09:26 AM UTC 24 53633591 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_intr_test.1116291813 Oct 15 01:09:04 AM UTC 24 Oct 15 01:09:06 AM UTC 24 64041072 ps
T3691 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_partial_access.3370398191 Oct 15 01:09:05 AM UTC 24 Oct 15 01:09:07 AM UTC 24 108019456 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_intg_err.3571559232 Oct 15 01:09:04 AM UTC 24 Oct 15 01:09:08 AM UTC 24 834117267 ps
T3692 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_walk.2919888610 Oct 15 01:09:04 AM UTC 24 Oct 15 01:09:09 AM UTC 24 233351773 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_intr_test.502768878 Oct 15 01:09:00 AM UTC 24 Oct 15 01:09:12 AM UTC 24 45155720 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_rw.2182991661 Oct 15 01:09:07 AM UTC 24 Oct 15 01:09:12 AM UTC 24 62127272 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.863786968 Oct 15 01:09:09 AM UTC 24 Oct 15 01:09:12 AM UTC 24 104168698 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_errors.2364240301 Oct 15 01:09:10 AM UTC 24 Oct 15 01:09:12 AM UTC 24 100649723 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3551301259 Oct 15 01:09:03 AM UTC 24 Oct 15 01:09:12 AM UTC 24 85868840 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2459977717 Oct 15 01:09:03 AM UTC 24 Oct 15 01:09:13 AM UTC 24 79144761 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1260663709 Oct 15 01:09:08 AM UTC 24 Oct 15 01:09:13 AM UTC 24 272128966 ps
T3693 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_walk.3390692521 Oct 15 01:09:00 AM UTC 24 Oct 15 01:09:14 AM UTC 24 163216078 ps
T3694 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_walk.465898332 Oct 15 01:08:58 AM UTC 24 Oct 15 01:09:14 AM UTC 24 274204961 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_aliasing.1765277881 Oct 15 01:09:03 AM UTC 24 Oct 15 01:09:15 AM UTC 24 359275311 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_errors.4229984675 Oct 15 01:09:03 AM UTC 24 Oct 15 01:09:15 AM UTC 24 289212009 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_aliasing.44276244 Oct 15 01:09:08 AM UTC 24 Oct 15 01:09:15 AM UTC 24 369510706 ps
T3695 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2923993593 Oct 15 01:09:08 AM UTC 24 Oct 15 01:09:15 AM UTC 24 420007113 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_intr_test.1170575499 Oct 15 01:08:58 AM UTC 24 Oct 15 01:09:17 AM UTC 24 47406508 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_rw.166568733 Oct 15 01:08:58 AM UTC 24 Oct 15 01:09:17 AM UTC 24 66303853 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1442945410 Oct 15 01:08:58 AM UTC 24 Oct 15 01:09:17 AM UTC 24 203054122 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2768110498 Oct 15 01:09:02 AM UTC 24 Oct 15 01:09:17 AM UTC 24 135170352 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_partial_access.3742316207 Oct 15 01:09:02 AM UTC 24 Oct 15 01:09:18 AM UTC 24 62036511 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_errors.176662429 Oct 15 01:08:58 AM UTC 24 Oct 15 01:09:18 AM UTC 24 144938715 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_partial_access.1497614138 Oct 15 01:08:58 AM UTC 24 Oct 15 01:09:18 AM UTC 24 166599744 ps
T3696 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_walk.4291965030 Oct 15 01:08:58 AM UTC 24 Oct 15 01:09:18 AM UTC 24 322271660 ps
T3697 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_aliasing.3866708667 Oct 15 01:08:58 AM UTC 24 Oct 15 01:09:19 AM UTC 24 296734392 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_bit_bash.459402700 Oct 15 01:09:15 AM UTC 24 Oct 15 01:09:19 AM UTC 24 249746040 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_intg_err.463785245 Oct 15 01:08:58 AM UTC 24 Oct 15 01:09:20 AM UTC 24 491996598 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_bit_bash.776572282 Oct 15 01:09:02 AM UTC 24 Oct 15 01:09:20 AM UTC 24 720145855 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_intr_test.2499039384 Oct 15 01:09:12 AM UTC 24 Oct 15 01:09:21 AM UTC 24 85021568 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_intr_test.396098910 Oct 15 01:09:20 AM UTC 24 Oct 15 01:09:21 AM UTC 24 53426680 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_csr_rw.450059259 Oct 15 01:09:19 AM UTC 24 Oct 15 01:09:22 AM UTC 24 77939703 ps
T3698 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2316839408 Oct 15 01:09:19 AM UTC 24 Oct 15 01:09:22 AM UTC 24 61171407 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3672526789 Oct 15 01:09:19 AM UTC 24 Oct 15 01:09:22 AM UTC 24 146023789 ps
T3699 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_rw.1280943521 Oct 15 01:09:17 AM UTC 24 Oct 15 01:09:22 AM UTC 24 80148825 ps
T3700 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_rw.2664173558 Oct 15 01:09:14 AM UTC 24 Oct 15 01:09:22 AM UTC 24 45101869 ps
T3701 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2656406463 Oct 15 01:09:14 AM UTC 24 Oct 15 01:09:22 AM UTC 24 89053320 ps
T3702 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_csr_rw.3648633678 Oct 15 01:09:21 AM UTC 24 Oct 15 01:09:23 AM UTC 24 50485935 ps
T3703 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1057811268 Oct 15 01:08:58 AM UTC 24 Oct 15 01:09:23 AM UTC 24 712859173 ps
T3704 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2778427895 Oct 15 01:09:17 AM UTC 24 Oct 15 01:09:23 AM UTC 24 156982916 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_tl_errors.2437053633 Oct 15 01:09:20 AM UTC 24 Oct 15 01:09:23 AM UTC 24 185572668 ps
T507 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_tl_intg_err.1738018400 Oct 15 01:09:20 AM UTC 24 Oct 15 01:09:23 AM UTC 24 480632799 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_intr_test.1506088234 Oct 15 01:09:19 AM UTC 24 Oct 15 01:09:23 AM UTC 24 86866160 ps
T3705 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1090812755 Oct 15 01:09:21 AM UTC 24 Oct 15 01:09:23 AM UTC 24 199389584 ps
T3706 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_partial_access.3050213072 Oct 15 01:09:13 AM UTC 24 Oct 15 01:09:23 AM UTC 24 122812249 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_tl_errors.1431813154 Oct 15 01:09:22 AM UTC 24 Oct 15 01:09:25 AM UTC 24 93775323 ps
T3707 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1353002705 Oct 15 01:09:18 AM UTC 24 Oct 15 01:09:24 AM UTC 24 93341310 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_intr_test.3050781715 Oct 15 01:09:22 AM UTC 24 Oct 15 01:09:24 AM UTC 24 43861312 ps
T3708 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.941901960 Oct 15 01:09:22 AM UTC 24 Oct 15 01:09:24 AM UTC 24 90642644 ps
T3709 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_rw.648635833 Oct 15 01:09:02 AM UTC 24 Oct 15 01:09:24 AM UTC 24 77866427 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_tl_errors.294285526 Oct 15 01:09:18 AM UTC 24 Oct 15 01:09:25 AM UTC 24 256802172 ps
T510 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_intg_err.2645357884 Oct 15 01:09:12 AM UTC 24 Oct 15 01:09:25 AM UTC 24 1142006312 ps
T3710 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3070715556 Oct 15 01:09:06 AM UTC 24 Oct 15 01:09:25 AM UTC 24 173296260 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_intr_test.3765304686 Oct 15 01:09:16 AM UTC 24 Oct 15 01:09:25 AM UTC 24 52114194 ps
T3711 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_walk.2734685901 Oct 15 01:09:13 AM UTC 24 Oct 15 01:09:25 AM UTC 24 166591031 ps
T3712 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_csr_rw.723098332 Oct 15 01:09:24 AM UTC 24 Oct 15 01:09:26 AM UTC 24 48965376 ps
T3713 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1911647577 Oct 15 01:09:16 AM UTC 24 Oct 15 01:09:26 AM UTC 24 297433271 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_intr_test.3158440306 Oct 15 01:09:24 AM UTC 24 Oct 15 01:09:26 AM UTC 24 128401804 ps
T3714 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1735451553 Oct 15 01:09:16 AM UTC 24 Oct 15 01:09:26 AM UTC 24 74470581 ps
T3715 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_aliasing.3034105860 Oct 15 01:09:16 AM UTC 24 Oct 15 01:09:26 AM UTC 24 167243505 ps
T3716 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2061792171 Oct 15 01:09:24 AM UTC 24 Oct 15 01:09:26 AM UTC 24 73645093 ps
T3717 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.4253819406 Oct 15 01:09:24 AM UTC 24 Oct 15 01:09:26 AM UTC 24 124671890 ps
T3718 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4105576862 Oct 15 01:09:24 AM UTC 24 Oct 15 01:09:26 AM UTC 24 120740661 ps
T3719 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_errors.1493507574 Oct 15 01:08:58 AM UTC 24 Oct 15 01:09:26 AM UTC 24 283815928 ps
T3720 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_errors.1887814478 Oct 15 01:09:16 AM UTC 24 Oct 15 01:09:26 AM UTC 24 226945292 ps
T3721 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3323057490 Oct 15 01:09:24 AM UTC 24 Oct 15 01:09:27 AM UTC 24 202143575 ps
T3722 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_errors.2426131285 Oct 15 01:09:24 AM UTC 24 Oct 15 01:09:27 AM UTC 24 142389930 ps
T3723 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_tl_errors.901984072 Oct 15 01:09:24 AM UTC 24 Oct 15 01:09:27 AM UTC 24 97949515 ps
T511 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_tl_intg_err.2320898104 Oct 15 01:09:18 AM UTC 24 Oct 15 01:09:27 AM UTC 24 898931742 ps
T508 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_tl_intg_err.3988388649 Oct 15 01:09:22 AM UTC 24 Oct 15 01:09:28 AM UTC 24 900350241 ps
T509 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_intg_err.261185726 Oct 15 01:09:16 AM UTC 24 Oct 15 01:09:29 AM UTC 24 812300617 ps
T3724 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_tl_intg_err.472509623 Oct 15 01:09:24 AM UTC 24 Oct 15 01:09:29 AM UTC 24 794630017 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/38.usbdev_intr_test.2804268784 Oct 15 01:09:49 AM UTC 24 Oct 15 01:09:51 AM UTC 24 68025443 ps
T3725 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/29.usbdev_intr_test.1414785313 Oct 15 01:09:49 AM UTC 24 Oct 15 01:09:52 AM UTC 24 39954590 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_intr_test.4096009077 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:33 AM UTC 24 40667938 ps
T3726 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_rw.1606647175 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:33 AM UTC 24 57231683 ps
T3727 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_intr_test.2075056910 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:34 AM UTC 24 35658131 ps
T3728 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_intr_test.2808705041 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:34 AM UTC 24 50373934 ps
T3729 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_rw.2941989002 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:34 AM UTC 24 68443869 ps
T3730 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1487282058 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:34 AM UTC 24 111139517 ps
T3731 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_rw.1165073262 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:34 AM UTC 24 62728340 ps
T3732 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.346956478 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:34 AM UTC 24 207087086 ps
T3733 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1637311078 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:34 AM UTC 24 73430701 ps
T3734 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_errors.917854650 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:35 AM UTC 24 101870811 ps
T3735 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_errors.3191339385 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:35 AM UTC 24 121080981 ps
T3736 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3953275806 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:35 AM UTC 24 125666208 ps
T3737 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_errors.1736399782 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:35 AM UTC 24 198311748 ps
T3738 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/41.usbdev_intr_test.1867228824 Oct 15 01:09:49 AM UTC 24 Oct 15 01:09:51 AM UTC 24 49134790 ps
T512 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_intg_err.1460981603 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:37 AM UTC 24 804555313 ps
T3739 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_intr_test.435789131 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:37 AM UTC 24 56925621 ps
T3740 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_intr_test.37671734 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:37 AM UTC 24 40317991 ps
T513 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_intg_err.992295719 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:37 AM UTC 24 1192722387 ps
T3741 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_intr_test.3648992438 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:37 AM UTC 24 88309683 ps
T3742 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_rw.3528703435 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:38 AM UTC 24 92117682 ps
T3743 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_rw.2367873666 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:38 AM UTC 24 106842038 ps
T3744 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_rw.2989361745 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:38 AM UTC 24 57289547 ps
T3745 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3162356612 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:38 AM UTC 24 111432969 ps
T3746 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_intg_err.264111088 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:38 AM UTC 24 1412037988 ps
T3747 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.281342352 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:38 AM UTC 24 79462070 ps
T3748 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3059810727 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:38 AM UTC 24 89780705 ps
T3749 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2744938449 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:38 AM UTC 24 140136678 ps
T3750 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1567839047 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:38 AM UTC 24 108313520 ps
T3751 /workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_errors.234566952 Oct 15 01:09:32 AM UTC 24 Oct 15 01:09:38 AM UTC 24 131489799 ps
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