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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.44 98.11 95.91 97.44 87.30 98.22 98.17 92.94


Total test records in report: 3732
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T451 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/77.usbdev_endpoint_types.1083532162 Feb 08 06:18:14 PM UTC 25 Feb 08 06:18:17 PM UTC 25 479346234 ps
T3143 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/79.usbdev_tx_rx_disruption.3208813070 Feb 08 06:18:14 PM UTC 25 Feb 08 06:18:17 PM UTC 25 427432695 ps
T3144 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/77.usbdev_tx_rx_disruption.2897235518 Feb 08 06:18:14 PM UTC 25 Feb 08 06:18:17 PM UTC 25 502787115 ps
T3145 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/78.usbdev_tx_rx_disruption.2730782186 Feb 08 06:18:14 PM UTC 25 Feb 08 06:18:17 PM UTC 25 463194953 ps
T455 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/81.usbdev_endpoint_types.3934758961 Feb 08 06:18:14 PM UTC 25 Feb 08 06:18:17 PM UTC 25 422219820 ps
T3146 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/76.usbdev_tx_rx_disruption.482757152 Feb 08 06:18:14 PM UTC 25 Feb 08 06:18:17 PM UTC 25 463074372 ps
T3147 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_streaming_out.3034413953 Feb 08 06:16:58 PM UTC 25 Feb 08 06:18:17 PM UTC 25 2594084357 ps
T3148 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/80.usbdev_tx_rx_disruption.3078706348 Feb 08 06:18:14 PM UTC 25 Feb 08 06:18:17 PM UTC 25 581270720 ps
T3149 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/81.usbdev_tx_rx_disruption.3883527186 Feb 08 06:18:14 PM UTC 25 Feb 08 06:18:17 PM UTC 25 495530207 ps
T3150 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/82.usbdev_tx_rx_disruption.2299703635 Feb 08 06:18:14 PM UTC 25 Feb 08 06:18:17 PM UTC 25 532080046 ps
T3151 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_low_speed_traffic.3349205487 Feb 08 06:16:51 PM UTC 25 Feb 08 06:18:17 PM UTC 25 3177151420 ps
T346 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/83.usbdev_endpoint_types.3160685491 Feb 08 06:18:14 PM UTC 25 Feb 08 06:18:18 PM UTC 25 698913461 ps
T3152 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/83.usbdev_tx_rx_disruption.1435831419 Feb 08 06:18:14 PM UTC 25 Feb 08 06:18:18 PM UTC 25 606787821 ps
T364 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/84.usbdev_endpoint_types.1295335490 Feb 08 06:18:14 PM UTC 25 Feb 08 06:18:18 PM UTC 25 685334743 ps
T343 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/80.usbdev_endpoint_types.570872689 Feb 08 06:18:14 PM UTC 25 Feb 08 06:18:18 PM UTC 25 799860282 ps
T3153 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_low_speed_traffic.3184602844 Feb 08 06:17:52 PM UTC 25 Feb 08 06:18:18 PM UTC 25 2722979029 ps
T3154 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/89.usbdev_endpoint_types.2398027763 Feb 08 06:18:16 PM UTC 25 Feb 08 06:18:18 PM UTC 25 267780348 ps
T3155 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/88.usbdev_endpoint_types.1665430250 Feb 08 06:18:16 PM UTC 25 Feb 08 06:18:18 PM UTC 25 246102114 ps
T359 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/85.usbdev_endpoint_types.244875350 Feb 08 06:18:16 PM UTC 25 Feb 08 06:18:19 PM UTC 25 400805739 ps
T3156 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/85.usbdev_tx_rx_disruption.2614778097 Feb 08 06:18:16 PM UTC 25 Feb 08 06:18:19 PM UTC 25 590697866 ps
T3157 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/86.usbdev_tx_rx_disruption.1597223902 Feb 08 06:18:16 PM UTC 25 Feb 08 06:18:19 PM UTC 25 494014330 ps
T452 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/87.usbdev_endpoint_types.3123000325 Feb 08 06:18:16 PM UTC 25 Feb 08 06:18:19 PM UTC 25 480508848 ps
T412 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/86.usbdev_endpoint_types.2747437596 Feb 08 06:18:16 PM UTC 25 Feb 08 06:18:19 PM UTC 25 613486062 ps
T350 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/90.usbdev_endpoint_types.719764717 Feb 08 06:18:16 PM UTC 25 Feb 08 06:18:19 PM UTC 25 508638390 ps
T3158 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/88.usbdev_tx_rx_disruption.4285449842 Feb 08 06:18:16 PM UTC 25 Feb 08 06:18:19 PM UTC 25 572972367 ps
T3159 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/89.usbdev_tx_rx_disruption.4181831180 Feb 08 06:18:16 PM UTC 25 Feb 08 06:18:19 PM UTC 25 438149448 ps
T3160 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/87.usbdev_tx_rx_disruption.4044743922 Feb 08 06:18:16 PM UTC 25 Feb 08 06:18:19 PM UTC 25 667390271 ps
T3161 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/84.usbdev_tx_rx_disruption.3004621153 Feb 08 06:18:16 PM UTC 25 Feb 08 06:18:19 PM UTC 25 541082249 ps
T3162 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/91.usbdev_endpoint_types.1022707106 Feb 08 06:18:17 PM UTC 25 Feb 08 06:18:20 PM UTC 25 364348029 ps
T3163 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/94.usbdev_endpoint_types.1332593042 Feb 08 06:18:18 PM UTC 25 Feb 08 06:18:20 PM UTC 25 172014795 ps
T3164 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/95.usbdev_endpoint_types.3891664340 Feb 08 06:18:18 PM UTC 25 Feb 08 06:18:20 PM UTC 25 259746763 ps
T440 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/93.usbdev_endpoint_types.2235970770 Feb 08 06:18:17 PM UTC 25 Feb 08 06:18:20 PM UTC 25 249322441 ps
T3165 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_pkt_buffer.1660465423 Feb 08 06:17:57 PM UTC 25 Feb 08 06:18:20 PM UTC 25 8867091409 ps
T3166 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/92.usbdev_tx_rx_disruption.2469276833 Feb 08 06:18:17 PM UTC 25 Feb 08 06:18:20 PM UTC 25 391756554 ps
T371 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/92.usbdev_endpoint_types.3831092124 Feb 08 06:18:17 PM UTC 25 Feb 08 06:18:20 PM UTC 25 593915229 ps
T3167 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/94.usbdev_tx_rx_disruption.3696117994 Feb 08 06:18:18 PM UTC 25 Feb 08 06:18:21 PM UTC 25 468671174 ps
T3168 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/91.usbdev_tx_rx_disruption.272233429 Feb 08 06:18:17 PM UTC 25 Feb 08 06:18:21 PM UTC 25 663660857 ps
T3169 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/93.usbdev_tx_rx_disruption.3352363174 Feb 08 06:18:17 PM UTC 25 Feb 08 06:18:21 PM UTC 25 517095761 ps
T3170 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/90.usbdev_tx_rx_disruption.595392784 Feb 08 06:18:17 PM UTC 25 Feb 08 06:18:21 PM UTC 25 521571569 ps
T446 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/96.usbdev_endpoint_types.3269293418 Feb 08 06:18:19 PM UTC 25 Feb 08 06:18:22 PM UTC 25 223715392 ps
T469 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/99.usbdev_endpoint_types.3815226517 Feb 08 06:18:19 PM UTC 25 Feb 08 06:18:22 PM UTC 25 266785079 ps
T3171 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/98.usbdev_tx_rx_disruption.237686959 Feb 08 06:18:19 PM UTC 25 Feb 08 06:18:22 PM UTC 25 464263548 ps
T449 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/100.usbdev_endpoint_types.791923361 Feb 08 06:18:20 PM UTC 25 Feb 08 06:18:22 PM UTC 25 325730801 ps
T3172 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/95.usbdev_tx_rx_disruption.3112356549 Feb 08 06:18:19 PM UTC 25 Feb 08 06:18:22 PM UTC 25 479634326 ps
T3173 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/97.usbdev_tx_rx_disruption.2338804235 Feb 08 06:18:19 PM UTC 25 Feb 08 06:18:22 PM UTC 25 502343718 ps
T394 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/97.usbdev_endpoint_types.1693215736 Feb 08 06:18:19 PM UTC 25 Feb 08 06:18:22 PM UTC 25 705215460 ps
T347 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/98.usbdev_endpoint_types.1701945614 Feb 08 06:18:19 PM UTC 25 Feb 08 06:18:22 PM UTC 25 714668924 ps
T3174 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/96.usbdev_tx_rx_disruption.1774756111 Feb 08 06:18:19 PM UTC 25 Feb 08 06:18:23 PM UTC 25 520444890 ps
T432 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/102.usbdev_endpoint_types.97691928 Feb 08 06:18:20 PM UTC 25 Feb 08 06:18:23 PM UTC 25 439017757 ps
T3175 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/100.usbdev_tx_rx_disruption.3898816801 Feb 08 06:18:20 PM UTC 25 Feb 08 06:18:23 PM UTC 25 538822040 ps
T380 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/103.usbdev_endpoint_types.509251937 Feb 08 06:18:20 PM UTC 25 Feb 08 06:18:23 PM UTC 25 459298378 ps
T3176 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_spurious_pids_ignored.77266569 Feb 08 06:17:59 PM UTC 25 Feb 08 06:18:23 PM UTC 25 3085304681 ps
T403 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/101.usbdev_endpoint_types.1032956768 Feb 08 06:18:20 PM UTC 25 Feb 08 06:18:23 PM UTC 25 815257370 ps
T189 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/103.usbdev_tx_rx_disruption.870671293 Feb 08 06:18:20 PM UTC 25 Feb 08 06:18:23 PM UTC 25 561266355 ps
T356 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/104.usbdev_endpoint_types.2752507509 Feb 08 06:18:20 PM UTC 25 Feb 08 06:18:23 PM UTC 25 583688175 ps
T3177 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/102.usbdev_tx_rx_disruption.9404795 Feb 08 06:18:20 PM UTC 25 Feb 08 06:18:23 PM UTC 25 542206870 ps
T3178 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/99.usbdev_tx_rx_disruption.2973572370 Feb 08 06:18:20 PM UTC 25 Feb 08 06:18:23 PM UTC 25 560728715 ps
T3179 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/104.usbdev_tx_rx_disruption.1037904310 Feb 08 06:18:20 PM UTC 25 Feb 08 06:18:23 PM UTC 25 549720531 ps
T3180 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/101.usbdev_tx_rx_disruption.4065672000 Feb 08 06:18:20 PM UTC 25 Feb 08 06:18:23 PM UTC 25 557538550 ps
T3181 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_min_inter_pkt_delay.1422681054 Feb 08 06:17:54 PM UTC 25 Feb 08 06:18:24 PM UTC 25 2774949555 ps
T413 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/105.usbdev_endpoint_types.339019940 Feb 08 06:18:21 PM UTC 25 Feb 08 06:18:24 PM UTC 25 275687805 ps
T3182 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/106.usbdev_endpoint_types.4039862442 Feb 08 06:18:22 PM UTC 25 Feb 08 06:18:24 PM UTC 25 276443346 ps
T464 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/110.usbdev_endpoint_types.4113554411 Feb 08 06:18:22 PM UTC 25 Feb 08 06:18:24 PM UTC 25 173785408 ps
T3183 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/107.usbdev_endpoint_types.3187412456 Feb 08 06:18:22 PM UTC 25 Feb 08 06:18:24 PM UTC 25 266357020 ps
T406 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/109.usbdev_endpoint_types.2767677622 Feb 08 06:18:22 PM UTC 25 Feb 08 06:18:24 PM UTC 25 343167208 ps
T3184 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/106.usbdev_tx_rx_disruption.465676224 Feb 08 06:18:22 PM UTC 25 Feb 08 06:18:24 PM UTC 25 485381228 ps
T3185 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/112.usbdev_endpoint_types.2018592460 Feb 08 06:18:22 PM UTC 25 Feb 08 06:18:25 PM UTC 25 237987182 ps
T453 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/111.usbdev_endpoint_types.184779712 Feb 08 06:18:22 PM UTC 25 Feb 08 06:18:25 PM UTC 25 357330502 ps
T3186 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/107.usbdev_tx_rx_disruption.3222136319 Feb 08 06:18:22 PM UTC 25 Feb 08 06:18:25 PM UTC 25 507499164 ps
T3187 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/105.usbdev_tx_rx_disruption.3776021801 Feb 08 06:18:21 PM UTC 25 Feb 08 06:18:25 PM UTC 25 606726125 ps
T3188 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/108.usbdev_tx_rx_disruption.3343138211 Feb 08 06:18:22 PM UTC 25 Feb 08 06:18:25 PM UTC 25 501581240 ps
T3189 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/108.usbdev_endpoint_types.560686619 Feb 08 06:18:22 PM UTC 25 Feb 08 06:18:25 PM UTC 25 642253122 ps
T3190 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/111.usbdev_tx_rx_disruption.1406709175 Feb 08 06:18:22 PM UTC 25 Feb 08 06:18:25 PM UTC 25 460938688 ps
T3191 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/109.usbdev_tx_rx_disruption.3663332755 Feb 08 06:18:22 PM UTC 25 Feb 08 06:18:25 PM UTC 25 647088467 ps
T3192 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/110.usbdev_tx_rx_disruption.1498882061 Feb 08 06:18:22 PM UTC 25 Feb 08 06:18:25 PM UTC 25 520767729 ps
T3193 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_iso_retraction.3111397616 Feb 08 06:17:49 PM UTC 25 Feb 08 06:18:26 PM UTC 25 4738259476 ps
T3194 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/116.usbdev_endpoint_types.1702809320 Feb 08 06:18:24 PM UTC 25 Feb 08 06:18:26 PM UTC 25 161051784 ps
T3195 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/140.usbdev_endpoint_types.1094972102 Feb 08 06:18:30 PM UTC 25 Feb 08 06:18:32 PM UTC 25 243978835 ps
T460 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/115.usbdev_endpoint_types.1411782666 Feb 08 06:18:24 PM UTC 25 Feb 08 06:18:26 PM UTC 25 197901299 ps
T479 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/114.usbdev_endpoint_types.3893590913 Feb 08 06:18:24 PM UTC 25 Feb 08 06:18:26 PM UTC 25 287699461 ps
T202 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/113.usbdev_tx_rx_disruption.510507496 Feb 08 06:18:24 PM UTC 25 Feb 08 06:18:26 PM UTC 25 571954647 ps
T438 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/119.usbdev_endpoint_types.4022685212 Feb 08 06:18:24 PM UTC 25 Feb 08 06:18:27 PM UTC 25 222244707 ps
T3196 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/114.usbdev_tx_rx_disruption.662613884 Feb 08 06:18:24 PM UTC 25 Feb 08 06:18:27 PM UTC 25 448319538 ps
T3197 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/112.usbdev_tx_rx_disruption.561582487 Feb 08 06:18:23 PM UTC 25 Feb 08 06:18:27 PM UTC 25 644514533 ps
T351 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/118.usbdev_endpoint_types.382695197 Feb 08 06:18:24 PM UTC 25 Feb 08 06:18:27 PM UTC 25 368832892 ps
T458 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/117.usbdev_endpoint_types.1145600284 Feb 08 06:18:24 PM UTC 25 Feb 08 06:18:27 PM UTC 25 373222310 ps
T3198 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/120.usbdev_endpoint_types.1334412016 Feb 08 06:18:24 PM UTC 25 Feb 08 06:18:27 PM UTC 25 264765751 ps
T404 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/113.usbdev_endpoint_types.2274331545 Feb 08 06:18:24 PM UTC 25 Feb 08 06:18:27 PM UTC 25 669112389 ps
T120 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/115.usbdev_tx_rx_disruption.189843560 Feb 08 06:18:24 PM UTC 25 Feb 08 06:18:27 PM UTC 25 603392109 ps
T3199 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/116.usbdev_tx_rx_disruption.502741319 Feb 08 06:18:24 PM UTC 25 Feb 08 06:18:27 PM UTC 25 590159294 ps
T3200 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/120.usbdev_tx_rx_disruption.423576872 Feb 08 06:18:24 PM UTC 25 Feb 08 06:18:27 PM UTC 25 635280761 ps
T168 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/118.usbdev_tx_rx_disruption.3736832467 Feb 08 06:18:24 PM UTC 25 Feb 08 06:18:27 PM UTC 25 623725488 ps
T3201 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/117.usbdev_tx_rx_disruption.2271143338 Feb 08 06:18:24 PM UTC 25 Feb 08 06:18:27 PM UTC 25 517128128 ps
T3202 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/119.usbdev_tx_rx_disruption.2035520039 Feb 08 06:18:24 PM UTC 25 Feb 08 06:18:27 PM UTC 25 558534211 ps
T3203 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/121.usbdev_endpoint_types.498936476 Feb 08 06:18:26 PM UTC 25 Feb 08 06:18:28 PM UTC 25 161171039 ps
T3204 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/122.usbdev_endpoint_types.2469038544 Feb 08 06:18:26 PM UTC 25 Feb 08 06:18:28 PM UTC 25 295156810 ps
T344 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/124.usbdev_endpoint_types.503277157 Feb 08 06:18:26 PM UTC 25 Feb 08 06:18:29 PM UTC 25 234178923 ps
T3205 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/121.usbdev_tx_rx_disruption.583625194 Feb 08 06:18:26 PM UTC 25 Feb 08 06:18:29 PM UTC 25 557125313 ps
T472 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/123.usbdev_endpoint_types.3745841538 Feb 08 06:18:26 PM UTC 25 Feb 08 06:18:29 PM UTC 25 462821478 ps
T491 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/125.usbdev_endpoint_types.2818034951 Feb 08 06:18:26 PM UTC 25 Feb 08 06:18:29 PM UTC 25 308921862 ps
T3206 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/128.usbdev_endpoint_types.1957154502 Feb 08 06:18:26 PM UTC 25 Feb 08 06:18:29 PM UTC 25 170791688 ps
T3207 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/130.usbdev_endpoint_types.411174900 Feb 08 06:18:26 PM UTC 25 Feb 08 06:18:29 PM UTC 25 248252973 ps
T457 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/126.usbdev_endpoint_types.2838424959 Feb 08 06:18:26 PM UTC 25 Feb 08 06:18:29 PM UTC 25 366066368 ps
T190 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/123.usbdev_tx_rx_disruption.4043664940 Feb 08 06:18:26 PM UTC 25 Feb 08 06:18:29 PM UTC 25 489161530 ps
T3208 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/122.usbdev_tx_rx_disruption.3028659580 Feb 08 06:18:26 PM UTC 25 Feb 08 06:18:29 PM UTC 25 587384273 ps
T3209 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/129.usbdev_endpoint_types.1937233322 Feb 08 06:18:26 PM UTC 25 Feb 08 06:18:29 PM UTC 25 280175967 ps
T3210 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/126.usbdev_tx_rx_disruption.680331880 Feb 08 06:18:26 PM UTC 25 Feb 08 06:18:29 PM UTC 25 483954542 ps
T3211 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/124.usbdev_tx_rx_disruption.1137935001 Feb 08 06:18:26 PM UTC 25 Feb 08 06:18:29 PM UTC 25 617092126 ps
T3212 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/125.usbdev_tx_rx_disruption.1424007172 Feb 08 06:18:26 PM UTC 25 Feb 08 06:18:29 PM UTC 25 527596830 ps
T3213 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/129.usbdev_tx_rx_disruption.1141056206 Feb 08 06:18:26 PM UTC 25 Feb 08 06:18:29 PM UTC 25 475777954 ps
T3214 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/127.usbdev_tx_rx_disruption.2110024687 Feb 08 06:18:26 PM UTC 25 Feb 08 06:18:29 PM UTC 25 598209064 ps
T419 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/127.usbdev_endpoint_types.1944138450 Feb 08 06:18:26 PM UTC 25 Feb 08 06:18:29 PM UTC 25 723872440 ps
T3215 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/128.usbdev_tx_rx_disruption.3031059315 Feb 08 06:18:26 PM UTC 25 Feb 08 06:18:29 PM UTC 25 617732396 ps
T3216 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_aon_wake_resume.625138114 Feb 08 06:17:45 PM UTC 25 Feb 08 06:18:30 PM UTC 25 26266270778 ps
T3217 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/135.usbdev_endpoint_types.3613648580 Feb 08 06:18:28 PM UTC 25 Feb 08 06:18:31 PM UTC 25 290109631 ps
T386 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/131.usbdev_endpoint_types.2075040712 Feb 08 06:18:28 PM UTC 25 Feb 08 06:18:31 PM UTC 25 410315941 ps
T379 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/134.usbdev_endpoint_types.636397747 Feb 08 06:18:28 PM UTC 25 Feb 08 06:18:31 PM UTC 25 498560813 ps
T409 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/132.usbdev_endpoint_types.1084325262 Feb 08 06:18:28 PM UTC 25 Feb 08 06:18:31 PM UTC 25 483889996 ps
T3218 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/136.usbdev_endpoint_types.1920770854 Feb 08 06:18:28 PM UTC 25 Feb 08 06:18:31 PM UTC 25 341447832 ps
T3219 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/133.usbdev_tx_rx_disruption.2457776207 Feb 08 06:18:28 PM UTC 25 Feb 08 06:18:31 PM UTC 25 508303726 ps
T3220 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/138.usbdev_endpoint_types.1475274304 Feb 08 06:18:28 PM UTC 25 Feb 08 06:18:31 PM UTC 25 228536848 ps
T3221 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/132.usbdev_tx_rx_disruption.102540938 Feb 08 06:18:28 PM UTC 25 Feb 08 06:18:31 PM UTC 25 534416816 ps
T3222 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/134.usbdev_tx_rx_disruption.2974799421 Feb 08 06:18:28 PM UTC 25 Feb 08 06:18:31 PM UTC 25 466717892 ps
T436 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/137.usbdev_endpoint_types.214660862 Feb 08 06:18:28 PM UTC 25 Feb 08 06:18:31 PM UTC 25 290252057 ps
T3223 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/131.usbdev_tx_rx_disruption.1245320397 Feb 08 06:18:28 PM UTC 25 Feb 08 06:18:31 PM UTC 25 578008342 ps
T3224 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/130.usbdev_tx_rx_disruption.3650777086 Feb 08 06:18:28 PM UTC 25 Feb 08 06:18:31 PM UTC 25 600687565 ps
T421 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/139.usbdev_endpoint_types.2290781487 Feb 08 06:18:28 PM UTC 25 Feb 08 06:18:31 PM UTC 25 453173165 ps
T408 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/133.usbdev_endpoint_types.1937660235 Feb 08 06:18:28 PM UTC 25 Feb 08 06:18:32 PM UTC 25 625993242 ps
T3225 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/135.usbdev_tx_rx_disruption.488595858 Feb 08 06:18:28 PM UTC 25 Feb 08 06:18:32 PM UTC 25 614899589 ps
T3226 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/137.usbdev_tx_rx_disruption.2097250980 Feb 08 06:18:28 PM UTC 25 Feb 08 06:18:32 PM UTC 25 599645585 ps
T3227 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_link_resume.298621749 Feb 08 06:17:51 PM UTC 25 Feb 08 06:18:32 PM UTC 25 25039226798 ps
T3228 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/136.usbdev_tx_rx_disruption.2658646491 Feb 08 06:18:28 PM UTC 25 Feb 08 06:18:32 PM UTC 25 527649828 ps
T3229 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/138.usbdev_tx_rx_disruption.523494871 Feb 08 06:18:28 PM UTC 25 Feb 08 06:18:32 PM UTC 25 645273016 ps
T3230 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/141.usbdev_endpoint_types.2514744805 Feb 08 06:18:30 PM UTC 25 Feb 08 06:18:33 PM UTC 25 222741493 ps
T3231 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/47.usbdev_low_speed_traffic.2033599262 Feb 08 06:17:09 PM UTC 25 Feb 08 06:18:33 PM UTC 25 2990719355 ps
T3232 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_device_timeout.3970314671 Feb 08 06:17:46 PM UTC 25 Feb 08 06:18:33 PM UTC 25 1952353320 ps
T3233 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/146.usbdev_endpoint_types.3710125942 Feb 08 06:18:30 PM UTC 25 Feb 08 06:18:33 PM UTC 25 163075412 ps
T3234 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_min_inter_pkt_delay.3379897988 Feb 08 06:17:33 PM UTC 25 Feb 08 06:18:33 PM UTC 25 2145070059 ps
T3235 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/144.usbdev_endpoint_types.2648751969 Feb 08 06:18:30 PM UTC 25 Feb 08 06:18:33 PM UTC 25 324754891 ps
T3236 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/145.usbdev_endpoint_types.620476965 Feb 08 06:18:30 PM UTC 25 Feb 08 06:18:33 PM UTC 25 337322168 ps
T3237 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/140.usbdev_tx_rx_disruption.1409773644 Feb 08 06:18:30 PM UTC 25 Feb 08 06:18:33 PM UTC 25 591001875 ps
T370 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/147.usbdev_endpoint_types.2859565368 Feb 08 06:18:30 PM UTC 25 Feb 08 06:18:33 PM UTC 25 284294039 ps
T352 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/142.usbdev_endpoint_types.2495602769 Feb 08 06:18:30 PM UTC 25 Feb 08 06:18:33 PM UTC 25 613493582 ps
T3238 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/141.usbdev_tx_rx_disruption.4065240160 Feb 08 06:18:30 PM UTC 25 Feb 08 06:18:33 PM UTC 25 488875247 ps
T3239 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/143.usbdev_endpoint_types.467278925 Feb 08 06:18:30 PM UTC 25 Feb 08 06:18:33 PM UTC 25 461944345 ps
T3240 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/139.usbdev_tx_rx_disruption.4043597588 Feb 08 06:18:30 PM UTC 25 Feb 08 06:18:33 PM UTC 25 549217408 ps
T3241 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/148.usbdev_endpoint_types.116252564 Feb 08 06:18:31 PM UTC 25 Feb 08 06:18:33 PM UTC 25 410803469 ps
T3242 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/143.usbdev_tx_rx_disruption.979141708 Feb 08 06:18:30 PM UTC 25 Feb 08 06:18:33 PM UTC 25 580911216 ps
T3243 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/146.usbdev_tx_rx_disruption.558698650 Feb 08 06:18:30 PM UTC 25 Feb 08 06:18:33 PM UTC 25 519093169 ps
T3244 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/144.usbdev_tx_rx_disruption.1126180146 Feb 08 06:18:30 PM UTC 25 Feb 08 06:18:33 PM UTC 25 411216721 ps
T3245 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/142.usbdev_tx_rx_disruption.1630907389 Feb 08 06:18:30 PM UTC 25 Feb 08 06:18:34 PM UTC 25 630685667 ps
T3246 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/145.usbdev_tx_rx_disruption.1162766028 Feb 08 06:18:30 PM UTC 25 Feb 08 06:18:34 PM UTC 25 505436907 ps
T3247 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/147.usbdev_tx_rx_disruption.1053146859 Feb 08 06:18:31 PM UTC 25 Feb 08 06:18:34 PM UTC 25 562158947 ps
T3248 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/148.usbdev_tx_rx_disruption.1029090644 Feb 08 06:18:31 PM UTC 25 Feb 08 06:18:34 PM UTC 25 516547693 ps
T3249 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_low_speed_traffic.1422316796 Feb 08 06:16:31 PM UTC 25 Feb 08 06:18:34 PM UTC 25 4446997191 ps
T3250 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/151.usbdev_endpoint_types.3895407573 Feb 08 06:18:32 PM UTC 25 Feb 08 06:18:34 PM UTC 25 207229028 ps
T433 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/150.usbdev_endpoint_types.1487403989 Feb 08 06:18:32 PM UTC 25 Feb 08 06:18:35 PM UTC 25 417283639 ps
T3251 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/153.usbdev_endpoint_types.1812630175 Feb 08 06:18:32 PM UTC 25 Feb 08 06:18:35 PM UTC 25 251888073 ps
T3252 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/151.usbdev_tx_rx_disruption.489936991 Feb 08 06:18:32 PM UTC 25 Feb 08 06:18:35 PM UTC 25 420836647 ps
T3253 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/149.usbdev_endpoint_types.4118491298 Feb 08 06:18:32 PM UTC 25 Feb 08 06:18:35 PM UTC 25 569484444 ps
T3254 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/149.usbdev_tx_rx_disruption.3926937590 Feb 08 06:18:32 PM UTC 25 Feb 08 06:18:35 PM UTC 25 623110813 ps
T493 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/152.usbdev_endpoint_types.3075096355 Feb 08 06:18:32 PM UTC 25 Feb 08 06:18:35 PM UTC 25 508332639 ps
T3255 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/150.usbdev_tx_rx_disruption.557967948 Feb 08 06:18:32 PM UTC 25 Feb 08 06:18:35 PM UTC 25 563675717 ps
T3256 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/153.usbdev_tx_rx_disruption.1937423761 Feb 08 06:18:32 PM UTC 25 Feb 08 06:18:35 PM UTC 25 486565287 ps
T3257 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_device_address.3800494690 Feb 08 06:17:46 PM UTC 25 Feb 08 06:18:35 PM UTC 25 22358077178 ps
T3258 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/152.usbdev_tx_rx_disruption.973302240 Feb 08 06:18:32 PM UTC 25 Feb 08 06:18:35 PM UTC 25 520242598 ps
T3259 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/154.usbdev_tx_rx_disruption.1767522214 Feb 08 06:18:32 PM UTC 25 Feb 08 06:18:35 PM UTC 25 602197415 ps
T415 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/154.usbdev_endpoint_types.1179672307 Feb 08 06:18:32 PM UTC 25 Feb 08 06:18:35 PM UTC 25 677550748 ps
T354 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/167.usbdev_endpoint_types.3752402826 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:37 PM UTC 25 438460607 ps
T475 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/155.usbdev_endpoint_types.4107887661 Feb 08 06:18:34 PM UTC 25 Feb 08 06:18:38 PM UTC 25 220434343 ps
T3260 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/166.usbdev_tx_rx_disruption.2841421189 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:38 PM UTC 25 514139095 ps
T3261 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/166.usbdev_endpoint_types.3884886807 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:38 PM UTC 25 498539623 ps
T3262 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/165.usbdev_tx_rx_disruption.3350607996 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:38 PM UTC 25 502373399 ps
T3263 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/156.usbdev_endpoint_types.2467962233 Feb 08 06:18:34 PM UTC 25 Feb 08 06:18:38 PM UTC 25 379026616 ps
T3264 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/158.usbdev_endpoint_types.824357393 Feb 08 06:18:34 PM UTC 25 Feb 08 06:18:38 PM UTC 25 226239615 ps
T3265 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/167.usbdev_tx_rx_disruption.28052152 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:38 PM UTC 25 610964916 ps
T477 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/159.usbdev_endpoint_types.649776671 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:38 PM UTC 25 351535104 ps
T3266 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/165.usbdev_endpoint_types.1121398072 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:38 PM UTC 25 153452714 ps
T3267 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/155.usbdev_tx_rx_disruption.3855277189 Feb 08 06:18:34 PM UTC 25 Feb 08 06:18:38 PM UTC 25 613997291 ps
T381 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/161.usbdev_endpoint_types.1681407249 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:38 PM UTC 25 278460974 ps
T478 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/157.usbdev_endpoint_types.4047072840 Feb 08 06:18:34 PM UTC 25 Feb 08 06:18:38 PM UTC 25 521014154 ps
T169 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/157.usbdev_tx_rx_disruption.1416377989 Feb 08 06:18:34 PM UTC 25 Feb 08 06:18:38 PM UTC 25 481997965 ps
T3268 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/169.usbdev_endpoint_types.1105108888 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:38 PM UTC 25 187013498 ps
T483 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/162.usbdev_endpoint_types.304879059 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:38 PM UTC 25 309158759 ps
T3269 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/156.usbdev_tx_rx_disruption.1280542645 Feb 08 06:18:34 PM UTC 25 Feb 08 06:18:38 PM UTC 25 537745180 ps
T3270 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/158.usbdev_tx_rx_disruption.556170978 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:39 PM UTC 25 456634835 ps
T3271 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/164.usbdev_endpoint_types.323718056 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:39 PM UTC 25 269659738 ps
T3272 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/160.usbdev_tx_rx_disruption.39362791 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:39 PM UTC 25 483442560 ps
T3273 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/159.usbdev_tx_rx_disruption.2549310963 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:39 PM UTC 25 628662170 ps
T422 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/160.usbdev_endpoint_types.3722830058 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:39 PM UTC 25 704230320 ps
T3274 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/164.usbdev_tx_rx_disruption.2887633208 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:39 PM UTC 25 513390454 ps
T3275 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/161.usbdev_tx_rx_disruption.2582747637 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:39 PM UTC 25 531709327 ps
T3276 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/162.usbdev_tx_rx_disruption.485211780 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:39 PM UTC 25 476238296 ps
T3277 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/168.usbdev_tx_rx_disruption.3329509736 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:39 PM UTC 25 564342193 ps
T3278 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/163.usbdev_tx_rx_disruption.2103337699 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:39 PM UTC 25 560916501 ps
T392 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/163.usbdev_endpoint_types.2380863494 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:39 PM UTC 25 652310464 ps
T3279 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/169.usbdev_tx_rx_disruption.1357852915 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:39 PM UTC 25 457663698 ps
T435 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/168.usbdev_endpoint_types.2123463588 Feb 08 06:18:35 PM UTC 25 Feb 08 06:18:39 PM UTC 25 639810956 ps
T481 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/175.usbdev_endpoint_types.4281151828 Feb 08 06:18:37 PM UTC 25 Feb 08 06:18:43 PM UTC 25 167472085 ps
T3280 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/170.usbdev_endpoint_types.1883533568 Feb 08 06:18:37 PM UTC 25 Feb 08 06:18:43 PM UTC 25 226945339 ps
T3281 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/171.usbdev_endpoint_types.3665344947 Feb 08 06:18:37 PM UTC 25 Feb 08 06:18:43 PM UTC 25 168640506 ps
T3282 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/173.usbdev_endpoint_types.1496428441 Feb 08 06:18:37 PM UTC 25 Feb 08 06:18:43 PM UTC 25 239861977 ps
T416 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/172.usbdev_endpoint_types.3916062746 Feb 08 06:18:37 PM UTC 25 Feb 08 06:18:43 PM UTC 25 227574469 ps
T467 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/174.usbdev_endpoint_types.1337654407 Feb 08 06:18:37 PM UTC 25 Feb 08 06:18:43 PM UTC 25 282657770 ps
T3283 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/173.usbdev_tx_rx_disruption.2224012833 Feb 08 06:18:37 PM UTC 25 Feb 08 06:18:43 PM UTC 25 483772639 ps
T3284 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/170.usbdev_tx_rx_disruption.2314188565 Feb 08 06:18:37 PM UTC 25 Feb 08 06:18:43 PM UTC 25 477596900 ps
T3285 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/172.usbdev_tx_rx_disruption.4089965987 Feb 08 06:18:37 PM UTC 25 Feb 08 06:18:43 PM UTC 25 461508308 ps
T3286 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/171.usbdev_tx_rx_disruption.3200279632 Feb 08 06:18:37 PM UTC 25 Feb 08 06:18:43 PM UTC 25 652630040 ps
T3287 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/176.usbdev_tx_rx_disruption.1866486797 Feb 08 06:18:37 PM UTC 25 Feb 08 06:18:43 PM UTC 25 545627923 ps
T3288 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/175.usbdev_tx_rx_disruption.4017481311 Feb 08 06:18:37 PM UTC 25 Feb 08 06:18:43 PM UTC 25 576660994 ps
T3289 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/174.usbdev_tx_rx_disruption.2427871300 Feb 08 06:18:37 PM UTC 25 Feb 08 06:18:43 PM UTC 25 617599137 ps
T3290 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/49.usbdev_max_inter_pkt_delay.1306402378 Feb 08 06:17:52 PM UTC 25 Feb 08 06:18:47 PM UTC 25 2127300603 ps
T3291 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_max_inter_pkt_delay.728381724 Feb 08 06:17:31 PM UTC 25 Feb 08 06:18:48 PM UTC 25 2911661059 ps
T3292 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/193.usbdev_endpoint_types.119349534 Feb 08 06:18:43 PM UTC 25 Feb 08 06:18:49 PM UTC 25 317833090 ps
T3293 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/192.usbdev_endpoint_types.3003488296 Feb 08 06:18:43 PM UTC 25 Feb 08 06:18:49 PM UTC 25 280474251 ps
T3294 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/194.usbdev_endpoint_types.2235021023 Feb 08 06:18:43 PM UTC 25 Feb 08 06:18:49 PM UTC 25 348439485 ps
T3295 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/193.usbdev_tx_rx_disruption.1414857891 Feb 08 06:18:43 PM UTC 25 Feb 08 06:18:49 PM UTC 25 464251747 ps
T3296 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/192.usbdev_tx_rx_disruption.3812701860 Feb 08 06:18:43 PM UTC 25 Feb 08 06:18:49 PM UTC 25 508155243 ps
T3297 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/194.usbdev_tx_rx_disruption.2989971465 Feb 08 06:18:43 PM UTC 25 Feb 08 06:18:50 PM UTC 25 650784848 ps
T3298 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/238.usbdev_tx_rx_disruption.1769000727 Feb 08 06:19:05 PM UTC 25 Feb 08 06:19:10 PM UTC 25 542815167 ps
T490 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/180.usbdev_endpoint_types.451971682 Feb 08 06:18:40 PM UTC 25 Feb 08 06:18:53 PM UTC 25 164887833 ps
T3299 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/183.usbdev_endpoint_types.753120121 Feb 08 06:18:40 PM UTC 25 Feb 08 06:18:53 PM UTC 25 236792668 ps
T3300 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/185.usbdev_endpoint_types.2054340358 Feb 08 06:18:41 PM UTC 25 Feb 08 06:18:53 PM UTC 25 247360765 ps
T3301 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/182.usbdev_endpoint_types.2971805891 Feb 08 06:18:40 PM UTC 25 Feb 08 06:18:53 PM UTC 25 331490140 ps
T3302 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/181.usbdev_tx_rx_disruption.179688176 Feb 08 06:18:40 PM UTC 25 Feb 08 06:18:53 PM UTC 25 620574762 ps
T3303 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/181.usbdev_endpoint_types.3335489112 Feb 08 06:18:40 PM UTC 25 Feb 08 06:18:53 PM UTC 25 374597325 ps
T3304 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/195.usbdev_endpoint_types.2272829114 Feb 08 06:18:44 PM UTC 25 Feb 08 06:18:53 PM UTC 25 424721079 ps
T373 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/188.usbdev_endpoint_types.1728684179 Feb 08 06:18:41 PM UTC 25 Feb 08 06:18:54 PM UTC 25 478887023 ps
T355 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/176.usbdev_endpoint_types.281110513 Feb 08 06:18:37 PM UTC 25 Feb 08 06:18:54 PM UTC 25 468379592 ps
T3305 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/195.usbdev_tx_rx_disruption.60064406 Feb 08 06:18:45 PM UTC 25 Feb 08 06:18:54 PM UTC 25 518443507 ps
T441 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/196.usbdev_endpoint_types.409292186 Feb 08 06:18:45 PM UTC 25 Feb 08 06:18:54 PM UTC 25 600633501 ps
T3306 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/187.usbdev_endpoint_types.1157033927 Feb 08 06:18:41 PM UTC 25 Feb 08 06:18:54 PM UTC 25 549466431 ps
T3307 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/180.usbdev_tx_rx_disruption.708769287 Feb 08 06:18:40 PM UTC 25 Feb 08 06:18:54 PM UTC 25 583813267 ps
T3308 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/196.usbdev_tx_rx_disruption.3516466480 Feb 08 06:18:45 PM UTC 25 Feb 08 06:18:54 PM UTC 25 482056141 ps
T170 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/183.usbdev_tx_rx_disruption.1843419562 Feb 08 06:18:40 PM UTC 25 Feb 08 06:18:54 PM UTC 25 618312568 ps
T3309 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/184.usbdev_endpoint_types.592596947 Feb 08 06:18:41 PM UTC 25 Feb 08 06:18:54 PM UTC 25 578732986 ps
T3310 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/197.usbdev_tx_rx_disruption.396255908 Feb 08 06:18:45 PM UTC 25 Feb 08 06:18:54 PM UTC 25 530312312 ps
T3311 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/187.usbdev_tx_rx_disruption.3480640564 Feb 08 06:18:41 PM UTC 25 Feb 08 06:18:54 PM UTC 25 532963373 ps
T3312 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/182.usbdev_tx_rx_disruption.1581989100 Feb 08 06:18:40 PM UTC 25 Feb 08 06:18:54 PM UTC 25 556409471 ps
T3313 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_streaming_out.2674103687 Feb 08 06:17:42 PM UTC 25 Feb 08 06:18:54 PM UTC 25 2643901146 ps
T3314 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/184.usbdev_tx_rx_disruption.356114245 Feb 08 06:18:41 PM UTC 25 Feb 08 06:18:54 PM UTC 25 609201313 ps
T3315 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/48.usbdev_iso_retraction.2700326603 Feb 08 06:17:30 PM UTC 25 Feb 08 06:18:54 PM UTC 25 11653233688 ps
T3316 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/199.usbdev_endpoint_types.1384165113 Feb 08 06:18:49 PM UTC 25 Feb 08 06:18:58 PM UTC 25 305254227 ps
T3317 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/212.usbdev_tx_rx_disruption.1479097333 Feb 08 06:18:55 PM UTC 25 Feb 08 06:18:59 PM UTC 25 429135227 ps
T3318 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/198.usbdev_tx_rx_disruption.94624367 Feb 08 06:18:49 PM UTC 25 Feb 08 06:18:59 PM UTC 25 529758918 ps
T3319 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/211.usbdev_tx_rx_disruption.958267144 Feb 08 06:18:55 PM UTC 25 Feb 08 06:18:59 PM UTC 25 522398370 ps
T3320 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/208.usbdev_tx_rx_disruption.35642894 Feb 08 06:18:55 PM UTC 25 Feb 08 06:18:59 PM UTC 25 492697498 ps
T3321 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/207.usbdev_tx_rx_disruption.3240719865 Feb 08 06:18:55 PM UTC 25 Feb 08 06:18:59 PM UTC 25 667423053 ps
T3322 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/186.usbdev_tx_rx_disruption.2497334506 Feb 08 06:18:41 PM UTC 25 Feb 08 06:19:03 PM UTC 25 517905908 ps
T3323 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/189.usbdev_endpoint_types.657696821 Feb 08 06:18:41 PM UTC 25 Feb 08 06:19:03 PM UTC 25 441948994 ps