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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.44 98.11 95.91 97.44 87.30 98.22 98.17 92.94


Total test records in report: 3732
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T1960 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_setup_stage.1435444756 Feb 08 06:11:25 PM UTC 25 Feb 08 06:11:28 PM UTC 25 145002372 ps
T1961 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_rx_full.833996924 Feb 08 06:11:25 PM UTC 25 Feb 08 06:11:28 PM UTC 25 311491506 ps
T1962 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_stall_priority_over_nak.213161653 Feb 08 06:11:25 PM UTC 25 Feb 08 06:11:28 PM UTC 25 235850302 ps
T1963 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_setup_stage.2067901536 Feb 08 06:11:46 PM UTC 25 Feb 08 06:11:49 PM UTC 25 194203910 ps
T1964 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_alert_test.4236756846 Feb 08 06:11:27 PM UTC 25 Feb 08 06:11:29 PM UTC 25 67106657 ps
T1965 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_stall_trans.1898862769 Feb 08 06:11:27 PM UTC 25 Feb 08 06:11:29 PM UTC 25 152692357 ps
T1966 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_tx_rx_disruption.1938252668 Feb 08 06:11:27 PM UTC 25 Feb 08 06:11:30 PM UTC 25 474541532 ps
T1967 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_av_buffer.3430649776 Feb 08 06:11:28 PM UTC 25 Feb 08 06:11:31 PM UTC 25 153051535 ps
T207 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_aon_wake_reset.3210257285 Feb 08 06:11:10 PM UTC 25 Feb 08 06:11:31 PM UTC 25 15183135096 ps
T1968 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_link_suspend.3377115371 Feb 08 06:11:18 PM UTC 25 Feb 08 06:11:32 PM UTC 25 4319045290 ps
T1969 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_data_toggle_clear.1769648271 Feb 08 06:11:30 PM UTC 25 Feb 08 06:11:32 PM UTC 25 257536939 ps
T1970 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_streaming_out.668166561 Feb 08 06:10:52 PM UTC 25 Feb 08 06:11:32 PM UTC 25 1518982788 ps
T1971 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_spurious_pids_ignored.1358606457 Feb 08 06:11:08 PM UTC 25 Feb 08 06:11:32 PM UTC 25 2030708283 ps
T1972 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_bitstuff_err.4179991933 Feb 08 06:11:30 PM UTC 25 Feb 08 06:11:32 PM UTC 25 163790900 ps
T1973 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_streaming_out.3127689445 Feb 08 06:11:08 PM UTC 25 Feb 08 06:11:32 PM UTC 25 2045066434 ps
T1974 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_rx_full.3223665457 Feb 08 06:11:45 PM UTC 25 Feb 08 06:11:48 PM UTC 25 482203388 ps
T1975 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_data_toggle_restore.564249887 Feb 08 06:11:30 PM UTC 25 Feb 08 06:11:34 PM UTC 25 877834529 ps
T1976 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_disconnected.2023525311 Feb 08 06:11:32 PM UTC 25 Feb 08 06:11:34 PM UTC 25 158647517 ps
T1977 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_stream_len_max.3780976392 Feb 08 06:11:27 PM UTC 25 Feb 08 06:11:35 PM UTC 25 1397290266 ps
T1978 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_disable_endpoint.4102768612 Feb 08 06:11:32 PM UTC 25 Feb 08 06:11:36 PM UTC 25 820663757 ps
T1979 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_enable.1367603159 Feb 08 06:11:34 PM UTC 25 Feb 08 06:11:36 PM UTC 25 48232215 ps
T361 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_endpoint_types.1360877988 Feb 08 06:11:34 PM UTC 25 Feb 08 06:11:36 PM UTC 25 244142065 ps
T1980 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_in_iso.1727096471 Feb 08 06:11:34 PM UTC 25 Feb 08 06:11:37 PM UTC 25 250402721 ps
T1981 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_fifo_rst.2658975984 Feb 08 06:11:34 PM UTC 25 Feb 08 06:11:37 PM UTC 25 177529267 ps
T1982 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_in_stall.237729638 Feb 08 06:11:35 PM UTC 25 Feb 08 06:11:38 PM UTC 25 146718484 ps
T1983 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_timeout_missing_host_handshake.1178975398 Feb 08 06:11:15 PM UTC 25 Feb 08 06:11:38 PM UTC 25 985567101 ps
T1984 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_in_trans.1637964045 Feb 08 06:11:35 PM UTC 25 Feb 08 06:11:38 PM UTC 25 215018155 ps
T1985 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_endpoint_access.932855413 Feb 08 06:11:34 PM UTC 25 Feb 08 06:11:39 PM UTC 25 1037517241 ps
T1986 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_link_in_err.501046502 Feb 08 06:11:37 PM UTC 25 Feb 08 06:11:39 PM UTC 25 192517648 ps
T1987 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_spurious_pids_ignored.3223581147 Feb 08 06:10:29 PM UTC 25 Feb 08 06:11:39 PM UTC 25 2534687859 ps
T1988 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_min_inter_pkt_delay.2800906468 Feb 08 06:11:01 PM UTC 25 Feb 08 06:11:40 PM UTC 25 4185085889 ps
T1989 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_timeout_missing_host_handshake.803724766 Feb 08 06:10:55 PM UTC 25 Feb 08 06:11:41 PM UTC 25 1780274585 ps
T1990 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_device_address.2433865037 Feb 08 06:10:33 PM UTC 25 Feb 08 06:11:41 PM UTC 25 39594341296 ps
T1991 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_max_length_out_transaction.1129169622 Feb 08 06:11:38 PM UTC 25 Feb 08 06:11:41 PM UTC 25 226582478 ps
T1992 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_max_length_in_transaction.2950622811 Feb 08 06:11:38 PM UTC 25 Feb 08 06:11:41 PM UTC 25 253368819 ps
T1993 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_aon_wake_disconnect.530852056 Feb 08 06:11:28 PM UTC 25 Feb 08 06:11:42 PM UTC 25 7068881534 ps
T1994 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_min_length_in_transaction.2269258200 Feb 08 06:11:39 PM UTC 25 Feb 08 06:11:42 PM UTC 25 174661617 ps
T1995 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_min_length_out_transaction.2455705750 Feb 08 06:11:39 PM UTC 25 Feb 08 06:11:42 PM UTC 25 139348697 ps
T1996 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_out_stall.1803230610 Feb 08 06:11:41 PM UTC 25 Feb 08 06:11:43 PM UTC 25 149922089 ps
T1997 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_out_iso.4189688026 Feb 08 06:11:41 PM UTC 25 Feb 08 06:11:43 PM UTC 25 155803157 ps
T1998 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_max_inter_pkt_delay.3116397982 Feb 08 06:11:19 PM UTC 25 Feb 08 06:11:43 PM UTC 25 2141995021 ps
T1999 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_aon_wake_resume.879606565 Feb 08 06:10:52 PM UTC 25 Feb 08 06:11:43 PM UTC 25 28774491501 ps
T146 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_nak_trans.2938316562 Feb 08 06:11:41 PM UTC 25 Feb 08 06:11:44 PM UTC 25 227294082 ps
T2000 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_min_inter_pkt_delay.551562443 Feb 08 06:11:20 PM UTC 25 Feb 08 06:11:44 PM UTC 25 2047848983 ps
T2001 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_out_trans_nak.837213388 Feb 08 06:11:43 PM UTC 25 Feb 08 06:11:46 PM UTC 25 167903796 ps
T2002 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_phy_pins_sense.414215533 Feb 08 06:11:43 PM UTC 25 Feb 08 06:11:46 PM UTC 25 50407875 ps
T2003 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_phy_config_usb_ref_disable.72978878 Feb 08 06:11:43 PM UTC 25 Feb 08 06:11:46 PM UTC 25 162205322 ps
T2004 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_pending_in_trans.4124033334 Feb 08 06:11:43 PM UTC 25 Feb 08 06:11:46 PM UTC 25 158106273 ps
T2005 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_pkt_received.1402772992 Feb 08 06:11:43 PM UTC 25 Feb 08 06:11:46 PM UTC 25 171159289 ps
T2006 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_device_timeout.548733582 Feb 08 06:11:31 PM UTC 25 Feb 08 06:11:46 PM UTC 25 1575879990 ps
T2007 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_max_inter_pkt_delay.2010956479 Feb 08 06:10:41 PM UTC 25 Feb 08 06:11:46 PM UTC 25 2068153547 ps
T2008 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_phy_config_pinflip.3031877814 Feb 08 06:11:43 PM UTC 25 Feb 08 06:11:46 PM UTC 25 233551899 ps
T2009 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_random_length_in_transaction.2708949986 Feb 08 06:11:44 PM UTC 25 Feb 08 06:11:47 PM UTC 25 202008457 ps
T2010 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_random_length_out_transaction.413113070 Feb 08 06:11:45 PM UTC 25 Feb 08 06:11:47 PM UTC 25 191754210 ps
T2011 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_pkt_sent.3045520722 Feb 08 06:11:44 PM UTC 25 Feb 08 06:11:47 PM UTC 25 170724192 ps
T2012 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_rx_crc_err.3517131405 Feb 08 06:11:45 PM UTC 25 Feb 08 06:11:48 PM UTC 25 236922765 ps
T2013 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_low_speed_traffic.99449084 Feb 08 06:10:58 PM UTC 25 Feb 08 06:11:48 PM UTC 25 3948323904 ps
T2014 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_device_address.2183180111 Feb 08 06:11:12 PM UTC 25 Feb 08 06:11:48 PM UTC 25 19910921914 ps
T2015 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_setup_trans_ignored.259735517 Feb 08 06:11:47 PM UTC 25 Feb 08 06:11:50 PM UTC 25 169059165 ps
T2016 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_stall_priority_over_nak.3218320530 Feb 08 06:11:47 PM UTC 25 Feb 08 06:11:50 PM UTC 25 199503228 ps
T2017 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_smoke.3006753219 Feb 08 06:11:47 PM UTC 25 Feb 08 06:11:50 PM UTC 25 199090699 ps
T2018 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_stall_trans.2439694235 Feb 08 06:11:47 PM UTC 25 Feb 08 06:11:51 PM UTC 25 251806384 ps
T119 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_tx_rx_disruption.4222871407 Feb 08 06:11:48 PM UTC 25 Feb 08 06:11:51 PM UTC 25 643918727 ps
T2019 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_link_resume.2944957869 Feb 08 06:11:18 PM UTC 25 Feb 08 06:11:51 PM UTC 25 15230697449 ps
T2020 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_in_iso.2687455268 Feb 08 06:12:13 PM UTC 25 Feb 08 06:12:17 PM UTC 25 258295846 ps
T2021 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_alert_test.1246667648 Feb 08 06:11:49 PM UTC 25 Feb 08 06:11:52 PM UTC 25 37588294 ps
T2022 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_stream_len_max.3932516462 Feb 08 06:11:48 PM UTC 25 Feb 08 06:11:52 PM UTC 25 960589015 ps
T2023 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_bitstuff_err.1472044043 Feb 08 06:11:49 PM UTC 25 Feb 08 06:11:52 PM UTC 25 169339329 ps
T2024 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_av_buffer.379898546 Feb 08 06:11:49 PM UTC 25 Feb 08 06:11:52 PM UTC 25 220460368 ps
T2025 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_data_toggle_clear.3428979304 Feb 08 06:11:49 PM UTC 25 Feb 08 06:11:53 PM UTC 25 362889213 ps
T2026 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_link_suspend.298507941 Feb 08 06:11:37 PM UTC 25 Feb 08 06:11:54 PM UTC 25 9490438394 ps
T2027 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_enable.2082534704 Feb 08 06:11:52 PM UTC 25 Feb 08 06:11:55 PM UTC 25 54853700 ps
T2028 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_disconnected.2404289735 Feb 08 06:11:52 PM UTC 25 Feb 08 06:11:55 PM UTC 25 142009166 ps
T2029 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_data_toggle_restore.131970180 Feb 08 06:11:51 PM UTC 25 Feb 08 06:11:55 PM UTC 25 611317817 ps
T2030 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_device_address.911494009 Feb 08 06:10:53 PM UTC 25 Feb 08 06:12:17 PM UTC 25 33366715154 ps
T2031 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_link_resume.1148877485 Feb 08 06:10:58 PM UTC 25 Feb 08 06:11:56 PM UTC 25 32689658679 ps
T2032 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_in_stall.975307649 Feb 08 06:11:54 PM UTC 25 Feb 08 06:11:56 PM UTC 25 146547608 ps
T2033 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_in_iso.3407616612 Feb 08 06:11:54 PM UTC 25 Feb 08 06:11:57 PM UTC 25 253579915 ps
T2034 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_disable_endpoint.3225042272 Feb 08 06:11:52 PM UTC 25 Feb 08 06:11:57 PM UTC 25 970666489 ps
T383 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_endpoint_types.1339839825 Feb 08 06:11:52 PM UTC 25 Feb 08 06:11:57 PM UTC 25 681327662 ps
T2035 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_in_trans.4047098291 Feb 08 06:11:54 PM UTC 25 Feb 08 06:11:57 PM UTC 25 231631001 ps
T2036 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_device_timeout.139507047 Feb 08 06:11:15 PM UTC 25 Feb 08 06:11:57 PM UTC 25 5501942769 ps
T2037 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_fifo_rst.3994794967 Feb 08 06:11:53 PM UTC 25 Feb 08 06:11:58 PM UTC 25 313891158 ps
T2038 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_link_in_err.3471720053 Feb 08 06:11:55 PM UTC 25 Feb 08 06:11:58 PM UTC 25 212036716 ps
T2039 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_endpoint_access.1045215481 Feb 08 06:11:52 PM UTC 25 Feb 08 06:11:58 PM UTC 25 1040067743 ps
T2040 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_aon_wake_resume.2205061588 Feb 08 06:11:11 PM UTC 25 Feb 08 06:11:58 PM UTC 25 30416234929 ps
T2041 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_low_speed_traffic.4118312837 Feb 08 06:11:19 PM UTC 25 Feb 08 06:12:00 PM UTC 25 3999033975 ps
T2042 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_timeout_missing_host_handshake.1972066950 Feb 08 06:11:31 PM UTC 25 Feb 08 06:12:00 PM UTC 25 1173011504 ps
T2043 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_max_length_in_transaction.1050062186 Feb 08 06:11:58 PM UTC 25 Feb 08 06:12:00 PM UTC 25 234475589 ps
T2044 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_max_length_out_transaction.558192687 Feb 08 06:11:58 PM UTC 25 Feb 08 06:12:01 PM UTC 25 209025369 ps
T2045 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_min_length_out_transaction.1909918430 Feb 08 06:11:58 PM UTC 25 Feb 08 06:12:01 PM UTC 25 156054960 ps
T2046 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_min_length_in_transaction.2156966774 Feb 08 06:11:58 PM UTC 25 Feb 08 06:12:01 PM UTC 25 158302211 ps
T2047 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_out_iso.3087035420 Feb 08 06:11:59 PM UTC 25 Feb 08 06:12:02 PM UTC 25 170918717 ps
T2048 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_out_stall.1395533521 Feb 08 06:11:59 PM UTC 25 Feb 08 06:12:02 PM UTC 25 217391492 ps
T2049 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_out_trans_nak.2808350787 Feb 08 06:12:00 PM UTC 25 Feb 08 06:12:02 PM UTC 25 219219449 ps
T130 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_nak_trans.3855804806 Feb 08 06:11:59 PM UTC 25 Feb 08 06:12:03 PM UTC 25 288007510 ps
T2050 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_pkt_buffer.2500278351 Feb 08 06:11:05 PM UTC 25 Feb 08 06:12:03 PM UTC 25 20156419613 ps
T2051 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_phy_config_usb_ref_disable.2479807864 Feb 08 06:12:01 PM UTC 25 Feb 08 06:12:03 PM UTC 25 162216853 ps
T2052 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_pending_in_trans.3369785964 Feb 08 06:12:01 PM UTC 25 Feb 08 06:12:03 PM UTC 25 229353066 ps
T2053 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_device_address.600491648 Feb 08 06:10:10 PM UTC 25 Feb 08 06:12:03 PM UTC 25 46329272324 ps
T2054 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_phy_config_pinflip.1721135124 Feb 08 06:12:01 PM UTC 25 Feb 08 06:12:04 PM UTC 25 264853870 ps
T2055 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_phy_pins_sense.1351024522 Feb 08 06:12:02 PM UTC 25 Feb 08 06:12:05 PM UTC 25 34687407 ps
T2056 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/24.usbdev_low_speed_traffic.1616973540 Feb 08 06:09:58 PM UTC 25 Feb 08 06:12:05 PM UTC 25 4590798575 ps
T2057 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_pkt_received.3839138736 Feb 08 06:12:02 PM UTC 25 Feb 08 06:12:05 PM UTC 25 160213116 ps
T2058 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_pkt_sent.1737489278 Feb 08 06:12:04 PM UTC 25 Feb 08 06:12:07 PM UTC 25 159272818 ps
T2059 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_random_length_in_transaction.187695132 Feb 08 06:12:04 PM UTC 25 Feb 08 06:12:07 PM UTC 25 175908511 ps
T2060 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_random_length_out_transaction.3647901071 Feb 08 06:12:04 PM UTC 25 Feb 08 06:12:07 PM UTC 25 232822476 ps
T2061 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_rx_crc_err.2857511838 Feb 08 06:12:04 PM UTC 25 Feb 08 06:12:07 PM UTC 25 180580620 ps
T2062 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_setup_stage.3932052048 Feb 08 06:12:04 PM UTC 25 Feb 08 06:12:07 PM UTC 25 166854420 ps
T2063 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_rx_full.3659320757 Feb 08 06:12:04 PM UTC 25 Feb 08 06:12:08 PM UTC 25 371036486 ps
T2064 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/25.usbdev_min_inter_pkt_delay.4166287865 Feb 08 06:10:20 PM UTC 25 Feb 08 06:12:08 PM UTC 25 4066312326 ps
T2065 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_setup_trans_ignored.1382399928 Feb 08 06:12:07 PM UTC 25 Feb 08 06:12:10 PM UTC 25 166022179 ps
T2066 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_aon_wake_disconnect.3878951736 Feb 08 06:11:49 PM UTC 25 Feb 08 06:12:10 PM UTC 25 9237651899 ps
T2067 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_stall_trans.4235357153 Feb 08 06:12:07 PM UTC 25 Feb 08 06:12:10 PM UTC 25 184120838 ps
T2068 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_smoke.1106813194 Feb 08 06:12:07 PM UTC 25 Feb 08 06:12:10 PM UTC 25 223447118 ps
T2069 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_stall_priority_over_nak.2500561561 Feb 08 06:12:07 PM UTC 25 Feb 08 06:12:10 PM UTC 25 171835420 ps
T2070 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_pkt_buffer.3858269742 Feb 08 06:11:43 PM UTC 25 Feb 08 06:12:10 PM UTC 25 9561628059 ps
T2071 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_data_toggle_clear.2522271573 Feb 08 06:12:12 PM UTC 25 Feb 08 06:12:15 PM UTC 25 290149558 ps
T384 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_endpoint_types.20883019 Feb 08 06:12:13 PM UTC 25 Feb 08 06:12:16 PM UTC 25 435393446 ps
T2072 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_link_suspend.2814966534 Feb 08 06:11:56 PM UTC 25 Feb 08 06:12:11 PM UTC 25 3874084512 ps
T2073 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_alert_test.3357563984 Feb 08 06:12:09 PM UTC 25 Feb 08 06:12:11 PM UTC 25 37107414 ps
T2074 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_spurious_pids_ignored.4031021595 Feb 08 06:11:47 PM UTC 25 Feb 08 06:12:11 PM UTC 25 2663195575 ps
T2075 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_streaming_out.829684209 Feb 08 06:11:27 PM UTC 25 Feb 08 06:12:12 PM UTC 25 1687740440 ps
T2076 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_av_buffer.3509624109 Feb 08 06:12:10 PM UTC 25 Feb 08 06:12:12 PM UTC 25 167020952 ps
T2077 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_tx_rx_disruption.1279142975 Feb 08 06:12:09 PM UTC 25 Feb 08 06:12:13 PM UTC 25 474169758 ps
T2078 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_stream_len_max.2488993259 Feb 08 06:12:08 PM UTC 25 Feb 08 06:12:13 PM UTC 25 649867508 ps
T2079 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_aon_wake_resume.3900231064 Feb 08 06:11:28 PM UTC 25 Feb 08 06:12:13 PM UTC 25 25659137524 ps
T2080 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_max_inter_pkt_delay.3846020610 Feb 08 06:10:59 PM UTC 25 Feb 08 06:12:13 PM UTC 25 2496628455 ps
T2081 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_disconnected.1288544466 Feb 08 06:12:12 PM UTC 25 Feb 08 06:12:14 PM UTC 25 154714283 ps
T2082 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_max_inter_pkt_delay.1390061944 Feb 08 06:11:58 PM UTC 25 Feb 08 06:12:14 PM UTC 25 1905913266 ps
T2083 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_enable.741685294 Feb 08 06:12:12 PM UTC 25 Feb 08 06:12:14 PM UTC 25 35294964 ps
T2084 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_bitstuff_err.1715996130 Feb 08 06:12:12 PM UTC 25 Feb 08 06:12:14 PM UTC 25 150644489 ps
T2085 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_aon_wake_reset.3335842328 Feb 08 06:11:49 PM UTC 25 Feb 08 06:12:15 PM UTC 25 13381494036 ps
T2086 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_data_toggle_restore.710358390 Feb 08 06:12:12 PM UTC 25 Feb 08 06:12:15 PM UTC 25 463319320 ps
T2087 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_disable_endpoint.2103143866 Feb 08 06:12:12 PM UTC 25 Feb 08 06:12:15 PM UTC 25 831146811 ps
T2088 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_invalid_sync.3460737737 Feb 08 06:11:53 PM UTC 25 Feb 08 06:12:16 PM UTC 25 2847558881 ps
T2089 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_min_inter_pkt_delay.2375668243 Feb 08 06:11:58 PM UTC 25 Feb 08 06:12:17 PM UTC 25 1855909795 ps
T2090 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_fifo_rst.3585447084 Feb 08 06:12:13 PM UTC 25 Feb 08 06:12:17 PM UTC 25 268458343 ps
T2091 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_in_trans.846622293 Feb 08 06:12:15 PM UTC 25 Feb 08 06:12:18 PM UTC 25 231570781 ps
T2092 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_link_in_err.2981678805 Feb 08 06:12:15 PM UTC 25 Feb 08 06:12:18 PM UTC 25 245764083 ps
T2093 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_min_inter_pkt_delay.1399585594 Feb 08 06:11:39 PM UTC 25 Feb 08 06:12:18 PM UTC 25 3653288292 ps
T2094 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_pkt_buffer.117122724 Feb 08 06:11:22 PM UTC 25 Feb 08 06:12:18 PM UTC 25 20340270428 ps
T2095 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_endpoint_access.3571283073 Feb 08 06:12:13 PM UTC 25 Feb 08 06:12:19 PM UTC 25 890738337 ps
T2096 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_iso_retraction.3625034717 Feb 08 06:11:17 PM UTC 25 Feb 08 06:12:19 PM UTC 25 8187696115 ps
T2097 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_timeout_missing_host_handshake.2163009090 Feb 08 06:12:12 PM UTC 25 Feb 08 06:12:19 PM UTC 25 748711234 ps
T2098 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_max_length_out_transaction.1313394939 Feb 08 06:12:17 PM UTC 25 Feb 08 06:12:19 PM UTC 25 193253348 ps
T2099 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_max_length_in_transaction.802637715 Feb 08 06:12:16 PM UTC 25 Feb 08 06:12:19 PM UTC 25 278198138 ps
T2100 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_device_timeout.1463992811 Feb 08 06:11:51 PM UTC 25 Feb 08 06:12:21 PM UTC 25 1343936405 ps
T2101 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_min_length_in_transaction.2525883142 Feb 08 06:12:19 PM UTC 25 Feb 08 06:12:21 PM UTC 25 165225041 ps
T141 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_nak_trans.2493634446 Feb 08 06:12:19 PM UTC 25 Feb 08 06:12:21 PM UTC 25 226731647 ps
T2102 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_out_stall.2546148426 Feb 08 06:12:19 PM UTC 25 Feb 08 06:12:21 PM UTC 25 171798162 ps
T2103 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_phy_config_usb_ref_disable.3201245137 Feb 08 06:12:19 PM UTC 25 Feb 08 06:12:21 PM UTC 25 155664731 ps
T2104 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_min_length_out_transaction.654485170 Feb 08 06:12:19 PM UTC 25 Feb 08 06:12:22 PM UTC 25 195018464 ps
T2105 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_out_trans_nak.507662499 Feb 08 06:12:19 PM UTC 25 Feb 08 06:12:22 PM UTC 25 190407563 ps
T2106 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_pending_in_trans.1590706244 Feb 08 06:12:19 PM UTC 25 Feb 08 06:12:22 PM UTC 25 154042153 ps
T2107 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_out_iso.1228102154 Feb 08 06:12:19 PM UTC 25 Feb 08 06:12:22 PM UTC 25 176421370 ps
T2108 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_aon_wake_disconnect.3834719016 Feb 08 06:12:09 PM UTC 25 Feb 08 06:12:22 PM UTC 25 7117800079 ps
T2109 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_phy_config_pinflip.3072791917 Feb 08 06:12:19 PM UTC 25 Feb 08 06:12:22 PM UTC 25 204257610 ps
T2110 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_phy_pins_sense.1054040409 Feb 08 06:12:21 PM UTC 25 Feb 08 06:12:23 PM UTC 25 32967858 ps
T2111 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_rx_crc_err.3185278474 Feb 08 06:12:21 PM UTC 25 Feb 08 06:12:24 PM UTC 25 176191358 ps
T2112 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_pkt_received.3640028994 Feb 08 06:12:21 PM UTC 25 Feb 08 06:12:24 PM UTC 25 202927099 ps
T2113 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_random_length_out_transaction.2659882906 Feb 08 06:12:21 PM UTC 25 Feb 08 06:12:24 PM UTC 25 199467188 ps
T2114 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_pkt_sent.3213907470 Feb 08 06:12:21 PM UTC 25 Feb 08 06:12:24 PM UTC 25 235312977 ps
T2115 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_random_length_in_transaction.431131004 Feb 08 06:12:21 PM UTC 25 Feb 08 06:12:24 PM UTC 25 166065398 ps
T2116 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_setup_trans_ignored.3290244258 Feb 08 06:12:23 PM UTC 25 Feb 08 06:12:25 PM UTC 25 212451238 ps
T2117 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_setup_stage.2938296616 Feb 08 06:12:23 PM UTC 25 Feb 08 06:12:25 PM UTC 25 171714218 ps
T2118 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_stall_priority_over_nak.1727089209 Feb 08 06:12:23 PM UTC 25 Feb 08 06:12:25 PM UTC 25 169226494 ps
T2119 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_iso_retraction.1924573490 Feb 08 06:10:37 PM UTC 25 Feb 08 06:12:26 PM UTC 25 13372524709 ps
T2120 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_timeout_missing_host_handshake.4249173120 Feb 08 06:11:51 PM UTC 25 Feb 08 06:12:26 PM UTC 25 5035016603 ps
T2121 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_smoke.3684489202 Feb 08 06:12:23 PM UTC 25 Feb 08 06:12:26 PM UTC 25 229163055 ps
T2122 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_stall_trans.3331471605 Feb 08 06:12:23 PM UTC 25 Feb 08 06:12:26 PM UTC 25 156589770 ps
T2123 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_invalid_sync.211787486 Feb 08 06:11:17 PM UTC 25 Feb 08 06:12:26 PM UTC 25 2582615227 ps
T2124 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_rx_full.3175176684 Feb 08 06:12:23 PM UTC 25 Feb 08 06:12:26 PM UTC 25 364450945 ps
T2125 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_alert_test.1201045424 Feb 08 06:12:24 PM UTC 25 Feb 08 06:12:26 PM UTC 25 64476387 ps
T2126 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_tx_rx_disruption.2997967187 Feb 08 06:12:23 PM UTC 25 Feb 08 06:12:27 PM UTC 25 513980770 ps
T2127 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_stream_len_max.1434812361 Feb 08 06:12:23 PM UTC 25 Feb 08 06:12:27 PM UTC 25 829696256 ps
T504 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_low_speed_traffic.3286229645 Feb 08 06:11:37 PM UTC 25 Feb 08 06:12:27 PM UTC 25 4971606973 ps
T2128 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_link_suspend.3865506749 Feb 08 06:12:15 PM UTC 25 Feb 08 06:12:28 PM UTC 25 6149950720 ps
T2129 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_av_buffer.3576811733 Feb 08 06:12:26 PM UTC 25 Feb 08 06:12:28 PM UTC 25 200166564 ps
T2130 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_bitstuff_err.895455886 Feb 08 06:12:26 PM UTC 25 Feb 08 06:12:28 PM UTC 25 141210049 ps
T2131 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_low_speed_traffic.2010205041 Feb 08 06:11:57 PM UTC 25 Feb 08 06:12:29 PM UTC 25 3682378802 ps
T2132 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_link_resume.2894640979 Feb 08 06:12:15 PM UTC 25 Feb 08 06:12:29 PM UTC 25 6788232921 ps
T2133 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_enable.2801280815 Feb 08 06:12:28 PM UTC 25 Feb 08 06:12:30 PM UTC 25 40520742 ps
T2134 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_data_toggle_clear.4183586020 Feb 08 06:12:28 PM UTC 25 Feb 08 06:12:30 PM UTC 25 382877659 ps
T2135 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_iso_retraction.4168001771 Feb 08 06:10:58 PM UTC 25 Feb 08 06:12:31 PM UTC 25 13857257511 ps
T2136 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_disconnected.2090150400 Feb 08 06:12:28 PM UTC 25 Feb 08 06:12:31 PM UTC 25 174979217 ps
T439 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_endpoint_types.3054313926 Feb 08 06:12:28 PM UTC 25 Feb 08 06:12:31 PM UTC 25 347330425 ps
T2137 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_in_stall.4232644506 Feb 08 06:12:29 PM UTC 25 Feb 08 06:12:32 PM UTC 25 136046091 ps
T2138 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_fifo_rst.398075052 Feb 08 06:12:28 PM UTC 25 Feb 08 06:12:32 PM UTC 25 167107521 ps
T2139 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_in_trans.4245861262 Feb 08 06:12:29 PM UTC 25 Feb 08 06:12:32 PM UTC 25 183745126 ps
T2140 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_endpoint_access.727605771 Feb 08 06:12:28 PM UTC 25 Feb 08 06:12:32 PM UTC 25 786016149 ps
T2141 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_in_iso.503882702 Feb 08 06:12:29 PM UTC 25 Feb 08 06:12:32 PM UTC 25 213214742 ps
T2142 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_link_in_err.2786838347 Feb 08 06:12:30 PM UTC 25 Feb 08 06:12:32 PM UTC 25 280023617 ps
T2143 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_disable_endpoint.2982307781 Feb 08 06:12:28 PM UTC 25 Feb 08 06:12:32 PM UTC 25 680430291 ps
T2144 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_data_toggle_restore.3276348285 Feb 08 06:12:28 PM UTC 25 Feb 08 06:12:33 PM UTC 25 1042588665 ps
T2145 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_aon_wake_resume.3216643271 Feb 08 06:11:49 PM UTC 25 Feb 08 06:12:34 PM UTC 25 24078095501 ps
T2146 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_aon_wake_disconnect.3489116313 Feb 08 06:12:26 PM UTC 25 Feb 08 06:12:34 PM UTC 25 4831342681 ps
T2147 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_min_length_in_transaction.103064078 Feb 08 06:12:32 PM UTC 25 Feb 08 06:12:35 PM UTC 25 165010488 ps
T2148 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_max_length_in_transaction.3368856888 Feb 08 06:12:32 PM UTC 25 Feb 08 06:12:35 PM UTC 25 300203029 ps
T2149 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_spurious_pids_ignored.1863386623 Feb 08 06:12:07 PM UTC 25 Feb 08 06:12:35 PM UTC 25 2546327543 ps
T2150 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_max_length_out_transaction.373797294 Feb 08 06:12:32 PM UTC 25 Feb 08 06:12:35 PM UTC 25 196176325 ps
T2151 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/28.usbdev_spurious_pids_ignored.2249649385 Feb 08 06:11:25 PM UTC 25 Feb 08 06:12:35 PM UTC 25 2154889176 ps
T2152 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_out_iso.283124891 Feb 08 06:12:34 PM UTC 25 Feb 08 06:12:36 PM UTC 25 211355227 ps
T2153 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_out_trans_nak.745876760 Feb 08 06:12:34 PM UTC 25 Feb 08 06:12:36 PM UTC 25 155917154 ps
T2154 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_out_stall.1833784385 Feb 08 06:12:34 PM UTC 25 Feb 08 06:12:36 PM UTC 25 175960222 ps
T2155 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_pending_in_trans.2286184734 Feb 08 06:12:34 PM UTC 25 Feb 08 06:12:36 PM UTC 25 194128369 ps
T2156 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_nak_trans.130692287 Feb 08 06:12:34 PM UTC 25 Feb 08 06:12:37 PM UTC 25 208969165 ps
T2157 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_min_length_out_transaction.781586167 Feb 08 06:12:34 PM UTC 25 Feb 08 06:12:37 PM UTC 25 191378319 ps
T2158 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_phy_pins_sense.758151814 Feb 08 06:12:35 PM UTC 25 Feb 08 06:12:37 PM UTC 25 37545360 ps
T2159 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_phy_config_pinflip.2649681802 Feb 08 06:12:35 PM UTC 25 Feb 08 06:12:38 PM UTC 25 234102044 ps
T2160 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_device_timeout.192621471 Feb 08 06:12:12 PM UTC 25 Feb 08 06:12:38 PM UTC 25 1151663434 ps
T2161 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_phy_config_usb_ref_disable.333397712 Feb 08 06:12:35 PM UTC 25 Feb 08 06:12:38 PM UTC 25 164474030 ps
T2162 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_min_inter_pkt_delay.2578705034 Feb 08 06:12:19 PM UTC 25 Feb 08 06:12:39 PM UTC 25 1967276324 ps
T2163 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_random_length_in_transaction.763921788 Feb 08 06:12:37 PM UTC 25 Feb 08 06:12:39 PM UTC 25 168040124 ps
T2164 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_pkt_received.637831469 Feb 08 06:12:36 PM UTC 25 Feb 08 06:12:39 PM UTC 25 147603168 ps
T2165 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_pkt_sent.3346220200 Feb 08 06:12:37 PM UTC 25 Feb 08 06:12:39 PM UTC 25 213332114 ps
T2166 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_link_resume.2084040709 Feb 08 06:11:56 PM UTC 25 Feb 08 06:12:39 PM UTC 25 25937499805 ps
T2167 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_random_length_out_transaction.1833464742 Feb 08 06:12:37 PM UTC 25 Feb 08 06:12:39 PM UTC 25 211218388 ps
T2168 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_rx_crc_err.2572147102 Feb 08 06:12:38 PM UTC 25 Feb 08 06:12:41 PM UTC 25 166993097 ps
T2169 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_setup_trans_ignored.1171178127 Feb 08 06:12:38 PM UTC 25 Feb 08 06:12:41 PM UTC 25 155307132 ps
T2170 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_setup_stage.1084329586 Feb 08 06:12:38 PM UTC 25 Feb 08 06:12:41 PM UTC 25 155134649 ps
T302 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_rx_full.3797428744 Feb 08 06:12:38 PM UTC 25 Feb 08 06:12:41 PM UTC 25 273994730 ps
T2171 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_stall_priority_over_nak.1462554033 Feb 08 06:12:38 PM UTC 25 Feb 08 06:12:41 PM UTC 25 180885006 ps
T2172 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_smoke.931524014 Feb 08 06:12:38 PM UTC 25 Feb 08 06:12:41 PM UTC 25 261378974 ps
T2173 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_stream_len_max.1933417974 Feb 08 06:12:55 PM UTC 25 Feb 08 06:12:59 PM UTC 25 579875899 ps
T2174 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_alert_test.2097821861 Feb 08 06:12:40 PM UTC 25 Feb 08 06:12:42 PM UTC 25 35643048 ps
T2175 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_timeout_missing_host_handshake.502167747 Feb 08 06:12:28 PM UTC 25 Feb 08 06:12:43 PM UTC 25 552160077 ps
T2176 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_stall_trans.3413109850 Feb 08 06:12:40 PM UTC 25 Feb 08 06:12:43 PM UTC 25 210312571 ps
T2177 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_tx_rx_disruption.3589347904 Feb 08 06:12:40 PM UTC 25 Feb 08 06:12:43 PM UTC 25 458176724 ps
T2178 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_link_resume.1841761721 Feb 08 06:11:37 PM UTC 25 Feb 08 06:12:43 PM UTC 25 27919459039 ps
T2179 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_aon_wake_resume.2893311585 Feb 08 06:12:09 PM UTC 25 Feb 08 06:12:43 PM UTC 25 25456019393 ps
T2180 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_device_timeout.4210324711 Feb 08 06:12:28 PM UTC 25 Feb 08 06:12:43 PM UTC 25 752455752 ps
T2181 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_aon_wake_reset.602750110 Feb 08 06:12:09 PM UTC 25 Feb 08 06:12:43 PM UTC 25 18899048626 ps
T2182 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_device_address.3517836284 Feb 08 06:11:51 PM UTC 25 Feb 08 06:12:44 PM UTC 25 25689524989 ps
T2183 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_av_buffer.1226736824 Feb 08 06:12:41 PM UTC 25 Feb 08 06:12:44 PM UTC 25 207370492 ps
T2184 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_bitstuff_err.1708393681 Feb 08 06:12:41 PM UTC 25 Feb 08 06:12:44 PM UTC 25 188410192 ps
T2185 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/30.usbdev_pkt_buffer.3901955346 Feb 08 06:12:02 PM UTC 25 Feb 08 06:12:44 PM UTC 25 15273878764 ps
T2186 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_max_inter_pkt_delay.628468406 Feb 08 06:12:16 PM UTC 25 Feb 08 06:12:45 PM UTC 25 3959059505 ps
T2187 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/32.usbdev_stream_len_max.2846367668 Feb 08 06:12:40 PM UTC 25 Feb 08 06:12:45 PM UTC 25 1255212937 ps
T2188 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_pkt_buffer.1252667426 Feb 08 06:12:21 PM UTC 25 Feb 08 06:12:45 PM UTC 25 7071607021 ps
T2189 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_data_toggle_clear.897208934 Feb 08 06:12:43 PM UTC 25 Feb 08 06:12:46 PM UTC 25 375050103 ps
T2190 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_device_address.3073296519 Feb 08 06:11:30 PM UTC 25 Feb 08 06:12:46 PM UTC 25 46587873795 ps
T314 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_data_toggle_restore.1876194892 Feb 08 06:12:43 PM UTC 25 Feb 08 06:12:46 PM UTC 25 654777194 ps
T2191 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_tx_rx_disruption.2611398694 Feb 08 06:12:55 PM UTC 25 Feb 08 06:12:58 PM UTC 25 508501654 ps
T2192 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/34.usbdev_bitstuff_err.4152117247 Feb 08 06:12:56 PM UTC 25 Feb 08 06:12:59 PM UTC 25 143566127 ps
T2193 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/29.usbdev_max_inter_pkt_delay.2398538708 Feb 08 06:11:38 PM UTC 25 Feb 08 06:12:47 PM UTC 25 2366094834 ps
T2194 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_enable.2230735257 Feb 08 06:12:45 PM UTC 25 Feb 08 06:12:47 PM UTC 25 49654106 ps
T2195 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/31.usbdev_spurious_pids_ignored.4125902572 Feb 08 06:12:23 PM UTC 25 Feb 08 06:12:47 PM UTC 25 2386274465 ps
T2196 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_disconnected.2959969328 Feb 08 06:12:45 PM UTC 25 Feb 08 06:12:47 PM UTC 25 153365811 ps
T2197 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/33.usbdev_in_iso.991105036 Feb 08 06:12:45 PM UTC 25 Feb 08 06:12:47 PM UTC 25 182659644 ps