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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.44 98.11 95.91 97.44 87.30 98.22 98.17 92.94


Total test records in report: 3732
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T1247 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_phy_config_pinflip.3039387124 Feb 08 06:06:13 PM UTC 25 Feb 08 06:06:16 PM UTC 25 252794058 ps
T1248 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_phy_pins_sense.2565377634 Feb 08 06:06:14 PM UTC 25 Feb 08 06:06:16 PM UTC 25 46311221 ps
T1249 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_max_usb_traffic.737469402 Feb 08 06:04:36 PM UTC 25 Feb 08 06:06:16 PM UTC 25 2871300719 ps
T1250 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_phy_config_usb_ref_disable.1341921604 Feb 08 06:06:14 PM UTC 25 Feb 08 06:06:16 PM UTC 25 146331823 ps
T1251 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_streaming_out.231642626 Feb 08 06:05:52 PM UTC 25 Feb 08 06:06:17 PM UTC 25 2701542963 ps
T106 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_aon_wake_reset.34351728 Feb 08 06:05:54 PM UTC 25 Feb 08 06:06:17 PM UTC 25 13982928524 ps
T1252 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_random_length_in_transaction.55322712 Feb 08 06:06:16 PM UTC 25 Feb 08 06:06:18 PM UTC 25 185667922 ps
T1253 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_pkt_sent.3146715015 Feb 08 06:06:16 PM UTC 25 Feb 08 06:06:18 PM UTC 25 214028679 ps
T1254 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_pkt_received.1772315727 Feb 08 06:06:16 PM UTC 25 Feb 08 06:06:18 PM UTC 25 194317696 ps
T1255 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_resume_link_active.2961384370 Feb 08 06:05:48 PM UTC 25 Feb 08 06:06:19 PM UTC 25 20144359676 ps
T1256 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_rx_crc_err.1984333064 Feb 08 06:06:17 PM UTC 25 Feb 08 06:06:19 PM UTC 25 192543096 ps
T1257 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_timeout_missing_host_handshake.2369104957 Feb 08 06:05:58 PM UTC 25 Feb 08 06:06:20 PM UTC 25 2107280985 ps
T1258 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_random_length_out_transaction.844983133 Feb 08 06:06:17 PM UTC 25 Feb 08 06:06:20 PM UTC 25 183534166 ps
T503 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_pkt_buffer.109080563 Feb 08 06:05:17 PM UTC 25 Feb 08 06:06:20 PM UTC 25 21864021708 ps
T1259 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/12.usbdev_max_inter_pkt_delay.3335205134 Feb 08 06:04:33 PM UTC 25 Feb 08 06:06:21 PM UTC 25 3640467900 ps
T1260 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_setup_trans_ignored.169275238 Feb 08 06:06:18 PM UTC 25 Feb 08 06:06:21 PM UTC 25 156787267 ps
T300 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_rx_full.549363513 Feb 08 06:06:18 PM UTC 25 Feb 08 06:06:21 PM UTC 25 249317256 ps
T1261 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_link_suspend.3356817986 Feb 08 06:06:07 PM UTC 25 Feb 08 06:06:21 PM UTC 25 5930382665 ps
T1262 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_setup_stage.4168189842 Feb 08 06:06:18 PM UTC 25 Feb 08 06:06:21 PM UTC 25 231937224 ps
T1263 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_stall_priority_over_nak.367667830 Feb 08 06:06:20 PM UTC 25 Feb 08 06:06:22 PM UTC 25 186587058 ps
T1264 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_smoke.887946443 Feb 08 06:06:20 PM UTC 25 Feb 08 06:06:22 PM UTC 25 200006586 ps
T1265 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_bitstuff_err.4246963013 Feb 08 06:06:23 PM UTC 25 Feb 08 06:06:26 PM UTC 25 145304122 ps
T1266 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_max_inter_pkt_delay.102837151 Feb 08 06:06:08 PM UTC 25 Feb 08 06:06:24 PM UTC 25 1497468598 ps
T1267 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_alert_test.457335125 Feb 08 06:06:22 PM UTC 25 Feb 08 06:06:24 PM UTC 25 90663551 ps
T1268 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_stall_trans.1578528369 Feb 08 06:06:22 PM UTC 25 Feb 08 06:06:25 PM UTC 25 184173129 ps
T1269 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_stream_len_max.1932997811 Feb 08 06:06:22 PM UTC 25 Feb 08 06:06:25 PM UTC 25 571142205 ps
T1270 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_min_inter_pkt_delay.825457467 Feb 08 06:06:08 PM UTC 25 Feb 08 06:06:26 PM UTC 25 1724518705 ps
T1271 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_data_toggle_restore.1626929643 Feb 08 06:06:25 PM UTC 25 Feb 08 06:06:28 PM UTC 25 292511363 ps
T1272 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_disconnected.4208131659 Feb 08 06:06:27 PM UTC 25 Feb 08 06:06:30 PM UTC 25 147282516 ps
T1273 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_enable.1098978047 Feb 08 06:06:27 PM UTC 25 Feb 08 06:06:30 PM UTC 25 71830319 ps
T1274 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_disable_endpoint.1740028100 Feb 08 06:06:26 PM UTC 25 Feb 08 06:06:30 PM UTC 25 769494953 ps
T382 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_endpoint_types.2695993298 Feb 08 06:06:28 PM UTC 25 Feb 08 06:06:31 PM UTC 25 566869518 ps
T1275 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_device_address.609771193 Feb 08 06:05:27 PM UTC 25 Feb 08 06:06:31 PM UTC 25 32283294386 ps
T1276 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_fifo_rst.56562251 Feb 08 06:06:28 PM UTC 25 Feb 08 06:06:31 PM UTC 25 246047392 ps
T1277 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_invalid_sync.4243592974 Feb 08 06:05:04 PM UTC 25 Feb 08 06:06:32 PM UTC 25 3004552168 ps
T1278 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/11.usbdev_spurious_pids_ignored.2825092791 Feb 08 06:04:18 PM UTC 25 Feb 08 06:06:32 PM UTC 25 3986853772 ps
T1279 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_endpoint_access.3283245812 Feb 08 06:06:28 PM UTC 25 Feb 08 06:06:33 PM UTC 25 965743748 ps
T1280 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_max_non_iso_usb_traffic.2686586087 Feb 08 06:06:08 PM UTC 25 Feb 08 06:06:33 PM UTC 25 1903529332 ps
T1281 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_in_stall.2229247451 Feb 08 06:06:31 PM UTC 25 Feb 08 06:06:34 PM UTC 25 145286311 ps
T1282 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_in_iso.2156316087 Feb 08 06:06:31 PM UTC 25 Feb 08 06:06:34 PM UTC 25 186800266 ps
T1283 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_in_trans.4236966907 Feb 08 06:06:31 PM UTC 25 Feb 08 06:06:34 PM UTC 25 201321121 ps
T1284 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_aon_wake_disconnect.1955189217 Feb 08 06:06:22 PM UTC 25 Feb 08 06:06:34 PM UTC 25 6364499180 ps
T1285 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_max_usb_traffic.2345986522 Feb 08 06:05:11 PM UTC 25 Feb 08 06:06:34 PM UTC 25 2849964477 ps
T192 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_device_address.308537940 Feb 08 06:05:58 PM UTC 25 Feb 08 06:06:35 PM UTC 25 19959057436 ps
T1286 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_link_in_err.3565915299 Feb 08 06:06:33 PM UTC 25 Feb 08 06:06:35 PM UTC 25 232248835 ps
T1287 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_max_length_in_transaction.1146173895 Feb 08 06:06:34 PM UTC 25 Feb 08 06:06:37 PM UTC 25 251631100 ps
T1288 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_max_length_out_transaction.1166205823 Feb 08 06:06:35 PM UTC 25 Feb 08 06:06:37 PM UTC 25 190952214 ps
T1289 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_min_length_in_transaction.2454511944 Feb 08 06:06:35 PM UTC 25 Feb 08 06:06:37 PM UTC 25 165956040 ps
T1290 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_aon_wake_resume.324646096 Feb 08 06:05:54 PM UTC 25 Feb 08 06:06:38 PM UTC 25 30232974016 ps
T1291 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_nak_trans.1760423856 Feb 08 06:06:36 PM UTC 25 Feb 08 06:06:39 PM UTC 25 219248633 ps
T1292 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_min_length_out_transaction.1574956547 Feb 08 06:06:36 PM UTC 25 Feb 08 06:06:39 PM UTC 25 151363662 ps
T1293 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_out_iso.1564149988 Feb 08 06:06:36 PM UTC 25 Feb 08 06:06:39 PM UTC 25 259651113 ps
T1294 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_out_stall.3557350629 Feb 08 06:06:37 PM UTC 25 Feb 08 06:06:40 PM UTC 25 176241389 ps
T1295 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_device_timeout.287591206 Feb 08 06:06:25 PM UTC 25 Feb 08 06:06:40 PM UTC 25 1994875884 ps
T1296 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_phy_config_pinflip.2481365814 Feb 08 06:06:39 PM UTC 25 Feb 08 06:06:41 PM UTC 25 221503513 ps
T1297 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_out_trans_nak.1950515869 Feb 08 06:06:39 PM UTC 25 Feb 08 06:06:41 PM UTC 25 164845730 ps
T1298 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_pending_in_trans.265646261 Feb 08 06:06:39 PM UTC 25 Feb 08 06:06:41 PM UTC 25 151285329 ps
T1299 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_phy_pins_sense.541923196 Feb 08 06:06:40 PM UTC 25 Feb 08 06:06:42 PM UTC 25 34120343 ps
T1300 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_device_address.4010326477 Feb 08 06:04:59 PM UTC 25 Feb 08 06:06:42 PM UTC 25 36367136334 ps
T1301 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_phy_config_usb_ref_disable.1565152128 Feb 08 06:06:40 PM UTC 25 Feb 08 06:06:43 PM UTC 25 148880687 ps
T1302 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_pkt_received.3422035613 Feb 08 06:06:41 PM UTC 25 Feb 08 06:06:44 PM UTC 25 178305070 ps
T1303 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_pkt_sent.1013787348 Feb 08 06:06:41 PM UTC 25 Feb 08 06:06:44 PM UTC 25 199079334 ps
T1304 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_spurious_pids_ignored.4045970461 Feb 08 06:06:20 PM UTC 25 Feb 08 06:06:45 PM UTC 25 3297200627 ps
T1305 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_random_length_out_transaction.3594120050 Feb 08 06:06:43 PM UTC 25 Feb 08 06:06:45 PM UTC 25 188210931 ps
T1306 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_random_length_in_transaction.1685898788 Feb 08 06:06:43 PM UTC 25 Feb 08 06:06:45 PM UTC 25 164155943 ps
T1307 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_device_timeout.4206413240 Feb 08 06:05:58 PM UTC 25 Feb 08 06:06:45 PM UTC 25 1923718750 ps
T1308 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_low_speed_traffic.664958571 Feb 08 06:05:08 PM UTC 25 Feb 08 06:06:46 PM UTC 25 3404733636 ps
T1309 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_link_suspend.342864439 Feb 08 06:06:33 PM UTC 25 Feb 08 06:06:46 PM UTC 25 8698112190 ps
T1310 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_setup_stage.2748536338 Feb 08 06:06:44 PM UTC 25 Feb 08 06:06:47 PM UTC 25 215278721 ps
T1311 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_rx_crc_err.292977570 Feb 08 06:06:44 PM UTC 25 Feb 08 06:06:47 PM UTC 25 152519850 ps
T1312 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_rx_full.1329486887 Feb 08 06:06:44 PM UTC 25 Feb 08 06:06:48 PM UTC 25 390486992 ps
T1313 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_stall_trans.3644546043 Feb 08 06:06:46 PM UTC 25 Feb 08 06:06:48 PM UTC 25 249476751 ps
T1314 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_low_speed_traffic.3734314815 Feb 08 06:06:07 PM UTC 25 Feb 08 06:06:48 PM UTC 25 4903701513 ps
T1315 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_stall_priority_over_nak.2840783483 Feb 08 06:06:46 PM UTC 25 Feb 08 06:06:48 PM UTC 25 159373884 ps
T1316 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_setup_trans_ignored.702617982 Feb 08 06:06:46 PM UTC 25 Feb 08 06:06:49 PM UTC 25 148943966 ps
T1317 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_smoke.913372586 Feb 08 06:06:46 PM UTC 25 Feb 08 06:06:49 PM UTC 25 234538401 ps
T1318 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_spurious_pids_ignored.3445025065 Feb 08 06:05:22 PM UTC 25 Feb 08 06:06:49 PM UTC 25 3046412726 ps
T131 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_nak_trans.3225930888 Feb 08 06:07:02 PM UTC 25 Feb 08 06:07:05 PM UTC 25 215472593 ps
T1319 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_alert_test.2110130669 Feb 08 06:06:47 PM UTC 25 Feb 08 06:06:50 PM UTC 25 29269851 ps
T1320 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_stream_len_max.308545576 Feb 08 06:06:47 PM UTC 25 Feb 08 06:06:50 PM UTC 25 406633964 ps
T1321 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_resume_link_active.3090204189 Feb 08 06:06:17 PM UTC 25 Feb 08 06:06:50 PM UTC 25 20209582123 ps
T1322 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_max_non_iso_usb_traffic.2249234653 Feb 08 06:05:09 PM UTC 25 Feb 08 06:06:50 PM UTC 25 2996032495 ps
T1323 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_tx_rx_disruption.1443757020 Feb 08 06:06:47 PM UTC 25 Feb 08 06:06:50 PM UTC 25 477002976 ps
T1324 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_link_resume.3956890290 Feb 08 06:06:07 PM UTC 25 Feb 08 06:06:52 PM UTC 25 23466376651 ps
T1325 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_link_resume.4244644539 Feb 08 06:06:33 PM UTC 25 Feb 08 06:06:53 PM UTC 25 14221518925 ps
T1326 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_av_buffer.4146451049 Feb 08 06:06:50 PM UTC 25 Feb 08 06:06:53 PM UTC 25 148306182 ps
T1327 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_bitstuff_err.2974911278 Feb 08 06:06:50 PM UTC 25 Feb 08 06:06:53 PM UTC 25 135400432 ps
T1328 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_data_toggle_clear.2765049268 Feb 08 06:06:50 PM UTC 25 Feb 08 06:06:53 PM UTC 25 477830330 ps
T1329 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_enable.1711748909 Feb 08 06:06:52 PM UTC 25 Feb 08 06:06:54 PM UTC 25 58104630 ps
T1330 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_iso_retraction.1773552664 Feb 08 06:05:33 PM UTC 25 Feb 08 06:06:54 PM UTC 25 10933618283 ps
T1331 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_disconnected.3475932511 Feb 08 06:06:52 PM UTC 25 Feb 08 06:06:54 PM UTC 25 140547992 ps
T1332 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_data_toggle_restore.1826310902 Feb 08 06:06:50 PM UTC 25 Feb 08 06:06:56 PM UTC 25 1029018704 ps
T407 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_endpoint_types.2212770765 Feb 08 06:06:53 PM UTC 25 Feb 08 06:06:57 PM UTC 25 572633934 ps
T1333 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_disable_endpoint.1144310459 Feb 08 06:06:52 PM UTC 25 Feb 08 06:06:57 PM UTC 25 1058812303 ps
T1334 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_in_stall.2651609624 Feb 08 06:06:55 PM UTC 25 Feb 08 06:06:58 PM UTC 25 205273150 ps
T1335 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_in_trans.1874167939 Feb 08 06:06:55 PM UTC 25 Feb 08 06:06:58 PM UTC 25 182031837 ps
T1336 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_endpoint_access.1253304200 Feb 08 06:06:53 PM UTC 25 Feb 08 06:06:58 PM UTC 25 767918262 ps
T1337 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_in_iso.2571316673 Feb 08 06:06:55 PM UTC 25 Feb 08 06:06:58 PM UTC 25 193491037 ps
T1338 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_fifo_rst.3750995260 Feb 08 06:06:55 PM UTC 25 Feb 08 06:06:59 PM UTC 25 353563123 ps
T1339 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_link_in_err.633500723 Feb 08 06:06:57 PM UTC 25 Feb 08 06:07:00 PM UTC 25 190395150 ps
T1340 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_max_length_in_transaction.3874514846 Feb 08 06:06:58 PM UTC 25 Feb 08 06:07:01 PM UTC 25 255400578 ps
T1341 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_max_length_out_transaction.3325089052 Feb 08 06:06:58 PM UTC 25 Feb 08 06:07:01 PM UTC 25 187385665 ps
T1342 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_min_length_out_transaction.4251846027 Feb 08 06:07:02 PM UTC 25 Feb 08 06:07:05 PM UTC 25 139145066 ps
T1343 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_min_length_in_transaction.3730612763 Feb 08 06:07:02 PM UTC 25 Feb 08 06:07:05 PM UTC 25 177715053 ps
T1344 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_low_speed_traffic.392792532 Feb 08 06:06:34 PM UTC 25 Feb 08 06:07:05 PM UTC 25 3099491693 ps
T1345 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_spurious_pids_ignored.1756280687 Feb 08 06:05:50 PM UTC 25 Feb 08 06:07:05 PM UTC 25 2255064172 ps
T1346 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_aon_wake_reset.2442670052 Feb 08 06:06:22 PM UTC 25 Feb 08 06:07:05 PM UTC 25 20863571038 ps
T270 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_pkt_buffer.1966243081 Feb 08 06:06:40 PM UTC 25 Feb 08 06:07:05 PM UTC 25 7454096063 ps
T271 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_pkt_buffer.42111455 Feb 08 06:05:44 PM UTC 25 Feb 08 06:07:06 PM UTC 25 20728804883 ps
T1347 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_out_iso.250410825 Feb 08 06:07:06 PM UTC 25 Feb 08 06:07:08 PM UTC 25 218478134 ps
T1348 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_out_trans_nak.2731027668 Feb 08 06:07:06 PM UTC 25 Feb 08 06:07:08 PM UTC 25 150894089 ps
T1349 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_out_stall.3381043123 Feb 08 06:07:06 PM UTC 25 Feb 08 06:07:08 PM UTC 25 183011361 ps
T1350 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_pending_in_trans.1006637287 Feb 08 06:07:06 PM UTC 25 Feb 08 06:07:08 PM UTC 25 173247361 ps
T1351 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_phy_config_pinflip.3542344948 Feb 08 06:07:06 PM UTC 25 Feb 08 06:07:09 PM UTC 25 270356905 ps
T1352 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_min_inter_pkt_delay.2524097077 Feb 08 06:06:35 PM UTC 25 Feb 08 06:07:09 PM UTC 25 3289605873 ps
T1353 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_phy_pins_sense.3749826772 Feb 08 06:07:08 PM UTC 25 Feb 08 06:07:10 PM UTC 25 67906630 ps
T1354 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_phy_config_usb_ref_disable.1014049281 Feb 08 06:07:08 PM UTC 25 Feb 08 06:07:10 PM UTC 25 141939180 ps
T1355 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_pkt_received.209574882 Feb 08 06:07:09 PM UTC 25 Feb 08 06:07:11 PM UTC 25 181371889 ps
T1356 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_timeout_missing_host_handshake.3659322235 Feb 08 06:06:26 PM UTC 25 Feb 08 06:07:11 PM UTC 25 5585460903 ps
T1357 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_random_length_out_transaction.47793166 Feb 08 06:07:09 PM UTC 25 Feb 08 06:07:12 PM UTC 25 147751355 ps
T1358 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_pkt_sent.4288315832 Feb 08 06:07:09 PM UTC 25 Feb 08 06:07:12 PM UTC 25 163653309 ps
T1359 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_random_length_in_transaction.3993174803 Feb 08 06:07:09 PM UTC 25 Feb 08 06:07:12 PM UTC 25 277415459 ps
T1360 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_rx_crc_err.3052966545 Feb 08 06:07:11 PM UTC 25 Feb 08 06:07:14 PM UTC 25 174247422 ps
T1361 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_rx_full.970341578 Feb 08 06:07:11 PM UTC 25 Feb 08 06:07:14 PM UTC 25 251893991 ps
T1362 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_setup_stage.4157766610 Feb 08 06:07:12 PM UTC 25 Feb 08 06:07:14 PM UTC 25 153977606 ps
T498 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_device_address.3245958851 Feb 08 06:06:25 PM UTC 25 Feb 08 06:07:15 PM UTC 25 26370323215 ps
T1363 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_setup_trans_ignored.1791965808 Feb 08 06:07:13 PM UTC 25 Feb 08 06:07:16 PM UTC 25 154146728 ps
T1364 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_link_resume.2011689695 Feb 08 06:06:58 PM UTC 25 Feb 08 06:07:16 PM UTC 25 7426962932 ps
T1365 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_smoke.659877061 Feb 08 06:07:13 PM UTC 25 Feb 08 06:07:16 PM UTC 25 248350984 ps
T1366 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_stall_trans.1483504901 Feb 08 06:07:13 PM UTC 25 Feb 08 06:07:16 PM UTC 25 154644575 ps
T1367 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_stall_priority_over_nak.370486244 Feb 08 06:07:13 PM UTC 25 Feb 08 06:07:16 PM UTC 25 167187984 ps
T1368 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_aon_wake_resume.2329167428 Feb 08 06:06:22 PM UTC 25 Feb 08 06:07:16 PM UTC 25 28893533301 ps
T1369 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_link_suspend.4273216328 Feb 08 06:06:58 PM UTC 25 Feb 08 06:07:17 PM UTC 25 9640876148 ps
T1370 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_max_inter_pkt_delay.3330121049 Feb 08 06:05:08 PM UTC 25 Feb 08 06:07:17 PM UTC 25 4113108431 ps
T1371 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_timeout_missing_host_handshake.2381358163 Feb 08 06:06:52 PM UTC 25 Feb 08 06:07:18 PM UTC 25 2939559259 ps
T1372 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_stream_len_max.2251467935 Feb 08 06:07:14 PM UTC 25 Feb 08 06:07:19 PM UTC 25 438202331 ps
T1373 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_tx_rx_disruption.3803219145 Feb 08 06:07:16 PM UTC 25 Feb 08 06:07:19 PM UTC 25 592173933 ps
T1374 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_aon_wake_reset.3786185521 Feb 08 06:06:50 PM UTC 25 Feb 08 06:07:19 PM UTC 25 21093845836 ps
T1375 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/26.usbdev_tx_rx_disruption.205038906 Feb 08 06:10:52 PM UTC 25 Feb 08 06:10:56 PM UTC 25 528730167 ps
T1376 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_iso_retraction.1684334544 Feb 08 06:06:04 PM UTC 25 Feb 08 06:07:20 PM UTC 25 6217334734 ps
T1377 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_alert_test.1765576379 Feb 08 06:07:18 PM UTC 25 Feb 08 06:07:20 PM UTC 25 71053549 ps
T1378 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_av_buffer.3106304203 Feb 08 06:07:18 PM UTC 25 Feb 08 06:07:20 PM UTC 25 152606156 ps
T1379 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_min_inter_pkt_delay.1545136274 Feb 08 06:07:01 PM UTC 25 Feb 08 06:07:21 PM UTC 25 2334232334 ps
T1380 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_aon_wake_disconnect.1886889296 Feb 08 06:06:49 PM UTC 25 Feb 08 06:07:21 PM UTC 25 10867529417 ps
T1381 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_bitstuff_err.393926019 Feb 08 06:07:18 PM UTC 25 Feb 08 06:07:21 PM UTC 25 156492034 ps
T1382 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_data_toggle_clear.3158284186 Feb 08 06:07:18 PM UTC 25 Feb 08 06:07:22 PM UTC 25 357026150 ps
T1383 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_enable.3061524866 Feb 08 06:07:21 PM UTC 25 Feb 08 06:07:23 PM UTC 25 39762340 ps
T1384 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_disconnected.1321292635 Feb 08 06:07:21 PM UTC 25 Feb 08 06:07:23 PM UTC 25 146868340 ps
T317 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_data_toggle_restore.3381703723 Feb 08 06:07:19 PM UTC 25 Feb 08 06:07:24 PM UTC 25 989036880 ps
T1385 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_max_inter_pkt_delay.3031888682 Feb 08 06:06:58 PM UTC 25 Feb 08 06:07:24 PM UTC 25 2296166014 ps
T272 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_pkt_buffer.520604949 Feb 08 06:06:16 PM UTC 25 Feb 08 06:07:24 PM UTC 25 23590005229 ps
T1386 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_disable_endpoint.2783993781 Feb 08 06:07:21 PM UTC 25 Feb 08 06:07:25 PM UTC 25 744832624 ps
T391 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_endpoint_types.4057409191 Feb 08 06:07:22 PM UTC 25 Feb 08 06:07:25 PM UTC 25 520603646 ps
T1387 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/13.usbdev_iso_retraction.3019642215 Feb 08 06:05:06 PM UTC 25 Feb 08 06:07:25 PM UTC 25 9599839622 ps
T1388 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_in_iso.1488652772 Feb 08 06:07:22 PM UTC 25 Feb 08 06:07:26 PM UTC 25 271954945 ps
T1389 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_fifo_rst.1353831710 Feb 08 06:07:22 PM UTC 25 Feb 08 06:07:26 PM UTC 25 218864455 ps
T1390 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_in_stall.1046695753 Feb 08 06:07:24 PM UTC 25 Feb 08 06:07:26 PM UTC 25 142340998 ps
T1391 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_in_trans.2653670345 Feb 08 06:07:24 PM UTC 25 Feb 08 06:07:26 PM UTC 25 249723299 ps
T1392 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_endpoint_access.3855426796 Feb 08 06:07:22 PM UTC 25 Feb 08 06:07:27 PM UTC 25 740051620 ps
T1393 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_resume_link_active.2380200703 Feb 08 06:06:43 PM UTC 25 Feb 08 06:07:27 PM UTC 25 20197318801 ps
T1394 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/15.usbdev_streaming_out.1550599332 Feb 08 06:06:22 PM UTC 25 Feb 08 06:07:28 PM UTC 25 2041469730 ps
T1395 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_link_in_err.2832948354 Feb 08 06:07:25 PM UTC 25 Feb 08 06:07:28 PM UTC 25 225177827 ps
T1396 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_max_length_out_transaction.1719384871 Feb 08 06:07:27 PM UTC 25 Feb 08 06:07:30 PM UTC 25 235505216 ps
T1397 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_min_length_in_transaction.3672437023 Feb 08 06:07:27 PM UTC 25 Feb 08 06:07:30 PM UTC 25 153931981 ps
T1398 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_max_length_in_transaction.2243453738 Feb 08 06:07:27 PM UTC 25 Feb 08 06:07:30 PM UTC 25 283230028 ps
T1399 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_min_length_out_transaction.517323130 Feb 08 06:07:28 PM UTC 25 Feb 08 06:07:31 PM UTC 25 164761520 ps
T1400 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_out_iso.1280420265 Feb 08 06:07:29 PM UTC 25 Feb 08 06:07:31 PM UTC 25 147260033 ps
T145 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_nak_trans.3669703657 Feb 08 06:07:28 PM UTC 25 Feb 08 06:07:32 PM UTC 25 241363243 ps
T1401 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_out_stall.1164031121 Feb 08 06:07:30 PM UTC 25 Feb 08 06:07:32 PM UTC 25 185953374 ps
T1402 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/8.usbdev_rand_bus_disconnects.690048166 Feb 08 06:02:38 PM UTC 25 Feb 08 06:07:33 PM UTC 25 14149433974 ps
T1403 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_device_timeout.1822637149 Feb 08 06:07:19 PM UTC 25 Feb 08 06:07:33 PM UTC 25 1100536660 ps
T1404 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_out_trans_nak.1325822252 Feb 08 06:07:31 PM UTC 25 Feb 08 06:07:33 PM UTC 25 153308095 ps
T1405 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_pending_in_trans.4232406453 Feb 08 06:07:31 PM UTC 25 Feb 08 06:07:33 PM UTC 25 154941221 ps
T1406 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_phy_config_pinflip.955567700 Feb 08 06:07:31 PM UTC 25 Feb 08 06:07:34 PM UTC 25 184419711 ps
T1407 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_phy_pins_sense.1232832336 Feb 08 06:07:32 PM UTC 25 Feb 08 06:07:34 PM UTC 25 35613064 ps
T508 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_phy_config_usb_ref_disable.1600635165 Feb 08 06:07:32 PM UTC 25 Feb 08 06:07:35 PM UTC 25 160072498 ps
T1408 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_pkt_received.2069217115 Feb 08 06:07:34 PM UTC 25 Feb 08 06:07:36 PM UTC 25 165498011 ps
T1409 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_random_length_in_transaction.2132498805 Feb 08 06:07:34 PM UTC 25 Feb 08 06:07:36 PM UTC 25 233188742 ps
T1410 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_pkt_sent.4202525341 Feb 08 06:07:34 PM UTC 25 Feb 08 06:07:36 PM UTC 25 227950968 ps
T1411 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_random_length_out_transaction.148334055 Feb 08 06:07:35 PM UTC 25 Feb 08 06:07:37 PM UTC 25 152540047 ps
T1412 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_rx_crc_err.2352933912 Feb 08 06:07:35 PM UTC 25 Feb 08 06:07:37 PM UTC 25 155931125 ps
T1413 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_rx_full.3071623526 Feb 08 06:07:35 PM UTC 25 Feb 08 06:07:38 PM UTC 25 316071771 ps
T1414 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_setup_stage.2217066991 Feb 08 06:07:36 PM UTC 25 Feb 08 06:07:39 PM UTC 25 145009630 ps
T1415 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_setup_trans_ignored.1407778250 Feb 08 06:07:37 PM UTC 25 Feb 08 06:07:40 PM UTC 25 181126219 ps
T1416 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_resume_link_active.751739403 Feb 08 06:07:09 PM UTC 25 Feb 08 06:07:40 PM UTC 25 20151929313 ps
T1417 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_spurious_pids_ignored.2075905083 Feb 08 06:07:13 PM UTC 25 Feb 08 06:07:40 PM UTC 25 2677927459 ps
T1418 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_smoke.2555121968 Feb 08 06:07:37 PM UTC 25 Feb 08 06:07:40 PM UTC 25 210748489 ps
T1419 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_stall_trans.1793463072 Feb 08 06:07:39 PM UTC 25 Feb 08 06:07:41 PM UTC 25 152648817 ps
T1420 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_link_suspend.123319378 Feb 08 06:07:25 PM UTC 25 Feb 08 06:07:41 PM UTC 25 9172887006 ps
T1421 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_stall_priority_over_nak.169352419 Feb 08 06:07:39 PM UTC 25 Feb 08 06:07:41 PM UTC 25 179115530 ps
T1422 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_aon_wake_disconnect.2766236785 Feb 08 06:07:18 PM UTC 25 Feb 08 06:07:42 PM UTC 25 9986306498 ps
T1423 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_max_non_iso_usb_traffic.725821113 Feb 08 06:07:27 PM UTC 25 Feb 08 06:07:43 PM UTC 25 1389369513 ps
T1424 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_aon_wake_resume.2801210566 Feb 08 06:06:50 PM UTC 25 Feb 08 06:07:43 PM UTC 25 29667589951 ps
T1425 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_max_inter_pkt_delay.877805768 Feb 08 06:06:34 PM UTC 25 Feb 08 06:07:43 PM UTC 25 2258435120 ps
T1426 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/27.usbdev_av_buffer.3637074281 Feb 08 06:10:52 PM UTC 25 Feb 08 06:10:55 PM UTC 25 212524930 ps
T1427 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_alert_test.2562717772 Feb 08 06:07:41 PM UTC 25 Feb 08 06:07:44 PM UTC 25 65546502 ps
T1428 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_invalid_sync.1397621376 Feb 08 06:06:55 PM UTC 25 Feb 08 06:07:45 PM UTC 25 4483273823 ps
T1429 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_tx_rx_disruption.3146426666 Feb 08 06:07:41 PM UTC 25 Feb 08 06:07:45 PM UTC 25 608067293 ps
T1430 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_link_resume.857096169 Feb 08 06:07:25 PM UTC 25 Feb 08 06:07:45 PM UTC 25 6249964851 ps
T1431 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/21.usbdev_device_timeout.400453762 Feb 08 06:08:33 PM UTC 25 Feb 08 06:08:45 PM UTC 25 1066006317 ps
T1432 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_device_address.1784909845 Feb 08 06:07:19 PM UTC 25 Feb 08 06:07:45 PM UTC 25 14264847004 ps
T1433 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_bitstuff_err.3785991194 Feb 08 06:07:43 PM UTC 25 Feb 08 06:07:45 PM UTC 25 152324364 ps
T1434 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_av_buffer.1645930616 Feb 08 06:07:43 PM UTC 25 Feb 08 06:07:46 PM UTC 25 189076409 ps
T1435 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_stream_len_max.829350606 Feb 08 06:07:40 PM UTC 25 Feb 08 06:07:46 PM UTC 25 918190441 ps
T1436 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/16.usbdev_spurious_pids_ignored.2103826022 Feb 08 06:06:46 PM UTC 25 Feb 08 06:07:47 PM UTC 25 2208491289 ps
T1437 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_data_toggle_clear.546595331 Feb 08 06:07:44 PM UTC 25 Feb 08 06:07:47 PM UTC 25 254426312 ps
T1438 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/17.usbdev_device_timeout.2479687490 Feb 08 06:06:50 PM UTC 25 Feb 08 06:07:48 PM UTC 25 7872951560 ps
T1439 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_aon_wake_reset.3481080940 Feb 08 06:07:18 PM UTC 25 Feb 08 06:07:48 PM UTC 25 14939443295 ps
T1440 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_data_toggle_restore.2184143970 Feb 08 06:07:44 PM UTC 25 Feb 08 06:07:48 PM UTC 25 597669172 ps
T1441 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_enable.2306149899 Feb 08 06:07:47 PM UTC 25 Feb 08 06:07:49 PM UTC 25 86239175 ps
T1442 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_disable_endpoint.2759636877 Feb 08 06:07:45 PM UTC 25 Feb 08 06:07:49 PM UTC 25 765140474 ps
T1443 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_disconnected.3354209958 Feb 08 06:07:47 PM UTC 25 Feb 08 06:07:50 PM UTC 25 141919894 ps
T1444 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_invalid_sync.2716279381 Feb 08 06:07:22 PM UTC 25 Feb 08 06:07:50 PM UTC 25 3326167527 ps
T1445 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_fifo_rst.171510281 Feb 08 06:07:47 PM UTC 25 Feb 08 06:07:51 PM UTC 25 206036709 ps
T402 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_endpoint_types.1191850203 Feb 08 06:07:47 PM UTC 25 Feb 08 06:07:51 PM UTC 25 374706146 ps
T1446 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_endpoint_access.3496694693 Feb 08 06:07:47 PM UTC 25 Feb 08 06:07:51 PM UTC 25 781755338 ps
T1447 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_in_iso.939198761 Feb 08 06:07:48 PM UTC 25 Feb 08 06:07:51 PM UTC 25 215273123 ps
T1448 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_in_stall.3333104254 Feb 08 06:07:48 PM UTC 25 Feb 08 06:07:51 PM UTC 25 177551873 ps
T1449 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_in_trans.406074760 Feb 08 06:07:48 PM UTC 25 Feb 08 06:07:51 PM UTC 25 254025388 ps
T1450 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_link_in_err.2158000065 Feb 08 06:07:50 PM UTC 25 Feb 08 06:07:52 PM UTC 25 242127870 ps
T1451 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_max_length_in_transaction.3391379831 Feb 08 06:07:51 PM UTC 25 Feb 08 06:07:54 PM UTC 25 242407104 ps
T1452 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/14.usbdev_low_speed_traffic.3909462140 Feb 08 06:05:34 PM UTC 25 Feb 08 06:07:55 PM UTC 25 4584628317 ps
T1453 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_min_length_in_transaction.2217629640 Feb 08 06:07:53 PM UTC 25 Feb 08 06:07:55 PM UTC 25 163975999 ps
T1454 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_min_length_out_transaction.1504808983 Feb 08 06:07:53 PM UTC 25 Feb 08 06:07:55 PM UTC 25 142222130 ps
T1455 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_max_length_out_transaction.2792396441 Feb 08 06:07:53 PM UTC 25 Feb 08 06:07:56 PM UTC 25 188529895 ps
T143 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_nak_trans.4289458759 Feb 08 06:07:54 PM UTC 25 Feb 08 06:07:57 PM UTC 25 190732359 ps
T1456 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_streaming_out.4232270457 Feb 08 06:07:40 PM UTC 25 Feb 08 06:07:57 PM UTC 25 1797273887 ps
T1457 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_timeout_missing_host_handshake.2040854309 Feb 08 06:07:21 PM UTC 25 Feb 08 06:07:57 PM UTC 25 2938434896 ps
T1458 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_out_iso.2660831379 Feb 08 06:07:55 PM UTC 25 Feb 08 06:07:57 PM UTC 25 188179877 ps
T1459 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_aon_wake_disconnect.916288788 Feb 08 06:07:41 PM UTC 25 Feb 08 06:07:59 PM UTC 25 9899922522 ps
T1460 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_out_stall.3263463858 Feb 08 06:07:56 PM UTC 25 Feb 08 06:07:59 PM UTC 25 167490051 ps
T1461 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_pending_in_trans.1532224059 Feb 08 06:07:56 PM UTC 25 Feb 08 06:07:59 PM UTC 25 182441026 ps
T1462 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_out_trans_nak.1038856481 Feb 08 06:07:56 PM UTC 25 Feb 08 06:07:59 PM UTC 25 186726588 ps
T1463 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_phy_config_pinflip.2011706429 Feb 08 06:07:56 PM UTC 25 Feb 08 06:07:59 PM UTC 25 223777629 ps
T1464 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_min_inter_pkt_delay.2177119985 Feb 08 06:07:27 PM UTC 25 Feb 08 06:07:59 PM UTC 25 3130869202 ps
T1465 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_phy_pins_sense.2084856922 Feb 08 06:07:58 PM UTC 25 Feb 08 06:08:00 PM UTC 25 32926325 ps
T1466 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_phy_config_usb_ref_disable.558938179 Feb 08 06:07:58 PM UTC 25 Feb 08 06:08:00 PM UTC 25 145490130 ps
T1467 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_pkt_received.535162126 Feb 08 06:07:59 PM UTC 25 Feb 08 06:08:01 PM UTC 25 196328549 ps
T1468 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_device_timeout.1745631747 Feb 08 06:07:45 PM UTC 25 Feb 08 06:08:01 PM UTC 25 2246197771 ps
T1469 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_pkt_sent.4195703097 Feb 08 06:08:00 PM UTC 25 Feb 08 06:08:03 PM UTC 25 159446009 ps
T1470 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_random_length_out_transaction.913618174 Feb 08 06:08:00 PM UTC 25 Feb 08 06:08:03 PM UTC 25 164535232 ps
T1471 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_rx_crc_err.983643655 Feb 08 06:08:01 PM UTC 25 Feb 08 06:08:03 PM UTC 25 157499938 ps
T1472 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_random_length_in_transaction.3450923873 Feb 08 06:08:00 PM UTC 25 Feb 08 06:08:03 PM UTC 25 210437463 ps
T1473 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_setup_stage.3587794133 Feb 08 06:08:01 PM UTC 25 Feb 08 06:08:03 PM UTC 25 151404567 ps
T304 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_rx_full.3314363408 Feb 08 06:08:01 PM UTC 25 Feb 08 06:08:03 PM UTC 25 294211120 ps
T1474 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/18.usbdev_aon_wake_resume.2926964228 Feb 08 06:07:18 PM UTC 25 Feb 08 06:08:04 PM UTC 25 25145681311 ps
T1475 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_setup_trans_ignored.2693851409 Feb 08 06:08:02 PM UTC 25 Feb 08 06:08:04 PM UTC 25 180659224 ps
T1476 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_aon_wake_reset.2025379284 Feb 08 06:07:43 PM UTC 25 Feb 08 06:08:05 PM UTC 25 13394059727 ps
T1477 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_smoke.1145818176 Feb 08 06:08:03 PM UTC 25 Feb 08 06:08:06 PM UTC 25 185710646 ps
T1478 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/19.usbdev_stall_trans.1914575512 Feb 08 06:08:04 PM UTC 25 Feb 08 06:08:07 PM UTC 25 189035032 ps