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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.44 98.11 95.91 97.44 87.30 98.22 98.17 92.94


Total test records in report: 3732
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T463 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_endpoint_types.582839815 Feb 08 06:15:30 PM UTC 25 Feb 08 06:15:33 PM UTC 25 213246683 ps
T2681 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_data_toggle_restore.1571950388 Feb 08 06:15:27 PM UTC 25 Feb 08 06:15:33 PM UTC 25 781106111 ps
T2682 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_disable_endpoint.4056942252 Feb 08 06:15:29 PM UTC 25 Feb 08 06:15:33 PM UTC 25 760873005 ps
T2683 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_aon_wake_reset.1346712536 Feb 08 06:15:07 PM UTC 25 Feb 08 06:15:34 PM UTC 25 15928732133 ps
T2684 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_in_stall.2527941237 Feb 08 06:15:31 PM UTC 25 Feb 08 06:15:34 PM UTC 25 151048051 ps
T2685 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_fifo_rst.971847414 Feb 08 06:15:30 PM UTC 25 Feb 08 06:15:34 PM UTC 25 303837661 ps
T2686 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_in_iso.3368422734 Feb 08 06:15:31 PM UTC 25 Feb 08 06:15:34 PM UTC 25 216668352 ps
T2687 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_endpoint_access.541388234 Feb 08 06:15:30 PM UTC 25 Feb 08 06:15:35 PM UTC 25 1030268522 ps
T2688 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_aon_wake_disconnect.1613098145 Feb 08 06:15:27 PM UTC 25 Feb 08 06:15:35 PM UTC 25 4616614410 ps
T2689 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_in_trans.2919300086 Feb 08 06:15:33 PM UTC 25 Feb 08 06:15:36 PM UTC 25 194646686 ps
T2690 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_link_in_err.1649862981 Feb 08 06:15:33 PM UTC 25 Feb 08 06:15:36 PM UTC 25 225301496 ps
T2691 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_iso_retraction.3416891689 Feb 08 06:14:18 PM UTC 25 Feb 08 06:15:37 PM UTC 25 9952662318 ps
T2692 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_aon_wake_disconnect.1272803288 Feb 08 06:15:45 PM UTC 25 Feb 08 06:16:02 PM UTC 25 6821329073 ps
T2693 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/35.usbdev_iso_retraction.1980913537 Feb 08 06:13:21 PM UTC 25 Feb 08 06:16:03 PM UTC 25 13028183952 ps
T2694 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_aon_wake_resume.3758412185 Feb 08 06:14:45 PM UTC 25 Feb 08 06:15:37 PM UTC 25 29187528499 ps
T2695 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_min_length_in_transaction.641076486 Feb 08 06:15:35 PM UTC 25 Feb 08 06:15:37 PM UTC 25 184351312 ps
T2696 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_max_length_in_transaction.3672651480 Feb 08 06:15:35 PM UTC 25 Feb 08 06:15:37 PM UTC 25 247098600 ps
T2697 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_max_length_out_transaction.522559867 Feb 08 06:15:35 PM UTC 25 Feb 08 06:15:38 PM UTC 25 193561299 ps
T2698 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_min_length_out_transaction.2216303554 Feb 08 06:15:35 PM UTC 25 Feb 08 06:15:38 PM UTC 25 158848641 ps
T2699 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_spurious_pids_ignored.3407449553 Feb 08 06:15:02 PM UTC 25 Feb 08 06:15:38 PM UTC 25 3487494488 ps
T2700 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_nak_trans.3671494418 Feb 08 06:15:36 PM UTC 25 Feb 08 06:15:39 PM UTC 25 214765804 ps
T2701 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_out_trans_nak.785030522 Feb 08 06:15:36 PM UTC 25 Feb 08 06:15:39 PM UTC 25 181890070 ps
T2702 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_out_iso.1810185280 Feb 08 06:15:36 PM UTC 25 Feb 08 06:15:39 PM UTC 25 161595661 ps
T2703 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_out_stall.713515312 Feb 08 06:15:36 PM UTC 25 Feb 08 06:15:39 PM UTC 25 162126308 ps
T2704 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_phy_config_pinflip.790111228 Feb 08 06:15:38 PM UTC 25 Feb 08 06:15:40 PM UTC 25 193221970 ps
T2705 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_phy_config_usb_ref_disable.1652722098 Feb 08 06:15:38 PM UTC 25 Feb 08 06:15:40 PM UTC 25 156209465 ps
T2706 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_low_speed_traffic.2022002767 Feb 08 06:14:56 PM UTC 25 Feb 08 06:15:40 PM UTC 25 4134231985 ps
T2707 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_pending_in_trans.4192150942 Feb 08 06:15:38 PM UTC 25 Feb 08 06:15:40 PM UTC 25 163690901 ps
T2708 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_pkt_received.3632238462 Feb 08 06:15:39 PM UTC 25 Feb 08 06:15:41 PM UTC 25 244484087 ps
T2709 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_phy_pins_sense.628060933 Feb 08 06:15:39 PM UTC 25 Feb 08 06:15:42 PM UTC 25 107580379 ps
T2710 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_pkt_sent.1921649586 Feb 08 06:15:39 PM UTC 25 Feb 08 06:15:42 PM UTC 25 191786069 ps
T2711 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_random_length_out_transaction.3667321153 Feb 08 06:15:39 PM UTC 25 Feb 08 06:15:42 PM UTC 25 160346739 ps
T2712 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_rx_crc_err.2436974243 Feb 08 06:15:39 PM UTC 25 Feb 08 06:15:42 PM UTC 25 205664012 ps
T2713 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_random_length_in_transaction.3193265965 Feb 08 06:15:39 PM UTC 25 Feb 08 06:15:42 PM UTC 25 287025898 ps
T2714 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_rx_full.2362724089 Feb 08 06:15:40 PM UTC 25 Feb 08 06:15:43 PM UTC 25 339606433 ps
T2715 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_streaming_out.3554889982 Feb 08 06:14:12 PM UTC 25 Feb 08 06:15:44 PM UTC 25 3206954637 ps
T2716 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_setup_trans_ignored.731245117 Feb 08 06:15:42 PM UTC 25 Feb 08 06:15:44 PM UTC 25 151101007 ps
T2717 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_smoke.381349045 Feb 08 06:15:42 PM UTC 25 Feb 08 06:15:44 PM UTC 25 270526317 ps
T2718 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_timeout_missing_host_handshake.1889699205 Feb 08 06:15:09 PM UTC 25 Feb 08 06:15:44 PM UTC 25 1422933546 ps
T2719 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_setup_stage.2844101049 Feb 08 06:15:42 PM UTC 25 Feb 08 06:15:44 PM UTC 25 152575489 ps
T2720 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_stall_priority_over_nak.3997948645 Feb 08 06:15:42 PM UTC 25 Feb 08 06:15:45 PM UTC 25 175686242 ps
T2721 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/38.usbdev_invalid_sync.2634937395 Feb 08 06:14:18 PM UTC 25 Feb 08 06:15:45 PM UTC 25 3008068474 ps
T2722 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_rx_crc_err.1102113480 Feb 08 06:16:02 PM UTC 25 Feb 08 06:16:04 PM UTC 25 144287796 ps
T2723 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_low_speed_traffic.3314311693 Feb 08 06:15:13 PM UTC 25 Feb 08 06:15:46 PM UTC 25 3817360551 ps
T2724 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_aon_wake_reset.3267963008 Feb 08 06:15:27 PM UTC 25 Feb 08 06:15:46 PM UTC 25 13853811104 ps
T2725 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_stall_trans.3423849383 Feb 08 06:15:43 PM UTC 25 Feb 08 06:15:46 PM UTC 25 182816073 ps
T2726 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_alert_test.713976296 Feb 08 06:15:45 PM UTC 25 Feb 08 06:15:47 PM UTC 25 56842970 ps
T2727 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_link_suspend.1724704215 Feb 08 06:15:33 PM UTC 25 Feb 08 06:15:47 PM UTC 25 5747202895 ps
T2728 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_link_resume.134400772 Feb 08 06:14:34 PM UTC 25 Feb 08 06:15:47 PM UTC 25 30216553179 ps
T2729 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_spurious_pids_ignored.391606737 Feb 08 06:15:24 PM UTC 25 Feb 08 06:15:47 PM UTC 25 2244264610 ps
T2730 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_tx_rx_disruption.89663302 Feb 08 06:15:43 PM UTC 25 Feb 08 06:15:47 PM UTC 25 466468899 ps
T2731 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_pkt_buffer.16117719 Feb 08 06:15:00 PM UTC 25 Feb 08 06:15:47 PM UTC 25 14929667088 ps
T2732 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_streaming_out.930243763 Feb 08 06:15:25 PM UTC 25 Feb 08 06:15:48 PM UTC 25 1992398009 ps
T2733 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_bitstuff_err.407828033 Feb 08 06:15:46 PM UTC 25 Feb 08 06:15:49 PM UTC 25 156640280 ps
T2734 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_av_buffer.1624420783 Feb 08 06:15:46 PM UTC 25 Feb 08 06:15:49 PM UTC 25 149491363 ps
T2735 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_stream_len_max.3081283017 Feb 08 06:15:43 PM UTC 25 Feb 08 06:15:49 PM UTC 25 1295242938 ps
T2736 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_data_toggle_clear.4176695837 Feb 08 06:15:46 PM UTC 25 Feb 08 06:15:49 PM UTC 25 396397451 ps
T2737 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_data_toggle_restore.1147820867 Feb 08 06:15:46 PM UTC 25 Feb 08 06:15:49 PM UTC 25 327735716 ps
T2738 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_enable.171720998 Feb 08 06:15:48 PM UTC 25 Feb 08 06:15:51 PM UTC 25 43006477 ps
T2739 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_disconnected.3411345586 Feb 08 06:15:48 PM UTC 25 Feb 08 06:15:51 PM UTC 25 179252424 ps
T362 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_endpoint_types.3183377010 Feb 08 06:15:48 PM UTC 25 Feb 08 06:15:52 PM UTC 25 299013043 ps
T2740 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_in_stall.4263199147 Feb 08 06:15:50 PM UTC 25 Feb 08 06:15:53 PM UTC 25 181924017 ps
T2741 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_disable_endpoint.2624243869 Feb 08 06:15:48 PM UTC 25 Feb 08 06:15:53 PM UTC 25 693048213 ps
T2742 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_in_trans.2955072108 Feb 08 06:15:50 PM UTC 25 Feb 08 06:15:53 PM UTC 25 204016278 ps
T2743 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_link_in_err.1278725671 Feb 08 06:15:50 PM UTC 25 Feb 08 06:15:53 PM UTC 25 252806894 ps
T2744 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_in_iso.96461272 Feb 08 06:15:50 PM UTC 25 Feb 08 06:15:53 PM UTC 25 271777163 ps
T2745 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_endpoint_access.1168251024 Feb 08 06:15:48 PM UTC 25 Feb 08 06:15:53 PM UTC 25 1019238389 ps
T2746 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_fifo_rst.1423411478 Feb 08 06:15:48 PM UTC 25 Feb 08 06:15:53 PM UTC 25 365506712 ps
T2747 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_iso_retraction.722565931 Feb 08 06:15:13 PM UTC 25 Feb 08 06:15:55 PM UTC 25 5796674886 ps
T2748 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_min_length_in_transaction.3185554164 Feb 08 06:15:54 PM UTC 25 Feb 08 06:15:56 PM UTC 25 230489839 ps
T2749 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_min_length_out_transaction.8839005 Feb 08 06:15:54 PM UTC 25 Feb 08 06:15:57 PM UTC 25 156818875 ps
T2750 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_max_length_out_transaction.4190489716 Feb 08 06:15:54 PM UTC 25 Feb 08 06:15:57 PM UTC 25 233071466 ps
T2751 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_max_length_in_transaction.2539272964 Feb 08 06:15:54 PM UTC 25 Feb 08 06:15:57 PM UTC 25 276049371 ps
T2752 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_nak_trans.3569791987 Feb 08 06:15:54 PM UTC 25 Feb 08 06:15:57 PM UTC 25 167563118 ps
T2753 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_out_iso.1852804608 Feb 08 06:15:55 PM UTC 25 Feb 08 06:15:58 PM UTC 25 195041713 ps
T2754 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_aon_wake_resume.3188666868 Feb 08 06:15:07 PM UTC 25 Feb 08 06:15:58 PM UTC 25 29571397141 ps
T2755 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/37.usbdev_invalid_sync.50020461 Feb 08 06:13:57 PM UTC 25 Feb 08 06:15:59 PM UTC 25 4108737932 ps
T2756 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_out_stall.215087048 Feb 08 06:15:56 PM UTC 25 Feb 08 06:15:59 PM UTC 25 173647108 ps
T2757 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_phy_pins_sense.469308553 Feb 08 06:15:58 PM UTC 25 Feb 08 06:16:00 PM UTC 25 35193438 ps
T2758 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_out_trans_nak.3009375612 Feb 08 06:15:58 PM UTC 25 Feb 08 06:16:00 PM UTC 25 155441562 ps
T2759 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_pending_in_trans.2368636772 Feb 08 06:15:58 PM UTC 25 Feb 08 06:16:00 PM UTC 25 161535989 ps
T2760 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_phy_config_usb_ref_disable.1238839533 Feb 08 06:15:58 PM UTC 25 Feb 08 06:16:00 PM UTC 25 158956358 ps
T2761 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_phy_config_pinflip.226919263 Feb 08 06:15:58 PM UTC 25 Feb 08 06:16:01 PM UTC 25 182802284 ps
T2762 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_link_resume.810755665 Feb 08 06:15:13 PM UTC 25 Feb 08 06:16:01 PM UTC 25 24194694149 ps
T2763 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_pkt_sent.2873302757 Feb 08 06:15:59 PM UTC 25 Feb 08 06:16:02 PM UTC 25 177383045 ps
T2764 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_pkt_received.3739754577 Feb 08 06:15:59 PM UTC 25 Feb 08 06:16:02 PM UTC 25 192855883 ps
T2765 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_min_inter_pkt_delay.2980630615 Feb 08 06:15:35 PM UTC 25 Feb 08 06:16:02 PM UTC 25 2357611435 ps
T2766 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_random_length_in_transaction.2265849077 Feb 08 06:15:59 PM UTC 25 Feb 08 06:16:02 PM UTC 25 194223311 ps
T2767 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_link_resume.4130740670 Feb 08 06:15:50 PM UTC 25 Feb 08 06:16:03 PM UTC 25 6052667629 ps
T2768 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_random_length_out_transaction.2569470095 Feb 08 06:16:02 PM UTC 25 Feb 08 06:16:04 PM UTC 25 181833466 ps
T2769 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_setup_trans_ignored.722022468 Feb 08 06:16:02 PM UTC 25 Feb 08 06:16:04 PM UTC 25 156493975 ps
T2770 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_timeout_missing_host_handshake.1220221188 Feb 08 06:15:29 PM UTC 25 Feb 08 06:16:05 PM UTC 25 4981733802 ps
T2771 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_rx_full.3755568590 Feb 08 06:16:02 PM UTC 25 Feb 08 06:16:05 PM UTC 25 373896363 ps
T2772 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_smoke.3975100338 Feb 08 06:16:02 PM UTC 25 Feb 08 06:16:05 PM UTC 25 278034798 ps
T2773 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_stall_priority_over_nak.984650115 Feb 08 06:16:03 PM UTC 25 Feb 08 06:16:06 PM UTC 25 164118005 ps
T2774 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_stall_trans.1880617495 Feb 08 06:16:03 PM UTC 25 Feb 08 06:16:06 PM UTC 25 187896768 ps
T2775 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_timeout_missing_host_handshake.2961937400 Feb 08 06:15:48 PM UTC 25 Feb 08 06:16:06 PM UTC 25 2235019198 ps
T2776 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_stream_len_max.3521613370 Feb 08 06:16:04 PM UTC 25 Feb 08 06:16:06 PM UTC 25 451722031 ps
T2777 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_disable_endpoint.451706833 Feb 08 06:16:25 PM UTC 25 Feb 08 06:16:30 PM UTC 25 727573762 ps
T2778 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_tx_rx_disruption.2271237671 Feb 08 06:16:04 PM UTC 25 Feb 08 06:16:07 PM UTC 25 533340711 ps
T2779 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_endpoint_access.1301891246 Feb 08 06:16:26 PM UTC 25 Feb 08 06:16:31 PM UTC 25 741085205 ps
T2780 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_spurious_pids_ignored.3931883639 Feb 08 06:15:42 PM UTC 25 Feb 08 06:16:07 PM UTC 25 2770491495 ps
T2781 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_alert_test.2028020345 Feb 08 06:16:05 PM UTC 25 Feb 08 06:16:07 PM UTC 25 41237789 ps
T2782 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_av_buffer.2416715883 Feb 08 06:16:05 PM UTC 25 Feb 08 06:16:07 PM UTC 25 167908225 ps
T2783 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_min_inter_pkt_delay.1921381798 Feb 08 06:14:36 PM UTC 25 Feb 08 06:16:08 PM UTC 25 2821239427 ps
T2784 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_bitstuff_err.2475099409 Feb 08 06:16:06 PM UTC 25 Feb 08 06:16:09 PM UTC 25 160664374 ps
T2785 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_device_timeout.1187277082 Feb 08 06:15:48 PM UTC 25 Feb 08 06:16:09 PM UTC 25 878556664 ps
T2786 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_data_toggle_clear.1811907192 Feb 08 06:16:07 PM UTC 25 Feb 08 06:16:09 PM UTC 25 424608001 ps
T2787 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_link_suspend.158026556 Feb 08 06:15:51 PM UTC 25 Feb 08 06:16:10 PM UTC 25 5866924403 ps
T2788 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_data_toggle_restore.3788486167 Feb 08 06:16:07 PM UTC 25 Feb 08 06:16:10 PM UTC 25 642890560 ps
T2789 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_pkt_buffer.482548664 Feb 08 06:15:21 PM UTC 25 Feb 08 06:16:10 PM UTC 25 18686202069 ps
T2790 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_device_address.1873729291 Feb 08 06:15:07 PM UTC 25 Feb 08 06:16:10 PM UTC 25 30353091970 ps
T2791 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_enable.2565858666 Feb 08 06:16:08 PM UTC 25 Feb 08 06:16:10 PM UTC 25 37236282 ps
T2792 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_disconnected.345822619 Feb 08 06:16:08 PM UTC 25 Feb 08 06:16:11 PM UTC 25 139719513 ps
T2793 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_max_inter_pkt_delay.2349922387 Feb 08 06:15:13 PM UTC 25 Feb 08 06:16:11 PM UTC 25 2006821097 ps
T357 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_endpoint_types.2792668820 Feb 08 06:16:08 PM UTC 25 Feb 08 06:16:12 PM UTC 25 454325267 ps
T2794 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_device_timeout.1891703507 Feb 08 06:15:09 PM UTC 25 Feb 08 06:16:12 PM UTC 25 9102332840 ps
T2795 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_fifo_rst.1348545232 Feb 08 06:16:08 PM UTC 25 Feb 08 06:16:12 PM UTC 25 165596991 ps
T2796 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_in_iso.1685680764 Feb 08 06:16:10 PM UTC 25 Feb 08 06:16:12 PM UTC 25 152711247 ps
T2797 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_in_stall.1859760673 Feb 08 06:16:10 PM UTC 25 Feb 08 06:16:12 PM UTC 25 142044289 ps
T2798 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_disable_endpoint.227937479 Feb 08 06:16:08 PM UTC 25 Feb 08 06:16:13 PM UTC 25 845703569 ps
T2799 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_aon_wake_reset.226410480 Feb 08 06:15:45 PM UTC 25 Feb 08 06:16:14 PM UTC 25 18588412172 ps
T2800 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_endpoint_access.189701972 Feb 08 06:16:08 PM UTC 25 Feb 08 06:16:14 PM UTC 25 1013405463 ps
T2801 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_endpoint_types.944765664 Feb 08 06:16:27 PM UTC 25 Feb 08 06:16:30 PM UTC 25 190553696 ps
T2802 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_link_in_err.230758158 Feb 08 06:16:12 PM UTC 25 Feb 08 06:16:14 PM UTC 25 152350841 ps
T2803 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_in_trans.619213815 Feb 08 06:16:12 PM UTC 25 Feb 08 06:16:14 PM UTC 25 173677103 ps
T2804 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_max_length_in_transaction.2588649435 Feb 08 06:16:12 PM UTC 25 Feb 08 06:16:15 PM UTC 25 259059823 ps
T2805 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_low_speed_traffic.2224765319 Feb 08 06:15:35 PM UTC 25 Feb 08 06:16:16 PM UTC 25 3741929685 ps
T2806 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_min_length_in_transaction.3254531057 Feb 08 06:16:14 PM UTC 25 Feb 08 06:16:16 PM UTC 25 175289010 ps
T2807 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_out_iso.151482462 Feb 08 06:16:14 PM UTC 25 Feb 08 06:16:16 PM UTC 25 192264034 ps
T2808 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_max_length_out_transaction.1787550853 Feb 08 06:16:14 PM UTC 25 Feb 08 06:16:17 PM UTC 25 193570604 ps
T2809 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_min_length_out_transaction.1362515138 Feb 08 06:16:14 PM UTC 25 Feb 08 06:16:17 PM UTC 25 185173610 ps
T2810 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_nak_trans.842214462 Feb 08 06:16:14 PM UTC 25 Feb 08 06:16:17 PM UTC 25 226804268 ps
T2811 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_pending_in_trans.1499863062 Feb 08 06:16:15 PM UTC 25 Feb 08 06:16:18 PM UTC 25 141974989 ps
T2812 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_out_trans_nak.1172474780 Feb 08 06:16:15 PM UTC 25 Feb 08 06:16:18 PM UTC 25 203500529 ps
T2813 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_out_stall.4242112938 Feb 08 06:16:15 PM UTC 25 Feb 08 06:16:18 PM UTC 25 245799628 ps
T2814 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_phy_config_pinflip.2026111644 Feb 08 06:16:15 PM UTC 25 Feb 08 06:16:18 PM UTC 25 263352469 ps
T2815 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_invalid_sync.1326061681 Feb 08 06:15:31 PM UTC 25 Feb 08 06:16:18 PM UTC 25 4329738276 ps
T2816 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_phy_config_usb_ref_disable.2642351481 Feb 08 06:16:17 PM UTC 25 Feb 08 06:16:19 PM UTC 25 137318379 ps
T2817 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/36.usbdev_iso_retraction.1299561130 Feb 08 06:13:39 PM UTC 25 Feb 08 06:16:19 PM UTC 25 12516474776 ps
T2818 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_aon_wake_resume.2304419676 Feb 08 06:15:27 PM UTC 25 Feb 08 06:16:19 PM UTC 25 29766215064 ps
T2819 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_aon_wake_disconnect.2472564432 Feb 08 06:16:05 PM UTC 25 Feb 08 06:16:20 PM UTC 25 6408300566 ps
T2820 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_phy_pins_sense.346372797 Feb 08 06:16:18 PM UTC 25 Feb 08 06:16:20 PM UTC 25 47095583 ps
T2821 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_pkt_sent.3798625731 Feb 08 06:16:18 PM UTC 25 Feb 08 06:16:21 PM UTC 25 180119351 ps
T2822 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_random_length_out_transaction.3512493156 Feb 08 06:16:18 PM UTC 25 Feb 08 06:16:21 PM UTC 25 205286024 ps
T2823 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_pkt_received.807198528 Feb 08 06:16:18 PM UTC 25 Feb 08 06:16:21 PM UTC 25 179272631 ps
T2824 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_random_length_in_transaction.1206091822 Feb 08 06:16:18 PM UTC 25 Feb 08 06:16:21 PM UTC 25 169106872 ps
T2825 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_link_suspend.2410484817 Feb 08 06:16:12 PM UTC 25 Feb 08 06:16:22 PM UTC 25 3947688439 ps
T2826 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_rx_crc_err.629814522 Feb 08 06:16:20 PM UTC 25 Feb 08 06:16:22 PM UTC 25 148242565 ps
T2827 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_setup_trans_ignored.1339021938 Feb 08 06:16:20 PM UTC 25 Feb 08 06:16:22 PM UTC 25 147362488 ps
T2828 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_setup_stage.2090053409 Feb 08 06:16:20 PM UTC 25 Feb 08 06:16:23 PM UTC 25 223999012 ps
T2829 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/39.usbdev_streaming_out.65158617 Feb 08 06:14:43 PM UTC 25 Feb 08 06:16:23 PM UTC 25 3403471926 ps
T2830 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_smoke.4040120074 Feb 08 06:16:20 PM UTC 25 Feb 08 06:16:23 PM UTC 25 210258186 ps
T2831 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_stall_priority_over_nak.79480916 Feb 08 06:16:20 PM UTC 25 Feb 08 06:16:23 PM UTC 25 199921257 ps
T2832 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_rx_full.742160604 Feb 08 06:16:20 PM UTC 25 Feb 08 06:16:23 PM UTC 25 331265326 ps
T2833 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_in_iso.2862952838 Feb 08 06:16:28 PM UTC 25 Feb 08 06:16:31 PM UTC 25 274272297 ps
T2834 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_stall_trans.14039347 Feb 08 06:16:22 PM UTC 25 Feb 08 06:16:24 PM UTC 25 178664230 ps
T2835 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_alert_test.3639022823 Feb 08 06:16:22 PM UTC 25 Feb 08 06:16:24 PM UTC 25 72125527 ps
T2836 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_stream_len_max.2683582521 Feb 08 06:16:22 PM UTC 25 Feb 08 06:16:25 PM UTC 25 198412094 ps
T2837 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_tx_rx_disruption.2928819390 Feb 08 06:16:22 PM UTC 25 Feb 08 06:16:25 PM UTC 25 495826368 ps
T2838 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_av_buffer.451907518 Feb 08 06:16:24 PM UTC 25 Feb 08 06:16:26 PM UTC 25 167570192 ps
T2839 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_bitstuff_err.4244456133 Feb 08 06:16:24 PM UTC 25 Feb 08 06:16:26 PM UTC 25 185884585 ps
T2840 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_data_toggle_clear.21947432 Feb 08 06:16:24 PM UTC 25 Feb 08 06:16:28 PM UTC 25 432314035 ps
T2841 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_enable.18952648 Feb 08 06:16:26 PM UTC 25 Feb 08 06:16:28 PM UTC 25 117594679 ps
T2842 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_disconnected.48876675 Feb 08 06:16:26 PM UTC 25 Feb 08 06:16:28 PM UTC 25 153164311 ps
T2843 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_link_resume.2758910524 Feb 08 06:16:12 PM UTC 25 Feb 08 06:16:28 PM UTC 25 9073079008 ps
T2844 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_aon_wake_reset.3610826802 Feb 08 06:16:05 PM UTC 25 Feb 08 06:16:29 PM UTC 25 15443550814 ps
T2845 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_data_toggle_restore.2692598533 Feb 08 06:16:24 PM UTC 25 Feb 08 06:16:30 PM UTC 25 961206652 ps
T2846 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_aon_wake_disconnect.2255221129 Feb 08 06:16:22 PM UTC 25 Feb 08 06:16:33 PM UTC 25 4573679445 ps
T2847 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_link_in_err.3353323247 Feb 08 06:16:31 PM UTC 25 Feb 08 06:16:33 PM UTC 25 204465456 ps
T2848 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_min_inter_pkt_delay.239384939 Feb 08 06:16:14 PM UTC 25 Feb 08 06:16:34 PM UTC 25 2570313432 ps
T2849 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_max_length_in_transaction.2940237258 Feb 08 06:16:32 PM UTC 25 Feb 08 06:16:35 PM UTC 25 269797218 ps
T2850 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_streaming_out.3557642176 Feb 08 06:16:03 PM UTC 25 Feb 08 06:16:35 PM UTC 25 3337594325 ps
T2851 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_streaming_out.800554414 Feb 08 06:15:43 PM UTC 25 Feb 08 06:16:36 PM UTC 25 1719239906 ps
T2852 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_min_length_in_transaction.2241240055 Feb 08 06:16:34 PM UTC 25 Feb 08 06:16:36 PM UTC 25 181900287 ps
T133 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_nak_trans.327215339 Feb 08 06:16:34 PM UTC 25 Feb 08 06:16:36 PM UTC 25 170163469 ps
T2853 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_min_length_out_transaction.888802199 Feb 08 06:16:34 PM UTC 25 Feb 08 06:16:36 PM UTC 25 154656112 ps
T2854 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_max_length_out_transaction.815886182 Feb 08 06:16:34 PM UTC 25 Feb 08 06:16:36 PM UTC 25 239124298 ps
T2855 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_out_iso.2038271947 Feb 08 06:16:35 PM UTC 25 Feb 08 06:16:38 PM UTC 25 190940922 ps
T2856 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_pending_in_trans.3546066931 Feb 08 06:16:35 PM UTC 25 Feb 08 06:16:38 PM UTC 25 161905678 ps
T2857 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_out_stall.1269135881 Feb 08 06:16:35 PM UTC 25 Feb 08 06:16:38 PM UTC 25 158572781 ps
T2858 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_out_trans_nak.1887502018 Feb 08 06:16:35 PM UTC 25 Feb 08 06:16:38 PM UTC 25 161123172 ps
T2859 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/41.usbdev_min_inter_pkt_delay.1234433264 Feb 08 06:15:17 PM UTC 25 Feb 08 06:16:38 PM UTC 25 2669112264 ps
T2860 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_device_address.255256923 Feb 08 06:16:07 PM UTC 25 Feb 08 06:16:38 PM UTC 25 16747068208 ps
T2861 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_aon_wake_resume.2093073926 Feb 08 06:15:45 PM UTC 25 Feb 08 06:16:39 PM UTC 25 29392232003 ps
T2862 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_phy_config_usb_ref_disable.2794476696 Feb 08 06:16:37 PM UTC 25 Feb 08 06:16:39 PM UTC 25 141075498 ps
T2863 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_phy_config_pinflip.2525480149 Feb 08 06:16:37 PM UTC 25 Feb 08 06:16:39 PM UTC 25 210945880 ps
T2864 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_iso_retraction.3445718510 Feb 08 06:15:33 PM UTC 25 Feb 08 06:16:40 PM UTC 25 8661811891 ps
T2865 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_phy_pins_sense.941370483 Feb 08 06:16:38 PM UTC 25 Feb 08 06:16:40 PM UTC 25 90800105 ps
T2866 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_random_length_in_transaction.1318585535 Feb 08 06:16:38 PM UTC 25 Feb 08 06:16:41 PM UTC 25 160980803 ps
T2867 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_pkt_received.3547023077 Feb 08 06:16:38 PM UTC 25 Feb 08 06:16:41 PM UTC 25 190257046 ps
T2868 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_pkt_sent.769017724 Feb 08 06:16:38 PM UTC 25 Feb 08 06:16:41 PM UTC 25 248098872 ps
T2869 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_device_timeout.3944019021 Feb 08 06:16:24 PM UTC 25 Feb 08 06:16:42 PM UTC 25 2216340997 ps
T2870 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_rx_crc_err.3913043803 Feb 08 06:16:40 PM UTC 25 Feb 08 06:16:42 PM UTC 25 147190501 ps
T2871 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_stall_priority_over_nak.3374579352 Feb 08 06:16:40 PM UTC 25 Feb 08 06:16:43 PM UTC 25 185926204 ps
T2872 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_setup_stage.539461744 Feb 08 06:16:40 PM UTC 25 Feb 08 06:16:43 PM UTC 25 199893029 ps
T2873 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_smoke.2168957859 Feb 08 06:16:40 PM UTC 25 Feb 08 06:16:43 PM UTC 25 234887146 ps
T2874 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_setup_trans_ignored.3203055132 Feb 08 06:16:40 PM UTC 25 Feb 08 06:16:43 PM UTC 25 174828358 ps
T2875 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_random_length_out_transaction.4104266958 Feb 08 06:16:40 PM UTC 25 Feb 08 06:16:43 PM UTC 25 190551977 ps
T2876 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_pkt_buffer.508800785 Feb 08 06:16:18 PM UTC 25 Feb 08 06:16:44 PM UTC 25 8521271052 ps
T2877 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_rx_full.3990918106 Feb 08 06:16:40 PM UTC 25 Feb 08 06:16:44 PM UTC 25 402108064 ps
T2878 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_phy_pins_sense.2063310054 Feb 08 06:16:54 PM UTC 25 Feb 08 06:16:56 PM UTC 25 82483976 ps
T2879 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_stall_trans.2570203363 Feb 08 06:16:42 PM UTC 25 Feb 08 06:16:44 PM UTC 25 178118463 ps
T2880 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_timeout_missing_host_handshake.1157117016 Feb 08 06:16:08 PM UTC 25 Feb 08 06:16:45 PM UTC 25 1430217876 ps
T2881 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_alert_test.2216621891 Feb 08 06:16:43 PM UTC 25 Feb 08 06:16:45 PM UTC 25 86387789 ps
T2882 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_stream_len_max.2884599214 Feb 08 06:16:42 PM UTC 25 Feb 08 06:16:45 PM UTC 25 798312999 ps
T2883 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/40.usbdev_min_inter_pkt_delay.2992329872 Feb 08 06:14:56 PM UTC 25 Feb 08 06:16:46 PM UTC 25 3927857339 ps
T2884 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_tx_rx_disruption.1791510058 Feb 08 06:16:42 PM UTC 25 Feb 08 06:16:46 PM UTC 25 529092532 ps
T2885 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_aon_wake_resume.3325660234 Feb 08 06:16:05 PM UTC 25 Feb 08 06:16:46 PM UTC 25 26238782095 ps
T2886 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_aon_wake_reset.3600615865 Feb 08 06:16:22 PM UTC 25 Feb 08 06:16:46 PM UTC 25 14687997480 ps
T2887 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_bitstuff_err.760728532 Feb 08 06:16:45 PM UTC 25 Feb 08 06:16:47 PM UTC 25 159080968 ps
T2888 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_av_buffer.2131029491 Feb 08 06:16:45 PM UTC 25 Feb 08 06:16:48 PM UTC 25 158736006 ps
T2889 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_link_suspend.3857747312 Feb 08 06:16:31 PM UTC 25 Feb 08 06:16:48 PM UTC 25 4985672643 ps
T2890 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_link_resume.405462583 Feb 08 06:15:33 PM UTC 25 Feb 08 06:16:48 PM UTC 25 32415439865 ps
T2891 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_data_toggle_clear.378872970 Feb 08 06:16:45 PM UTC 25 Feb 08 06:16:48 PM UTC 25 566495520 ps
T2892 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_disconnected.1260321306 Feb 08 06:16:46 PM UTC 25 Feb 08 06:16:49 PM UTC 25 137489696 ps
T2893 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_enable.4142862702 Feb 08 06:16:46 PM UTC 25 Feb 08 06:16:49 PM UTC 25 129811887 ps
T2894 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_data_toggle_restore.3089315169 Feb 08 06:16:45 PM UTC 25 Feb 08 06:16:50 PM UTC 25 973689775 ps
T2895 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_device_timeout.3621724374 Feb 08 06:16:07 PM UTC 25 Feb 08 06:16:50 PM UTC 25 4777070060 ps
T454 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_endpoint_types.2646409715 Feb 08 06:16:47 PM UTC 25 Feb 08 06:16:50 PM UTC 25 306086519 ps
T2896 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_endpoint_access.1203777410 Feb 08 06:16:47 PM UTC 25 Feb 08 06:16:50 PM UTC 25 772659177 ps
T2897 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_device_address.3399418658 Feb 08 06:15:27 PM UTC 25 Feb 08 06:16:50 PM UTC 25 38791856140 ps
T2898 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_pkt_buffer.1129588118 Feb 08 06:15:59 PM UTC 25 Feb 08 06:16:50 PM UTC 25 14588327916 ps
T2899 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_disable_endpoint.3349096767 Feb 08 06:16:46 PM UTC 25 Feb 08 06:16:51 PM UTC 25 776079248 ps
T2900 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_in_iso.2339505392 Feb 08 06:16:48 PM UTC 25 Feb 08 06:16:51 PM UTC 25 233583856 ps
T2901 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_max_inter_pkt_delay.3039222366 Feb 08 06:15:52 PM UTC 25 Feb 08 06:16:51 PM UTC 25 2057834231 ps
T2902 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_spurious_pids_ignored.3759343736 Feb 08 06:16:20 PM UTC 25 Feb 08 06:16:51 PM UTC 25 2481769734 ps
T2903 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/44.usbdev_streaming_out.2362896077 Feb 08 06:16:22 PM UTC 25 Feb 08 06:16:51 PM UTC 25 2515689974 ps
T2904 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_min_inter_pkt_delay.1944897078 Feb 08 06:16:34 PM UTC 25 Feb 08 06:16:52 PM UTC 25 2129772805 ps
T2905 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_in_stall.648582557 Feb 08 06:16:49 PM UTC 25 Feb 08 06:16:52 PM UTC 25 150205017 ps
T2906 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_link_in_err.678000166 Feb 08 06:16:49 PM UTC 25 Feb 08 06:16:52 PM UTC 25 235630887 ps
T2907 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_max_inter_pkt_delay.596958261 Feb 08 06:16:32 PM UTC 25 Feb 08 06:16:52 PM UTC 25 2373273932 ps
T2908 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/45.usbdev_link_resume.2286409478 Feb 08 06:16:31 PM UTC 25 Feb 08 06:16:52 PM UTC 25 8556337297 ps
T2909 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_in_trans.2588857961 Feb 08 06:16:49 PM UTC 25 Feb 08 06:16:52 PM UTC 25 275111895 ps
T2910 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_fifo_rst.4246777621 Feb 08 06:16:48 PM UTC 25 Feb 08 06:16:52 PM UTC 25 354046407 ps
T2911 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_max_length_in_transaction.1540177556 Feb 08 06:16:51 PM UTC 25 Feb 08 06:16:54 PM UTC 25 241438680 ps
T2912 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_min_length_out_transaction.3595389909 Feb 08 06:16:54 PM UTC 25 Feb 08 06:16:56 PM UTC 25 145959137 ps
T2913 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_out_stall.2580980747 Feb 08 06:16:54 PM UTC 25 Feb 08 06:16:56 PM UTC 25 178495657 ps
T2914 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/42.usbdev_max_inter_pkt_delay.1528043110 Feb 08 06:15:35 PM UTC 25 Feb 08 06:16:56 PM UTC 25 2704838269 ps
T2915 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_min_length_in_transaction.2478682902 Feb 08 06:16:54 PM UTC 25 Feb 08 06:16:56 PM UTC 25 166547366 ps
T2916 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_max_length_out_transaction.1779307 Feb 08 06:16:54 PM UTC 25 Feb 08 06:16:56 PM UTC 25 187264303 ps
T144 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_nak_trans.4272820440 Feb 08 06:16:54 PM UTC 25 Feb 08 06:16:56 PM UTC 25 218005048 ps
T2917 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_pkt_sent.2163134538 Feb 08 06:16:54 PM UTC 25 Feb 08 06:16:56 PM UTC 25 198184039 ps
T2918 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_out_trans_nak.3569150567 Feb 08 06:16:54 PM UTC 25 Feb 08 06:16:56 PM UTC 25 188574334 ps
T2919 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_out_iso.1340543360 Feb 08 06:16:54 PM UTC 25 Feb 08 06:16:56 PM UTC 25 158482080 ps
T2920 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_pending_in_trans.3605039185 Feb 08 06:16:54 PM UTC 25 Feb 08 06:16:56 PM UTC 25 146964598 ps
T2921 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_phy_config_usb_ref_disable.46616607 Feb 08 06:16:54 PM UTC 25 Feb 08 06:16:57 PM UTC 25 169741597 ps
T2922 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_pkt_received.567276292 Feb 08 06:16:54 PM UTC 25 Feb 08 06:16:57 PM UTC 25 186400405 ps
T2923 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/46.usbdev_phy_config_pinflip.2934192693 Feb 08 06:16:54 PM UTC 25 Feb 08 06:16:57 PM UTC 25 231628368 ps
T2924 /workspaces/repo/scratch/os_regression/usbdev-sim-vcs/coverage/default/43.usbdev_device_address.3068582242 Feb 08 06:15:46 PM UTC 25 Feb 08 06:16:57 PM UTC 25 40136165875 ps