| T71 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.2980333504 |
|
|
Oct 15 06:51:09 PM UTC 24 |
Oct 15 06:55:38 PM UTC 24 |
2883646404 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pattgen_ios.1711853418 |
|
|
Oct 15 06:52:09 PM UTC 24 |
Oct 15 06:55:40 PM UTC 24 |
2090979648 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3636666171 |
|
|
Oct 15 05:50:09 PM UTC 24 |
Oct 15 06:55:58 PM UTC 24 |
14666305108 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_smoke.2235010474 |
|
|
Oct 15 05:44:51 PM UTC 24 |
Oct 15 06:56:37 PM UTC 24 |
14986439976 ps |
| T19 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3883379957 |
|
|
Oct 15 06:50:28 PM UTC 24 |
Oct 15 06:57:04 PM UTC 24 |
3096629833 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.1666230560 |
|
|
Oct 15 06:49:14 PM UTC 24 |
Oct 15 06:57:21 PM UTC 24 |
5410977422 ps |
| T24 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.3768603348 |
|
|
Oct 15 06:50:29 PM UTC 24 |
Oct 15 06:57:43 PM UTC 24 |
6596014250 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3952319693 |
|
|
Oct 15 05:45:27 PM UTC 24 |
Oct 15 06:57:59 PM UTC 24 |
15019776936 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.1841179764 |
|
|
Oct 15 05:44:12 PM UTC 24 |
Oct 15 06:58:10 PM UTC 24 |
25508050280 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1059104694 |
|
|
Oct 15 06:49:35 PM UTC 24 |
Oct 15 06:58:40 PM UTC 24 |
4685256032 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3286313668 |
|
|
Oct 15 05:49:05 PM UTC 24 |
Oct 15 06:59:35 PM UTC 24 |
14375874295 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2695348354 |
|
|
Oct 15 05:48:40 PM UTC 24 |
Oct 15 06:59:36 PM UTC 24 |
14820326536 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1248777593 |
|
|
Oct 15 05:44:57 PM UTC 24 |
Oct 15 06:59:52 PM UTC 24 |
15570669490 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2379310441 |
|
|
Oct 15 05:48:39 PM UTC 24 |
Oct 15 07:00:00 PM UTC 24 |
15954345870 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.128781064 |
|
|
Oct 15 05:45:26 PM UTC 24 |
Oct 15 07:00:56 PM UTC 24 |
15272758808 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.2613145175 |
|
|
Oct 15 06:52:40 PM UTC 24 |
Oct 15 07:01:15 PM UTC 24 |
4716219056 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2659214503 |
|
|
Oct 15 05:46:54 PM UTC 24 |
Oct 15 07:01:17 PM UTC 24 |
15011129288 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.1304696618 |
|
|
Oct 15 06:50:25 PM UTC 24 |
Oct 15 07:02:45 PM UTC 24 |
6071864734 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_smoketest.1151439256 |
|
|
Oct 15 06:42:57 PM UTC 24 |
Oct 15 07:02:50 PM UTC 24 |
6718626046 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_tpm.3989726753 |
|
|
Oct 15 06:56:41 PM UTC 24 |
Oct 15 07:02:51 PM UTC 24 |
2948503853 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.2383306759 |
|
|
Oct 15 06:52:40 PM UTC 24 |
Oct 15 07:02:57 PM UTC 24 |
4172593350 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1985247024 |
|
|
Oct 15 06:55:05 PM UTC 24 |
Oct 15 07:03:01 PM UTC 24 |
4746690771 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.45821946 |
|
|
Oct 15 06:57:17 PM UTC 24 |
Oct 15 07:03:05 PM UTC 24 |
2978929224 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.4159285579 |
|
|
Oct 15 06:57:43 PM UTC 24 |
Oct 15 07:03:30 PM UTC 24 |
3933231046 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.818377959 |
|
|
Oct 15 06:53:59 PM UTC 24 |
Oct 15 07:03:36 PM UTC 24 |
4606773426 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.934628392 |
|
|
Oct 15 06:54:03 PM UTC 24 |
Oct 15 07:05:47 PM UTC 24 |
4737631540 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3271048901 |
|
|
Oct 15 05:47:54 PM UTC 24 |
Oct 15 07:05:48 PM UTC 24 |
15519448940 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.3381313723 |
|
|
Oct 15 06:56:40 PM UTC 24 |
Oct 15 07:05:55 PM UTC 24 |
4439079444 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.409819450 |
|
|
Oct 15 07:02:06 PM UTC 24 |
Oct 15 07:06:07 PM UTC 24 |
3059532900 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.2122556461 |
|
|
Oct 15 06:58:24 PM UTC 24 |
Oct 15 07:06:21 PM UTC 24 |
4536788951 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2287453083 |
|
|
Oct 15 07:00:44 PM UTC 24 |
Oct 15 07:06:30 PM UTC 24 |
3633840504 ps |
| T40 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.3400356568 |
|
|
Oct 15 06:58:51 PM UTC 24 |
Oct 15 07:06:52 PM UTC 24 |
3702993437 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.4237048860 |
|
|
Oct 15 05:46:50 PM UTC 24 |
Oct 15 07:07:03 PM UTC 24 |
16319704286 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.2802063581 |
|
|
Oct 15 05:54:36 PM UTC 24 |
Oct 15 07:07:28 PM UTC 24 |
14871151280 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.205958092 |
|
|
Oct 15 06:56:37 PM UTC 24 |
Oct 15 07:08:30 PM UTC 24 |
4470359230 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.4150060294 |
|
|
Oct 15 06:55:41 PM UTC 24 |
Oct 15 07:08:42 PM UTC 24 |
5245856798 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.509454477 |
|
|
Oct 15 06:55:41 PM UTC 24 |
Oct 15 07:08:42 PM UTC 24 |
4742745928 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.2223086405 |
|
|
Oct 15 04:47:29 PM UTC 24 |
Oct 15 07:09:33 PM UTC 24 |
31767567192 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.3804154198 |
|
|
Oct 15 06:58:52 PM UTC 24 |
Oct 15 07:09:37 PM UTC 24 |
3985547736 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.535747216 |
|
|
Oct 15 07:07:25 PM UTC 24 |
Oct 15 07:09:51 PM UTC 24 |
1962963170 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3972632111 |
|
|
Oct 15 06:59:33 PM UTC 24 |
Oct 15 07:10:01 PM UTC 24 |
3877828921 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3711762626 |
|
|
Oct 15 07:07:51 PM UTC 24 |
Oct 15 07:10:05 PM UTC 24 |
2696263630 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3396535290 |
|
|
Oct 15 07:04:57 PM UTC 24 |
Oct 15 07:10:07 PM UTC 24 |
3417024085 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.4055675281 |
|
|
Oct 15 07:04:44 PM UTC 24 |
Oct 15 07:10:11 PM UTC 24 |
3499075008 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3062267894 |
|
|
Oct 15 06:59:33 PM UTC 24 |
Oct 15 07:10:27 PM UTC 24 |
4928592450 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.34445844 |
|
|
Oct 15 07:04:51 PM UTC 24 |
Oct 15 07:10:41 PM UTC 24 |
3294671066 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.1182738486 |
|
|
Oct 15 06:51:09 PM UTC 24 |
Oct 15 07:10:44 PM UTC 24 |
8894961440 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2932921333 |
|
|
Oct 15 06:09:56 PM UTC 24 |
Oct 15 07:11:21 PM UTC 24 |
32022754614 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.4210194157 |
|
|
Oct 15 07:07:25 PM UTC 24 |
Oct 15 07:11:32 PM UTC 24 |
3660444405 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.2666629280 |
|
|
Oct 15 06:57:58 PM UTC 24 |
Oct 15 07:12:10 PM UTC 24 |
7797278916 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.3210657975 |
|
|
Oct 15 05:59:38 PM UTC 24 |
Oct 15 07:12:23 PM UTC 24 |
15140089252 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.3736940548 |
|
|
Oct 15 07:09:34 PM UTC 24 |
Oct 15 07:13:17 PM UTC 24 |
2698145662 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_descrambling.3411696720 |
|
|
Oct 15 07:05:01 PM UTC 24 |
Oct 15 07:13:25 PM UTC 24 |
4198783048 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.2024220725 |
|
|
Oct 15 05:57:21 PM UTC 24 |
Oct 15 07:13:57 PM UTC 24 |
15582296904 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.183658595 |
|
|
Oct 15 06:09:55 PM UTC 24 |
Oct 15 07:14:15 PM UTC 24 |
39964082814 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2589888065 |
|
|
Oct 15 07:04:47 PM UTC 24 |
Oct 15 07:15:11 PM UTC 24 |
3959623192 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.866506882 |
|
|
Oct 15 06:10:02 PM UTC 24 |
Oct 15 07:15:13 PM UTC 24 |
31095246901 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.4114708261 |
|
|
Oct 15 07:09:30 PM UTC 24 |
Oct 15 07:15:40 PM UTC 24 |
4555257720 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.2962746148 |
|
|
Oct 15 05:59:37 PM UTC 24 |
Oct 15 07:16:13 PM UTC 24 |
15780812995 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.2149458552 |
|
|
Oct 15 07:00:44 PM UTC 24 |
Oct 15 07:16:24 PM UTC 24 |
5069851860 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3476079052 |
|
|
Oct 15 07:11:01 PM UTC 24 |
Oct 15 07:17:07 PM UTC 24 |
5106425507 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1460938287 |
|
|
Oct 15 07:13:04 PM UTC 24 |
Oct 15 07:17:21 PM UTC 24 |
2662600344 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.1613063605 |
|
|
Oct 15 07:14:06 PM UTC 24 |
Oct 15 07:17:24 PM UTC 24 |
2413368222 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1425335204 |
|
|
Oct 15 07:00:44 PM UTC 24 |
Oct 15 07:19:14 PM UTC 24 |
6428230620 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3089096011 |
|
|
Oct 15 07:02:05 PM UTC 24 |
Oct 15 07:20:42 PM UTC 24 |
5338662987 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3352462363 |
|
|
Oct 15 07:12:21 PM UTC 24 |
Oct 15 07:20:43 PM UTC 24 |
7660116720 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2522412804 |
|
|
Oct 15 07:12:11 PM UTC 24 |
Oct 15 07:20:54 PM UTC 24 |
7156011856 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.658505661 |
|
|
Oct 15 07:12:18 PM UTC 24 |
Oct 15 07:20:58 PM UTC 24 |
9486646208 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2313284859 |
|
|
Oct 15 07:14:55 PM UTC 24 |
Oct 15 07:22:04 PM UTC 24 |
3253887641 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.3373928325 |
|
|
Oct 15 07:11:50 PM UTC 24 |
Oct 15 07:22:16 PM UTC 24 |
6393509316 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2809927591 |
|
|
Oct 15 06:55:05 PM UTC 24 |
Oct 15 07:22:18 PM UTC 24 |
8364440532 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.969755717 |
|
|
Oct 15 07:12:12 PM UTC 24 |
Oct 15 07:22:25 PM UTC 24 |
6925001895 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.3417937208 |
|
|
Oct 15 07:07:17 PM UTC 24 |
Oct 15 07:22:53 PM UTC 24 |
10855838504 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2466777343 |
|
|
Oct 15 07:04:42 PM UTC 24 |
Oct 15 07:22:59 PM UTC 24 |
8094765220 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2758916261 |
|
|
Oct 15 07:16:03 PM UTC 24 |
Oct 15 07:23:00 PM UTC 24 |
5121786734 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.601304583 |
|
|
Oct 15 07:17:06 PM UTC 24 |
Oct 15 07:24:13 PM UTC 24 |
3945438922 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.4182290136 |
|
|
Oct 15 07:18:22 PM UTC 24 |
Oct 15 07:25:19 PM UTC 24 |
3881144280 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3920680297 |
|
|
Oct 15 07:04:43 PM UTC 24 |
Oct 15 07:26:07 PM UTC 24 |
9882723334 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3757606250 |
|
|
Oct 15 07:14:06 PM UTC 24 |
Oct 15 07:26:15 PM UTC 24 |
5196510206 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.21761029 |
|
|
Oct 15 07:07:45 PM UTC 24 |
Oct 15 07:26:22 PM UTC 24 |
11265083688 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.1164414537 |
|
|
Oct 15 07:18:06 PM UTC 24 |
Oct 15 07:26:23 PM UTC 24 |
4302591164 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2394557170 |
|
|
Oct 15 07:16:03 PM UTC 24 |
Oct 15 07:26:26 PM UTC 24 |
4473111333 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2480788030 |
|
|
Oct 15 07:04:49 PM UTC 24 |
Oct 15 07:26:39 PM UTC 24 |
7430836740 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1993098325 |
|
|
Oct 15 07:18:21 PM UTC 24 |
Oct 15 07:26:45 PM UTC 24 |
6533690164 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.392434420 |
|
|
Oct 15 07:23:55 PM UTC 24 |
Oct 15 07:27:57 PM UTC 24 |
2521614290 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.667797039 |
|
|
Oct 15 07:23:55 PM UTC 24 |
Oct 15 07:28:40 PM UTC 24 |
3391308989 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2294844880 |
|
|
Oct 15 07:19:53 PM UTC 24 |
Oct 15 07:28:43 PM UTC 24 |
5222709208 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.2023377473 |
|
|
Oct 15 07:23:56 PM UTC 24 |
Oct 15 07:28:53 PM UTC 24 |
3046270285 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2344240784 |
|
|
Oct 15 05:49:20 PM UTC 24 |
Oct 15 07:29:01 PM UTC 24 |
17980508482 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.87036012 |
|
|
Oct 15 07:23:16 PM UTC 24 |
Oct 15 07:29:18 PM UTC 24 |
2590757368 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.908793971 |
|
|
Oct 15 07:00:38 PM UTC 24 |
Oct 15 07:29:25 PM UTC 24 |
17995814247 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1003819789 |
|
|
Oct 15 07:11:28 PM UTC 24 |
Oct 15 07:29:31 PM UTC 24 |
8433636696 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.74744370 |
|
|
Oct 15 07:24:55 PM UTC 24 |
Oct 15 07:29:44 PM UTC 24 |
2380301240 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2154688911 |
|
|
Oct 15 05:47:38 PM UTC 24 |
Oct 15 07:29:59 PM UTC 24 |
18932826674 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.985221636 |
|
|
Oct 15 07:22:39 PM UTC 24 |
Oct 15 07:30:37 PM UTC 24 |
3260185250 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1874433193 |
|
|
Oct 15 07:21:52 PM UTC 24 |
Oct 15 07:31:09 PM UTC 24 |
19717789272 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2222460753 |
|
|
Oct 15 07:12:22 PM UTC 24 |
Oct 15 07:32:16 PM UTC 24 |
12662610343 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3017299290 |
|
|
Oct 15 07:18:18 PM UTC 24 |
Oct 15 07:32:43 PM UTC 24 |
9631913412 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2546947477 |
|
|
Oct 15 06:14:30 PM UTC 24 |
Oct 15 07:33:26 PM UTC 24 |
14802953520 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.460118853 |
|
|
Oct 15 07:25:59 PM UTC 24 |
Oct 15 07:33:29 PM UTC 24 |
5383564234 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.797881974 |
|
|
Oct 15 07:12:26 PM UTC 24 |
Oct 15 07:33:35 PM UTC 24 |
10770532018 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.3013331859 |
|
|
Oct 15 07:28:37 PM UTC 24 |
Oct 15 07:33:36 PM UTC 24 |
3219402290 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.3357502669 |
|
|
Oct 15 07:28:04 PM UTC 24 |
Oct 15 07:33:42 PM UTC 24 |
2881384038 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.4270925600 |
|
|
Oct 15 05:39:09 PM UTC 24 |
Oct 15 07:33:44 PM UTC 24 |
34728297249 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.1892885397 |
|
|
Oct 15 07:29:59 PM UTC 24 |
Oct 15 07:34:06 PM UTC 24 |
2539020556 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.320266329 |
|
|
Oct 15 07:28:05 PM UTC 24 |
Oct 15 07:34:57 PM UTC 24 |
4209899384 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1576732235 |
|
|
Oct 15 06:17:48 PM UTC 24 |
Oct 15 07:35:05 PM UTC 24 |
14976453150 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.3088421420 |
|
|
Oct 15 07:30:57 PM UTC 24 |
Oct 15 07:35:08 PM UTC 24 |
2597235840 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.1246623211 |
|
|
Oct 15 07:30:55 PM UTC 24 |
Oct 15 07:35:53 PM UTC 24 |
2818535302 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.4284035910 |
|
|
Oct 15 07:21:53 PM UTC 24 |
Oct 15 07:36:03 PM UTC 24 |
6282700724 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2240715917 |
|
|
Oct 15 07:31:49 PM UTC 24 |
Oct 15 07:36:23 PM UTC 24 |
2514380024 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1786334022 |
|
|
Oct 15 07:23:17 PM UTC 24 |
Oct 15 07:37:22 PM UTC 24 |
4392806536 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.4192235779 |
|
|
Oct 15 06:54:04 PM UTC 24 |
Oct 15 07:37:32 PM UTC 24 |
12538291270 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.3150593864 |
|
|
Oct 15 07:30:10 PM UTC 24 |
Oct 15 07:38:27 PM UTC 24 |
2776192296 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.3003048047 |
|
|
Oct 15 07:35:19 PM UTC 24 |
Oct 15 07:39:16 PM UTC 24 |
2876044240 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.799557207 |
|
|
Oct 15 07:11:39 PM UTC 24 |
Oct 15 07:39:26 PM UTC 24 |
10975174727 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.207255654 |
|
|
Oct 15 07:09:30 PM UTC 24 |
Oct 15 07:39:44 PM UTC 24 |
12572344814 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.1792877466 |
|
|
Oct 15 07:23:15 PM UTC 24 |
Oct 15 07:39:52 PM UTC 24 |
5251241860 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.1821349798 |
|
|
Oct 15 07:35:12 PM UTC 24 |
Oct 15 07:39:56 PM UTC 24 |
2645213472 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.4101249022 |
|
|
Oct 15 07:35:13 PM UTC 24 |
Oct 15 07:40:13 PM UTC 24 |
2801263363 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.1015901220 |
|
|
Oct 15 06:12:40 PM UTC 24 |
Oct 15 07:40:14 PM UTC 24 |
18050680928 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2892819014 |
|
|
Oct 15 06:19:20 PM UTC 24 |
Oct 15 07:40:19 PM UTC 24 |
15399645624 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.3639972129 |
|
|
Oct 15 07:35:24 PM UTC 24 |
Oct 15 07:40:48 PM UTC 24 |
2520232342 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3477656562 |
|
|
Oct 15 07:31:18 PM UTC 24 |
Oct 15 07:40:49 PM UTC 24 |
4424439510 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.2169077383 |
|
|
Oct 15 07:37:04 PM UTC 24 |
Oct 15 07:41:29 PM UTC 24 |
3113138780 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3700096942 |
|
|
Oct 15 07:30:49 PM UTC 24 |
Oct 15 07:41:55 PM UTC 24 |
5407891200 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.3331971110 |
|
|
Oct 15 07:30:52 PM UTC 24 |
Oct 15 07:42:06 PM UTC 24 |
3768639936 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.3661071481 |
|
|
Oct 15 07:39:08 PM UTC 24 |
Oct 15 07:42:15 PM UTC 24 |
2585747088 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3929453942 |
|
|
Oct 15 07:38:14 PM UTC 24 |
Oct 15 07:42:42 PM UTC 24 |
3209944999 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1588396657 |
|
|
Oct 15 07:28:04 PM UTC 24 |
Oct 15 07:43:11 PM UTC 24 |
4702542644 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.862615812 |
|
|
Oct 15 07:16:20 PM UTC 24 |
Oct 15 07:43:18 PM UTC 24 |
23458428574 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.1319869981 |
|
|
Oct 15 07:38:10 PM UTC 24 |
Oct 15 07:43:19 PM UTC 24 |
2809187860 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.2783112590 |
|
|
Oct 15 07:40:07 PM UTC 24 |
Oct 15 07:43:32 PM UTC 24 |
2083224564 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.896733675 |
|
|
Oct 15 07:27:57 PM UTC 24 |
Oct 15 07:44:46 PM UTC 24 |
9521865422 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1205112022 |
|
|
Oct 15 07:08:08 PM UTC 24 |
Oct 15 07:45:50 PM UTC 24 |
30058511112 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.114670374 |
|
|
Oct 15 07:41:46 PM UTC 24 |
Oct 15 07:46:56 PM UTC 24 |
3203763034 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.3712520950 |
|
|
Oct 15 07:43:21 PM UTC 24 |
Oct 15 07:47:17 PM UTC 24 |
2602772200 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1011660027 |
|
|
Oct 15 07:40:16 PM UTC 24 |
Oct 15 07:48:16 PM UTC 24 |
8809567732 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.271713699 |
|
|
Oct 15 07:11:40 PM UTC 24 |
Oct 15 07:49:29 PM UTC 24 |
25966492389 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2861181763 |
|
|
Oct 15 05:49:09 PM UTC 24 |
Oct 15 07:49:56 PM UTC 24 |
23957567690 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.693000609 |
|
|
Oct 15 07:41:43 PM UTC 24 |
Oct 15 07:50:22 PM UTC 24 |
4863037960 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2071431597 |
|
|
Oct 15 07:41:12 PM UTC 24 |
Oct 15 07:50:31 PM UTC 24 |
4072464371 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.534658821 |
|
|
Oct 15 07:33:24 PM UTC 24 |
Oct 15 07:50:35 PM UTC 24 |
7021661840 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2027641912 |
|
|
Oct 15 07:44:21 PM UTC 24 |
Oct 15 07:50:38 PM UTC 24 |
4298165000 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3882033806 |
|
|
Oct 15 07:44:21 PM UTC 24 |
Oct 15 07:51:04 PM UTC 24 |
4346226744 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1698765867 |
|
|
Oct 15 07:28:01 PM UTC 24 |
Oct 15 07:51:13 PM UTC 24 |
7347645754 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.39463344 |
|
|
Oct 15 05:49:53 PM UTC 24 |
Oct 15 07:51:27 PM UTC 24 |
23235316356 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.533499528 |
|
|
Oct 15 07:35:22 PM UTC 24 |
Oct 15 07:51:31 PM UTC 24 |
6160085112 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2180364126 |
|
|
Oct 15 07:44:25 PM UTC 24 |
Oct 15 07:51:38 PM UTC 24 |
4403654812 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.122113420 |
|
|
Oct 15 05:49:34 PM UTC 24 |
Oct 15 07:52:24 PM UTC 24 |
23591799265 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.2971668796 |
|
|
Oct 15 07:28:03 PM UTC 24 |
Oct 15 07:52:36 PM UTC 24 |
7406496220 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.790652363 |
|
|
Oct 15 07:42:59 PM UTC 24 |
Oct 15 07:52:51 PM UTC 24 |
3624632280 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3289199349 |
|
|
Oct 15 07:41:41 PM UTC 24 |
Oct 15 07:53:00 PM UTC 24 |
7748306990 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2989137688 |
|
|
Oct 15 07:40:28 PM UTC 24 |
Oct 15 07:53:20 PM UTC 24 |
5485580888 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.596338418 |
|
|
Oct 15 07:45:26 PM UTC 24 |
Oct 15 07:54:00 PM UTC 24 |
3848161630 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1458593946 |
|
|
Oct 15 05:47:09 PM UTC 24 |
Oct 15 07:54:08 PM UTC 24 |
24150173960 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.4001103958 |
|
|
Oct 15 05:46:52 PM UTC 24 |
Oct 15 07:54:26 PM UTC 24 |
24956974456 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3907675690 |
|
|
Oct 15 07:41:48 PM UTC 24 |
Oct 15 07:54:30 PM UTC 24 |
8283638032 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.538916749 |
|
|
Oct 15 05:47:51 PM UTC 24 |
Oct 15 07:54:34 PM UTC 24 |
25078023560 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.2758994308 |
|
|
Oct 15 07:30:59 PM UTC 24 |
Oct 15 07:54:37 PM UTC 24 |
7093084616 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1351412272 |
|
|
Oct 15 07:46:28 PM UTC 24 |
Oct 15 07:54:42 PM UTC 24 |
7137383242 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.687480618 |
|
|
Oct 15 07:41:12 PM UTC 24 |
Oct 15 07:54:46 PM UTC 24 |
9795938126 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.63146853 |
|
|
Oct 15 07:42:59 PM UTC 24 |
Oct 15 07:55:27 PM UTC 24 |
4019864180 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.2997534520 |
|
|
Oct 15 07:51:48 PM UTC 24 |
Oct 15 07:56:33 PM UTC 24 |
3423603920 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.515267203 |
|
|
Oct 15 05:50:02 PM UTC 24 |
Oct 15 07:56:39 PM UTC 24 |
23419076408 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3572021861 |
|
|
Oct 15 07:47:55 PM UTC 24 |
Oct 15 07:56:50 PM UTC 24 |
4772694504 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.2080133057 |
|
|
Oct 15 07:41:47 PM UTC 24 |
Oct 15 07:56:55 PM UTC 24 |
6558910290 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1248756600 |
|
|
Oct 15 05:47:58 PM UTC 24 |
Oct 15 07:57:15 PM UTC 24 |
23979279848 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2722127724 |
|
|
Oct 15 07:47:35 PM UTC 24 |
Oct 15 07:57:20 PM UTC 24 |
4195319164 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.57060055 |
|
|
Oct 15 07:51:51 PM UTC 24 |
Oct 15 07:59:07 PM UTC 24 |
3978984144 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.2733811031 |
|
|
Oct 15 07:44:22 PM UTC 24 |
Oct 15 07:59:13 PM UTC 24 |
8297509492 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.3264554698 |
|
|
Oct 15 07:55:32 PM UTC 24 |
Oct 15 07:59:16 PM UTC 24 |
3434508958 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.3964610258 |
|
|
Oct 15 07:30:56 PM UTC 24 |
Oct 15 07:59:52 PM UTC 24 |
7599391864 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1114150303 |
|
|
Oct 15 07:53:58 PM UTC 24 |
Oct 15 08:00:03 PM UTC 24 |
6116981360 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.3245871870 |
|
|
Oct 15 07:55:42 PM UTC 24 |
Oct 15 08:00:14 PM UTC 24 |
3389176890 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.1221412707 |
|
|
Oct 15 07:51:46 PM UTC 24 |
Oct 15 08:00:24 PM UTC 24 |
3413542500 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3591388108 |
|
|
Oct 15 07:50:10 PM UTC 24 |
Oct 15 08:00:25 PM UTC 24 |
5169054680 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.810043195 |
|
|
Oct 15 07:48:57 PM UTC 24 |
Oct 15 08:00:31 PM UTC 24 |
4689981336 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.924896028 |
|
|
Oct 15 07:53:16 PM UTC 24 |
Oct 15 08:00:38 PM UTC 24 |
7124611632 ps |
| T1038 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.108729721 |
|
|
Oct 15 07:51:19 PM UTC 24 |
Oct 15 08:00:40 PM UTC 24 |
4870217762 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2726207450 |
|
|
Oct 15 07:53:38 PM UTC 24 |
Oct 15 08:00:42 PM UTC 24 |
3671139240 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.4098756749 |
|
|
Oct 15 07:42:31 PM UTC 24 |
Oct 15 08:01:50 PM UTC 24 |
6887464120 ps |
| T1039 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.189739072 |
|
|
Oct 15 08:12:31 PM UTC 24 |
Oct 15 08:16:38 PM UTC 24 |
2792509490 ps |
| T1040 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.897296710 |
|
|
Oct 15 07:58:07 PM UTC 24 |
Oct 15 08:02:04 PM UTC 24 |
2363038433 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.3608714856 |
|
|
Oct 15 07:52:23 PM UTC 24 |
Oct 15 08:02:16 PM UTC 24 |
4706927174 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.3949024433 |
|
|
Oct 15 07:55:38 PM UTC 24 |
Oct 15 08:02:36 PM UTC 24 |
6170759029 ps |
| T1041 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2455504568 |
|
|
Oct 15 07:50:36 PM UTC 24 |
Oct 15 08:02:41 PM UTC 24 |
3749799000 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2281081810 |
|
|
Oct 15 07:58:05 PM UTC 24 |
Oct 15 08:02:54 PM UTC 24 |
3108651869 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1412053827 |
|
|
Oct 15 07:55:46 PM UTC 24 |
Oct 15 08:02:56 PM UTC 24 |
4174938620 ps |
| T1042 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.103923807 |
|
|
Oct 15 07:51:52 PM UTC 24 |
Oct 15 08:03:09 PM UTC 24 |
4796512134 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.2141899285 |
|
|
Oct 15 07:32:58 PM UTC 24 |
Oct 15 08:03:22 PM UTC 24 |
7804289280 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.3075586898 |
|
|
Oct 15 07:54:52 PM UTC 24 |
Oct 15 08:03:33 PM UTC 24 |
4014055756 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1677828760 |
|
|
Oct 15 07:57:37 PM UTC 24 |
Oct 15 08:03:36 PM UTC 24 |
2541571704 ps |
| T1043 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.1761322176 |
|
|
Oct 15 08:12:04 PM UTC 24 |
Oct 15 08:16:38 PM UTC 24 |
2683978584 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2711818683 |
|
|
Oct 15 07:54:52 PM UTC 24 |
Oct 15 08:03:51 PM UTC 24 |
5893661740 ps |
| T1044 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.355151303 |
|
|
Oct 15 07:58:06 PM UTC 24 |
Oct 15 08:03:54 PM UTC 24 |
3384372426 ps |
| T1045 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.1287795861 |
|
|
Oct 15 07:55:47 PM UTC 24 |
Oct 15 08:04:34 PM UTC 24 |
7209746498 ps |
| T1046 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.1387867118 |
|
|
Oct 15 07:36:02 PM UTC 24 |
Oct 15 08:04:46 PM UTC 24 |
9583146336 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1191415073 |
|
|
Oct 15 07:55:48 PM UTC 24 |
Oct 15 08:05:14 PM UTC 24 |
4810957630 ps |
| T1047 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2567552566 |
|
|
Oct 15 08:00:40 PM UTC 24 |
Oct 15 08:05:22 PM UTC 24 |
2722058237 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3088273916 |
|
|
Oct 15 08:01:54 PM UTC 24 |
Oct 15 08:06:14 PM UTC 24 |
3588224098 ps |
| T1048 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.374867793 |
|
|
Oct 15 08:01:48 PM UTC 24 |
Oct 15 08:06:35 PM UTC 24 |
3745782381 ps |
| T1049 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.2759773471 |
|
|
Oct 15 07:58:07 PM UTC 24 |
Oct 15 08:06:42 PM UTC 24 |
4702587846 ps |
| T1050 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.3761217175 |
|
|
Oct 15 07:35:22 PM UTC 24 |
Oct 15 08:06:51 PM UTC 24 |
8641432134 ps |
| T1051 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.37171339 |
|
|
Oct 15 08:04:25 PM UTC 24 |
Oct 15 08:07:43 PM UTC 24 |
3028127528 ps |
| T1052 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.3689432731 |
|
|
Oct 15 07:55:59 PM UTC 24 |
Oct 15 08:08:02 PM UTC 24 |
8664634170 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1025060055 |
|
|
Oct 15 08:02:16 PM UTC 24 |
Oct 15 08:09:55 PM UTC 24 |
5387396692 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.666692745 |
|
|
Oct 15 08:00:08 PM UTC 24 |
Oct 15 08:09:59 PM UTC 24 |
4912342002 ps |
| T1053 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.2945904110 |
|
|
Oct 15 07:52:22 PM UTC 24 |
Oct 15 08:10:27 PM UTC 24 |
7192494904 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.1268816861 |
|
|
Oct 15 07:51:40 PM UTC 24 |
Oct 15 08:10:31 PM UTC 24 |
11769075942 ps |
| T1054 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.2225060695 |
|
|
Oct 15 08:08:08 PM UTC 24 |
Oct 15 08:10:48 PM UTC 24 |
2523339693 ps |
| T1055 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.3991840568 |
|
|
Oct 15 08:08:04 PM UTC 24 |
Oct 15 08:11:05 PM UTC 24 |
2609681064 ps |
| T1056 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.3186423415 |
|
|
Oct 15 08:01:56 PM UTC 24 |
Oct 15 08:11:13 PM UTC 24 |
10800123988 ps |
| T1057 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1114549826 |
|
|
Oct 15 07:12:47 PM UTC 24 |
Oct 15 08:11:14 PM UTC 24 |
37125930616 ps |
| T1058 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1745929781 |
|
|
Oct 15 07:17:07 PM UTC 24 |
Oct 15 08:11:40 PM UTC 24 |
20004442772 ps |
| T1059 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.3491945899 |
|
|
Oct 15 08:07:56 PM UTC 24 |
Oct 15 08:11:52 PM UTC 24 |
2715352200 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.404791742 |
|
|
Oct 15 08:07:15 PM UTC 24 |
Oct 15 08:12:05 PM UTC 24 |
6527853939 ps |
| T1060 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.2411539835 |
|
|
Oct 15 08:07:30 PM UTC 24 |
Oct 15 08:12:17 PM UTC 24 |
2942588016 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.2632336758 |
|
|
Oct 15 08:08:26 PM UTC 24 |
Oct 15 08:12:37 PM UTC 24 |
2754579170 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.2688372615 |
|
|
Oct 15 08:02:10 PM UTC 24 |
Oct 15 08:13:26 PM UTC 24 |
4653954112 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.2929707814 |
|
|
Oct 15 08:08:24 PM UTC 24 |
Oct 15 08:13:39 PM UTC 24 |
2760109608 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.27961122 |
|
|
Oct 15 08:07:55 PM UTC 24 |
Oct 15 08:14:12 PM UTC 24 |
3265367980 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.4106479552 |
|
|
Oct 15 07:51:51 PM UTC 24 |
Oct 15 08:14:56 PM UTC 24 |
13307126808 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.1861021809 |
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Oct 15 08:08:43 PM UTC 24 |
Oct 15 08:15:24 PM UTC 24 |
3366341244 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.453108895 |
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Oct 15 08:12:48 PM UTC 24 |
Oct 15 08:15:28 PM UTC 24 |
3013430860 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.1123257375 |
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Oct 15 08:12:04 PM UTC 24 |
Oct 15 08:16:10 PM UTC 24 |
2970242236 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.3258913538 |
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Oct 15 08:12:05 PM UTC 24 |
Oct 15 08:16:13 PM UTC 24 |
3105336696 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.2972405902 |
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Oct 15 08:12:27 PM UTC 24 |
Oct 15 08:16:24 PM UTC 24 |
2653113720 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.2920278134 |
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Oct 15 08:12:47 PM UTC 24 |
Oct 15 08:16:26 PM UTC 24 |
2779571128 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.3470199955 |
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|
Oct 15 08:10:46 PM UTC 24 |
Oct 15 08:16:36 PM UTC 24 |
3374184408 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.2017785159 |
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Oct 15 08:11:29 PM UTC 24 |
Oct 15 08:16:53 PM UTC 24 |
2642347130 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.2232652260 |
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Oct 15 08:13:16 PM UTC 24 |
Oct 15 08:17:16 PM UTC 24 |
2055773236 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.835084029 |
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Oct 15 07:53:45 PM UTC 24 |
Oct 15 08:17:35 PM UTC 24 |
23124895888 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.1513121105 |
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Oct 15 08:08:09 PM UTC 24 |
Oct 15 08:18:04 PM UTC 24 |
4420065430 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3757255131 |
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Oct 15 08:11:39 PM UTC 24 |
Oct 15 08:18:09 PM UTC 24 |
5735895332 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.574848705 |
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|
Oct 15 08:14:06 PM UTC 24 |
Oct 15 08:18:22 PM UTC 24 |
2832072664 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_aes.1489719717 |
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Oct 15 07:36:42 PM UTC 24 |
Oct 15 08:18:49 PM UTC 24 |
13246228500 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.3239326631 |
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Oct 15 08:14:20 PM UTC 24 |
Oct 15 08:18:52 PM UTC 24 |
2737796768 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.1404720321 |
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Oct 15 08:11:26 PM UTC 24 |
Oct 15 08:19:00 PM UTC 24 |
6879421488 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1796750578 |
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Oct 15 08:00:07 PM UTC 24 |
Oct 15 08:19:12 PM UTC 24 |
7537966003 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2604134595 |
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|
Oct 15 08:02:58 PM UTC 24 |
Oct 15 08:19:21 PM UTC 24 |
5349029406 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3761864085 |
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Oct 15 07:53:45 PM UTC 24 |
Oct 15 08:21:49 PM UTC 24 |
23591763070 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.3222071457 |
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Oct 15 08:18:16 PM UTC 24 |
Oct 15 08:22:29 PM UTC 24 |
2639020000 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.1876355282 |
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Oct 15 08:18:27 PM UTC 24 |
Oct 15 08:24:03 PM UTC 24 |
3709231628 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.1096858357 |
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Oct 15 08:14:54 PM UTC 24 |
Oct 15 08:24:42 PM UTC 24 |
5792603866 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.119125465 |
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Oct 15 08:18:39 PM UTC 24 |
Oct 15 08:25:30 PM UTC 24 |
5178678662 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.748806370 |
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Oct 15 08:21:21 PM UTC 24 |
Oct 15 08:26:09 PM UTC 24 |
2955544280 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.4286764901 |
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Oct 15 08:15:38 PM UTC 24 |
Oct 15 08:26:16 PM UTC 24 |
4796080384 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2747023931 |
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Oct 15 08:22:31 PM UTC 24 |
Oct 15 08:27:14 PM UTC 24 |
3633043242 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_virus.518762776 |
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Oct 15 08:04:11 PM UTC 24 |
Oct 15 08:27:54 PM UTC 24 |
5977302320 ps |