| T939 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_smoketest.2117038863 |
|
|
Feb 09 07:48:17 PM UTC 25 |
Feb 09 07:54:37 PM UTC 25 |
3171810884 ps |
| T940 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.4045185814 |
|
|
Feb 09 06:31:56 PM UTC 25 |
Feb 09 07:54:41 PM UTC 25 |
15927727688 ps |
| T941 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_concurrency.4082815767 |
|
|
Feb 09 07:49:19 PM UTC 25 |
Feb 09 07:54:49 PM UTC 25 |
3686621850 ps |
| T942 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sival_flash_info_access.1394009744 |
|
|
Feb 09 07:49:19 PM UTC 25 |
Feb 09 07:55:08 PM UTC 25 |
3390891806 ps |
| T943 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_manufacturer.3942608972 |
|
|
Feb 09 07:48:51 PM UTC 25 |
Feb 09 07:55:11 PM UTC 25 |
3459348910 ps |
| T463 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.852299166 |
|
|
Feb 09 07:08:22 PM UTC 25 |
Feb 09 07:55:19 PM UTC 25 |
32656658573 ps |
| T944 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.4236293013 |
|
|
Feb 09 06:39:18 PM UTC 25 |
Feb 09 07:55:23 PM UTC 25 |
14797000375 ps |
| T945 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.845698949 |
|
|
Feb 09 06:39:39 PM UTC 25 |
Feb 09 07:55:25 PM UTC 25 |
14142926750 ps |
| T253 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.2868670624 |
|
|
Feb 09 05:43:46 PM UTC 25 |
Feb 09 07:55:27 PM UTC 25 |
47870854153 ps |
| T946 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1702172546 |
|
|
Feb 09 06:41:38 PM UTC 25 |
Feb 09 07:55:32 PM UTC 25 |
14360928600 ps |
| T947 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1203949504 |
|
|
Feb 09 06:33:29 PM UTC 25 |
Feb 09 07:56:08 PM UTC 25 |
15748142234 ps |
| T25 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.2663841827 |
|
|
Feb 09 07:51:46 PM UTC 25 |
Feb 09 07:56:11 PM UTC 25 |
3248878786 ps |
| T135 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pattgen_ios.4036214532 |
|
|
Feb 09 07:52:09 PM UTC 25 |
Feb 09 07:56:44 PM UTC 25 |
3298972196 ps |
| T449 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1390861443 |
|
|
Feb 09 06:33:35 PM UTC 25 |
Feb 09 07:56:55 PM UTC 25 |
14950692656 ps |
| T21 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1305670900 |
|
|
Feb 09 07:51:06 PM UTC 25 |
Feb 09 07:56:58 PM UTC 25 |
3007022681 ps |
| T79 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.794455607 |
|
|
Feb 09 07:51:44 PM UTC 25 |
Feb 09 07:57:10 PM UTC 25 |
4070934040 ps |
| T450 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_smoketest.3178421857 |
|
|
Feb 09 07:42:16 PM UTC 25 |
Feb 09 07:57:21 PM UTC 25 |
5159596600 ps |
| T451 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3157491201 |
|
|
Feb 09 06:32:38 PM UTC 25 |
Feb 09 07:58:14 PM UTC 25 |
15873795492 ps |
| T452 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1990570867 |
|
|
Feb 09 06:42:21 PM UTC 25 |
Feb 09 07:58:14 PM UTC 25 |
15292515736 ps |
| T453 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.4151267963 |
|
|
Feb 09 06:41:34 PM UTC 25 |
Feb 09 07:59:14 PM UTC 25 |
15264653416 ps |
| T454 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.3327278310 |
|
|
Feb 09 06:57:06 PM UTC 25 |
Feb 09 08:00:20 PM UTC 25 |
32571446982 ps |
| T97 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.1409800259 |
|
|
Feb 09 05:33:32 PM UTC 25 |
Feb 09 08:00:52 PM UTC 25 |
31588834642 ps |
| T389 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.275733848 |
|
|
Feb 09 07:49:38 PM UTC 25 |
Feb 09 08:00:53 PM UTC 25 |
5163874272 ps |
| T388 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1092730691 |
|
|
Feb 09 07:50:51 PM UTC 25 |
Feb 09 08:01:00 PM UTC 25 |
5108108712 ps |
| T51 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.419705065 |
|
|
Feb 09 07:58:14 PM UTC 25 |
Feb 09 08:05:57 PM UTC 25 |
4076307480 ps |
| T472 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.4105035978 |
|
|
Feb 09 05:57:27 PM UTC 25 |
Feb 09 08:02:19 PM UTC 25 |
21797608472 ps |
| T67 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.8912509 |
|
|
Feb 09 07:57:23 PM UTC 25 |
Feb 09 08:03:13 PM UTC 25 |
3368470692 ps |
| T398 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.59771171 |
|
|
Feb 09 06:31:12 PM UTC 25 |
Feb 09 08:03:17 PM UTC 25 |
27122322460 ps |
| T948 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.1131833499 |
|
|
Feb 09 06:52:02 PM UTC 25 |
Feb 09 08:04:00 PM UTC 25 |
15101427486 ps |
| T56 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.1433311874 |
|
|
Feb 09 07:57:37 PM UTC 25 |
Feb 09 08:04:05 PM UTC 25 |
3075104272 ps |
| T132 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.3132777707 |
|
|
Feb 09 07:54:45 PM UTC 25 |
Feb 09 08:04:38 PM UTC 25 |
3911075320 ps |
| T134 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.4282097407 |
|
|
Feb 09 07:54:41 PM UTC 25 |
Feb 09 08:04:43 PM UTC 25 |
4093326024 ps |
| T350 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.1106658047 |
|
|
Feb 09 07:52:51 PM UTC 25 |
Feb 09 08:04:58 PM UTC 25 |
4715270308 ps |
| T58 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_tpm.512818152 |
|
|
Feb 09 07:57:26 PM UTC 25 |
Feb 09 08:05:19 PM UTC 25 |
3554848992 ps |
| T949 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.4267743990 |
|
|
Feb 09 06:49:04 PM UTC 25 |
Feb 09 08:05:32 PM UTC 25 |
15057442588 ps |
| T950 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.112992385 |
|
|
Feb 09 07:54:44 PM UTC 25 |
Feb 09 08:05:56 PM UTC 25 |
4713154856 ps |
| T951 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1423955823 |
|
|
Feb 09 07:59:03 PM UTC 25 |
Feb 09 08:06:01 PM UTC 25 |
3340776984 ps |
| T380 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.240538177 |
|
|
Feb 09 07:57:26 PM UTC 25 |
Feb 09 08:06:41 PM UTC 25 |
4422806616 ps |
| T301 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.4148536056 |
|
|
Feb 09 07:50:51 PM UTC 25 |
Feb 09 08:06:46 PM UTC 25 |
5520388620 ps |
| T304 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2676770294 |
|
|
Feb 09 07:56:54 PM UTC 25 |
Feb 09 08:06:51 PM UTC 25 |
4602119496 ps |
| T191 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.180760289 |
|
|
Feb 09 08:04:49 PM UTC 25 |
Feb 09 08:07:17 PM UTC 25 |
2534767226 ps |
| T305 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1261228376 |
|
|
Feb 09 08:01:52 PM UTC 25 |
Feb 09 08:07:37 PM UTC 25 |
3261727922 ps |
| T226 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.2591741138 |
|
|
Feb 09 07:57:59 PM UTC 25 |
Feb 09 08:08:01 PM UTC 25 |
4414065514 ps |
| T258 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2524156836 |
|
|
Feb 09 07:58:23 PM UTC 25 |
Feb 09 08:08:16 PM UTC 25 |
4273117757 ps |
| T306 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1940639830 |
|
|
Feb 09 06:43:01 PM UTC 25 |
Feb 09 08:08:37 PM UTC 25 |
14172868381 ps |
| T307 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2802649798 |
|
|
Feb 09 07:58:21 PM UTC 25 |
Feb 09 08:09:55 PM UTC 25 |
4448247062 ps |
| T308 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.585214584 |
|
|
Feb 09 07:57:58 PM UTC 25 |
Feb 09 08:10:27 PM UTC 25 |
4604802866 ps |
| T309 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3857051039 |
|
|
Feb 09 08:06:57 PM UTC 25 |
Feb 09 08:10:31 PM UTC 25 |
2731757935 ps |
| T649 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2574348824 |
|
|
Feb 09 08:07:36 PM UTC 25 |
Feb 09 08:10:33 PM UTC 25 |
2157857092 ps |
| T650 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.868805336 |
|
|
Feb 09 08:06:05 PM UTC 25 |
Feb 09 08:10:36 PM UTC 25 |
3339683604 ps |
| T952 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2895167291 |
|
|
Feb 09 08:05:42 PM UTC 25 |
Feb 09 08:10:51 PM UTC 25 |
2732066831 ps |
| T70 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1677094239 |
|
|
Feb 09 07:58:02 PM UTC 25 |
Feb 09 08:11:00 PM UTC 25 |
4214395450 ps |
| T385 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.659369739 |
|
|
Feb 09 07:58:19 PM UTC 25 |
Feb 09 08:11:51 PM UTC 25 |
3723264120 ps |
| T953 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.1235197723 |
|
|
Feb 09 08:07:55 PM UTC 25 |
Feb 09 08:11:58 PM UTC 25 |
2983510920 ps |
| T954 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.293207948 |
|
|
Feb 09 08:08:16 PM UTC 25 |
Feb 09 08:12:59 PM UTC 25 |
2321164662 ps |
| T955 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.3508006366 |
|
|
Feb 09 07:51:47 PM UTC 25 |
Feb 09 08:13:03 PM UTC 25 |
7659583270 ps |
| T69 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.1610277038 |
|
|
Feb 09 07:57:24 PM UTC 25 |
Feb 09 08:13:14 PM UTC 25 |
5421114850 ps |
| T956 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2934044591 |
|
|
Feb 09 08:02:58 PM UTC 25 |
Feb 09 08:13:35 PM UTC 25 |
4295738400 ps |
| T957 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.1703867525 |
|
|
Feb 09 08:05:41 PM UTC 25 |
Feb 09 08:13:45 PM UTC 25 |
6805047201 ps |
| T958 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1283834728 |
|
|
Feb 09 06:36:07 PM UTC 25 |
Feb 09 08:13:47 PM UTC 25 |
18007926460 ps |
| T227 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.1324219215 |
|
|
Feb 09 07:57:37 PM UTC 25 |
Feb 09 08:14:01 PM UTC 25 |
8150961962 ps |
| T959 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.2368107275 |
|
|
Feb 09 06:51:55 PM UTC 25 |
Feb 09 08:14:46 PM UTC 25 |
15367762947 ps |
| T960 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.3047009576 |
|
|
Feb 09 07:58:23 PM UTC 25 |
Feb 09 08:14:52 PM UTC 25 |
5563820312 ps |
| T464 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.3282629099 |
|
|
Feb 09 07:11:36 PM UTC 25 |
Feb 09 08:16:04 PM UTC 25 |
40663685824 ps |
| T961 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2970275197 |
|
|
Feb 09 08:10:34 PM UTC 25 |
Feb 09 08:17:29 PM UTC 25 |
4834711132 ps |
| T962 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_descrambling.2960911313 |
|
|
Feb 09 08:05:45 PM UTC 25 |
Feb 09 08:18:18 PM UTC 25 |
3982126540 ps |
| T963 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1283234653 |
|
|
Feb 09 07:59:03 PM UTC 25 |
Feb 09 08:18:18 PM UTC 25 |
5685222560 ps |
| T663 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.161107143 |
|
|
Feb 09 08:14:07 PM UTC 25 |
Feb 09 08:18:57 PM UTC 25 |
2974775238 ps |
| T178 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1211523783 |
|
|
Feb 09 08:09:15 PM UTC 25 |
Feb 09 08:19:09 PM UTC 25 |
7038726673 ps |
| T964 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.4105707219 |
|
|
Feb 09 08:14:48 PM UTC 25 |
Feb 09 08:19:49 PM UTC 25 |
3451389712 ps |
| T232 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.122417408 |
|
|
Feb 09 08:14:47 PM UTC 25 |
Feb 09 08:20:49 PM UTC 25 |
3197789716 ps |
| T965 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3722096976 |
|
|
Feb 09 08:01:53 PM UTC 25 |
Feb 09 08:20:58 PM UTC 25 |
5715217357 ps |
| T966 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3907902190 |
|
|
Feb 09 08:12:24 PM UTC 25 |
Feb 09 08:20:59 PM UTC 25 |
6788098920 ps |
| T967 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2490991627 |
|
|
Feb 09 08:14:00 PM UTC 25 |
Feb 09 08:21:07 PM UTC 25 |
5814839874 ps |
| T133 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.1771666376 |
|
|
Feb 09 07:56:43 PM UTC 25 |
Feb 09 08:21:42 PM UTC 25 |
8267658616 ps |
| T968 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.56888551 |
|
|
Feb 09 08:12:38 PM UTC 25 |
Feb 09 08:22:00 PM UTC 25 |
6852978488 ps |
| T969 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1710009381 |
|
|
Feb 09 08:14:42 PM UTC 25 |
Feb 09 08:22:01 PM UTC 25 |
5185820830 ps |
| T270 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.3000421508 |
|
|
Feb 09 08:08:55 PM UTC 25 |
Feb 09 08:22:40 PM UTC 25 |
5555708920 ps |
| T970 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.546797472 |
|
|
Feb 09 08:06:58 PM UTC 25 |
Feb 09 08:22:46 PM UTC 25 |
10208233225 ps |
| T971 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.578023218 |
|
|
Feb 09 08:04:05 PM UTC 25 |
Feb 09 08:23:21 PM UTC 25 |
7255135676 ps |
| T972 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3950749086 |
|
|
Feb 09 08:04:48 PM UTC 25 |
Feb 09 08:24:21 PM UTC 25 |
7861176852 ps |
| T54 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3897267494 |
|
|
Feb 09 08:15:38 PM UTC 25 |
Feb 09 08:25:38 PM UTC 25 |
7231279110 ps |
| T973 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.1429623171 |
|
|
Feb 09 06:50:47 PM UTC 25 |
Feb 09 08:25:58 PM UTC 25 |
15453015610 ps |
| T974 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1737202994 |
|
|
Feb 09 07:57:00 PM UTC 25 |
Feb 09 08:26:37 PM UTC 25 |
8816542893 ps |
| T975 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.616974735 |
|
|
Feb 09 08:12:05 PM UTC 25 |
Feb 09 08:26:45 PM UTC 25 |
8396519604 ps |
| T976 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.1114762739 |
|
|
Feb 09 08:23:28 PM UTC 25 |
Feb 09 08:27:37 PM UTC 25 |
2928998720 ps |
| T233 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.2616309475 |
|
|
Feb 09 08:18:09 PM UTC 25 |
Feb 09 08:27:55 PM UTC 25 |
3941084296 ps |
| T977 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2057094941 |
|
|
Feb 09 08:12:00 PM UTC 25 |
Feb 09 08:28:14 PM UTC 25 |
8327814936 ps |
| T978 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.2241246947 |
|
|
Feb 09 08:23:57 PM UTC 25 |
Feb 09 08:28:24 PM UTC 25 |
2540949299 ps |
| T979 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2287203960 |
|
|
Feb 09 08:20:27 PM UTC 25 |
Feb 09 08:28:33 PM UTC 25 |
5251945452 ps |
| T980 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2444895737 |
|
|
Feb 09 08:04:05 PM UTC 25 |
Feb 09 08:28:47 PM UTC 25 |
9070231764 ps |
| T981 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3267418144 |
|
|
Feb 09 08:19:42 PM UTC 25 |
Feb 09 08:29:10 PM UTC 25 |
7480083184 ps |
| T982 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.1520266410 |
|
|
Feb 09 08:24:58 PM UTC 25 |
Feb 09 08:29:35 PM UTC 25 |
2541932428 ps |
| T983 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.1992147643 |
|
|
Feb 09 08:19:07 PM UTC 25 |
Feb 09 08:29:30 PM UTC 25 |
3820678008 ps |
| T678 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.2563476587 |
|
|
Feb 09 08:26:18 PM UTC 25 |
Feb 09 08:31:59 PM UTC 25 |
2606241026 ps |
| T234 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2454187221 |
|
|
Feb 09 08:15:38 PM UTC 25 |
Feb 09 08:29:52 PM UTC 25 |
4925092980 ps |
| T984 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3250660099 |
|
|
Feb 09 08:11:54 PM UTC 25 |
Feb 09 08:30:50 PM UTC 25 |
14844307101 ps |
| T985 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3288248733 |
|
|
Feb 09 08:22:06 PM UTC 25 |
Feb 09 08:30:50 PM UTC 25 |
5097258392 ps |
| T423 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2594889388 |
|
|
Feb 09 06:33:29 PM UTC 25 |
Feb 09 08:31:36 PM UTC 25 |
19296170920 ps |
| T310 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.2089462715 |
|
|
Feb 09 08:22:47 PM UTC 25 |
Feb 09 08:32:20 PM UTC 25 |
3151756940 ps |
| T986 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2816825811 |
|
|
Feb 09 08:12:05 PM UTC 25 |
Feb 09 08:33:07 PM UTC 25 |
9110874677 ps |
| T84 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.1793652163 |
|
|
Feb 09 08:26:39 PM UTC 25 |
Feb 09 08:33:32 PM UTC 25 |
3441726912 ps |
| T987 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.2688255741 |
|
|
Feb 09 08:30:30 PM UTC 25 |
Feb 09 08:33:37 PM UTC 25 |
2617171434 ps |
| T988 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.4079292673 |
|
|
Feb 09 08:19:45 PM UTC 25 |
Feb 09 08:35:41 PM UTC 25 |
10203827200 ps |
| T989 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.2058541324 |
|
|
Feb 09 08:01:54 PM UTC 25 |
Feb 09 08:35:49 PM UTC 25 |
7444961376 ps |
| T103 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.1145922807 |
|
|
Feb 09 08:29:46 PM UTC 25 |
Feb 09 08:35:51 PM UTC 25 |
3602263897 ps |
| T104 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.2274222572 |
|
|
Feb 09 08:27:26 PM UTC 25 |
Feb 09 08:36:19 PM UTC 25 |
4237006088 ps |
| T990 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.237129520 |
|
|
Feb 09 08:30:20 PM UTC 25 |
Feb 09 08:36:37 PM UTC 25 |
3007778988 ps |
| T107 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2826839156 |
|
|
Feb 09 08:29:24 PM UTC 25 |
Feb 09 08:36:57 PM UTC 25 |
4605960038 ps |
| T111 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.39639018 |
|
|
Feb 09 08:22:06 PM UTC 25 |
Feb 09 08:38:06 PM UTC 25 |
19786234294 ps |
| T112 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.943531036 |
|
|
Feb 09 08:08:42 PM UTC 25 |
Feb 09 08:38:32 PM UTC 25 |
11186532324 ps |
| T113 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.2755958051 |
|
|
Feb 09 08:22:05 PM UTC 25 |
Feb 09 08:38:50 PM UTC 25 |
5445965066 ps |
| T114 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.1489279047 |
|
|
Feb 09 08:27:24 PM UTC 25 |
Feb 09 08:38:53 PM UTC 25 |
5136347024 ps |
| T115 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.1524066536 |
|
|
Feb 09 08:33:46 PM UTC 25 |
Feb 09 08:39:48 PM UTC 25 |
3142873416 ps |
| T116 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2628750600 |
|
|
Feb 09 08:34:21 PM UTC 25 |
Feb 09 08:40:03 PM UTC 25 |
3534593572 ps |
| T117 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.427506175 |
|
|
Feb 09 08:31:41 PM UTC 25 |
Feb 09 08:40:13 PM UTC 25 |
3234801120 ps |
| T118 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.4040362911 |
|
|
Feb 09 08:22:48 PM UTC 25 |
Feb 09 08:40:21 PM UTC 25 |
5522429056 ps |
| T119 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3818739752 |
|
|
Feb 09 08:23:27 PM UTC 25 |
Feb 09 08:41:00 PM UTC 25 |
4614432494 ps |
| T991 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.757399332 |
|
|
Feb 09 08:37:36 PM UTC 25 |
Feb 09 08:41:23 PM UTC 25 |
3151576792 ps |
| T992 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.1032264791 |
|
|
Feb 09 08:37:00 PM UTC 25 |
Feb 09 08:41:28 PM UTC 25 |
3464654466 ps |
| T993 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.4253008613 |
|
|
Feb 09 08:37:16 PM UTC 25 |
Feb 09 08:42:21 PM UTC 25 |
2968859338 ps |
| T994 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2667228736 |
|
|
Feb 09 08:12:04 PM UTC 25 |
Feb 09 08:42:30 PM UTC 25 |
11719861064 ps |
| T259 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.2604858512 |
|
|
Feb 09 07:59:47 PM UTC 25 |
Feb 09 08:43:18 PM UTC 25 |
23192090910 ps |
| T995 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.1764258452 |
|
|
Feb 09 08:38:44 PM UTC 25 |
Feb 09 08:43:26 PM UTC 25 |
2274416934 ps |
| T996 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1483755812 |
|
|
Feb 09 08:34:21 PM UTC 25 |
Feb 09 08:43:27 PM UTC 25 |
4008359874 ps |
| T997 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.2043014200 |
|
|
Feb 09 08:31:41 PM UTC 25 |
Feb 09 08:45:02 PM UTC 25 |
3771213198 ps |
| T998 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3305580834 |
|
|
Feb 09 08:32:38 PM UTC 25 |
Feb 09 08:45:35 PM UTC 25 |
5281051796 ps |
| T439 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.740677122 |
|
|
Feb 09 08:43:11 PM UTC 25 |
Feb 09 08:46:09 PM UTC 25 |
2554718680 ps |
| T999 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.1409159394 |
|
|
Feb 09 08:41:40 PM UTC 25 |
Feb 09 08:46:14 PM UTC 25 |
3403176712 ps |
| T1000 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2166784982 |
|
|
Feb 09 08:07:40 PM UTC 25 |
Feb 09 08:46:15 PM UTC 25 |
27869397064 ps |
| T1001 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.584249470 |
|
|
Feb 09 06:35:37 PM UTC 25 |
Feb 09 08:46:22 PM UTC 25 |
23575579980 ps |
| T424 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.81820733 |
|
|
Feb 09 06:35:08 PM UTC 25 |
Feb 09 08:46:34 PM UTC 25 |
23882223136 ps |
| T1002 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.181499172 |
|
|
Feb 09 08:43:12 PM UTC 25 |
Feb 09 08:47:45 PM UTC 25 |
2683085682 ps |
| T235 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.2829422174 |
|
|
Feb 09 08:16:44 PM UTC 25 |
Feb 09 08:47:51 PM UTC 25 |
24659943648 ps |
| T1003 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.3465872312 |
|
|
Feb 09 08:42:12 PM UTC 25 |
Feb 09 08:47:52 PM UTC 25 |
3418136034 ps |
| T1004 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1027762779 |
|
|
Feb 09 08:42:12 PM UTC 25 |
Feb 09 08:48:33 PM UTC 25 |
2987401855 ps |
| T1005 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.4116141510 |
|
|
Feb 09 06:36:16 PM UTC 25 |
Feb 09 08:49:20 PM UTC 25 |
23663154336 ps |
| T1006 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.2781417066 |
|
|
Feb 09 07:12:14 PM UTC 25 |
Feb 09 08:49:58 PM UTC 25 |
17837071076 ps |
| T1007 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1521092707 |
|
|
Feb 09 06:36:39 PM UTC 25 |
Feb 09 08:52:54 PM UTC 25 |
22873333918 ps |
| T284 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.761144512 |
|
|
Feb 09 08:49:10 PM UTC 25 |
Feb 09 08:53:27 PM UTC 25 |
2624923200 ps |
| T359 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.518558517 |
|
|
Feb 09 08:47:37 PM UTC 25 |
Feb 09 08:53:32 PM UTC 25 |
3259857024 ps |
| T1008 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2722762446 |
|
|
Feb 09 06:36:29 PM UTC 25 |
Feb 09 08:54:03 PM UTC 25 |
23842750894 ps |
| T440 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3663931116 |
|
|
Feb 09 08:44:19 PM UTC 25 |
Feb 09 08:54:13 PM UTC 25 |
9663319716 ps |
| T1009 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.369537359 |
|
|
Feb 09 08:28:17 PM UTC 25 |
Feb 09 08:54:28 PM UTC 25 |
7352711980 ps |
| T166 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2743981677 |
|
|
Feb 09 08:47:36 PM UTC 25 |
Feb 09 08:54:35 PM UTC 25 |
5653657160 ps |
| T311 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2460603066 |
|
|
Feb 09 08:44:20 PM UTC 25 |
Feb 09 08:54:43 PM UTC 25 |
4852854154 ps |
| T643 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.3399489056 |
|
|
Feb 09 08:30:34 PM UTC 25 |
Feb 09 08:55:07 PM UTC 25 |
5110049800 ps |
| T312 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1473558759 |
|
|
Feb 09 08:44:17 PM UTC 25 |
Feb 09 08:55:27 PM UTC 25 |
4557555352 ps |
| T471 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.104545174 |
|
|
Feb 09 08:29:27 PM UTC 25 |
Feb 09 08:55:37 PM UTC 25 |
7129002800 ps |
| T1010 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.174394514 |
|
|
Feb 09 08:46:15 PM UTC 25 |
Feb 09 08:55:38 PM UTC 25 |
6605449994 ps |
| T425 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1283767251 |
|
|
Feb 09 06:34:27 PM UTC 25 |
Feb 09 08:55:56 PM UTC 25 |
24763648588 ps |
| T1011 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.2863591746 |
|
|
Feb 09 08:36:45 PM UTC 25 |
Feb 09 08:57:56 PM UTC 25 |
6653429720 ps |
| T1012 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.533660029 |
|
|
Feb 09 08:12:02 PM UTC 25 |
Feb 09 08:57:57 PM UTC 25 |
25381620554 ps |
| T1013 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.280596733 |
|
|
Feb 09 08:29:31 PM UTC 25 |
Feb 09 08:57:59 PM UTC 25 |
7692613984 ps |
| T1014 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3645945533 |
|
|
Feb 09 06:33:28 PM UTC 25 |
Feb 09 08:58:08 PM UTC 25 |
24250985396 ps |
| T1015 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1316147650 |
|
|
Feb 09 06:34:47 PM UTC 25 |
Feb 09 08:58:11 PM UTC 25 |
24832380920 ps |
| T1016 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2694009937 |
|
|
Feb 09 08:47:36 PM UTC 25 |
Feb 09 08:58:17 PM UTC 25 |
8046434520 ps |
| T1017 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1772779980 |
|
|
Feb 09 08:50:36 PM UTC 25 |
Feb 09 08:58:21 PM UTC 25 |
4181647788 ps |
| T1018 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2102374661 |
|
|
Feb 09 08:36:46 PM UTC 25 |
Feb 09 08:58:45 PM UTC 25 |
6461015188 ps |
| T361 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.445525968 |
|
|
Feb 09 08:36:42 PM UTC 25 |
Feb 09 09:00:01 PM UTC 25 |
5456250696 ps |
| T186 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.4079572713 |
|
|
Feb 09 08:48:49 PM UTC 25 |
Feb 09 09:00:20 PM UTC 25 |
4433618000 ps |
| T1019 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.178962824 |
|
|
Feb 09 08:56:41 PM UTC 25 |
Feb 09 09:01:08 PM UTC 25 |
3077942020 ps |
| T167 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.2552308187 |
|
|
Feb 09 08:47:32 PM UTC 25 |
Feb 09 09:01:23 PM UTC 25 |
7623310168 ps |
| T1020 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.1851259823 |
|
|
Feb 09 08:32:16 PM UTC 25 |
Feb 09 09:01:41 PM UTC 25 |
7120053376 ps |
| T339 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.1507393349 |
|
|
Feb 09 08:45:41 PM UTC 25 |
Feb 09 09:01:56 PM UTC 25 |
9238217037 ps |
| T1021 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.914554775 |
|
|
Feb 09 08:53:32 PM UTC 25 |
Feb 09 09:02:11 PM UTC 25 |
4460219110 ps |
| T1022 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2143266658 |
|
|
Feb 09 08:54:17 PM UTC 25 |
Feb 09 09:02:42 PM UTC 25 |
4533027174 ps |
| T352 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.4267292035 |
|
|
Feb 09 08:48:50 PM UTC 25 |
Feb 09 09:02:52 PM UTC 25 |
5047470232 ps |
| T1023 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.4022401954 |
|
|
Feb 09 08:54:16 PM UTC 25 |
Feb 09 09:02:58 PM UTC 25 |
5297725272 ps |
| T1024 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.3322369679 |
|
|
Feb 09 08:56:42 PM UTC 25 |
Feb 09 09:03:48 PM UTC 25 |
3536241224 ps |
| T1025 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3153301341 |
|
|
Feb 09 08:39:39 PM UTC 25 |
Feb 09 09:04:53 PM UTC 25 |
6949586760 ps |
| T1026 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.782428380 |
|
|
Feb 09 08:55:25 PM UTC 25 |
Feb 09 09:04:54 PM UTC 25 |
5114167608 ps |
| T1027 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1611054754 |
|
|
Feb 09 08:54:49 PM UTC 25 |
Feb 09 09:05:09 PM UTC 25 |
6784134311 ps |
| T1028 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.1315970254 |
|
|
Feb 09 09:03:16 PM UTC 25 |
Feb 09 09:06:18 PM UTC 25 |
2804254586 ps |
| T1029 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.597050034 |
|
|
Feb 09 08:55:28 PM UTC 25 |
Feb 09 09:06:23 PM UTC 25 |
4490761376 ps |
| T1030 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2560592543 |
|
|
Feb 09 08:54:52 PM UTC 25 |
Feb 09 09:06:33 PM UTC 25 |
4148507660 ps |
| T1031 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.1190583581 |
|
|
Feb 09 09:03:31 PM UTC 25 |
Feb 09 09:06:41 PM UTC 25 |
2415693003 ps |
| T120 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3803675656 |
|
|
Feb 09 08:59:34 PM UTC 25 |
Feb 09 09:06:56 PM UTC 25 |
7711364320 ps |
| T1032 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.146944551 |
|
|
Feb 09 08:55:43 PM UTC 25 |
Feb 09 09:06:56 PM UTC 25 |
3845079032 ps |
| T1033 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2593275060 |
|
|
Feb 09 08:55:28 PM UTC 25 |
Feb 09 09:07:05 PM UTC 25 |
4492875000 ps |
| T1034 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2399681176 |
|
|
Feb 09 08:56:39 PM UTC 25 |
Feb 09 09:07:10 PM UTC 25 |
4612611716 ps |
| T123 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.3620467938 |
|
|
Feb 09 09:02:00 PM UTC 25 |
Feb 09 09:07:16 PM UTC 25 |
4500762248 ps |
| T1035 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3503744802 |
|
|
Feb 09 09:01:01 PM UTC 25 |
Feb 09 09:07:43 PM UTC 25 |
6223395984 ps |
| T382 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3495958583 |
|
|
Feb 09 08:59:33 PM UTC 25 |
Feb 09 09:08:05 PM UTC 25 |
3777722620 ps |
| T208 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.969881565 |
|
|
Feb 09 09:04:28 PM UTC 25 |
Feb 09 09:08:33 PM UTC 25 |
2541783844 ps |
| T1036 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2090845710 |
|
|
Feb 09 08:47:34 PM UTC 25 |
Feb 09 09:29:19 PM UTC 25 |
23519775192 ps |
| T1037 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.265634217 |
|
|
Feb 09 08:58:31 PM UTC 25 |
Feb 09 09:09:36 PM UTC 25 |
4056300184 ps |
| T1038 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3769302591 |
|
|
Feb 09 08:56:43 PM UTC 25 |
Feb 09 09:10:01 PM UTC 25 |
5227901309 ps |
| T333 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3878176356 |
|
|
Feb 09 09:05:54 PM UTC 25 |
Feb 09 09:10:04 PM UTC 25 |
2519364453 ps |
| T354 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.1597533413 |
|
|
Feb 09 08:48:48 PM UTC 25 |
Feb 09 09:10:23 PM UTC 25 |
6352751880 ps |
| T199 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.1016419489 |
|
|
Feb 09 08:59:24 PM UTC 25 |
Feb 09 09:10:25 PM UTC 25 |
5027623830 ps |
| T1039 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.2202254710 |
|
|
Feb 09 09:02:35 PM UTC 25 |
Feb 09 09:11:21 PM UTC 25 |
6333233298 ps |
| T263 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1387062150 |
|
|
Feb 09 09:02:20 PM UTC 25 |
Feb 09 09:11:29 PM UTC 25 |
5163857964 ps |
| T96 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.1853545281 |
|
|
Feb 09 09:03:16 PM UTC 25 |
Feb 09 09:11:32 PM UTC 25 |
5073822083 ps |
| T1040 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.3227715241 |
|
|
Feb 09 08:39:10 PM UTC 25 |
Feb 09 09:12:07 PM UTC 25 |
8832975360 ps |
| T402 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2632769186 |
|
|
Feb 09 09:01:57 PM UTC 25 |
Feb 09 09:12:10 PM UTC 25 |
7070733976 ps |
| T1041 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1227356216 |
|
|
Feb 09 09:08:32 PM UTC 25 |
Feb 09 09:13:09 PM UTC 25 |
3220732635 ps |
| T397 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2599912945 |
|
|
Feb 09 09:08:49 PM UTC 25 |
Feb 09 09:13:13 PM UTC 25 |
3456628839 ps |
| T1042 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2877418108 |
|
|
Feb 09 09:08:43 PM UTC 25 |
Feb 09 09:13:45 PM UTC 25 |
3096615068 ps |
| T1043 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3016043735 |
|
|
Feb 09 09:08:29 PM UTC 25 |
Feb 09 09:14:28 PM UTC 25 |
3248355403 ps |
| T1044 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation.2743993210 |
|
|
Feb 09 08:39:38 PM UTC 25 |
Feb 09 09:14:32 PM UTC 25 |
9247941056 ps |
| T1045 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.3452021692 |
|
|
Feb 09 09:08:27 PM UTC 25 |
Feb 09 09:15:27 PM UTC 25 |
3361403590 ps |
| T1046 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.4052993556 |
|
|
Feb 09 08:41:07 PM UTC 25 |
Feb 09 09:16:01 PM UTC 25 |
10477759652 ps |
| T1047 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.3226579837 |
|
|
Feb 09 09:12:05 PM UTC 25 |
Feb 09 09:16:16 PM UTC 25 |
2522890344 ps |
| T1048 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.981973894 |
|
|
Feb 09 08:49:58 PM UTC 25 |
Feb 09 09:16:18 PM UTC 25 |
11575120776 ps |
| T666 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.1748907934 |
|
|
Feb 09 09:11:08 PM UTC 25 |
Feb 09 09:17:17 PM UTC 25 |
4296965444 ps |
| T1049 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.448252587 |
|
|
Feb 09 08:59:30 PM UTC 25 |
Feb 09 09:17:34 PM UTC 25 |
8144035524 ps |
| T313 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3283002467 |
|
|
Feb 09 09:08:40 PM UTC 25 |
Feb 09 09:18:22 PM UTC 25 |
5277858910 ps |
| T1050 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.3747381201 |
|
|
Feb 09 09:05:56 PM UTC 25 |
Feb 09 09:18:33 PM UTC 25 |
5148214624 ps |
| T1051 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2458711063 |
|
|
Feb 09 08:40:28 PM UTC 25 |
Feb 09 09:18:40 PM UTC 25 |
12375175204 ps |
| T1052 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.2416048537 |
|
|
Feb 09 09:16:36 PM UTC 25 |
Feb 09 09:18:49 PM UTC 25 |
2245179947 ps |
| T1053 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3997424697 |
|
|
Feb 09 08:14:09 PM UTC 25 |
Feb 09 09:18:58 PM UTC 25 |
40341273872 ps |
| T390 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.535961469 |
|
|
Feb 09 09:07:54 PM UTC 25 |
Feb 09 09:20:16 PM UTC 25 |
5129701783 ps |
| T1054 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.632275852 |
|
|
Feb 09 09:09:21 PM UTC 25 |
Feb 09 09:21:30 PM UTC 25 |
4565519868 ps |
| T248 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_aes.792948300 |
|
|
Feb 09 08:41:09 PM UTC 25 |
Feb 09 09:22:51 PM UTC 25 |
11349637496 ps |
| T183 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.1504217758 |
|
|
Feb 09 09:17:11 PM UTC 25 |
Feb 09 09:23:33 PM UTC 25 |
6824751853 ps |
| T101 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.3758319045 |
|
|
Feb 09 08:58:22 PM UTC 25 |
Feb 09 09:23:52 PM UTC 25 |
12154072096 ps |
| T1055 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.328932028 |
|
|
Feb 09 09:18:13 PM UTC 25 |
Feb 09 09:24:04 PM UTC 25 |
2744961448 ps |
| T1056 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.1715942596 |
|
|
Feb 09 09:19:44 PM UTC 25 |
Feb 09 09:24:08 PM UTC 25 |
2904833595 ps |
| T1057 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.1314478258 |
|
|
Feb 09 09:18:58 PM UTC 25 |
Feb 09 09:24:47 PM UTC 25 |
3459315448 ps |
| T1058 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.442831210 |
|
|
Feb 09 09:19:43 PM UTC 25 |
Feb 09 09:25:10 PM UTC 25 |
2810705400 ps |
| T1059 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.1568186448 |
|
|
Feb 09 09:19:43 PM UTC 25 |
Feb 09 09:26:16 PM UTC 25 |
2815300352 ps |
| T230 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.3125568409 |
|
|
Feb 09 08:58:23 PM UTC 25 |
Feb 09 09:26:18 PM UTC 25 |
13509308524 ps |
| T442 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.660785980 |
|
|
Feb 09 08:59:32 PM UTC 25 |
Feb 09 09:26:26 PM UTC 25 |
22232752060 ps |
| T1060 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.2728409768 |
|
|
Feb 09 09:22:10 PM UTC 25 |
Feb 09 09:26:35 PM UTC 25 |
2537384980 ps |
| T1061 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.1684601942 |
|
|
Feb 09 09:17:58 PM UTC 25 |
Feb 09 09:26:36 PM UTC 25 |
3959858040 ps |
| T90 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.890923695 |
|
|
Feb 09 09:03:23 PM UTC 25 |
Feb 09 09:27:13 PM UTC 25 |
11851791926 ps |
| T1062 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.630452826 |
|
|
Feb 09 09:20:55 PM UTC 25 |
Feb 09 09:27:32 PM UTC 25 |
2710926680 ps |
| T1063 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.1735234636 |
|
|
Feb 09 09:19:44 PM UTC 25 |
Feb 09 09:28:00 PM UTC 25 |
3226267828 ps |
| T1064 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.4165014059 |
|
|
Feb 09 09:24:55 PM UTC 25 |
Feb 09 09:28:30 PM UTC 25 |
3055216676 ps |
| T1065 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.3439404528 |
|
|
Feb 09 09:24:10 PM UTC 25 |
Feb 09 09:29:02 PM UTC 25 |
2930897012 ps |
| T1066 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3435937095 |
|
|
Feb 09 09:08:46 PM UTC 25 |
Feb 09 09:29:03 PM UTC 25 |
8041834707 ps |
| T1067 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.281053357 |
|
|
Feb 09 09:25:46 PM UTC 25 |
Feb 09 09:29:22 PM UTC 25 |
2584423470 ps |
| T1068 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.3044173137 |
|
|
Feb 09 09:27:32 PM UTC 25 |
Feb 09 09:30:35 PM UTC 25 |
2344968420 ps |
| T1069 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.3454245645 |
|
|
Feb 09 09:27:25 PM UTC 25 |
Feb 09 09:30:39 PM UTC 25 |
2976574186 ps |
| T1070 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.2322027559 |
|
|
Feb 09 09:25:27 PM UTC 25 |
Feb 09 09:30:45 PM UTC 25 |
3023052808 ps |
| T1071 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.2974915498 |
|
|
Feb 09 09:27:29 PM UTC 25 |
Feb 09 09:30:47 PM UTC 25 |
2585172008 ps |
| T1072 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.2895805579 |
|
|
Feb 09 09:27:51 PM UTC 25 |
Feb 09 09:31:52 PM UTC 25 |
2783540156 ps |
| T1073 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3516890524 |
|
|
Feb 09 09:24:55 PM UTC 25 |
Feb 09 09:32:24 PM UTC 25 |
5228400206 ps |
| T1074 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.3897773691 |
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Feb 09 09:27:30 PM UTC 25 |
Feb 09 09:32:31 PM UTC 25 |
2753070140 ps |
| T1075 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.3419677557 |
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Feb 09 09:28:11 PM UTC 25 |
Feb 09 09:32:46 PM UTC 25 |
2851935944 ps |
| T1076 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.1248751021 |
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Feb 09 09:24:40 PM UTC 25 |
Feb 09 09:32:57 PM UTC 25 |
4930334408 ps |
| T1077 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3947755259 |
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Feb 09 09:11:46 PM UTC 25 |
Feb 09 09:33:06 PM UTC 25 |
6372527624 ps |
| T1078 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.2360973821 |
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Feb 09 09:27:31 PM UTC 25 |
Feb 09 09:33:09 PM UTC 25 |
3135194688 ps |
| T1079 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3604821117 |
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Feb 09 08:19:06 PM UTC 25 |
Feb 09 09:34:03 PM UTC 25 |
20535096412 ps |
| T26 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.748181373 |
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Feb 09 09:30:18 PM UTC 25 |
Feb 09 09:35:25 PM UTC 25 |
3606118880 ps |
| T86 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.3253793072 |
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Feb 09 09:30:17 PM UTC 25 |
Feb 09 09:36:26 PM UTC 25 |
3523895062 ps |
| T49 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3196326093 |
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Feb 09 09:30:13 PM UTC 25 |
Feb 09 09:36:32 PM UTC 25 |
3523513239 ps |
| T1080 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2207773160 |
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Feb 09 08:22:21 PM UTC 25 |
Feb 09 09:37:08 PM UTC 25 |
19291222062 ps |
| T387 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.1274610588 |
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Feb 09 09:31:53 PM UTC 25 |
Feb 09 09:38:19 PM UTC 25 |
3371330620 ps |