| T94 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.1814981314 |
|
|
Oct 15 02:35:32 PM UTC 24 |
Oct 15 02:35:40 PM UTC 24 |
46427592 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1295054350 |
|
|
Oct 15 02:35:34 PM UTC 24 |
Oct 15 02:35:42 PM UTC 24 |
46894930 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.893910055 |
|
|
Oct 15 02:35:35 PM UTC 24 |
Oct 15 02:35:56 PM UTC 24 |
182651548 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.2962897092 |
|
|
Oct 15 02:35:38 PM UTC 24 |
Oct 15 02:35:56 PM UTC 24 |
126884575 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.1937604364 |
|
|
Oct 15 02:35:34 PM UTC 24 |
Oct 15 02:35:59 PM UTC 24 |
246105473 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1996709499 |
|
|
Oct 15 02:35:40 PM UTC 24 |
Oct 15 02:36:02 PM UTC 24 |
460225407 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3704600559 |
|
|
Oct 15 02:35:43 PM UTC 24 |
Oct 15 02:36:17 PM UTC 24 |
91059401 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.3820958803 |
|
|
Oct 15 02:35:36 PM UTC 24 |
Oct 15 02:36:19 PM UTC 24 |
4352658284 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.144280168 |
|
|
Oct 15 02:35:38 PM UTC 24 |
Oct 15 02:36:20 PM UTC 24 |
587961240 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.145394080 |
|
|
Oct 15 02:35:39 PM UTC 24 |
Oct 15 02:36:24 PM UTC 24 |
1087321787 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.2587145476 |
|
|
Oct 15 02:36:17 PM UTC 24 |
Oct 15 02:36:26 PM UTC 24 |
194504519 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.605005905 |
|
|
Oct 15 02:36:24 PM UTC 24 |
Oct 15 02:36:34 PM UTC 24 |
55837671 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.1235338693 |
|
|
Oct 15 02:36:25 PM UTC 24 |
Oct 15 02:36:45 PM UTC 24 |
286035274 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.849563140 |
|
|
Oct 15 02:36:29 PM UTC 24 |
Oct 15 02:37:07 PM UTC 24 |
346158484 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.214340773 |
|
|
Oct 15 02:35:34 PM UTC 24 |
Oct 15 02:37:08 PM UTC 24 |
6564972312 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.2947946459 |
|
|
Oct 15 02:36:52 PM UTC 24 |
Oct 15 02:37:22 PM UTC 24 |
373629494 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.1063905248 |
|
|
Oct 15 02:37:00 PM UTC 24 |
Oct 15 02:37:29 PM UTC 24 |
370123124 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.112429211 |
|
|
Oct 15 02:36:57 PM UTC 24 |
Oct 15 02:37:35 PM UTC 24 |
843115901 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.2021124001 |
|
|
Oct 15 02:35:35 PM UTC 24 |
Oct 15 02:37:45 PM UTC 24 |
2816310317 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1632968768 |
|
|
Oct 15 02:37:11 PM UTC 24 |
Oct 15 02:37:51 PM UTC 24 |
907553941 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.2503038513 |
|
|
Oct 15 02:36:45 PM UTC 24 |
Oct 15 02:37:52 PM UTC 24 |
3268653597 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.2759213920 |
|
|
Oct 15 02:36:26 PM UTC 24 |
Oct 15 02:38:06 PM UTC 24 |
8143532255 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.3206134075 |
|
|
Oct 15 02:36:11 PM UTC 24 |
Oct 15 02:38:23 PM UTC 24 |
4589390918 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1760641400 |
|
|
Oct 15 02:36:28 PM UTC 24 |
Oct 15 02:38:25 PM UTC 24 |
4792593548 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.1300601798 |
|
|
Oct 15 02:35:35 PM UTC 24 |
Oct 15 02:38:37 PM UTC 24 |
5081857256 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.1043148884 |
|
|
Oct 15 02:35:42 PM UTC 24 |
Oct 15 02:38:39 PM UTC 24 |
4465577869 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.2975095113 |
|
|
Oct 15 02:37:15 PM UTC 24 |
Oct 15 02:38:48 PM UTC 24 |
2025272449 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.526007793 |
|
|
Oct 15 02:38:49 PM UTC 24 |
Oct 15 02:39:00 PM UTC 24 |
50428942 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.119132068 |
|
|
Oct 15 02:36:45 PM UTC 24 |
Oct 15 02:39:00 PM UTC 24 |
2780772387 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.1276965142 |
|
|
Oct 15 02:38:51 PM UTC 24 |
Oct 15 02:39:01 PM UTC 24 |
39609665 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.1085338609 |
|
|
Oct 15 02:35:45 PM UTC 24 |
Oct 15 02:39:43 PM UTC 24 |
5246808187 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.2492898320 |
|
|
Oct 15 02:39:25 PM UTC 24 |
Oct 15 02:39:44 PM UTC 24 |
266857780 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.876951803 |
|
|
Oct 15 02:39:12 PM UTC 24 |
Oct 15 02:40:04 PM UTC 24 |
408305682 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.2330656185 |
|
|
Oct 15 02:39:05 PM UTC 24 |
Oct 15 02:40:04 PM UTC 24 |
4170531030 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.332674546 |
|
|
Oct 15 02:39:04 PM UTC 24 |
Oct 15 02:40:09 PM UTC 24 |
1550015705 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.2486320966 |
|
|
Oct 15 02:35:32 PM UTC 24 |
Oct 15 02:40:19 PM UTC 24 |
4280282117 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.3370923679 |
|
|
Oct 15 02:38:52 PM UTC 24 |
Oct 15 02:40:20 PM UTC 24 |
8925552191 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.2882889184 |
|
|
Oct 15 02:40:10 PM UTC 24 |
Oct 15 02:40:22 PM UTC 24 |
74607680 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.3829108913 |
|
|
Oct 15 02:36:00 PM UTC 24 |
Oct 15 02:40:33 PM UTC 24 |
3398006514 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.3023167311 |
|
|
Oct 15 02:39:27 PM UTC 24 |
Oct 15 02:40:45 PM UTC 24 |
5698980684 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.3050251005 |
|
|
Oct 15 02:40:10 PM UTC 24 |
Oct 15 02:40:54 PM UTC 24 |
556560754 ps |
| T1353 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.3281541039 |
|
|
Oct 15 02:40:30 PM UTC 24 |
Oct 15 02:40:56 PM UTC 24 |
147043130 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.2283195393 |
|
|
Oct 15 02:40:33 PM UTC 24 |
Oct 15 02:41:04 PM UTC 24 |
57578577 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.1957782106 |
|
|
Oct 15 02:35:46 PM UTC 24 |
Oct 15 02:41:05 PM UTC 24 |
4634294250 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.1127888717 |
|
|
Oct 15 02:40:15 PM UTC 24 |
Oct 15 02:41:08 PM UTC 24 |
924964023 ps |
| T1354 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.3131924468 |
|
|
Oct 15 02:41:19 PM UTC 24 |
Oct 15 02:41:28 PM UTC 24 |
36182546 ps |
| T1355 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.1334886032 |
|
|
Oct 15 02:41:20 PM UTC 24 |
Oct 15 02:41:30 PM UTC 24 |
55961728 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.2737342931 |
|
|
Oct 15 02:36:42 PM UTC 24 |
Oct 15 02:41:48 PM UTC 24 |
31716652044 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1811700218 |
|
|
Oct 15 02:36:46 PM UTC 24 |
Oct 15 02:41:56 PM UTC 24 |
18510549564 ps |
| T1356 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.2795418646 |
|
|
Oct 15 02:41:29 PM UTC 24 |
Oct 15 02:42:02 PM UTC 24 |
232764465 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1923535748 |
|
|
Oct 15 02:37:44 PM UTC 24 |
Oct 15 02:42:07 PM UTC 24 |
4542327652 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.3026862603 |
|
|
Oct 15 02:41:32 PM UTC 24 |
Oct 15 02:42:33 PM UTC 24 |
1895617554 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.1501300648 |
|
|
Oct 15 02:42:16 PM UTC 24 |
Oct 15 02:42:34 PM UTC 24 |
128911176 ps |
| T1357 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.4206679641 |
|
|
Oct 15 02:38:23 PM UTC 24 |
Oct 15 02:42:35 PM UTC 24 |
6011972136 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.3815906772 |
|
|
Oct 15 02:42:23 PM UTC 24 |
Oct 15 02:42:44 PM UTC 24 |
225133900 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.3490405431 |
|
|
Oct 15 02:42:30 PM UTC 24 |
Oct 15 02:42:59 PM UTC 24 |
163604135 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.3883322517 |
|
|
Oct 15 02:41:30 PM UTC 24 |
Oct 15 02:43:00 PM UTC 24 |
5270563745 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.4098126740 |
|
|
Oct 15 02:37:32 PM UTC 24 |
Oct 15 02:43:02 PM UTC 24 |
7841197988 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.3010227807 |
|
|
Oct 15 02:41:23 PM UTC 24 |
Oct 15 02:43:08 PM UTC 24 |
10017859725 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.134072331 |
|
|
Oct 15 02:41:57 PM UTC 24 |
Oct 15 02:43:10 PM UTC 24 |
1385019011 ps |
| T1358 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.4148935189 |
|
|
Oct 15 02:42:31 PM UTC 24 |
Oct 15 02:43:25 PM UTC 24 |
1110136073 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.454435975 |
|
|
Oct 15 02:37:48 PM UTC 24 |
Oct 15 02:43:33 PM UTC 24 |
4269006573 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.2518803727 |
|
|
Oct 15 02:37:45 PM UTC 24 |
Oct 15 02:43:41 PM UTC 24 |
5712741118 ps |
| T1359 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.2467758391 |
|
|
Oct 15 02:43:39 PM UTC 24 |
Oct 15 02:43:47 PM UTC 24 |
51335017 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1560509237 |
|
|
Oct 15 02:37:30 PM UTC 24 |
Oct 15 02:43:47 PM UTC 24 |
864739633 ps |
| T1360 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.554515486 |
|
|
Oct 15 02:43:50 PM UTC 24 |
Oct 15 02:44:00 PM UTC 24 |
45037408 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.831781322 |
|
|
Oct 15 02:35:36 PM UTC 24 |
Oct 15 02:44:12 PM UTC 24 |
36320605370 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.3191078155 |
|
|
Oct 15 02:43:00 PM UTC 24 |
Oct 15 02:44:41 PM UTC 24 |
231548044 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.3283910137 |
|
|
Oct 15 02:44:14 PM UTC 24 |
Oct 15 02:45:04 PM UTC 24 |
429389018 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.2884699151 |
|
|
Oct 15 02:44:14 PM UTC 24 |
Oct 15 02:45:12 PM UTC 24 |
1501941782 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.3667233011 |
|
|
Oct 15 02:35:35 PM UTC 24 |
Oct 15 02:45:19 PM UTC 24 |
45854686166 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.1229001012 |
|
|
Oct 15 02:41:55 PM UTC 24 |
Oct 15 02:45:22 PM UTC 24 |
14513368020 ps |
| T1361 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.198468444 |
|
|
Oct 15 02:43:59 PM UTC 24 |
Oct 15 02:45:34 PM UTC 24 |
8311402761 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.4009070900 |
|
|
Oct 15 02:41:20 PM UTC 24 |
Oct 15 02:45:45 PM UTC 24 |
3593760297 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.2654056990 |
|
|
Oct 15 02:43:00 PM UTC 24 |
Oct 15 02:45:46 PM UTC 24 |
4496023438 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.1259236638 |
|
|
Oct 15 02:44:39 PM UTC 24 |
Oct 15 02:45:50 PM UTC 24 |
1564157721 ps |
| T1362 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.3372291526 |
|
|
Oct 15 02:45:31 PM UTC 24 |
Oct 15 02:45:50 PM UTC 24 |
387762847 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.188249142 |
|
|
Oct 15 02:45:37 PM UTC 24 |
Oct 15 02:46:07 PM UTC 24 |
585923089 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.1709693008 |
|
|
Oct 15 02:40:46 PM UTC 24 |
Oct 15 02:46:10 PM UTC 24 |
8068861382 ps |
| T1363 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.1570590969 |
|
|
Oct 15 02:44:09 PM UTC 24 |
Oct 15 02:46:11 PM UTC 24 |
5078856422 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.3428243165 |
|
|
Oct 15 02:35:39 PM UTC 24 |
Oct 15 02:46:11 PM UTC 24 |
15962295662 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.2942080484 |
|
|
Oct 15 02:39:25 PM UTC 24 |
Oct 15 02:46:14 PM UTC 24 |
21210621814 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.2347353174 |
|
|
Oct 15 02:40:32 PM UTC 24 |
Oct 15 02:46:36 PM UTC 24 |
9349337320 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.2922385414 |
|
|
Oct 15 02:43:11 PM UTC 24 |
Oct 15 02:46:15 PM UTC 24 |
4240700432 ps |
| T1364 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.3435902402 |
|
|
Oct 15 02:45:43 PM UTC 24 |
Oct 15 02:46:37 PM UTC 24 |
960911342 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.1534873813 |
|
|
Oct 15 02:40:46 PM UTC 24 |
Oct 15 02:46:40 PM UTC 24 |
7783305621 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.1507612436 |
|
|
Oct 15 02:46:36 PM UTC 24 |
Oct 15 02:46:44 PM UTC 24 |
135325240 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.3283496629 |
|
|
Oct 15 02:46:35 PM UTC 24 |
Oct 15 02:46:45 PM UTC 24 |
46232938 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.3812361079 |
|
|
Oct 15 02:45:08 PM UTC 24 |
Oct 15 02:46:47 PM UTC 24 |
2612277876 ps |
| T1365 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1420867645 |
|
|
Oct 15 02:35:31 PM UTC 24 |
Oct 15 02:46:49 PM UTC 24 |
12826377455 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.681149008 |
|
|
Oct 15 02:46:01 PM UTC 24 |
Oct 15 02:47:02 PM UTC 24 |
108212306 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.4272735108 |
|
|
Oct 15 02:47:02 PM UTC 24 |
Oct 15 02:47:19 PM UTC 24 |
93863800 ps |
| T1366 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.2321559493 |
|
|
Oct 15 02:47:03 PM UTC 24 |
Oct 15 02:47:19 PM UTC 24 |
92641721 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.847134791 |
|
|
Oct 15 02:43:01 PM UTC 24 |
Oct 15 02:47:24 PM UTC 24 |
2010187311 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.4285018930 |
|
|
Oct 15 02:38:16 PM UTC 24 |
Oct 15 02:47:31 PM UTC 24 |
4965945540 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.4131737279 |
|
|
Oct 15 02:47:09 PM UTC 24 |
Oct 15 02:47:51 PM UTC 24 |
682738668 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.2638842106 |
|
|
Oct 15 02:44:23 PM UTC 24 |
Oct 15 02:47:51 PM UTC 24 |
18087067219 ps |
| T1367 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.1571830488 |
|
|
Oct 15 02:47:17 PM UTC 24 |
Oct 15 02:47:51 PM UTC 24 |
289297394 ps |
| T1368 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.221781192 |
|
|
Oct 15 02:47:44 PM UTC 24 |
Oct 15 02:47:59 PM UTC 24 |
189733041 ps |
| T1369 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.1417734542 |
|
|
Oct 15 02:46:52 PM UTC 24 |
Oct 15 02:48:11 PM UTC 24 |
4720329357 ps |
| T1370 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.3082214641 |
|
|
Oct 15 02:47:29 PM UTC 24 |
Oct 15 02:48:12 PM UTC 24 |
1088475402 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.3711463231 |
|
|
Oct 15 02:47:11 PM UTC 24 |
Oct 15 02:48:16 PM UTC 24 |
1397695596 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.2946857349 |
|
|
Oct 15 02:47:07 PM UTC 24 |
Oct 15 02:48:31 PM UTC 24 |
3591612800 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.2485968885 |
|
|
Oct 15 02:35:48 PM UTC 24 |
Oct 15 02:48:39 PM UTC 24 |
10918588008 ps |
| T1371 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.1144241178 |
|
|
Oct 15 02:38:33 PM UTC 24 |
Oct 15 02:48:39 PM UTC 24 |
19061772721 ps |
| T1372 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.3925046028 |
|
|
Oct 15 02:48:39 PM UTC 24 |
Oct 15 02:48:48 PM UTC 24 |
168847677 ps |
| T1373 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.4109298087 |
|
|
Oct 15 02:48:43 PM UTC 24 |
Oct 15 02:48:54 PM UTC 24 |
45180618 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.3708437834 |
|
|
Oct 15 02:46:40 PM UTC 24 |
Oct 15 02:48:54 PM UTC 24 |
8788759652 ps |
| T1374 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.2986722587 |
|
|
Oct 15 02:49:05 PM UTC 24 |
Oct 15 02:49:18 PM UTC 24 |
217475966 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.1635664869 |
|
|
Oct 15 02:49:14 PM UTC 24 |
Oct 15 02:49:37 PM UTC 24 |
161859645 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.3226680087 |
|
|
Oct 15 02:41:09 PM UTC 24 |
Oct 15 02:49:59 PM UTC 24 |
6534532812 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.1507717828 |
|
|
Oct 15 02:43:14 PM UTC 24 |
Oct 15 02:50:00 PM UTC 24 |
4255279740 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.401370608 |
|
|
Oct 15 02:40:42 PM UTC 24 |
Oct 15 02:50:01 PM UTC 24 |
13336161161 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.1049546085 |
|
|
Oct 15 02:46:12 PM UTC 24 |
Oct 15 02:50:03 PM UTC 24 |
6716813080 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.1635854579 |
|
|
Oct 15 02:43:38 PM UTC 24 |
Oct 15 02:50:17 PM UTC 24 |
4143326932 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.513400156 |
|
|
Oct 15 02:41:31 PM UTC 24 |
Oct 15 02:50:18 PM UTC 24 |
48904492517 ps |
| T1375 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.1771591452 |
|
|
Oct 15 02:44:27 PM UTC 24 |
Oct 15 02:50:28 PM UTC 24 |
21540921606 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.914236984 |
|
|
Oct 15 02:46:15 PM UTC 24 |
Oct 15 02:50:29 PM UTC 24 |
4875458080 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.345691854 |
|
|
Oct 15 02:48:17 PM UTC 24 |
Oct 15 02:50:37 PM UTC 24 |
637713140 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.1447832428 |
|
|
Oct 15 02:47:57 PM UTC 24 |
Oct 15 02:50:40 PM UTC 24 |
4432612714 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.3682469533 |
|
|
Oct 15 02:50:26 PM UTC 24 |
Oct 15 02:50:43 PM UTC 24 |
254358988 ps |
| T1376 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.1527406560 |
|
|
Oct 15 02:48:57 PM UTC 24 |
Oct 15 02:50:48 PM UTC 24 |
7775439798 ps |
| T1377 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.3439348033 |
|
|
Oct 15 02:50:42 PM UTC 24 |
Oct 15 02:50:49 PM UTC 24 |
6408678 ps |
| T1378 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.1886445928 |
|
|
Oct 15 02:49:02 PM UTC 24 |
Oct 15 02:50:52 PM UTC 24 |
5825031348 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.1914039832 |
|
|
Oct 15 02:50:25 PM UTC 24 |
Oct 15 02:50:56 PM UTC 24 |
711847387 ps |
| T1379 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.837572786 |
|
|
Oct 15 02:49:20 PM UTC 24 |
Oct 15 02:51:03 PM UTC 24 |
6366428633 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.3320663689 |
|
|
Oct 15 02:49:45 PM UTC 24 |
Oct 15 02:51:13 PM UTC 24 |
884555438 ps |
| T1380 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.1537360078 |
|
|
Oct 15 02:51:20 PM UTC 24 |
Oct 15 02:51:27 PM UTC 24 |
41800074 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.3067345424 |
|
|
Oct 15 02:51:15 PM UTC 24 |
Oct 15 02:51:30 PM UTC 24 |
230406685 ps |
| T1381 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.2407055037 |
|
|
Oct 15 02:50:25 PM UTC 24 |
Oct 15 02:51:31 PM UTC 24 |
1755724634 ps |
| T1382 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3007864206 |
|
|
Oct 15 02:50:30 PM UTC 24 |
Oct 15 02:51:33 PM UTC 24 |
1113662064 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.1283127390 |
|
|
Oct 15 02:47:05 PM UTC 24 |
Oct 15 02:52:03 PM UTC 24 |
32924257733 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2513297111 |
|
|
Oct 15 02:39:26 PM UTC 24 |
Oct 15 02:52:19 PM UTC 24 |
60408568886 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.2642398390 |
|
|
Oct 15 02:45:46 PM UTC 24 |
Oct 15 02:52:21 PM UTC 24 |
4141514901 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.1288307359 |
|
|
Oct 15 02:51:40 PM UTC 24 |
Oct 15 02:52:29 PM UTC 24 |
359825636 ps |
| T1383 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1983175253 |
|
|
Oct 15 02:36:20 PM UTC 24 |
Oct 15 02:52:30 PM UTC 24 |
20691476187 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.1129101773 |
|
|
Oct 15 02:51:53 PM UTC 24 |
Oct 15 02:52:32 PM UTC 24 |
338972190 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.2357891817 |
|
|
Oct 15 02:42:46 PM UTC 24 |
Oct 15 02:52:33 PM UTC 24 |
15255981221 ps |
| T1384 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.580419738 |
|
|
Oct 15 02:52:31 PM UTC 24 |
Oct 15 02:52:43 PM UTC 24 |
146664274 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.2271284629 |
|
|
Oct 15 02:40:59 PM UTC 24 |
Oct 15 02:52:50 PM UTC 24 |
5746124305 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.2182370743 |
|
|
Oct 15 02:47:47 PM UTC 24 |
Oct 15 02:52:50 PM UTC 24 |
4916154565 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.4044267816 |
|
|
Oct 15 02:46:33 PM UTC 24 |
Oct 15 02:52:51 PM UTC 24 |
3962777090 ps |
| T1385 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.3618811182 |
|
|
Oct 15 02:51:30 PM UTC 24 |
Oct 15 02:52:56 PM UTC 24 |
5043134400 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.2878629858 |
|
|
Oct 15 02:51:19 PM UTC 24 |
Oct 15 02:52:58 PM UTC 24 |
7238731969 ps |
| T1386 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.3114340449 |
|
|
Oct 15 02:52:46 PM UTC 24 |
Oct 15 02:52:59 PM UTC 24 |
42192420 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.757943572 |
|
|
Oct 15 02:50:43 PM UTC 24 |
Oct 15 02:53:02 PM UTC 24 |
278740382 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.2663995794 |
|
|
Oct 15 02:47:45 PM UTC 24 |
Oct 15 02:53:10 PM UTC 24 |
2375032168 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.2080288698 |
|
|
Oct 15 02:49:20 PM UTC 24 |
Oct 15 02:53:13 PM UTC 24 |
22516292048 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.2885696022 |
|
|
Oct 15 02:51:59 PM UTC 24 |
Oct 15 02:53:15 PM UTC 24 |
1350708636 ps |
| T1387 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3036698005 |
|
|
Oct 15 02:53:23 PM UTC 24 |
Oct 15 02:53:33 PM UTC 24 |
48714512 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.3057327210 |
|
|
Oct 15 02:53:20 PM UTC 24 |
Oct 15 02:53:37 PM UTC 24 |
248982232 ps |
| T1388 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.2573291980 |
|
|
Oct 15 02:52:56 PM UTC 24 |
Oct 15 02:53:41 PM UTC 24 |
849895774 ps |
| T1389 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.3251678141 |
|
|
Oct 15 02:52:46 PM UTC 24 |
Oct 15 02:53:47 PM UTC 24 |
1338957189 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.2938946638 |
|
|
Oct 15 02:52:57 PM UTC 24 |
Oct 15 02:53:52 PM UTC 24 |
548409906 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3527250003 |
|
|
Oct 15 02:37:56 PM UTC 24 |
Oct 15 02:53:54 PM UTC 24 |
12454951820 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.3528373549 |
|
|
Oct 15 02:51:57 PM UTC 24 |
Oct 15 02:53:54 PM UTC 24 |
6549996303 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2398973709 |
|
|
Oct 15 02:35:40 PM UTC 24 |
Oct 15 02:54:14 PM UTC 24 |
24862547192 ps |
| T1390 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.2115073424 |
|
|
Oct 15 02:54:19 PM UTC 24 |
Oct 15 02:54:31 PM UTC 24 |
37182865 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3104908762 |
|
|
Oct 15 02:35:38 PM UTC 24 |
Oct 15 02:54:34 PM UTC 24 |
69537843977 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.3094265000 |
|
|
Oct 15 02:53:41 PM UTC 24 |
Oct 15 02:54:37 PM UTC 24 |
551506827 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.3891887478 |
|
|
Oct 15 02:53:39 PM UTC 24 |
Oct 15 02:54:40 PM UTC 24 |
567882076 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.2611725273 |
|
|
Oct 15 02:54:04 PM UTC 24 |
Oct 15 02:55:04 PM UTC 24 |
492222308 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.3254289188 |
|
|
Oct 15 02:53:28 PM UTC 24 |
Oct 15 02:55:09 PM UTC 24 |
9864266779 ps |
| T1391 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.950802350 |
|
|
Oct 15 02:53:37 PM UTC 24 |
Oct 15 02:55:09 PM UTC 24 |
5539278780 ps |
| T1392 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.2967372571 |
|
|
Oct 15 02:54:18 PM UTC 24 |
Oct 15 02:55:12 PM UTC 24 |
1437422761 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1568782698 |
|
|
Oct 15 02:50:57 PM UTC 24 |
Oct 15 02:55:16 PM UTC 24 |
3008325139 ps |
| T1393 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.4197564459 |
|
|
Oct 15 02:54:19 PM UTC 24 |
Oct 15 02:55:18 PM UTC 24 |
1004694411 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.226557794 |
|
|
Oct 15 02:54:11 PM UTC 24 |
Oct 15 02:55:20 PM UTC 24 |
1671687162 ps |
| T1394 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.96174530 |
|
|
Oct 15 02:35:58 PM UTC 24 |
Oct 15 02:55:25 PM UTC 24 |
13436627037 ps |
| T1395 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.1616455567 |
|
|
Oct 15 02:55:01 PM UTC 24 |
Oct 15 02:55:26 PM UTC 24 |
283952069 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.1674724425 |
|
|
Oct 15 02:46:12 PM UTC 24 |
Oct 15 02:55:26 PM UTC 24 |
12494595142 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.36965200 |
|
|
Oct 15 02:48:37 PM UTC 24 |
Oct 15 02:55:26 PM UTC 24 |
3877344285 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.66550688 |
|
|
Oct 15 02:53:01 PM UTC 24 |
Oct 15 02:55:30 PM UTC 24 |
1547146945 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.4100001412 |
|
|
Oct 15 02:52:31 PM UTC 24 |
Oct 15 02:55:41 PM UTC 24 |
13293452028 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.1744484876 |
|
|
Oct 15 02:48:18 PM UTC 24 |
Oct 15 02:55:43 PM UTC 24 |
4272667850 ps |
| T1396 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.3507652072 |
|
|
Oct 15 02:55:38 PM UTC 24 |
Oct 15 02:55:48 PM UTC 24 |
52516299 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.507208135 |
|
|
Oct 15 02:55:04 PM UTC 24 |
Oct 15 02:55:51 PM UTC 24 |
268574612 ps |
| T1397 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.146413362 |
|
|
Oct 15 02:55:44 PM UTC 24 |
Oct 15 02:55:54 PM UTC 24 |
48868642 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.1937076362 |
|
|
Oct 15 02:51:12 PM UTC 24 |
Oct 15 02:55:54 PM UTC 24 |
3407250338 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.2403134458 |
|
|
Oct 15 02:50:53 PM UTC 24 |
Oct 15 02:56:15 PM UTC 24 |
8131670078 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.1402410063 |
|
|
Oct 15 02:55:50 PM UTC 24 |
Oct 15 02:56:34 PM UTC 24 |
360497448 ps |
| T1398 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.2024203278 |
|
|
Oct 15 02:56:14 PM UTC 24 |
Oct 15 02:56:36 PM UTC 24 |
368013714 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.511212417 |
|
|
Oct 15 02:54:55 PM UTC 24 |
Oct 15 02:56:38 PM UTC 24 |
1086415886 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.3518693770 |
|
|
Oct 15 02:48:19 PM UTC 24 |
Oct 15 02:56:42 PM UTC 24 |
5533937477 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.2068601349 |
|
|
Oct 15 02:56:17 PM UTC 24 |
Oct 15 02:56:47 PM UTC 24 |
476703472 ps |
| T1399 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.3147125662 |
|
|
Oct 15 02:56:20 PM UTC 24 |
Oct 15 02:56:49 PM UTC 24 |
182224513 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.3128699833 |
|
|
Oct 15 02:55:50 PM UTC 24 |
Oct 15 02:56:53 PM UTC 24 |
550527927 ps |
| T1400 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.1311867947 |
|
|
Oct 15 02:55:40 PM UTC 24 |
Oct 15 02:56:55 PM UTC 24 |
7601357924 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.1328526189 |
|
|
Oct 15 02:54:42 PM UTC 24 |
Oct 15 02:57:00 PM UTC 24 |
3255177273 ps |
| T1401 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.1352820179 |
|
|
Oct 15 02:56:10 PM UTC 24 |
Oct 15 02:57:02 PM UTC 24 |
1191436601 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.4046567460 |
|
|
Oct 15 02:43:25 PM UTC 24 |
Oct 15 02:57:10 PM UTC 24 |
9471434456 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.4122771346 |
|
|
Oct 15 02:44:57 PM UTC 24 |
Oct 15 02:57:20 PM UTC 24 |
53785990484 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.678612027 |
|
|
Oct 15 02:55:57 PM UTC 24 |
Oct 15 02:57:22 PM UTC 24 |
1539563283 ps |
| T1402 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.3188952761 |
|
|
Oct 15 02:57:16 PM UTC 24 |
Oct 15 02:57:25 PM UTC 24 |
37221495 ps |
| T1403 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2973766029 |
|
|
Oct 15 02:57:20 PM UTC 24 |
Oct 15 02:57:29 PM UTC 24 |
55322175 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.2177510879 |
|
|
Oct 15 02:53:07 PM UTC 24 |
Oct 15 02:57:45 PM UTC 24 |
431976044 ps |
| T1404 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.1669315670 |
|
|
Oct 15 02:55:43 PM UTC 24 |
Oct 15 02:57:46 PM UTC 24 |
6255210246 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.2603029005 |
|
|
Oct 15 02:56:47 PM UTC 24 |
Oct 15 02:57:54 PM UTC 24 |
1976667031 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.4240891337 |
|
|
Oct 15 02:57:28 PM UTC 24 |
Oct 15 02:58:11 PM UTC 24 |
774511342 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.3317126324 |
|
|
Oct 15 02:57:00 PM UTC 24 |
Oct 15 02:58:14 PM UTC 24 |
175192636 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.2497309563 |
|
|
Oct 15 02:55:53 PM UTC 24 |
Oct 15 02:58:21 PM UTC 24 |
10357715404 ps |
| T1405 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.1138510700 |
|
|
Oct 15 02:57:23 PM UTC 24 |
Oct 15 02:58:26 PM UTC 24 |
4475276551 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.4017564249 |
|
|
Oct 15 02:57:50 PM UTC 24 |
Oct 15 02:58:27 PM UTC 24 |
401782111 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.3301728044 |
|
|
Oct 15 02:50:05 PM UTC 24 |
Oct 15 02:58:30 PM UTC 24 |
30757327462 ps |
| T1406 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.1536244087 |
|
|
Oct 15 02:58:11 PM UTC 24 |
Oct 15 02:58:35 PM UTC 24 |
252883541 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.4018498604 |
|
|
Oct 15 02:53:20 PM UTC 24 |
Oct 15 02:58:42 PM UTC 24 |
3649922296 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.3004907555 |
|
|
Oct 15 02:57:37 PM UTC 24 |
Oct 15 02:58:51 PM UTC 24 |
592724770 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.1613697302 |
|
|
Oct 15 02:58:21 PM UTC 24 |
Oct 15 02:59:03 PM UTC 24 |
745127398 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.3929903910 |
|
|
Oct 15 02:46:17 PM UTC 24 |
Oct 15 02:59:04 PM UTC 24 |
6360720823 ps |
| T1407 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.2930019038 |
|
|
Oct 15 02:51:57 PM UTC 24 |
Oct 15 02:59:07 PM UTC 24 |
35148045840 ps |
| T1408 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.2644045949 |
|
|
Oct 15 02:54:00 PM UTC 24 |
Oct 15 02:59:07 PM UTC 24 |
20235878205 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.4256123751 |
|
|
Oct 15 02:55:35 PM UTC 24 |
Oct 15 02:59:13 PM UTC 24 |
3176263055 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3562138454 |
|
|
Oct 15 02:58:31 PM UTC 24 |
Oct 15 02:59:14 PM UTC 24 |
915252477 ps |
| T1409 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.4265274145 |
|
|
Oct 15 02:59:18 PM UTC 24 |
Oct 15 02:59:27 PM UTC 24 |
40871846 ps |
| T1410 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.4007004014 |
|
|
Oct 15 02:57:26 PM UTC 24 |
Oct 15 02:59:30 PM UTC 24 |
6264126951 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2125832180 |
|
|
Oct 15 02:58:39 PM UTC 24 |
Oct 15 02:59:30 PM UTC 24 |
198916390 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.1648433276 |
|
|
Oct 15 02:35:31 PM UTC 24 |
Oct 15 02:59:36 PM UTC 24 |
14392453800 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.384859027 |
|
|
Oct 15 02:56:22 PM UTC 24 |
Oct 15 02:59:37 PM UTC 24 |
2338260096 ps |
| T1411 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.763086505 |
|
|
Oct 15 02:59:30 PM UTC 24 |
Oct 15 02:59:40 PM UTC 24 |
43511337 ps |
| T1412 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.3457536851 |
|
|
Oct 15 02:58:14 PM UTC 24 |
Oct 15 03:00:00 PM UTC 24 |
2645806317 ps |
| T1413 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.725858902 |
|
|
Oct 15 02:59:38 PM UTC 24 |
Oct 15 03:00:00 PM UTC 24 |
218125306 ps |
| T1414 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3893243787 |
|
|
Oct 15 02:59:34 PM UTC 24 |
Oct 15 03:00:12 PM UTC 24 |
2623931853 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.969172512 |
|
|
Oct 15 02:59:31 PM UTC 24 |
Oct 15 03:00:15 PM UTC 24 |
339844987 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3207984540 |
|
|
Oct 15 02:42:13 PM UTC 24 |
Oct 15 03:00:19 PM UTC 24 |
67039245263 ps |
| T1415 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.2083884726 |
|
|
Oct 15 03:00:03 PM UTC 24 |
Oct 15 03:00:20 PM UTC 24 |
105481426 ps |
| T1416 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.1005605891 |
|
|
Oct 15 03:00:05 PM UTC 24 |
Oct 15 03:00:25 PM UTC 24 |
294027376 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.3718732176 |
|
|
Oct 15 02:59:58 PM UTC 24 |
Oct 15 03:00:50 PM UTC 24 |
1100509596 ps |
| T1417 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2485518472 |
|
|
Oct 15 03:00:19 PM UTC 24 |
Oct 15 03:00:55 PM UTC 24 |
814817054 ps |
| T1418 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.1739568913 |
|
|
Oct 15 03:00:03 PM UTC 24 |
Oct 15 03:00:55 PM UTC 24 |
1132194103 ps |
| T1419 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.2270221344 |
|
|
Oct 15 02:59:31 PM UTC 24 |
Oct 15 03:00:58 PM UTC 24 |
7014792971 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3437116877 |
|
|
Oct 15 02:58:49 PM UTC 24 |
Oct 15 03:01:01 PM UTC 24 |
450865153 ps |
| T1420 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1999558532 |
|
|
Oct 15 03:00:42 PM UTC 24 |
Oct 15 03:01:02 PM UTC 24 |
66565803 ps |
| T1421 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.2552806905 |
|
|
Oct 15 03:01:21 PM UTC 24 |
Oct 15 03:01:32 PM UTC 24 |
48357350 ps |
| T1422 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.490301704 |
|
|
Oct 15 03:01:25 PM UTC 24 |
Oct 15 03:01:35 PM UTC 24 |
42832127 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1557678197 |
|
|
Oct 15 02:47:12 PM UTC 24 |
Oct 15 03:01:36 PM UTC 24 |
56248416324 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.3499242187 |
|
|
Oct 15 02:53:58 PM UTC 24 |
Oct 15 03:01:39 PM UTC 24 |
41315462114 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.1473014365 |
|
|
Oct 15 02:58:36 PM UTC 24 |
Oct 15 03:01:52 PM UTC 24 |
2237342671 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.3282095709 |
|
|
Oct 15 02:57:49 PM UTC 24 |
Oct 15 03:02:00 PM UTC 24 |
13218632765 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.4177952935 |
|
|
Oct 15 02:51:01 PM UTC 24 |
Oct 15 03:02:18 PM UTC 24 |
6451639128 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.742608945 |
|
|
Oct 15 03:02:02 PM UTC 24 |
Oct 15 03:02:41 PM UTC 24 |
436274545 ps |
| T1423 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1208164924 |
|
|
Oct 15 03:01:29 PM UTC 24 |
Oct 15 03:02:49 PM UTC 24 |
5093806491 ps |
| T1424 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.1758576076 |
|
|
Oct 15 03:01:59 PM UTC 24 |
Oct 15 03:03:17 PM UTC 24 |
1474342307 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.2439822474 |
|
|
Oct 15 02:58:46 PM UTC 24 |
Oct 15 03:03:17 PM UTC 24 |
7059373675 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.3496066123 |
|
|
Oct 15 02:46:27 PM UTC 24 |
Oct 15 03:03:18 PM UTC 24 |
10534005558 ps |
| T1425 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.1738088735 |
|
|
Oct 15 03:03:07 PM UTC 24 |
Oct 15 03:03:20 PM UTC 24 |
175384453 ps |
| T1426 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.2429665201 |
|
|
Oct 15 03:03:16 PM UTC 24 |
Oct 15 03:03:23 PM UTC 24 |
70705074 ps |
| T1427 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.2595063547 |
|
|
Oct 15 03:01:28 PM UTC 24 |
Oct 15 03:03:23 PM UTC 24 |
9157219269 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.53743191 |
|
|
Oct 15 02:59:40 PM UTC 24 |
Oct 15 03:03:35 PM UTC 24 |
25520751681 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.4117604441 |
|
|
Oct 15 02:53:17 PM UTC 24 |
Oct 15 03:03:37 PM UTC 24 |
5609122618 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.2617276912 |
|
|
Oct 15 03:02:44 PM UTC 24 |
Oct 15 03:03:44 PM UTC 24 |
575944225 ps |