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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.96 95.39 93.47 95.36 94.22 97.71 99.60


Total test records in report: 2930
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T1339 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.2370675494 Feb 09 11:08:57 PM UTC 25 Feb 10 01:06:47 AM UTC 25 25912882310 ps
T239 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1497441677 Feb 09 07:54:43 PM UTC 25 Feb 10 01:07:02 AM UTC 25 82457584796 ps
T1340 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.2377926023 Feb 09 11:50:59 PM UTC 25 Feb 10 01:13:20 AM UTC 25 18598138380 ps
T1341 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3705747715 Feb 09 11:08:11 PM UTC 25 Feb 10 01:20:36 AM UTC 25 30437520406 ps
T1342 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3095908390 Feb 09 11:08:18 PM UTC 25 Feb 10 01:24:38 AM UTC 25 29923823020 ps
T1343 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3251646318 Feb 09 11:08:08 PM UTC 25 Feb 10 01:27:27 AM UTC 25 30503055976 ps
T399 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.2982141864 Feb 09 09:33:53 PM UTC 25 Feb 10 01:46:47 AM UTC 25 68304937761 ps
T644 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.1647617842 Feb 09 11:44:26 PM UTC 25 Feb 10 01:51:36 AM UTC 25 35308134744 ps
T1344 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.624303052 Feb 09 11:23:09 PM UTC 25 Feb 10 01:52:15 AM UTC 25 37646365880 ps
T1345 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2362135909 Feb 09 09:33:11 PM UTC 25 Feb 10 02:09:57 AM UTC 25 82324396136 ps
T645 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.139949142 Feb 09 09:09:20 PM UTC 25 Feb 10 03:12:24 AM UTC 25 147708876117 ps
T98 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.72501605 Feb 09 02:43:02 PM UTC 25 Feb 09 02:43:12 PM UTC 25 60016063 ps
T99 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.1185155697 Feb 09 02:43:04 PM UTC 25 Feb 09 02:43:18 PM UTC 25 176419517 ps
T100 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.315715204 Feb 09 02:43:04 PM UTC 25 Feb 09 02:43:56 PM UTC 25 1405867205 ps
T161 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3271984390 Feb 09 02:43:02 PM UTC 25 Feb 09 02:44:05 PM UTC 25 4213829885 ps
T185 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.4191889118 Feb 09 02:43:35 PM UTC 25 Feb 09 02:44:13 PM UTC 25 431182142 ps
T457 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.4265523193 Feb 09 02:43:45 PM UTC 25 Feb 09 02:44:14 PM UTC 25 229031494 ps
T236 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.3437672592 Feb 09 02:42:59 PM UTC 25 Feb 09 02:44:33 PM UTC 25 10419528666 ps
T281 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3397390534 Feb 09 02:44:24 PM UTC 25 Feb 09 02:44:47 PM UTC 25 179232625 ps
T462 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.3693760145 Feb 09 02:44:07 PM UTC 25 Feb 09 02:44:51 PM UTC 25 1388833360 ps
T282 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3667735851 Feb 09 02:44:59 PM UTC 25 Feb 09 02:45:22 PM UTC 25 34083478 ps
T458 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.2584503216 Feb 09 02:44:10 PM UTC 25 Feb 09 02:45:25 PM UTC 25 1239667789 ps
T478 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.122768674 Feb 09 02:45:58 PM UTC 25 Feb 09 02:46:12 PM UTC 25 201323163 ps
T477 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.2861159140 Feb 09 02:44:10 PM UTC 25 Feb 09 02:46:22 PM UTC 25 2371565376 ps
T566 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1590314337 Feb 09 02:46:23 PM UTC 25 Feb 09 02:46:33 PM UTC 25 39901208 ps
T428 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.2890868409 Feb 09 02:43:04 PM UTC 25 Feb 09 02:46:36 PM UTC 25 3235723516 ps
T461 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.1969690082 Feb 09 02:46:47 PM UTC 25 Feb 09 02:47:29 PM UTC 25 326729064 ps
T448 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.3599334186 Feb 09 02:44:32 PM UTC 25 Feb 09 02:47:47 PM UTC 25 4621777247 ps
T565 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.751380377 Feb 09 02:46:38 PM UTC 25 Feb 09 02:47:54 PM UTC 25 4528780159 ps
T564 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.2247503227 Feb 09 02:48:06 PM UTC 25 Feb 09 02:48:20 PM UTC 25 92254135 ps
T567 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.2268115635 Feb 09 02:48:06 PM UTC 25 Feb 09 02:48:27 PM UTC 25 384111453 ps
T559 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.2895202270 Feb 09 02:43:42 PM UTC 25 Feb 09 02:48:27 PM UTC 25 18109588396 ps
T841 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.2011887828 Feb 09 02:47:33 PM UTC 25 Feb 09 02:48:29 PM UTC 25 1013134144 ps
T563 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2006613546 Feb 09 02:46:41 PM UTC 25 Feb 09 02:48:34 PM UTC 25 4990459588 ps
T524 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.3050077185 Feb 09 02:46:43 PM UTC 25 Feb 09 02:48:38 PM UTC 25 2194174217 ps
T560 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.700003358 Feb 09 02:48:14 PM UTC 25 Feb 09 02:48:58 PM UTC 25 283553545 ps
T557 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.2259963363 Feb 09 02:47:54 PM UTC 25 Feb 09 02:49:00 PM UTC 25 1828160694 ps
T900 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.3185066254 Feb 09 02:43:04 PM UTC 25 Feb 09 02:49:03 PM UTC 25 9330022915 ps
T561 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.1734325228 Feb 09 02:49:02 PM UTC 25 Feb 09 02:49:13 PM UTC 25 184141073 ps
T610 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.493277648 Feb 09 02:49:04 PM UTC 25 Feb 09 02:49:14 PM UTC 25 43832286 ps
T429 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.2693674430 Feb 09 02:45:46 PM UTC 25 Feb 09 02:49:24 PM UTC 25 3247377085 ps
T558 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.56797372 Feb 09 02:49:17 PM UTC 25 Feb 09 02:49:33 PM UTC 25 97530576 ps
T169 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.4109239630 Feb 09 02:45:02 PM UTC 25 Feb 09 02:49:36 PM UTC 25 4592727022 ps
T581 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.932738452 Feb 09 02:49:24 PM UTC 25 Feb 09 02:49:43 PM UTC 25 127193393 ps
T844 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.2758840985 Feb 09 02:49:10 PM UTC 25 Feb 09 02:50:22 PM UTC 25 4555154193 ps
T562 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.3965819642 Feb 09 02:44:42 PM UTC 25 Feb 09 02:50:26 PM UTC 25 10126492443 ps
T672 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.1624920169 Feb 09 02:50:02 PM UTC 25 Feb 09 02:50:30 PM UTC 25 570846754 ps
T460 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.2971309689 Feb 09 02:50:10 PM UTC 25 Feb 09 02:50:44 PM UTC 25 247303360 ps
T538 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.3005924282 Feb 09 02:49:40 PM UTC 25 Feb 09 02:50:48 PM UTC 25 2112058605 ps
T679 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.4217476497 Feb 09 02:49:48 PM UTC 25 Feb 09 02:50:53 PM UTC 25 1504906441 ps
T421 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.249061715 Feb 09 02:45:08 PM UTC 25 Feb 09 02:50:54 PM UTC 25 4409716008 ps
T496 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.3784372738 Feb 09 02:50:00 PM UTC 25 Feb 09 02:51:00 PM UTC 25 1436457743 ps
T668 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.4270392193 Feb 09 02:49:01 PM UTC 25 Feb 09 02:51:06 PM UTC 25 8906337088 ps
T459 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.2927865876 Feb 09 02:48:21 PM UTC 25 Feb 09 02:51:14 PM UTC 25 1943666882 ps
T1346 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.2839820300 Feb 09 02:49:01 PM UTC 25 Feb 09 02:51:24 PM UTC 25 3235876318 ps
T803 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.1804652164 Feb 09 02:49:29 PM UTC 25 Feb 09 02:51:26 PM UTC 25 1107665504 ps
T580 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.118946500 Feb 09 02:51:22 PM UTC 25 Feb 09 02:51:30 PM UTC 25 42237578 ps
T607 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.3029794266 Feb 09 02:46:58 PM UTC 25 Feb 09 02:51:31 PM UTC 25 21731240903 ps
T631 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.2850279006 Feb 09 02:51:20 PM UTC 25 Feb 09 02:51:31 PM UTC 25 168377991 ps
T673 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.48909895 Feb 09 02:50:29 PM UTC 25 Feb 09 02:51:36 PM UTC 25 313677720 ps
T173 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.1535559690 Feb 09 02:48:40 PM UTC 25 Feb 09 02:52:06 PM UTC 25 4491310417 ps
T522 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.3190375311 Feb 09 02:51:55 PM UTC 25 Feb 09 02:52:26 PM UTC 25 613783143 ps
T652 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.994846463 Feb 09 02:51:55 PM UTC 25 Feb 09 02:52:28 PM UTC 25 257927972 ps
T593 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.3168440356 Feb 09 02:51:31 PM UTC 25 Feb 09 02:52:30 PM UTC 25 1219706856 ps
T627 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.1298320775 Feb 09 02:52:00 PM UTC 25 Feb 09 02:52:31 PM UTC 25 542431851 ps
T814 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.980996449 Feb 09 02:47:02 PM UTC 25 Feb 09 02:52:38 PM UTC 25 20422262453 ps
T595 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.4038590241 Feb 09 02:51:38 PM UTC 25 Feb 09 02:52:50 PM UTC 25 563048116 ps
T1347 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.2987181144 Feb 09 02:45:49 PM UTC 25 Feb 09 02:52:52 PM UTC 25 7689965501 ps
T865 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.2492226360 Feb 09 02:50:09 PM UTC 25 Feb 09 02:52:56 PM UTC 25 107445661 ps
T1348 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.591481574 Feb 09 02:52:33 PM UTC 25 Feb 09 02:52:58 PM UTC 25 138382869 ps
T1349 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.3017731286 Feb 09 02:51:28 PM UTC 25 Feb 09 02:53:01 PM UTC 25 9537004311 ps
T1350 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.1958117937 Feb 09 02:51:29 PM UTC 25 Feb 09 02:53:06 PM UTC 25 4791045575 ps
T653 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.505699537 Feb 09 02:48:27 PM UTC 25 Feb 09 02:53:11 PM UTC 25 7707577038 ps
T485 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1491334410 Feb 09 02:44:38 PM UTC 25 Feb 09 02:53:41 PM UTC 25 3620760442 ps
T594 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2982424325 Feb 09 02:48:31 PM UTC 25 Feb 09 02:53:43 PM UTC 25 7303394306 ps
T622 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.2867544115 Feb 09 02:53:29 PM UTC 25 Feb 09 02:53:44 PM UTC 25 230372692 ps
T571 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.2748844233 Feb 09 02:48:56 PM UTC 25 Feb 09 02:53:58 PM UTC 25 3943713741 ps
T798 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.1469696617 Feb 09 02:51:52 PM UTC 25 Feb 09 02:54:01 PM UTC 25 2440544531 ps
T1351 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.1953916232 Feb 09 02:54:07 PM UTC 25 Feb 09 02:54:16 PM UTC 25 42912070 ps
T605 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.2139786625 Feb 09 02:54:23 PM UTC 25 Feb 09 02:55:00 PM UTC 25 335442797 ps
T1352 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.1400231383 Feb 09 02:54:51 PM UTC 25 Feb 09 02:55:00 PM UTC 25 15042896 ps
T596 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.1998428309 Feb 09 02:50:14 PM UTC 25 Feb 09 02:55:00 PM UTC 25 3557321231 ps
T1353 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3057463180 Feb 09 02:43:00 PM UTC 25 Feb 09 02:55:10 PM UTC 25 16841567888 ps
T511 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1037777528 Feb 09 02:48:26 PM UTC 25 Feb 09 02:55:12 PM UTC 25 958277654 ps
T824 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.3507043692 Feb 09 02:54:09 PM UTC 25 Feb 09 02:55:27 PM UTC 25 5669666209 ps
T574 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.3136454803 Feb 09 02:54:26 PM UTC 25 Feb 09 02:55:28 PM UTC 25 520205047 ps
T1354 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.809465579 Feb 09 02:45:51 PM UTC 25 Feb 09 02:55:42 PM UTC 25 20171249209 ps
T1355 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.200945324 Feb 09 02:54:08 PM UTC 25 Feb 09 02:55:46 PM UTC 25 6551511341 ps
T179 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3463797672 Feb 09 02:45:12 PM UTC 25 Feb 09 02:55:52 PM UTC 25 8299584862 ps
T674 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.3010985008 Feb 09 02:55:28 PM UTC 25 Feb 09 02:55:58 PM UTC 25 348248625 ps
T864 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.2738278884 Feb 09 02:52:54 PM UTC 25 Feb 09 02:56:08 PM UTC 25 327617236 ps
T495 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.2286231935 Feb 09 02:55:25 PM UTC 25 Feb 09 02:56:11 PM UTC 25 807672621 ps
T1356 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.533847097 Feb 09 02:55:36 PM UTC 25 Feb 09 02:56:12 PM UTC 25 567010319 ps
T598 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.154883867 Feb 09 02:55:28 PM UTC 25 Feb 09 02:56:27 PM UTC 25 581141683 ps
T615 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.674684902 Feb 09 02:56:36 PM UTC 25 Feb 09 02:56:43 PM UTC 25 40352065 ps
T422 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.483652756 Feb 09 02:48:40 PM UTC 25 Feb 09 02:56:45 PM UTC 25 5568501882 ps
T632 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.3700339352 Feb 09 02:56:37 PM UTC 25 Feb 09 02:56:48 PM UTC 25 54648692 ps
T568 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.3950338092 Feb 09 02:51:12 PM UTC 25 Feb 09 02:57:07 PM UTC 25 3945041296 ps
T842 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.1352436857 Feb 09 02:55:54 PM UTC 25 Feb 09 02:57:10 PM UTC 25 2012727368 ps
T1357 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.1344543341 Feb 09 02:57:10 PM UTC 25 Feb 09 02:57:25 PM UTC 25 81677349 ps
T174 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.1387422187 Feb 09 02:53:04 PM UTC 25 Feb 09 02:57:27 PM UTC 25 4308777097 ps
T606 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.978271316 Feb 09 02:54:52 PM UTC 25 Feb 09 02:57:46 PM UTC 25 8424780519 ps
T583 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.1464367535 Feb 09 02:57:06 PM UTC 25 Feb 09 02:57:51 PM UTC 25 460796653 ps
T556 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.2506435368 Feb 09 02:43:00 PM UTC 25 Feb 09 02:58:09 PM UTC 25 7141124224 ps
T493 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.594131484 Feb 09 02:57:53 PM UTC 25 Feb 09 02:58:11 PM UTC 25 129063732 ps
T443 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.3276733006 Feb 09 02:50:50 PM UTC 25 Feb 09 02:58:26 PM UTC 25 6281189772 ps
T497 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.2229379031 Feb 09 02:52:52 PM UTC 25 Feb 09 02:58:27 PM UTC 25 3703421490 ps
T641 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2851934341 Feb 09 02:55:53 PM UTC 25 Feb 09 02:58:29 PM UTC 25 346911086 ps
T588 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.2726672880 Feb 09 02:57:03 PM UTC 25 Feb 09 02:58:37 PM UTC 25 3841194186 ps
T1358 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.1440096664 Feb 09 02:56:54 PM UTC 25 Feb 09 02:58:37 PM UTC 25 6303140837 ps
T629 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.2098352345 Feb 09 02:58:16 PM UTC 25 Feb 09 02:58:40 PM UTC 25 160334958 ps
T655 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.1978635075 Feb 09 02:52:57 PM UTC 25 Feb 09 02:58:42 PM UTC 25 8203629281 ps
T176 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.1317867924 Feb 09 02:50:35 PM UTC 25 Feb 09 02:58:58 PM UTC 25 8056095643 ps
T1359 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.510164914 Feb 09 02:58:34 PM UTC 25 Feb 09 02:59:02 PM UTC 25 524936785 ps
T628 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.652967254 Feb 09 02:59:01 PM UTC 25 Feb 09 02:59:11 PM UTC 25 211741386 ps
T620 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.3445412121 Feb 09 02:59:09 PM UTC 25 Feb 09 02:59:19 PM UTC 25 46204440 ps
T498 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.655979267 Feb 09 02:57:37 PM UTC 25 Feb 09 02:59:28 PM UTC 25 1352504035 ps
T640 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.1288482696 Feb 09 02:59:27 PM UTC 25 Feb 09 02:59:38 PM UTC 25 97948949 ps
T837 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.2135940349 Feb 09 02:58:12 PM UTC 25 Feb 09 02:59:43 PM UTC 25 2438195027 ps
T1360 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.1263530972 Feb 09 02:49:02 PM UTC 25 Feb 09 02:59:46 PM UTC 25 16483451581 ps
T817 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.2108949872 Feb 09 02:52:56 PM UTC 25 Feb 09 02:59:59 PM UTC 25 5127357879 ps
T609 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.1488607701 Feb 09 02:49:28 PM UTC 25 Feb 09 03:00:13 PM UTC 25 36859315251 ps
T541 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.523704663 Feb 09 02:55:33 PM UTC 25 Feb 09 03:00:22 PM UTC 25 3203512445 ps
T843 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2104656769 Feb 09 02:51:54 PM UTC 25 Feb 09 03:00:26 PM UTC 25 34554779019 ps
T657 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.3501279463 Feb 09 02:58:56 PM UTC 25 Feb 09 03:00:30 PM UTC 25 1258165768 ps
T1361 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.371226891 Feb 09 02:48:45 PM UTC 25 Feb 09 03:00:39 PM UTC 25 6147347525 ps
T514 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.855533770 Feb 09 02:58:37 PM UTC 25 Feb 09 03:00:40 PM UTC 25 1606898399 ps
T582 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.2932425759 Feb 09 02:59:36 PM UTC 25 Feb 09 03:00:42 PM UTC 25 608400394 ps
T1362 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.4228313565 Feb 09 03:00:25 PM UTC 25 Feb 09 03:00:45 PM UTC 25 163031180 ps
T444 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.1242528051 Feb 09 02:50:37 PM UTC 25 Feb 09 03:00:50 PM UTC 25 5645135036 ps
T635 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.3363600890 Feb 09 02:59:06 PM UTC 25 Feb 09 03:00:54 PM UTC 25 8514641767 ps
T585 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.1288372140 Feb 09 03:00:12 PM UTC 25 Feb 09 03:01:00 PM UTC 25 1287652176 ps
T572 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.1991904353 Feb 09 02:53:30 PM UTC 25 Feb 09 03:01:06 PM UTC 25 4101928504 ps
T578 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.567390354 Feb 09 02:56:35 PM UTC 25 Feb 09 03:01:11 PM UTC 25 3848882256 ps
T1363 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3192453669 Feb 09 03:00:49 PM UTC 25 Feb 09 03:01:17 PM UTC 25 510857561 ps
T1364 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.1958361788 Feb 09 02:59:25 PM UTC 25 Feb 09 03:01:17 PM UTC 25 5955119607 ps
T175 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.4263191960 Feb 09 02:56:11 PM UTC 25 Feb 09 03:01:22 PM UTC 25 5921143031 ps
T530 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.2242839407 Feb 09 03:00:04 PM UTC 25 Feb 09 03:01:23 PM UTC 25 1716700191 ps
T639 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.4122267880 Feb 09 03:00:38 PM UTC 25 Feb 09 03:01:36 PM UTC 25 996977429 ps
T614 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.704851723 Feb 09 03:01:26 PM UTC 25 Feb 09 03:01:37 PM UTC 25 55504841 ps
T616 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.4269926691 Feb 09 03:01:31 PM UTC 25 Feb 09 03:01:41 PM UTC 25 51978756 ps
T613 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.2597059860 Feb 09 03:01:40 PM UTC 25 Feb 09 03:01:54 PM UTC 25 73542151 ps
T833 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.2777891904 Feb 09 02:56:07 PM UTC 25 Feb 09 03:01:56 PM UTC 25 2115534145 ps
T591 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.3663467909 Feb 09 03:01:50 PM UTC 25 Feb 09 03:02:23 PM UTC 25 290060453 ps
T1365 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.223850916 Feb 09 02:59:47 PM UTC 25 Feb 09 03:02:56 PM UTC 25 17741707603 ps
T1366 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.2614266416 Feb 09 03:02:51 PM UTC 25 Feb 09 03:02:59 PM UTC 25 19106113 ps
T531 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.509236720 Feb 09 03:02:20 PM UTC 25 Feb 09 03:03:00 PM UTC 25 359846761 ps
T1367 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.201792634 Feb 09 03:02:48 PM UTC 25 Feb 09 03:03:02 PM UTC 25 59753562 ps
T432 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.293759696 Feb 09 02:48:42 PM UTC 25 Feb 09 03:03:06 PM UTC 25 13179123002 ps
T1368 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.2445059004 Feb 09 03:01:38 PM UTC 25 Feb 09 03:03:07 PM UTC 25 7898842933 ps
T1369 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.4232229131 Feb 09 03:01:40 PM UTC 25 Feb 09 03:03:07 PM UTC 25 3830803814 ps
T577 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.4212811803 Feb 09 02:59:01 PM UTC 25 Feb 09 03:03:16 PM UTC 25 3680832450 ps
T445 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.3457793894 Feb 09 02:56:23 PM UTC 25 Feb 09 03:03:21 PM UTC 25 5476533287 ps
T611 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.3406513955 Feb 09 02:43:39 PM UTC 25 Feb 09 03:03:27 PM UTC 25 109952477802 ps
T836 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.2404121332 Feb 09 03:02:05 PM UTC 25 Feb 09 03:03:28 PM UTC 25 888034666 ps
T1370 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.1244536325 Feb 09 03:02:23 PM UTC 25 Feb 09 03:03:32 PM UTC 25 1735165370 ps
T625 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.3880221397 Feb 09 03:00:54 PM UTC 25 Feb 09 03:03:39 PM UTC 25 1314187075 ps
T586 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.4276017318 Feb 09 02:49:25 PM UTC 25 Feb 09 03:03:40 PM UTC 25 83741094277 ps
T1371 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.1706894502 Feb 09 03:03:49 PM UTC 25 Feb 09 03:03:59 PM UTC 25 54009140 ps
T1372 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.1161839284 Feb 09 03:03:50 PM UTC 25 Feb 09 03:04:00 PM UTC 25 39067493 ps
T587 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.1656815342 Feb 09 02:57:35 PM UTC 25 Feb 09 03:04:09 PM UTC 25 25771251044 ps
T811 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.2993473174 Feb 09 02:58:55 PM UTC 25 Feb 09 03:04:15 PM UTC 25 6110128491 ps
T621 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.2010581057 Feb 09 02:58:54 PM UTC 25 Feb 09 03:04:17 PM UTC 25 1802578489 ps
T812 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1023998965 Feb 09 02:57:52 PM UTC 25 Feb 09 03:04:18 PM UTC 25 22580351535 ps
T512 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.1983051430 Feb 09 02:51:50 PM UTC 25 Feb 09 03:04:34 PM UTC 25 50429324310 ps
T446 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.3360015639 Feb 09 02:56:18 PM UTC 25 Feb 09 03:04:39 PM UTC 25 5676620232 ps
T1373 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.3572814479 Feb 09 03:03:50 PM UTC 25 Feb 09 03:04:48 PM UTC 25 5002624277 ps
T896 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.2906965468 Feb 09 03:03:26 PM UTC 25 Feb 09 03:04:52 PM UTC 25 44422708 ps
T534 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.3413146536 Feb 09 03:04:03 PM UTC 25 Feb 09 03:04:52 PM UTC 25 526946176 ps
T513 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.1611170490 Feb 09 03:04:06 PM UTC 25 Feb 09 03:04:54 PM UTC 25 595269128 ps
T1374 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.1919229240 Feb 09 03:03:27 PM UTC 25 Feb 09 03:05:06 PM UTC 25 1034661675 ps
T1375 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.3701110941 Feb 09 03:05:06 PM UTC 25 Feb 09 03:05:30 PM UTC 25 411384062 ps
T891 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3561576357 Feb 09 03:03:28 PM UTC 25 Feb 09 03:05:30 PM UTC 25 406219076 ps
T1376 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.2422067563 Feb 09 03:04:41 PM UTC 25 Feb 09 03:05:31 PM UTC 25 1200500163 ps
T830 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.1380552895 Feb 09 03:04:34 PM UTC 25 Feb 09 03:05:38 PM UTC 25 1162069445 ps
T447 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.2836544456 Feb 09 02:58:52 PM UTC 25 Feb 09 03:05:40 PM UTC 25 3765299595 ps
T1377 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.2470133379 Feb 09 03:03:55 PM UTC 25 Feb 09 03:05:42 PM UTC 25 5195753724 ps
T499 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.2046205991 Feb 09 03:04:59 PM UTC 25 Feb 09 03:05:42 PM UTC 25 1007333468 ps
T570 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.1517352368 Feb 09 03:01:18 PM UTC 25 Feb 09 03:05:54 PM UTC 25 4028039480 ps
T1378 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.1054061982 Feb 09 03:04:45 PM UTC 25 Feb 09 03:05:55 PM UTC 25 1723523053 ps
T532 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.1675149820 Feb 09 02:54:37 PM UTC 25 Feb 09 03:06:08 PM UTC 25 73477804121 ps
T1379 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.3427223530 Feb 09 03:06:07 PM UTC 25 Feb 09 03:06:15 PM UTC 25 42665381 ps
T1380 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.1376906610 Feb 09 03:06:04 PM UTC 25 Feb 09 03:06:16 PM UTC 25 169329507 ps
T1381 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.1456250613 Feb 09 03:06:05 PM UTC 25 Feb 09 03:07:01 PM UTC 25 4038587412 ps
T1382 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.703099526 Feb 09 03:06:20 PM UTC 25 Feb 09 03:07:03 PM UTC 25 743732756 ps
T510 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.478518368 Feb 09 03:06:20 PM UTC 25 Feb 09 03:07:04 PM UTC 25 479947047 ps
T486 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.2759734267 Feb 09 03:00:50 PM UTC 25 Feb 09 03:07:08 PM UTC 25 10382009416 ps
T599 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.2028759589 Feb 09 02:51:39 PM UTC 25 Feb 09 03:07:39 PM UTC 25 91149702567 ps
T1383 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.2131868896 Feb 09 03:07:29 PM UTC 25 Feb 09 03:07:40 PM UTC 25 81409368 ps
T433 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.2949175327 Feb 09 02:53:19 PM UTC 25 Feb 09 03:07:53 PM UTC 25 11025375415 ps
T1384 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.3822947671 Feb 09 03:06:11 PM UTC 25 Feb 09 03:08:04 PM UTC 25 9046910170 ps
T1385 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.3502970977 Feb 09 03:07:25 PM UTC 25 Feb 09 03:08:04 PM UTC 25 1014718213 ps
T669 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.120337780 Feb 09 03:06:43 PM UTC 25 Feb 09 03:08:06 PM UTC 25 901733601 ps
T1386 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.2853946712 Feb 09 03:07:31 PM UTC 25 Feb 09 03:08:27 PM UTC 25 1153487885 ps
T507 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.1170336622 Feb 09 03:05:12 PM UTC 25 Feb 09 03:08:36 PM UTC 25 1900324327 ps
T617 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.2001746938 Feb 09 03:07:25 PM UTC 25 Feb 09 03:08:40 PM UTC 25 2095469339 ps
T575 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.1833327033 Feb 09 03:03:38 PM UTC 25 Feb 09 03:08:47 PM UTC 25 3764425982 ps
T804 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.2681393933 Feb 09 03:01:04 PM UTC 25 Feb 09 03:09:08 PM UTC 25 10721326374 ps
T482 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.1604955823 Feb 09 03:03:32 PM UTC 25 Feb 09 03:09:11 PM UTC 25 4034890045 ps
T1387 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.589689742 Feb 09 03:09:01 PM UTC 25 Feb 09 03:09:11 PM UTC 25 202105169 ps
T1388 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3404780094 Feb 09 03:09:05 PM UTC 25 Feb 09 03:09:15 PM UTC 25 39086548 ps
T888 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.1914218783 Feb 09 03:08:18 PM UTC 25 Feb 09 03:09:25 PM UTC 25 229886827 ps
T480 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.732488012 Feb 09 02:53:18 PM UTC 25 Feb 09 03:09:26 PM UTC 25 6152166940 ps
T573 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.3709144653 Feb 09 03:05:57 PM UTC 25 Feb 09 03:09:35 PM UTC 25 3533905114 ps
T1389 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.2149205504 Feb 09 03:06:43 PM UTC 25 Feb 09 03:09:41 PM UTC 25 9698512388 ps
T1390 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.2381578035 Feb 09 03:03:33 PM UTC 25 Feb 09 03:09:42 PM UTC 25 5747114660 ps
T553 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.2921764907 Feb 09 03:04:23 PM UTC 25 Feb 09 03:09:52 PM UTC 25 25298476417 ps
T1391 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.1750861257 Feb 09 03:10:02 PM UTC 25 Feb 09 03:10:21 PM UTC 25 327934714 ps
T630 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.4193901269 Feb 09 03:09:37 PM UTC 25 Feb 09 03:10:30 PM UTC 25 414736307 ps
T658 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.3257987751 Feb 09 03:05:18 PM UTC 25 Feb 09 03:10:45 PM UTC 25 8509075981 ps
T488 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.3980470543 Feb 09 03:03:23 PM UTC 25 Feb 09 03:10:50 PM UTC 25 13476887557 ps
T1392 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.2551866412 Feb 09 03:10:18 PM UTC 25 Feb 09 03:10:52 PM UTC 25 530312174 ps
T1393 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.2673429295 Feb 09 03:09:14 PM UTC 25 Feb 09 03:10:59 PM UTC 25 6347700757 ps
T624 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.3997081712 Feb 09 03:01:48 PM UTC 25 Feb 09 03:11:21 PM UTC 25 43047854803 ps
T533 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.3381487586 Feb 09 03:09:37 PM UTC 25 Feb 09 03:11:23 PM UTC 25 2312945720 ps
T1394 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.174515751 Feb 09 03:10:48 PM UTC 25 Feb 09 03:11:23 PM UTC 25 224518393 ps
T589 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.2928884583 Feb 09 02:59:53 PM UTC 25 Feb 09 03:11:33 PM UTC 25 38932002185 ps
T545 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.1151585859 Feb 09 03:07:35 PM UTC 25 Feb 09 03:11:43 PM UTC 25 6783603239 ps
T862 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.3906234240 Feb 09 03:05:19 PM UTC 25 Feb 09 03:11:43 PM UTC 25 2423932886 ps
T1395 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.1831723535 Feb 09 03:10:07 PM UTC 25 Feb 09 03:11:44 PM UTC 25 2290684993 ps
T579 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.843168485 Feb 09 03:08:53 PM UTC 25 Feb 09 03:11:46 PM UTC 25 3789204068 ps
T818 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.3662127222 Feb 09 03:09:50 PM UTC 25 Feb 09 03:11:51 PM UTC 25 1718449963 ps
T483 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.2000137430 Feb 09 03:05:33 PM UTC 25 Feb 09 03:11:54 PM UTC 25 4372750132 ps
T1396 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.3159982101 Feb 09 03:11:49 PM UTC 25 Feb 09 03:12:01 PM UTC 25 230988934 ps
T1397 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2737548314 Feb 09 03:09:35 PM UTC 25 Feb 09 03:12:03 PM UTC 25 6147293675 ps
T1398 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1191742288 Feb 09 03:12:00 PM UTC 25 Feb 09 03:12:08 PM UTC 25 50939068 ps
T838 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2231502926 Feb 09 03:11:18 PM UTC 25 Feb 09 03:12:09 PM UTC 25 112169273 ps
T1399 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.232123664 Feb 09 03:12:06 PM UTC 25 Feb 09 03:12:23 PM UTC 25 129567926 ps
T549 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.1640740221 Feb 09 03:12:10 PM UTC 25 Feb 09 03:12:45 PM UTC 25 380982419 ps
T834 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.2249366421 Feb 09 03:12:24 PM UTC 25 Feb 09 03:12:56 PM UTC 25 440557009 ps
T525 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.3587654809 Feb 09 03:12:34 PM UTC 25 Feb 09 03:13:08 PM UTC 25 270765232 ps
T481 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.1823838749 Feb 09 02:58:54 PM UTC 25 Feb 09 03:13:14 PM UTC 25 12276793162 ps
T1400 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.1052107445 Feb 09 03:12:34 PM UTC 25 Feb 09 03:13:15 PM UTC 25 339706134 ps
T491 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.1570538388 Feb 09 03:08:06 PM UTC 25 Feb 09 03:13:17 PM UTC 25 1259657465 ps
T540 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.137337698 Feb 09 03:05:18 PM UTC 25 Feb 09 03:13:26 PM UTC 25 669120796 ps
T1401 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.441401434 Feb 09 03:01:08 PM UTC 25 Feb 09 03:13:30 PM UTC 25 5646101168 ps
T1402 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.320080294 Feb 09 03:13:12 PM UTC 25 Feb 09 03:13:39 PM UTC 25 144171996 ps
T515 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.4165136347 Feb 09 03:12:50 PM UTC 25 Feb 09 03:13:44 PM UTC 25 866974013 ps
T884 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1827642165 Feb 09 03:11:11 PM UTC 25 Feb 09 03:13:46 PM UTC 25 416547775 ps
T1403 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2970946793 Feb 09 03:12:06 PM UTC 25 Feb 09 03:14:17 PM UTC 25 5666369853 ps
T1404 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.4272593367 Feb 09 03:14:08 PM UTC 25 Feb 09 03:14:23 PM UTC 25 196116994 ps
T1405 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3209022243 Feb 09 03:14:12 PM UTC 25 Feb 09 03:14:23 PM UTC 25 50886869 ps
T882 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2730666022 Feb 09 03:13:41 PM UTC 25 Feb 09 03:14:48 PM UTC 25 95650708 ps
T1406 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.2958933008 Feb 09 03:12:10 PM UTC 25 Feb 09 03:14:51 PM UTC 25 9590730389 ps
T618 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.720212336 Feb 09 03:02:03 PM UTC 25 Feb 09 03:14:54 PM UTC 25 36328484963 ps
T494 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.1318687985 Feb 09 02:57:12 PM UTC 25 Feb 09 03:15:06 PM UTC 25 94969269244 ps
T826 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3752234168 Feb 09 03:01:06 PM UTC 25 Feb 09 03:15:23 PM UTC 25 7642917228 ps
T827 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.3735350070 Feb 09 03:13:23 PM UTC 25 Feb 09 03:15:26 PM UTC 25 1236693045 ps
T1407 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.3892746257 Feb 09 03:12:21 PM UTC 25 Feb 09 03:15:29 PM UTC 25 11700633826 ps
T1408 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.2553463815 Feb 09 03:04:28 PM UTC 25 Feb 09 03:15:37 PM UTC 25 40125634792 ps
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