| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 95.95 | 95.51 | 93.50 | 95.41 | 94.18 | 97.57 | 99.53 |
| T2762 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_large_delays.659857692 | Oct 15 04:32:46 PM UTC 24 | Oct 15 04:36:26 PM UTC 24 | 22583035293 ps | ||
| T2763 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random.953551035 | Oct 15 04:35:41 PM UTC 24 | Oct 15 04:36:26 PM UTC 24 | 509961355 ps | ||
| T2764 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_zero_delays.2252773099 | Oct 15 04:36:18 PM UTC 24 | Oct 15 04:36:29 PM UTC 24 | 51671474 ps | ||
| T2765 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.598233225 | Oct 15 04:36:07 PM UTC 24 | Oct 15 04:36:33 PM UTC 24 | 103847955 ps | ||
| T2766 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device.3342480638 | Oct 15 04:35:54 PM UTC 24 | Oct 15 04:36:35 PM UTC 24 | 393594175 ps | ||
| T2767 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2477033075 | Oct 15 04:30:04 PM UTC 24 | Oct 15 04:36:36 PM UTC 24 | 27660748409 ps | ||
| T2768 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_unmapped_addr.2484386738 | Oct 15 04:36:00 PM UTC 24 | Oct 15 04:36:48 PM UTC 24 | 325215520 ps | ||
| T2769 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.8468680 | Oct 15 04:20:14 PM UTC 24 | Oct 15 04:36:49 PM UTC 24 | 56304998297 ps | ||
| T2770 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random.3073068829 | Oct 15 04:36:28 PM UTC 24 | Oct 15 04:36:51 PM UTC 24 | 399596326 ps | ||
| T2771 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.2029155348 | Oct 15 04:23:46 PM UTC 24 | Oct 15 04:36:53 PM UTC 24 | 51177858763 ps | ||
| T2772 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device.1195354814 | Oct 15 04:34:42 PM UTC 24 | Oct 15 04:36:56 PM UTC 24 | 2252611175 ps | ||
| T2773 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_large_delays.196479115 | Oct 15 04:35:37 PM UTC 24 | Oct 15 04:36:57 PM UTC 24 | 8498824878 ps | ||
| T2774 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_zero_delays.841764538 | Oct 15 04:36:35 PM UTC 24 | Oct 15 04:36:58 PM UTC 24 | 186851618 ps | ||
| T2775 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_same_source.195153257 | Oct 15 04:36:46 PM UTC 24 | Oct 15 04:37:02 PM UTC 24 | 408722424 ps | ||
| T2776 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.3841753292 | Oct 15 04:35:43 PM UTC 24 | Oct 15 04:37:03 PM UTC 24 | 4946032425 ps | ||
| T2777 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.337916575 | Oct 15 04:21:49 PM UTC 24 | Oct 15 04:37:06 PM UTC 24 | 56818597182 ps | ||
| T2778 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.2154595938 | Oct 15 04:35:19 PM UTC 24 | Oct 15 04:37:07 PM UTC 24 | 998859989 ps | ||
| T2779 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_random.136290633 | Oct 15 04:35:53 PM UTC 24 | Oct 15 04:37:09 PM UTC 24 | 2111539529 ps | ||
| T2780 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.3161251672 | Oct 15 04:27:44 PM UTC 24 | Oct 15 04:37:16 PM UTC 24 | 15635103703 ps | ||
| T2781 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.843625141 | Oct 15 04:31:02 PM UTC 24 | Oct 15 04:37:18 PM UTC 24 | 16721290359 ps | ||
| T2782 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.4058619038 | Oct 15 04:33:09 PM UTC 24 | Oct 15 04:37:18 PM UTC 24 | 1296835863 ps | ||
| T2783 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_error.1323900030 | Oct 15 04:31:59 PM UTC 24 | Oct 15 04:37:18 PM UTC 24 | 8189065746 ps | ||
| T2784 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device.707297842 | Oct 15 04:36:47 PM UTC 24 | Oct 15 04:37:19 PM UTC 24 | 329552721 ps | ||
| T2785 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke.1308377929 | Oct 15 04:37:09 PM UTC 24 | Oct 15 04:37:19 PM UTC 24 | 189508579 ps | ||
| T2786 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_slow_rsp.2052700770 | Oct 15 04:33:43 PM UTC 24 | Oct 15 04:37:23 PM UTC 24 | 16604102971 ps | ||
| T2787 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.3385211990 | Oct 15 04:36:53 PM UTC 24 | Oct 15 04:37:25 PM UTC 24 | 675193955 ps | ||
| T2788 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_zero_delays.2091989049 | Oct 15 04:37:15 PM UTC 24 | Oct 15 04:37:25 PM UTC 24 | 49458101 ps | ||
| T2789 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_unmapped_addr.1417908403 | Oct 15 04:36:50 PM UTC 24 | Oct 15 04:37:28 PM UTC 24 | 286353119 ps | ||
| T2790 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all.152757398 | Oct 15 04:35:17 PM UTC 24 | Oct 15 04:37:30 PM UTC 24 | 1349281123 ps | ||
| T2791 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.914493828 | Oct 15 04:35:26 PM UTC 24 | Oct 15 04:37:33 PM UTC 24 | 2814427288 ps | ||
| T2792 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.2808086276 | Oct 15 04:36:24 PM UTC 24 | Oct 15 04:37:44 PM UTC 24 | 5245348786 ps | ||
| T2793 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all.3233274222 | Oct 15 04:36:58 PM UTC 24 | Oct 15 04:37:44 PM UTC 24 | 362422221 ps | ||
| T2794 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_slow_rsp.2282550694 | Oct 15 04:32:49 PM UTC 24 | Oct 15 04:37:46 PM UTC 24 | 22243174533 ps | ||
| T2795 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_slow_rsp.1483130651 | Oct 15 04:36:45 PM UTC 24 | Oct 15 04:37:52 PM UTC 24 | 3471138684 ps | ||
| T2796 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke.4035568680 | Oct 15 04:37:48 PM UTC 24 | Oct 15 04:37:57 PM UTC 24 | 45876621 ps | ||
| T2797 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_zero_delays.612532246 | Oct 15 04:37:49 PM UTC 24 | Oct 15 04:38:00 PM UTC 24 | 50946195 ps | ||
| T2798 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.3723688762 | Oct 15 04:37:43 PM UTC 24 | Oct 15 04:38:04 PM UTC 24 | 150378352 ps | ||
| T2799 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device.3854134413 | Oct 15 04:37:28 PM UTC 24 | Oct 15 04:38:09 PM UTC 24 | 506939271 ps | ||
| T2800 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_same_source.2647432893 | Oct 15 04:37:35 PM UTC 24 | Oct 15 04:38:11 PM UTC 24 | 411150321 ps | ||
| T2801 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_random.616050974 | Oct 15 04:36:54 PM UTC 24 | Oct 15 04:38:14 PM UTC 24 | 1813694998 ps | ||
| T2802 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random.2796863732 | Oct 15 04:37:59 PM UTC 24 | Oct 15 04:38:16 PM UTC 24 | 236195562 ps | ||
| T2803 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_large_delays.3682875496 | Oct 15 04:33:40 PM UTC 24 | Oct 15 04:38:18 PM UTC 24 | 20645541757 ps | ||
| T2804 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.4289319273 | Oct 15 04:37:31 PM UTC 24 | Oct 15 04:38:22 PM UTC 24 | 2901765619 ps | ||
| T2805 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random.3123915250 | Oct 15 04:37:24 PM UTC 24 | Oct 15 04:38:22 PM UTC 24 | 604046544 ps | ||
| T2806 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_random.2391065978 | Oct 15 04:37:40 PM UTC 24 | Oct 15 04:38:23 PM UTC 24 | 1416449271 ps | ||
| T2807 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_unmapped_addr.994118061 | Oct 15 04:37:41 PM UTC 24 | Oct 15 04:38:25 PM UTC 24 | 858232571 ps | ||
| T2808 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.1980827839 | Oct 15 04:31:55 PM UTC 24 | Oct 15 04:38:27 PM UTC 24 | 1942797523 ps | ||
| T2809 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_zero_delays.3900050334 | Oct 15 04:37:24 PM UTC 24 | Oct 15 04:38:30 PM UTC 24 | 585416020 ps | ||
| T2810 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.2910637877 | Oct 15 04:37:43 PM UTC 24 | Oct 15 04:38:30 PM UTC 24 | 90559554 ps | ||
| T2811 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_zero_delays.991303538 | Oct 15 04:38:10 PM UTC 24 | Oct 15 04:38:30 PM UTC 24 | 198161250 ps | ||
| T2812 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_large_delays.815680988 | Oct 15 04:37:18 PM UTC 24 | Oct 15 04:38:33 PM UTC 24 | 7720214892 ps | ||
| T2813 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.774432786 | Oct 15 04:37:22 PM UTC 24 | Oct 15 04:38:37 PM UTC 24 | 5333804193 ps | ||
| T2814 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all.1434478701 | Oct 15 04:34:08 PM UTC 24 | Oct 15 04:38:39 PM UTC 24 | 8278349163 ps | ||
| T2815 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_slow_rsp.94212348 | Oct 15 04:30:44 PM UTC 24 | Oct 15 04:38:40 PM UTC 24 | 30559078594 ps | ||
| T2816 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_large_delays.1060195355 | Oct 15 04:36:20 PM UTC 24 | Oct 15 04:38:41 PM UTC 24 | 9268198407 ps | ||
| T2817 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_unmapped_addr.1657239671 | Oct 15 04:38:32 PM UTC 24 | Oct 15 04:38:43 PM UTC 24 | 68350156 ps | ||
| T2818 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_large_delays.538411226 | Oct 15 04:38:12 PM UTC 24 | Oct 15 04:38:46 PM UTC 24 | 3276188937 ps | ||
| T2819 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_slow_rsp.34208357 | Oct 15 04:38:10 PM UTC 24 | Oct 15 04:38:50 PM UTC 24 | 1975101220 ps | ||
| T2820 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device.4033280634 | Oct 15 04:38:18 PM UTC 24 | Oct 15 04:38:50 PM UTC 24 | 316426359 ps | ||
| T2821 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.2875342920 | Oct 15 04:29:23 PM UTC 24 | Oct 15 04:38:57 PM UTC 24 | 17812300928 ps | ||
| T2822 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke.1963312966 | Oct 15 04:38:47 PM UTC 24 | Oct 15 04:38:59 PM UTC 24 | 161970682 ps | ||
| T2823 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_zero_delays.999671957 | Oct 15 04:38:49 PM UTC 24 | Oct 15 04:39:00 PM UTC 24 | 49177755 ps | ||
| T2824 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_error.3443749815 | Oct 15 04:31:11 PM UTC 24 | Oct 15 04:39:02 PM UTC 24 | 13581765436 ps | ||
| T2825 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_large_delays.1529686134 | Oct 15 04:37:53 PM UTC 24 | Oct 15 04:39:05 PM UTC 24 | 6499243589 ps | ||
| T2826 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.2439609138 | Oct 15 04:38:35 PM UTC 24 | Oct 15 04:39:12 PM UTC 24 | 906011515 ps | ||
| T2827 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_slow_rsp.86647962 | Oct 15 04:37:28 PM UTC 24 | Oct 15 04:39:12 PM UTC 24 | 6090000537 ps | ||
| T2828 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.400768431 | Oct 15 04:37:57 PM UTC 24 | Oct 15 04:39:13 PM UTC 24 | 4898226689 ps | ||
| T2829 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_zero_delays.338774997 | Oct 15 04:38:56 PM UTC 24 | Oct 15 04:39:14 PM UTC 24 | 195588127 ps | ||
| T2830 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_large_delays.2595239006 | Oct 15 04:34:34 PM UTC 24 | Oct 15 04:39:19 PM UTC 24 | 28732531431 ps | ||
| T2831 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_error.1762461148 | Oct 15 04:30:23 PM UTC 24 | Oct 15 04:39:19 PM UTC 24 | 15635322158 ps | ||
| T2832 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_same_source.1528863006 | Oct 15 04:39:05 PM UTC 24 | Oct 15 04:39:20 PM UTC 24 | 178209988 ps | ||
| T2833 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_same_source.3909368455 | Oct 15 04:38:27 PM UTC 24 | Oct 15 04:39:24 PM UTC 24 | 1971089487 ps | ||
| T2834 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_slow_rsp.272350831 | Oct 15 04:34:44 PM UTC 24 | Oct 15 04:39:24 PM UTC 24 | 20648882487 ps | ||
| T2835 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.2643485817 | Oct 15 04:39:11 PM UTC 24 | Oct 15 04:39:25 PM UTC 24 | 62554868 ps | ||
| T2836 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_unmapped_addr.614022401 | Oct 15 04:39:06 PM UTC 24 | Oct 15 04:39:26 PM UTC 24 | 167865966 ps | ||
| T2837 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_zero_delays.3564204291 | Oct 15 04:39:24 PM UTC 24 | Oct 15 04:39:31 PM UTC 24 | 41057711 ps | ||
| T2838 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.1584221144 | Oct 15 04:33:17 PM UTC 24 | Oct 15 04:39:33 PM UTC 24 | 2941697627 ps | ||
| T2839 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke.1420919950 | Oct 15 04:39:26 PM UTC 24 | Oct 15 04:39:35 PM UTC 24 | 228973731 ps | ||
| T2840 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_random.2222602952 | Oct 15 04:38:31 PM UTC 24 | Oct 15 04:39:37 PM UTC 24 | 2331765175 ps | ||
| T2841 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_error.2007311627 | Oct 15 04:39:23 PM UTC 24 | Oct 15 04:39:43 PM UTC 24 | 441195927 ps | ||
| T2842 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.3346869995 | Oct 15 04:34:14 PM UTC 24 | Oct 15 04:39:43 PM UTC 24 | 1460255905 ps | ||
| T2843 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_error.1735653928 | Oct 15 04:36:11 PM UTC 24 | Oct 15 04:39:47 PM UTC 24 | 6478237012 ps | ||
| T2844 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random.3563233356 | Oct 15 04:38:53 PM UTC 24 | Oct 15 04:39:57 PM UTC 24 | 1798229588 ps | ||
| T2845 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_random.1427030446 | Oct 15 04:39:46 PM UTC 24 | Oct 15 04:39:59 PM UTC 24 | 188511914 ps | ||
| T2846 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.1847251396 | Oct 15 04:39:48 PM UTC 24 | Oct 15 04:39:59 PM UTC 24 | 150105895 ps | ||
| T2847 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_zero_delays.3033739367 | Oct 15 04:39:35 PM UTC 24 | Oct 15 04:40:01 PM UTC 24 | 277619931 ps | ||
| T2848 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_large_delays.973325460 | Oct 15 04:38:49 PM UTC 24 | Oct 15 04:40:03 PM UTC 24 | 7821674689 ps | ||
| T2849 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.1711627143 | Oct 15 04:38:53 PM UTC 24 | Oct 15 04:40:03 PM UTC 24 | 4554877821 ps | ||
| T2850 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_error.1811586553 | Oct 15 04:35:24 PM UTC 24 | Oct 15 04:40:05 PM UTC 24 | 8526987912 ps | ||
| T2851 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_zero_delays.2949578441 | Oct 15 04:40:07 PM UTC 24 | Oct 15 04:40:17 PM UTC 24 | 48196286 ps | ||
| T2852 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random.1168255831 | Oct 15 04:39:34 PM UTC 24 | Oct 15 04:40:20 PM UTC 24 | 1335785495 ps | ||
| T2853 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all.4218132989 | Oct 15 04:38:41 PM UTC 24 | Oct 15 04:40:23 PM UTC 24 | 3185753883 ps | ||
| T2854 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke.2346691828 | Oct 15 04:40:10 PM UTC 24 | Oct 15 04:40:26 PM UTC 24 | 293757909 ps | ||
| T2855 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.3039172188 | Oct 15 04:31:07 PM UTC 24 | Oct 15 04:40:28 PM UTC 24 | 10802180883 ps | ||
| T2856 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_unmapped_addr.1406577124 | Oct 15 04:39:48 PM UTC 24 | Oct 15 04:40:31 PM UTC 24 | 848864497 ps | ||
| T2857 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device.2658754389 | Oct 15 04:39:46 PM UTC 24 | Oct 15 04:40:33 PM UTC 24 | 1085959259 ps | ||
| T2858 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_random.509757066 | Oct 15 04:39:06 PM UTC 24 | Oct 15 04:40:35 PM UTC 24 | 2433981494 ps | ||
| T2859 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random.2778678288 | Oct 15 04:40:22 PM UTC 24 | Oct 15 04:40:42 PM UTC 24 | 193872184 ps | ||
| T2860 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_same_source.543968655 | Oct 15 04:39:45 PM UTC 24 | Oct 15 04:40:47 PM UTC 24 | 2290865322 ps | ||
| T2861 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_random.3300513469 | Oct 15 04:40:43 PM UTC 24 | Oct 15 04:40:51 PM UTC 24 | 117906490 ps | ||
| T2862 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.3368657880 | Oct 15 04:25:20 PM UTC 24 | Oct 15 04:40:52 PM UTC 24 | 62388244012 ps | ||
| T2863 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_large_delays.2979810489 | Oct 15 04:39:26 PM UTC 24 | Oct 15 04:40:55 PM UTC 24 | 9236757260 ps | ||
| T2864 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all.2741861668 | Oct 15 04:36:06 PM UTC 24 | Oct 15 04:40:58 PM UTC 24 | 6916466972 ps | ||
| T2865 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_zero_delays.1492713376 | Oct 15 04:40:23 PM UTC 24 | Oct 15 04:40:59 PM UTC 24 | 314822681 ps | ||
| T2866 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device.2450763922 | Oct 15 04:39:03 PM UTC 24 | Oct 15 04:41:00 PM UTC 24 | 3005585713 ps | ||
| T2867 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.2459524647 | Oct 15 04:40:49 PM UTC 24 | Oct 15 04:41:00 PM UTC 24 | 188938319 ps | ||
| T2868 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_large_delays.209543727 | Oct 15 04:30:42 PM UTC 24 | Oct 15 04:41:01 PM UTC 24 | 54095703201 ps | ||
| T2869 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.1673201723 | Oct 15 04:37:15 PM UTC 24 | Oct 15 04:41:08 PM UTC 24 | 3858435545 ps | ||
| T2870 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.1061164437 | Oct 15 04:39:36 PM UTC 24 | Oct 15 04:41:08 PM UTC 24 | 4293390175 ps | ||
| T2871 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.424970072 | Oct 15 04:34:16 PM UTC 24 | Oct 15 04:41:13 PM UTC 24 | 9071857155 ps | ||
| T2872 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.2126300405 | Oct 15 04:40:21 PM UTC 24 | Oct 15 04:41:32 PM UTC 24 | 4268183994 ps | ||
| T2873 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_same_source.4607664 | Oct 15 04:40:44 PM UTC 24 | Oct 15 04:41:33 PM UTC 24 | 591082064 ps | ||
| T2874 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_unmapped_addr.1672933644 | Oct 15 04:40:47 PM UTC 24 | Oct 15 04:41:33 PM UTC 24 | 1349188336 ps | ||
| T2875 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_large_delays.1924784373 | Oct 15 04:40:10 PM UTC 24 | Oct 15 04:41:40 PM UTC 24 | 7695589424 ps | ||
| T2876 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_large_delays.1595891900 | Oct 15 04:37:29 PM UTC 24 | Oct 15 04:41:42 PM UTC 24 | 25542766016 ps | ||
| T2877 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.1134665694 | Oct 15 04:24:43 PM UTC 24 | Oct 15 04:41:43 PM UTC 24 | 71943413485 ps | ||
| T2878 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device.290412416 | Oct 15 04:40:26 PM UTC 24 | Oct 15 04:41:50 PM UTC 24 | 1609017446 ps | ||
| T2879 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1070765292 | Oct 15 04:22:04 PM UTC 24 | Oct 15 04:42:14 PM UTC 24 | 29195891544 ps | ||
| T2880 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_error.217407474 | Oct 15 04:40:01 PM UTC 24 | Oct 15 04:42:18 PM UTC 24 | 1589596256 ps | ||
| T2881 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_error.1264610070 | Oct 15 04:41:01 PM UTC 24 | Oct 15 04:42:22 PM UTC 24 | 2139767017 ps | ||
| T2882 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.1325729729 | Oct 15 04:40:58 PM UTC 24 | Oct 15 04:42:23 PM UTC 24 | 380007275 ps | ||
| T2883 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_slow_rsp.3115426622 | Oct 15 04:40:27 PM UTC 24 | Oct 15 04:42:52 PM UTC 24 | 8859877879 ps | ||
| T2884 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.41591209 | Oct 15 04:40:29 PM UTC 24 | Oct 15 04:43:11 PM UTC 24 | 9671912320 ps | ||
| T2885 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all.3820332812 | Oct 15 04:37:44 PM UTC 24 | Oct 15 04:43:30 PM UTC 24 | 3326069850 ps | ||
| T2886 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_large_delays.3513672925 | Oct 15 04:40:24 PM UTC 24 | Oct 15 04:43:39 PM UTC 24 | 18360677304 ps | ||
| T2887 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_slow_rsp.320523890 | Oct 15 04:35:48 PM UTC 24 | Oct 15 04:43:49 PM UTC 24 | 28574747304 ps | ||
| T2888 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.2395980444 | Oct 15 04:34:49 PM UTC 24 | Oct 15 04:44:05 PM UTC 24 | 39408494864 ps | ||
| T2889 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_error.4045296694 | Oct 15 04:37:44 PM UTC 24 | Oct 15 04:44:07 PM UTC 24 | 11001217697 ps | ||
| T2890 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.1488668709 | Oct 15 04:28:21 PM UTC 24 | Oct 15 04:44:15 PM UTC 24 | 62823432007 ps | ||
| T2891 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.513541189 | Oct 15 04:40:02 PM UTC 24 | Oct 15 04:44:18 PM UTC 24 | 2638439560 ps | ||
| T2892 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.2772570561 | Oct 15 04:38:43 PM UTC 24 | Oct 15 04:44:33 PM UTC 24 | 903917727 ps | ||
| T2893 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all.1935187873 | Oct 15 04:39:57 PM UTC 24 | Oct 15 04:44:33 PM UTC 24 | 3504137695 ps | ||
| T2894 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.3226083775 | Oct 15 04:36:59 PM UTC 24 | Oct 15 04:44:44 PM UTC 24 | 8705808749 ps | ||
| T2895 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_error.1649190467 | Oct 15 04:37:02 PM UTC 24 | Oct 15 04:44:55 PM UTC 24 | 14393152702 ps | ||
| T2896 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_large_delays.574014251 | Oct 15 04:35:45 PM UTC 24 | Oct 15 04:44:58 PM UTC 24 | 52833277215 ps | ||
| T2897 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_large_delays.1961013786 | Oct 15 04:38:58 PM UTC 24 | Oct 15 04:45:00 PM UTC 24 | 38469185312 ps | ||
| T2898 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all.4115370284 | Oct 15 04:39:16 PM UTC 24 | Oct 15 04:45:01 PM UTC 24 | 4032819173 ps | ||
| T2899 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_large_delays.1809499263 | Oct 15 04:36:41 PM UTC 24 | Oct 15 04:45:08 PM UTC 24 | 51869831929 ps | ||
| T2900 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_error.3776841201 | Oct 15 04:33:13 PM UTC 24 | Oct 15 04:45:12 PM UTC 24 | 21254228694 ps | ||
| T2901 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.3820012782 | Oct 15 04:41:00 PM UTC 24 | Oct 15 04:45:14 PM UTC 24 | 5013995430 ps | ||
| T2902 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_error.3786399673 | Oct 15 04:38:42 PM UTC 24 | Oct 15 04:45:21 PM UTC 24 | 12932418376 ps | ||
| T2903 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.4171367834 | Oct 15 04:36:48 PM UTC 24 | Oct 15 04:45:28 PM UTC 24 | 36431874831 ps | ||
| T606 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.638626205 | Oct 15 04:38:48 PM UTC 24 | Oct 15 04:45:54 PM UTC 24 | 9180534806 ps | ||
| T2904 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.1621377534 | Oct 15 04:37:49 PM UTC 24 | Oct 15 04:46:04 PM UTC 24 | 5177272953 ps | ||
| T2905 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all.930854181 | Oct 15 04:40:54 PM UTC 24 | Oct 15 04:46:22 PM UTC 24 | 9976479703 ps | ||
| T2906 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_slow_rsp.434615091 | Oct 15 04:38:57 PM UTC 24 | Oct 15 04:46:40 PM UTC 24 | 31382387244 ps | ||
| T2907 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_slow_rsp.1192085169 | Oct 15 04:39:44 PM UTC 24 | Oct 15 04:46:51 PM UTC 24 | 27343883733 ps | ||
| T2908 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.1775371249 | Oct 15 04:33:55 PM UTC 24 | Oct 15 04:47:28 PM UTC 24 | 56471695903 ps | ||
| T2909 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_large_delays.1032869850 | Oct 15 04:39:36 PM UTC 24 | Oct 15 04:48:29 PM UTC 24 | 60326100795 ps | ||
| T2910 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.1732695960 | Oct 15 04:35:53 PM UTC 24 | Oct 15 04:49:14 PM UTC 24 | 57623327182 ps | ||
| T2911 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.2877684158 | Oct 15 04:39:14 PM UTC 24 | Oct 15 04:49:16 PM UTC 24 | 9758673112 ps | ||
| T2912 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.1198828531 | Oct 15 04:39:03 PM UTC 24 | Oct 15 04:50:39 PM UTC 24 | 49185969779 ps | ||
| T2913 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.3399232675 | Oct 15 04:39:57 PM UTC 24 | Oct 15 04:52:20 PM UTC 24 | 16635677302 ps | ||
| T2914 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.2937805399 | Oct 15 04:36:07 PM UTC 24 | Oct 15 04:52:40 PM UTC 24 | 23612709628 ps | ||
| T2915 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.2969754988 | Oct 15 04:39:42 PM UTC 24 | Oct 15 04:54:06 PM UTC 24 | 64455053276 ps | ||
| T2916 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.1956889714 | Oct 15 04:38:24 PM UTC 24 | Oct 15 04:54:29 PM UTC 24 | 70420379374 ps | ||
| T2917 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.4009036478 | Oct 15 04:39:23 PM UTC 24 | Oct 15 04:56:42 PM UTC 24 | 12183998013 ps | ||
| T2918 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.1523825251 | Oct 15 02:35:31 PM UTC 24 | Oct 15 05:34:34 PM UTC 24 | 64530245625 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1518550779 | Oct 15 04:41:17 PM UTC 24 | Oct 15 04:45:19 PM UTC 24 | 4660244144 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3537552837 | Oct 15 04:41:09 PM UTC 24 | Oct 15 04:45:21 PM UTC 24 | 4091703952 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2541626455 | Oct 15 04:41:23 PM UTC 24 | Oct 15 04:45:23 PM UTC 24 | 5132317520 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.370398643 | Oct 15 04:41:17 PM UTC 24 | Oct 15 04:45:30 PM UTC 24 | 5299027800 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2795468401 | Oct 15 04:41:08 PM UTC 24 | Oct 15 04:45:35 PM UTC 24 | 4846435408 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2389656765 | Oct 15 04:41:24 PM UTC 24 | Oct 15 04:45:43 PM UTC 24 | 4617365644 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.612371195 | Oct 15 04:41:28 PM UTC 24 | Oct 15 04:45:43 PM UTC 24 | 5302896969 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1116460058 | Oct 15 04:41:25 PM UTC 24 | Oct 15 04:46:16 PM UTC 24 | 5307025012 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3551832131 | Oct 15 04:41:29 PM UTC 24 | Oct 15 04:46:26 PM UTC 24 | 6165052338 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2337620663 | Oct 15 04:41:21 PM UTC 24 | Oct 15 04:46:56 PM UTC 24 | 5044245400 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1306388313 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3909709478 ps |
| CPU time | 358.42 seconds |
| Started | Oct 15 04:48:09 PM UTC 24 |
| Finished | Oct 15 04:54:12 PM UTC 24 |
| Peak memory | 627544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306388313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_ mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.1306388313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.1957782106 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 4634294250 ps |
| CPU time | 314.39 seconds |
| Started | Oct 15 02:35:46 PM UTC 24 |
| Finished | Oct 15 02:41:05 PM UTC 24 |
| Peak memory | 615068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957782106 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.1957782106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.2489854872 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 5993197320 ps |
| CPU time | 1043.39 seconds |
| Started | Oct 15 05:20:30 PM UTC 24 |
| Finished | Oct 15 05:38:07 PM UTC 24 |
| Peak memory | 625252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489854872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_plic_all_irqs_0.2489854872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_plic_all_irqs_0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.893910055 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 182651548 ps |
| CPU time | 20.24 seconds |
| Started | Oct 15 02:35:35 PM UTC 24 |
| Finished | Oct 15 02:35:56 PM UTC 24 |
| Peak memory | 593808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893910055 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.893910055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3207409523 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3074580144 ps |
| CPU time | 185.37 seconds |
| Started | Oct 15 04:48:46 PM UTC 24 |
| Finished | Oct 15 04:51:54 PM UTC 24 |
| Peak memory | 637704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3207409523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.3207409523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1518550779 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4660244144 ps |
| CPU time | 237.83 seconds |
| Started | Oct 15 04:41:17 PM UTC 24 |
| Finished | Oct 15 04:45:19 PM UTC 24 |
| Peak memory | 658240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518550 779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 2.chip_ padctrl_attributes.1518550779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.119132068 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 2780772387 ps |
| CPU time | 133.28 seconds |
| Started | Oct 15 02:36:45 PM UTC 24 |
| Finished | Oct 15 02:39:00 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119132068 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.119132068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.1571003460 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 2532121980 ps |
| CPU time | 324.33 seconds |
| Started | Oct 15 05:05:41 PM UTC 24 |
| Finished | Oct 15 05:11:10 PM UTC 24 |
| Peak memory | 625472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand om_seed=1571003460 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aler t_test.1571003460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.3918988103 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 8642297000 ps |
| CPU time | 1657.1 seconds |
| Started | Oct 15 05:14:18 PM UTC 24 |
| Finished | Oct 15 05:42:17 PM UTC 24 |
| Peak memory | 627908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918988103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_side load_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.3918988103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2513297111 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 60408568886 ps |
| CPU time | 762.71 seconds |
| Started | Oct 15 02:39:26 PM UTC 24 |
| Finished | Oct 15 02:52:19 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513297111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_devi ce_slow_rsp.2513297111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.3315961131 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 52540688256 ps |
| CPU time | 724.29 seconds |
| Started | Oct 15 02:56:07 PM UTC 24 |
| Finished | Oct 15 03:08:21 PM UTC 24 |
| Peak memory | 593980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315961131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_devi ce_slow_rsp.3315961131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3104908762 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 69537843977 ps |
| CPU time | 1122.92 seconds |
| Started | Oct 15 02:35:38 PM UTC 24 |
| Finished | Oct 15 02:54:34 PM UTC 24 |
| Peak memory | 593976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104908762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_devi ce_slow_rsp.3104908762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.3542890733 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5828805390 ps |
| CPU time | 1455.01 seconds |
| Started | Oct 15 05:44:31 PM UTC 24 |
| Finished | Oct 15 06:09:03 PM UTC 24 |
| Peak memory | 642228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_tim eout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_ img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542890733 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_virus.3542890733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.3476517609 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 11842936376 ps |
| CPU time | 1066.89 seconds |
| Started | Oct 15 04:57:07 PM UTC 24 |
| Finished | Oct 15 05:15:07 PM UTC 24 |
| Peak memory | 642016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476517609 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.3476517609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.1043148884 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 4465577869 ps |
| CPU time | 174.52 seconds |
| Started | Oct 15 02:35:42 PM UTC 24 |
| Finished | Oct 15 02:38:39 PM UTC 24 |
| Peak memory | 593748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043148884 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1043148884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.2344320273 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 4891474704 ps |
| CPU time | 579.39 seconds |
| Started | Oct 15 04:51:31 PM UTC 24 |
| Finished | Oct 15 05:01:18 PM UTC 24 |
| Peak memory | 627744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344320273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ct rl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.2344320273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.3988919047 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 4631227690 ps |
| CPU time | 784.66 seconds |
| Started | Oct 15 05:21:37 PM UTC 24 |
| Finished | Oct 15 05:34:52 PM UTC 24 |
| Peak memory | 625388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3988919047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_plic_all_irqs_20.3988919047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_plic_all_irqs_20/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1129413028 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 60163588494 ps |
| CPU time | 915.51 seconds |
| Started | Oct 15 03:02:26 PM UTC 24 |
| Finished | Oct 15 03:17:53 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129413028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_dev ice_slow_rsp.1129413028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2594053075 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 8044081900 ps |
| CPU time | 491.29 seconds |
| Started | Oct 15 05:30:40 PM UTC 24 |
| Finished | Oct 15 05:38:58 PM UTC 24 |
| Peak memory | 627768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_w ake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2594053075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2594053075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.4072462383 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 3516452734 ps |
| CPU time | 247.62 seconds |
| Started | Oct 15 05:35:30 PM UTC 24 |
| Finished | Oct 15 05:39:42 PM UTC 24 |
| Peak memory | 627408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_im ages=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072462383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.4072462383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.2454376042 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 42935396136 ps |
| CPU time | 713.77 seconds |
| Started | Oct 15 03:20:58 PM UTC 24 |
| Finished | Oct 15 03:33:01 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454376042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_dev ice_slow_rsp.2454376042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.4252469196 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 8049825886 ps |
| CPU time | 298.67 seconds |
| Started | Oct 15 03:22:15 PM UTC 24 |
| Finished | Oct 15 03:27:18 PM UTC 24 |
| Peak memory | 593904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252469196 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.4252469196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.2760038309 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 39184490573 ps |
| CPU time | 601.5 seconds |
| Started | Oct 15 03:24:06 PM UTC 24 |
| Finished | Oct 15 03:34:15 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760038309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_dev ice_slow_rsp.2760038309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.2486320966 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 4280282117 ps |
| CPU time | 283.1 seconds |
| Started | Oct 15 02:35:32 PM UTC 24 |
| Finished | Oct 15 02:40:19 PM UTC 24 |
| Peak memory | 619264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486320966 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.2486320966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.2125597632 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4124506780 ps |
| CPU time | 393.26 seconds |
| Started | Oct 15 04:49:25 PM UTC 24 |
| Finished | Oct 15 04:56:04 PM UTC 24 |
| Peak memory | 625312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2125597632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_gpio.2125597632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_gpio/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.2021124001 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 2816310317 ps |
| CPU time | 127.02 seconds |
| Started | Oct 15 02:35:35 PM UTC 24 |
| Finished | Oct 15 02:37:45 PM UTC 24 |
| Peak memory | 593752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021124001 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2021124001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.2589638547 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 27128872956 ps |
| CPU time | 413.7 seconds |
| Started | Oct 15 03:15:21 PM UTC 24 |
| Finished | Oct 15 03:22:20 PM UTC 24 |
| Peak memory | 593984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589638547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_dev ice_slow_rsp.2589638547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.2182370743 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 4916154565 ps |
| CPU time | 298.45 seconds |
| Started | Oct 15 02:47:47 PM UTC 24 |
| Finished | Oct 15 02:52:50 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182370743 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.2182370743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.3307039762 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 4046816010 ps |
| CPU time | 788.16 seconds |
| Started | Oct 15 05:09:06 PM UTC 24 |
| Finished | Oct 15 05:22:24 PM UTC 24 |
| Peak memory | 625364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_ device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307039762 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_auto_mode.3307039762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2944693724 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4506710270 ps |
| CPU time | 487.74 seconds |
| Started | Oct 15 04:50:43 PM UTC 24 |
| Finished | Oct 15 04:58:57 PM UTC 24 |
| Peak memory | 627476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944693724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ct rl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.2944693724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2334965620 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 9502444116 ps |
| CPU time | 1069.18 seconds |
| Started | Oct 15 05:06:56 PM UTC 24 |
| Finished | Oct 15 05:24:59 PM UTC 24 |
| Peak memory | 627680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334965620 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_hand ler_lpg_sleep_mode_pings.2334965620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.2049130751 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 71559487788 ps |
| CPU time | 980.42 seconds |
| Started | Oct 15 03:31:19 PM UTC 24 |
| Finished | Oct 15 03:47:51 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049130751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_dev ice_slow_rsp.2049130751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.1304447684 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9162338744 ps |
| CPU time | 757.22 seconds |
| Started | Oct 15 05:29:11 PM UTC 24 |
| Finished | Oct 15 05:41:59 PM UTC 24 |
| Peak memory | 625032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130444 7684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_csr_rw.1304447684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.2581688470 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 3706783982 ps |
| CPU time | 617.41 seconds |
| Started | Oct 15 05:21:40 PM UTC 24 |
| Finished | Oct 15 05:32:06 PM UTC 24 |
| Peak memory | 625496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2581688470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_plic_all_irqs_10.2581688470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_plic_all_irqs_10/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1811700218 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 18510549564 ps |
| CPU time | 305.42 seconds |
| Started | Oct 15 02:36:46 PM UTC 24 |
| Finished | Oct 15 02:41:56 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811700218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_devi ce_slow_rsp.1811700218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.2271284629 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 5746124305 ps |
| CPU time | 701.67 seconds |
| Started | Oct 15 02:40:59 PM UTC 24 |
| Finished | Oct 15 02:52:50 PM UTC 24 |
| Peak memory | 616976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271284629 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.2271284629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.1477559899 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 43681280472 ps |
| CPU time | 5375.23 seconds |
| Started | Oct 15 04:47:50 PM UTC 24 |
| Finished | Oct 15 06:18:33 PM UTC 24 |
| Peak memory | 642496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw _build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477559899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip _earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.1477559899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3953305357 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 14179660586 ps |
| CPU time | 3708.06 seconds |
| Started | Oct 15 05:50:14 PM UTC 24 |
| Finished | Oct 15 06:52:46 PM UTC 24 |
| Peak memory | 629832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mas k_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3953305357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3953305357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1249021650 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 5317626670 ps |
| CPU time | 398.07 seconds |
| Started | Oct 15 05:19:36 PM UTC 24 |
| Finished | Oct 15 05:26:20 PM UTC 24 |
| Peak memory | 625248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_im ages=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249021650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1249021650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.3676207375 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 11851498473 ps |
| CPU time | 1975.51 seconds |
| Started | Oct 15 06:02:28 PM UTC 24 |
| Finished | Oct 15 06:35:48 PM UTC 24 |
| Peak memory | 642164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_devic e=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676207375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jta g_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.3676207375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.4287006219 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3591032026 ps |
| CPU time | 247.01 seconds |
| Started | Oct 15 04:50:16 PM UTC 24 |
| Finished | Oct 15 04:54:27 PM UTC 24 |
| Peak memory | 625460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287006219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 0.chip_sw_spi_host_tx_rx.4287006219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3883379957 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3096629833 ps |
| CPU time | 390.27 seconds |
| Started | Oct 15 06:50:28 PM UTC 24 |
| Finished | Oct 15 06:57:04 PM UTC 24 |
| Peak memory | 625744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883379957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_ mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.3883379957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.260524251 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3759920874 ps |
| CPU time | 268.8 seconds |
| Started | Oct 15 04:54:13 PM UTC 24 |
| Finished | Oct 15 04:58:46 PM UTC 24 |
| Peak memory | 639956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260524251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.260524251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.1674754665 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 3391237176 ps |
| CPU time | 141.83 seconds |
| Started | Oct 15 03:04:56 PM UTC 24 |
| Finished | Oct 15 03:07:20 PM UTC 24 |
| Peak memory | 593988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674754665 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.1674754665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.2737342931 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 31716652044 ps |
| CPU time | 301.92 seconds |
| Started | Oct 15 02:36:42 PM UTC 24 |
| Finished | Oct 15 02:41:48 PM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737342931 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2737342931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.3618386424 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 4655143090 ps |
| CPU time | 386.42 seconds |
| Started | Oct 15 03:08:42 PM UTC 24 |
| Finished | Oct 15 03:15:13 PM UTC 24 |
| Peak memory | 619024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618386424 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.3618386424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.2181454404 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 5806418712 ps |
| CPU time | 696.14 seconds |
| Started | Oct 15 04:50:38 PM UTC 24 |
| Finished | Oct 15 05:02:24 PM UTC 24 |
| Peak memory | 627368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181454404 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.2181454404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2398973709 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 24862547192 ps |
| CPU time | 1101.61 seconds |
| Started | Oct 15 02:35:40 PM UTC 24 |
| Finished | Oct 15 02:54:14 PM UTC 24 |
| Peak memory | 594048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398973709 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.2398973709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.1268816861 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 11769075942 ps |
| CPU time | 1117.76 seconds |
| Started | Oct 15 07:51:40 PM UTC 24 |
| Finished | Oct 15 08:10:31 PM UTC 24 |
| Peak memory | 624784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126881 6861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_csr_rw.1268816861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3537552837 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4091703952 ps |
| CPU time | 247.08 seconds |
| Started | Oct 15 04:41:09 PM UTC 24 |
| Finished | Oct 15 04:45:21 PM UTC 24 |
| Peak memory | 668392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537552 837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 1.chip_ padctrl_attributes.3537552837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.760865872 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3486146798 ps |
| CPU time | 299.4 seconds |
| Started | Oct 15 05:03:21 PM UTC 24 |
| Finished | Oct 15 05:08:25 PM UTC 24 |
| Peak memory | 625424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=760865872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_sysrst_ctrl_outputs.760865872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.2518803727 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 5712741118 ps |
| CPU time | 350.53 seconds |
| Started | Oct 15 02:37:45 PM UTC 24 |
| Finished | Oct 15 02:43:41 PM UTC 24 |
| Peak memory | 678412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518803727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_reset.2518803727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.1228763579 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 9136097656 ps |
| CPU time | 337.64 seconds |
| Started | Oct 15 03:16:09 PM UTC 24 |
| Finished | Oct 15 03:21:52 PM UTC 24 |
| Peak memory | 593764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228763579 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1228763579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.3781214030 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 3955612140 ps |
| CPU time | 470.43 seconds |
| Started | Oct 15 04:46:06 PM UTC 24 |
| Finished | Oct 15 04:54:02 PM UTC 24 |
| Peak memory | 637784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781214030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.3781214030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.4044267816 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 3962777090 ps |
| CPU time | 373.09 seconds |
| Started | Oct 15 02:46:33 PM UTC 24 |
| Finished | Oct 15 02:52:51 PM UTC 24 |
| Peak memory | 619016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044267816 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.4044267816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.2296573935 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 5673441300 ps |
| CPU time | 483.01 seconds |
| Started | Oct 15 04:56:29 PM UTC 24 |
| Finished | Oct 15 05:04:38 PM UTC 24 |
| Peak memory | 627772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296573935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_sw_rstmgr_cpu_info.2296573935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1923535748 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 4542327652 ps |
| CPU time | 258.68 seconds |
| Started | Oct 15 02:37:44 PM UTC 24 |
| Finished | Oct 15 02:42:07 PM UTC 24 |
| Peak memory | 594012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923535748 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.1923535748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1833041491 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 6739229477 ps |
| CPU time | 656.99 seconds |
| Started | Oct 15 05:10:39 PM UTC 24 |
| Finished | Oct 15 05:21:45 PM UTC 24 |
| Peak memory | 627348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_ otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833041491 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_lc_hw_debug_en_test.1833041491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.742189054 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 4272242776 ps |
| CPU time | 386.47 seconds |
| Started | Oct 15 05:06:40 PM UTC 24 |
| Finished | Oct 15 05:13:12 PM UTC 24 |
| Peak memory | 673816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742189054 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sl eep_mode_alerts.742189054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.277864208 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3066221186 ps |
| CPU time | 245.47 seconds |
| Started | Oct 15 04:50:03 PM UTC 24 |
| Finished | Oct 15 04:54:12 PM UTC 24 |
| Peak memory | 625228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277864208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.277864208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.555130794 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 5214301368 ps |
| CPU time | 520.01 seconds |
| Started | Oct 15 10:45:31 PM UTC 24 |
| Finished | Oct 15 10:54:18 PM UTC 24 |
| Peak memory | 676020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555130794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.555130794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.3920886767 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 5930192000 ps |
| CPU time | 580.98 seconds |
| Started | Oct 15 10:57:00 PM UTC 24 |
| Finished | Oct 15 11:06:49 PM UTC 24 |
| Peak memory | 675876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920886767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.3920886767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2128782994 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 3970058336 ps |
| CPU time | 390.34 seconds |
| Started | Oct 15 10:42:10 PM UTC 24 |
| Finished | Oct 15 10:48:47 PM UTC 24 |
| Peak memory | 673896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128782994 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2128782994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.3248569339 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 6167283948 ps |
| CPU time | 855.3 seconds |
| Started | Oct 15 10:03:35 PM UTC 24 |
| Finished | Oct 15 10:18:02 PM UTC 24 |
| Peak memory | 627616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248569339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.3248569339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.145394080 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1087321787 ps |
| CPU time | 43.96 seconds |
| Started | Oct 15 02:35:39 PM UTC 24 |
| Finished | Oct 15 02:36:24 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145394080 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.145394080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.222019219 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 15842015118 ps |
| CPU time | 962.21 seconds |
| Started | Oct 15 02:56:42 PM UTC 24 |
| Finished | Oct 15 03:12:56 PM UTC 24 |
| Peak memory | 594060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222019219 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.222019219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.3024375410 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 7466856102 ps |
| CPU time | 625.72 seconds |
| Started | Oct 15 05:34:51 PM UTC 24 |
| Finished | Oct 15 05:45:25 PM UTC 24 |
| Peak memory | 644384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024375410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_tap_straps_rma.3024375410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.3588952837 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 12540247804 ps |
| CPU time | 1322.56 seconds |
| Started | Oct 15 04:57:22 PM UTC 24 |
| Finished | Oct 15 05:19:41 PM UTC 24 |
| Peak memory | 627524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_buil d_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588952837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.3588952837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.1303787820 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 7199667888 ps |
| CPU time | 1017.42 seconds |
| Started | Oct 15 05:19:25 PM UTC 24 |
| Finished | Oct 15 05:36:35 PM UTC 24 |
| Peak memory | 627516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303787820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.1303787820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.2348272035 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 6197494552 ps |
| CPU time | 1041.3 seconds |
| Started | Oct 15 09:18:55 PM UTC 24 |
| Finished | Oct 15 09:36:30 PM UTC 24 |
| Peak memory | 627740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348272035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_plic_all_irqs_0.2348272035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_plic_all_irqs_0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.3991326269 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 4289407257 ps |
| CPU time | 457.49 seconds |
| Started | Oct 15 02:57:13 PM UTC 24 |
| Finished | Oct 15 03:04:57 PM UTC 24 |
| Peak memory | 619236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991326269 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.3991326269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.3768603348 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 6596014250 ps |
| CPU time | 428.27 seconds |
| Started | Oct 15 06:50:29 PM UTC 24 |
| Finished | Oct 15 06:57:43 PM UTC 24 |
| Peak memory | 627276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768603348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.3768603348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.2345341243 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 50102527890 ps |
| CPU time | 6622.41 seconds |
| Started | Oct 15 04:56:30 PM UTC 24 |
| Finished | Oct 15 06:48:13 PM UTC 24 |
| Peak memory | 644604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345341243 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_dev.2345341243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1560509237 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 864739633 ps |
| CPU time | 371.77 seconds |
| Started | Oct 15 02:37:30 PM UTC 24 |
| Finished | Oct 15 02:43:47 PM UTC 24 |
| Peak memory | 593728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560509237 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.1560509237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.3898896910 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3357611244 ps |
| CPU time | 375.51 seconds |
| Started | Oct 15 04:48:46 PM UTC 24 |
| Finished | Oct 15 04:55:07 PM UTC 24 |
| Peak memory | 625248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898896910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.3898896910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.299537368 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 5481648884 ps |
| CPU time | 535.72 seconds |
| Started | Oct 15 05:19:12 PM UTC 24 |
| Finished | Oct 15 05:28:16 PM UTC 24 |
| Peak memory | 627492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_ch eck=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299537368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctr l_scrambled_access_jitter_en.299537368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.4117604441 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 5609122618 ps |
| CPU time | 612.67 seconds |
| Started | Oct 15 02:53:17 PM UTC 24 |
| Finished | Oct 15 03:03:37 PM UTC 24 |
| Peak memory | 615244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117604441 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.4117604441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.2357891817 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 15255981221 ps |
| CPU time | 578.91 seconds |
| Started | Oct 15 02:42:46 PM UTC 24 |
| Finished | Oct 15 02:52:33 PM UTC 24 |
| Peak memory | 594140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357891817 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2357891817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.872858121 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 4695221150 ps |
| CPU time | 768.26 seconds |
| Started | Oct 15 09:19:08 PM UTC 24 |
| Finished | Oct 15 09:32:07 PM UTC 24 |
| Peak memory | 625408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=872858121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_plic_all_irqs_20.872858121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_plic_all_irqs_20/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.1905987109 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 72430774778 ps |
| CPU time | 1161.42 seconds |
| Started | Oct 15 03:41:28 PM UTC 24 |
| Finished | Oct 15 04:01:03 PM UTC 24 |
| Peak memory | 594124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905987109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_dev ice_slow_rsp.1905987109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.2980333504 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 2883646404 ps |
| CPU time | 265.21 seconds |
| Started | Oct 15 06:51:09 PM UTC 24 |
| Finished | Oct 15 06:55:38 PM UTC 24 |
| Peak memory | 625228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2980333504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_sleep_pin_retention.2980333504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.2947946459 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 373629494 ps |
| CPU time | 28.97 seconds |
| Started | Oct 15 02:36:52 PM UTC 24 |
| Finished | Oct 15 02:37:22 PM UTC 24 |
| Peak memory | 593676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947946459 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2947946459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.679410984 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 4348339216 ps |
| CPU time | 521.54 seconds |
| Started | Oct 15 05:01:32 PM UTC 24 |
| Finished | Oct 15 05:10:21 PM UTC 24 |
| Peak memory | 627372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_w hen_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=679410984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.679410984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1011553124 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 4575968691 ps |
| CPU time | 584.62 seconds |
| Started | Oct 15 04:50:01 PM UTC 24 |
| Finished | Oct 15 04:59:54 PM UTC 24 |
| Peak memory | 637680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011553124 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_alt_clk_freq.1011553124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.1274454738 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 9137001641 ps |
| CPU time | 573.06 seconds |
| Started | Oct 15 03:11:56 PM UTC 24 |
| Finished | Oct 15 03:21:36 PM UTC 24 |
| Peak memory | 594160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274454738 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.1274454738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.4098756749 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 6887464120 ps |
| CPU time | 1144.46 seconds |
| Started | Oct 15 07:42:31 PM UTC 24 |
| Finished | Oct 15 08:01:50 PM UTC 24 |
| Peak memory | 625468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098756749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_plic_all_irqs_0.4098756749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_plic_all_irqs_0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1334091840 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 74526198379 ps |
| CPU time | 1061.21 seconds |
| Started | Oct 15 03:46:22 PM UTC 24 |
| Finished | Oct 15 04:04:17 PM UTC 24 |
| Peak memory | 593740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334091840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_dev ice_slow_rsp.1334091840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.3305589034 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 10860749183 ps |
| CPU time | 859.08 seconds |
| Started | Oct 15 02:52:59 PM UTC 24 |
| Finished | Oct 15 03:07:29 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305589034 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.3305589034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1938722805 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 9273792123 ps |
| CPU time | 651.61 seconds |
| Started | Oct 15 05:17:52 PM UTC 24 |
| Finished | Oct 15 05:28:53 PM UTC 24 |
| Peak memory | 627540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1938722805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.1938722805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1301841266 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 5302428171 ps |
| CPU time | 355.67 seconds |
| Started | Oct 15 03:05:47 PM UTC 24 |
| Finished | Oct 15 03:11:48 PM UTC 24 |
| Peak memory | 594028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301841266 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.1301841266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.2099451887 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 17086453985 ps |
| CPU time | 2203.22 seconds |
| Started | Oct 15 02:41:16 PM UTC 24 |
| Finished | Oct 15 03:18:25 PM UTC 24 |
| Peak memory | 609028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2099451887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.chip_same_csr_outstanding.2099451887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.595486883 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 42851498769 ps |
| CPU time | 5894.52 seconds |
| Started | Oct 15 08:29:41 PM UTC 24 |
| Finished | Oct 15 10:09:10 PM UTC 24 |
| Peak memory | 640176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw _build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595486883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_ earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.595486883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.934407260 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 4979217880 ps |
| CPU time | 357.98 seconds |
| Started | Oct 15 05:32:55 PM UTC 24 |
| Finished | Oct 15 05:38:58 PM UTC 24 |
| Peak memory | 639748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934407260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.934407260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.1534873813 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 7783305621 ps |
| CPU time | 349.47 seconds |
| Started | Oct 15 02:40:46 PM UTC 24 |
| Finished | Oct 15 02:46:40 PM UTC 24 |
| Peak memory | 679508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534873813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_reset.1534873813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.2164972895 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 6074474418 ps |
| CPU time | 691.88 seconds |
| Started | Oct 15 09:15:20 PM UTC 24 |
| Finished | Oct 15 09:27:02 PM UTC 24 |
| Peak memory | 627292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164972895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.2164972895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.1635854579 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 4143326932 ps |
| CPU time | 393.91 seconds |
| Started | Oct 15 02:43:38 PM UTC 24 |
| Finished | Oct 15 02:50:17 PM UTC 24 |
| Peak memory | 619152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635854579 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.1635854579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.390962482 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 5946366440 ps |
| CPU time | 709.27 seconds |
| Started | Oct 15 10:01:41 PM UTC 24 |
| Finished | Oct 15 10:13:39 PM UTC 24 |
| Peak memory | 627688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390962482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.390962482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.2592805031 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 6326470199 ps |
| CPU time | 525.83 seconds |
| Started | Oct 15 03:31:34 PM UTC 24 |
| Finished | Oct 15 03:40:28 PM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592805031 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.2592805031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3396535290 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 3417024085 ps |
| CPU time | 305.13 seconds |
| Started | Oct 15 07:04:57 PM UTC 24 |
| Finished | Oct 15 07:10:07 PM UTC 24 |
| Peak memory | 641812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_ access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3396535290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.3396535290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2863386317 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 18655467832 ps |
| CPU time | 573.46 seconds |
| Started | Oct 15 05:02:21 PM UTC 24 |
| Finished | Oct 15 05:12:03 PM UTC 24 |
| Peak memory | 637532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863386317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/c hip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2863386317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.2180061143 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 5922964184 ps |
| CPU time | 725.92 seconds |
| Started | Oct 15 04:09:08 PM UTC 24 |
| Finished | Oct 15 04:21:23 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180061143 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_rand_reset.2180061143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.3562353885 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 4349697808 ps |
| CPU time | 703.86 seconds |
| Started | Oct 15 03:24:23 PM UTC 24 |
| Finished | Oct 15 03:36:17 PM UTC 24 |
| Peak memory | 594156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562353885 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.3562353885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1416242314 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 872590113 ps |
| CPU time | 182.84 seconds |
| Started | Oct 15 03:40:05 PM UTC 24 |
| Finished | Oct 15 03:43:10 PM UTC 24 |
| Peak memory | 594140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416242314 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.1416242314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.1689023247 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 18930670125 ps |
| CPU time | 1720.99 seconds |
| Started | Oct 15 04:49:21 PM UTC 24 |
| Finished | Oct 15 05:18:25 PM UTC 24 |
| Peak memory | 631616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689023247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_flash_init.1689023247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_init/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.790652363 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 3624632280 ps |
| CPU time | 585.01 seconds |
| Started | Oct 15 07:42:59 PM UTC 24 |
| Finished | Oct 15 07:52:51 PM UTC 24 |
| Peak memory | 625380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=790652363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_plic_all_irqs_10.790652363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_plic_all_irqs_10/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.1876355282 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 3709231628 ps |
| CPU time | 330.79 seconds |
| Started | Oct 15 08:18:27 PM UTC 24 |
| Finished | Oct 15 08:24:03 PM UTC 24 |
| Peak memory | 625380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1876355282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_sleep_pin_retention.1876355282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.3546590765 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3836360648 ps |
| CPU time | 534.03 seconds |
| Started | Oct 15 04:49:26 PM UTC 24 |
| Finished | Oct 15 04:58:28 PM UTC 24 |
| Peak memory | 637784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546590765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.3546590765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.295717720 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 3898535808 ps |
| CPU time | 546.26 seconds |
| Started | Oct 15 04:48:46 PM UTC 24 |
| Finished | Oct 15 04:57:59 PM UTC 24 |
| Peak memory | 627740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295717720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.295717720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1650751045 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 4117449960 ps |
| CPU time | 675.45 seconds |
| Started | Oct 15 05:25:13 PM UTC 24 |
| Finished | Oct 15 05:36:38 PM UTC 24 |
| Peak memory | 629772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650751045 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_dev.1650751045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.1440066468 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 8362094802 ps |
| CPU time | 356.35 seconds |
| Started | Oct 15 03:23:20 PM UTC 24 |
| Finished | Oct 15 03:29:21 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440066468 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.1440066468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.1865048805 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 8305925824 ps |
| CPU time | 1751.08 seconds |
| Started | Oct 15 04:49:12 PM UTC 24 |
| Finished | Oct 15 05:18:45 PM UTC 24 |
| Peak memory | 627928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865048805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.1865048805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.63146853 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 4019864180 ps |
| CPU time | 737.91 seconds |
| Started | Oct 15 07:42:59 PM UTC 24 |
| Finished | Oct 15 07:55:27 PM UTC 24 |
| Peak memory | 625492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=63146853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_plic_all_irqs_20.63146853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_plic_all_irqs_20/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.2736840894 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 4280786168 ps |
| CPU time | 560.67 seconds |
| Started | Oct 15 09:18:21 PM UTC 24 |
| Finished | Oct 15 09:27:50 PM UTC 24 |
| Peak memory | 625252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2736840894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_plic_all_irqs_10.2736840894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_plic_all_irqs_10/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.1392483567 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 7105568292 ps |
| CPU time | 1586.35 seconds |
| Started | Oct 15 05:12:19 PM UTC 24 |
| Finished | Oct 15 05:39:05 PM UTC 24 |
| Peak memory | 625492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_ srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392483567 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.1392483567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.2997783656 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 42195556639 ps |
| CPU time | 5424.21 seconds |
| Started | Oct 15 07:01:30 PM UTC 24 |
| Finished | Oct 15 08:33:02 PM UTC 24 |
| Peak memory | 640568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw _build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997783656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip _earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.2997783656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.1066727521 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 5181601960 ps |
| CPU time | 476 seconds |
| Started | Oct 15 03:04:03 PM UTC 24 |
| Finished | Oct 15 03:12:06 PM UTC 24 |
| Peak memory | 615072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066727521 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.1066727521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.2222930624 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 18153977014 ps |
| CPU time | 680.02 seconds |
| Started | Oct 15 03:38:20 PM UTC 24 |
| Finished | Oct 15 03:49:49 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222930624 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2222930624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/35.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.64111298 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 10763118628 ps |
| CPU time | 378.57 seconds |
| Started | Oct 15 04:00:52 PM UTC 24 |
| Finished | Oct 15 04:07:16 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64111298 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.64111298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/57.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.3400356568 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 3702993437 ps |
| CPU time | 474.27 seconds |
| Started | Oct 15 06:58:51 PM UTC 24 |
| Finished | Oct 15 07:06:52 PM UTC 24 |
| Peak memory | 625240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3400356568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_gpio.3400356568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_gpio/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.762190912 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 3719779386 ps |
| CPU time | 547.36 seconds |
| Started | Oct 15 04:49:09 PM UTC 24 |
| Finished | Oct 15 04:58:25 PM UTC 24 |
| Peak memory | 637780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762190912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.762190912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3659769456 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 24809247925 ps |
| CPU time | 4236.39 seconds |
| Started | Oct 15 05:38:55 PM UTC 24 |
| Finished | Oct 15 06:50:24 PM UTC 24 |
| Peak memory | 630128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659769456 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3659769456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2802991324 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2227083320 ps |
| CPU time | 208 seconds |
| Started | Oct 15 04:51:30 PM UTC 24 |
| Finished | Oct 15 04:55:02 PM UTC 24 |
| Peak memory | 641868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_ access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2802991324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.2802991324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.2394730861 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 5206862696 ps |
| CPU time | 573.26 seconds |
| Started | Oct 15 04:49:45 PM UTC 24 |
| Finished | Oct 15 04:59:26 PM UTC 24 |
| Peak memory | 675824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394730861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.2394730861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.3470243632 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 5122193908 ps |
| CPU time | 556.37 seconds |
| Started | Oct 15 10:44:27 PM UTC 24 |
| Finished | Oct 15 10:53:51 PM UTC 24 |
| Peak memory | 675920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470243632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.3470243632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1084356784 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 2520718477 ps |
| CPU time | 103.77 seconds |
| Started | Oct 15 04:56:18 PM UTC 24 |
| Finished | Oct 15 04:58:04 PM UTC 24 |
| Peak memory | 637144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSo urceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10843567 84 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc _ctrl_volatile_raw_unlock_ext_clk_48mhz.1084356784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.3571006043 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 2472116830 ps |
| CPU time | 210.22 seconds |
| Started | Oct 15 03:14:01 PM UTC 24 |
| Finished | Oct 15 03:17:35 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571006043 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3571006043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.1203504145 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 2285124579 ps |
| CPU time | 249.89 seconds |
| Started | Oct 15 04:04:13 PM UTC 24 |
| Finished | Oct 15 04:08:27 PM UTC 24 |
| Peak memory | 594008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203504145 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_rand_reset.1203504145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.666692745 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 4912342002 ps |
| CPU time | 583.97 seconds |
| Started | Oct 15 08:00:08 PM UTC 24 |
| Finished | Oct 15 08:09:59 PM UTC 24 |
| Peak memory | 625492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666692745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.666692745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2726207450 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 3671139240 ps |
| CPU time | 417.46 seconds |
| Started | Oct 15 07:53:38 PM UTC 24 |
| Finished | Oct 15 08:00:42 PM UTC 24 |
| Peak memory | 627516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=2726207450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_pwrmgr_lowpower_cancel.2726207450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.1628526757 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 23378020056 ps |
| CPU time | 1521.3 seconds |
| Started | Oct 15 05:02:20 PM UTC 24 |
| Finished | Oct 15 05:28:01 PM UTC 24 |
| Peak memory | 631808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_i mages=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628526757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.1628526757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.1814981314 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 46427592 ps |
| CPU time | 6.7 seconds |
| Started | Oct 15 02:35:32 PM UTC 24 |
| Finished | Oct 15 02:35:40 PM UTC 24 |
| Peak memory | 591676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814981314 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1814981314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3437116877 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 450865153 ps |
| CPU time | 129.96 seconds |
| Started | Oct 15 02:58:49 PM UTC 24 |
| Finished | Oct 15 03:01:01 PM UTC 24 |
| Peak memory | 593860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437116877 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.3437116877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.325693060 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 592140528 ps |
| CPU time | 194.14 seconds |
| Started | Oct 15 03:10:18 PM UTC 24 |
| Finished | Oct 15 03:13:35 PM UTC 24 |
| Peak memory | 593956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325693060 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.325693060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.320266329 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 4209899384 ps |
| CPU time | 406.95 seconds |
| Started | Oct 15 07:28:05 PM UTC 24 |
| Finished | Oct 15 07:34:57 PM UTC 24 |
| Peak memory | 673928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320266329 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sl eep_mode_alerts.320266329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.1666230560 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 5410977422 ps |
| CPU time | 479.96 seconds |
| Started | Oct 15 06:49:14 PM UTC 24 |
| Finished | Oct 15 06:57:21 PM UTC 24 |
| Peak memory | 675696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666230560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.1666230560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.616379289 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 4541811966 ps |
| CPU time | 420.17 seconds |
| Started | Oct 15 10:14:36 PM UTC 24 |
| Finished | Oct 15 10:21:43 PM UTC 24 |
| Peak memory | 673836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616379289 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_alert_handler_lpg_s leep_mode_alerts.616379289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3449186825 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 4006900192 ps |
| CPU time | 441.11 seconds |
| Started | Oct 15 10:15:35 PM UTC 24 |
| Finished | Oct 15 10:23:03 PM UTC 24 |
| Peak memory | 673892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449186825 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3449186825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.2040927038 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 6193441520 ps |
| CPU time | 714.63 seconds |
| Started | Oct 15 10:16:52 PM UTC 24 |
| Finished | Oct 15 10:28:57 PM UTC 24 |
| Peak memory | 675928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040927038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.2040927038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3767851500 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 4049596738 ps |
| CPU time | 471.34 seconds |
| Started | Oct 15 10:20:25 PM UTC 24 |
| Finished | Oct 15 10:28:23 PM UTC 24 |
| Peak memory | 673724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767851500 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3767851500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.2558051558 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 6493281880 ps |
| CPU time | 747.05 seconds |
| Started | Oct 15 10:18:18 PM UTC 24 |
| Finished | Oct 15 10:30:55 PM UTC 24 |
| Peak memory | 676008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558051558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.2558051558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.27839123 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 3679802440 ps |
| CPU time | 405.88 seconds |
| Started | Oct 15 10:20:27 PM UTC 24 |
| Finished | Oct 15 10:27:18 PM UTC 24 |
| Peak memory | 673732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27839123 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_alert_handler_lpg_sl eep_mode_alerts.27839123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.3081544491 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 5023516354 ps |
| CPU time | 582.78 seconds |
| Started | Oct 15 10:20:24 PM UTC 24 |
| Finished | Oct 15 10:30:14 PM UTC 24 |
| Peak memory | 676004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081544491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.3081544491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.492563653 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 3646073626 ps |
| CPU time | 396.35 seconds |
| Started | Oct 15 10:22:32 PM UTC 24 |
| Finished | Oct 15 10:29:14 PM UTC 24 |
| Peak memory | 673884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492563653 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_alert_handler_lpg_s leep_mode_alerts.492563653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.16660305 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 6079826100 ps |
| CPU time | 777.42 seconds |
| Started | Oct 15 10:21:10 PM UTC 24 |
| Finished | Oct 15 10:34:18 PM UTC 24 |
| Peak memory | 675692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16660305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esca lation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.16660305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.28068873 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 3902897848 ps |
| CPU time | 342.37 seconds |
| Started | Oct 15 10:23:59 PM UTC 24 |
| Finished | Oct 15 10:29:47 PM UTC 24 |
| Peak memory | 673732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28068873 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_alert_handler_lpg_sl eep_mode_alerts.28068873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.2458382729 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 6403417896 ps |
| CPU time | 551.58 seconds |
| Started | Oct 15 10:22:32 PM UTC 24 |
| Finished | Oct 15 10:31:52 PM UTC 24 |
| Peak memory | 675684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458382729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.2458382729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3471067837 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 3490333918 ps |
| CPU time | 356.53 seconds |
| Started | Oct 15 10:25:23 PM UTC 24 |
| Finished | Oct 15 10:31:26 PM UTC 24 |
| Peak memory | 673892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471067837 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3471067837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.2876946232 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 5036918928 ps |
| CPU time | 637.68 seconds |
| Started | Oct 15 10:24:49 PM UTC 24 |
| Finished | Oct 15 10:35:36 PM UTC 24 |
| Peak memory | 675748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876946232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.2876946232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.677545201 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3845282432 ps |
| CPU time | 503.45 seconds |
| Started | Oct 15 10:27:03 PM UTC 24 |
| Finished | Oct 15 10:35:34 PM UTC 24 |
| Peak memory | 675692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677545201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.677545201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1117293690 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 3683749906 ps |
| CPU time | 361.66 seconds |
| Started | Oct 15 08:59:57 PM UTC 24 |
| Finished | Oct 15 09:06:04 PM UTC 24 |
| Peak memory | 673852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117293690 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_s leep_mode_alerts.1117293690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3704845956 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 3901718792 ps |
| CPU time | 392.45 seconds |
| Started | Oct 15 10:29:18 PM UTC 24 |
| Finished | Oct 15 10:35:57 PM UTC 24 |
| Peak memory | 673644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704845956 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3704845956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.3027620644 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 4436472764 ps |
| CPU time | 508.3 seconds |
| Started | Oct 15 10:28:13 PM UTC 24 |
| Finished | Oct 15 10:36:48 PM UTC 24 |
| Peak memory | 675928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027620644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.3027620644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1602693643 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 3494446120 ps |
| CPU time | 386.51 seconds |
| Started | Oct 15 10:30:04 PM UTC 24 |
| Finished | Oct 15 10:36:36 PM UTC 24 |
| Peak memory | 673900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602693643 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1602693643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.3179621641 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 4419994400 ps |
| CPU time | 570.76 seconds |
| Started | Oct 15 10:29:19 PM UTC 24 |
| Finished | Oct 15 10:38:58 PM UTC 24 |
| Peak memory | 675696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179621641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.3179621641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.4201940802 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 4087469534 ps |
| CPU time | 479.05 seconds |
| Started | Oct 15 10:30:07 PM UTC 24 |
| Finished | Oct 15 10:38:13 PM UTC 24 |
| Peak memory | 673708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201940802 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_alert_handler_lpg_ sleep_mode_alerts.4201940802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.3153499393 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 5683655082 ps |
| CPU time | 703.67 seconds |
| Started | Oct 15 10:30:04 PM UTC 24 |
| Finished | Oct 15 10:41:57 PM UTC 24 |
| Peak memory | 675780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153499393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.3153499393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2113796347 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 3936063752 ps |
| CPU time | 404.56 seconds |
| Started | Oct 15 10:31:35 PM UTC 24 |
| Finished | Oct 15 10:38:25 PM UTC 24 |
| Peak memory | 673644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113796347 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2113796347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.2334104956 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 6232942086 ps |
| CPU time | 575.25 seconds |
| Started | Oct 15 10:30:59 PM UTC 24 |
| Finished | Oct 15 10:40:42 PM UTC 24 |
| Peak memory | 675932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334104956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.2334104956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.527018359 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 3962262554 ps |
| CPU time | 398.79 seconds |
| Started | Oct 15 10:32:46 PM UTC 24 |
| Finished | Oct 15 10:39:31 PM UTC 24 |
| Peak memory | 673904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527018359 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_alert_handler_lpg_s leep_mode_alerts.527018359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.2405015778 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 5999285592 ps |
| CPU time | 511.06 seconds |
| Started | Oct 15 10:32:09 PM UTC 24 |
| Finished | Oct 15 10:40:47 PM UTC 24 |
| Peak memory | 675684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405015778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.2405015778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2466573803 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 4331924312 ps |
| CPU time | 376.58 seconds |
| Started | Oct 15 10:34:12 PM UTC 24 |
| Finished | Oct 15 10:40:34 PM UTC 24 |
| Peak memory | 673848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466573803 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2466573803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.1917520292 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 4422611016 ps |
| CPU time | 490.33 seconds |
| Started | Oct 15 10:32:49 PM UTC 24 |
| Finished | Oct 15 10:41:06 PM UTC 24 |
| Peak memory | 675932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917520292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.1917520292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3597849758 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 2963512466 ps |
| CPU time | 340.73 seconds |
| Started | Oct 15 10:34:12 PM UTC 24 |
| Finished | Oct 15 10:39:58 PM UTC 24 |
| Peak memory | 673932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597849758 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3597849758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.119092272 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 3866214292 ps |
| CPU time | 341.06 seconds |
| Started | Oct 15 10:34:18 PM UTC 24 |
| Finished | Oct 15 10:40:04 PM UTC 24 |
| Peak memory | 673800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119092272 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_alert_handler_lpg_s leep_mode_alerts.119092272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3305498976 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 4173669864 ps |
| CPU time | 428.72 seconds |
| Started | Oct 15 10:35:41 PM UTC 24 |
| Finished | Oct 15 10:42:56 PM UTC 24 |
| Peak memory | 673644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305498976 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3305498976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2280897673 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 3200280990 ps |
| CPU time | 448.19 seconds |
| Started | Oct 15 10:38:01 PM UTC 24 |
| Finished | Oct 15 10:45:36 PM UTC 24 |
| Peak memory | 673648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280897673 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2280897673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.3589078227 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 5793661616 ps |
| CPU time | 784.27 seconds |
| Started | Oct 15 10:38:01 PM UTC 24 |
| Finished | Oct 15 10:51:16 PM UTC 24 |
| Peak memory | 675928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589078227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.3589078227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.220708375 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 5125329700 ps |
| CPU time | 779.3 seconds |
| Started | Oct 15 10:37:38 PM UTC 24 |
| Finished | Oct 15 10:50:48 PM UTC 24 |
| Peak memory | 675688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220708375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.220708375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.3142889702 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 5017878040 ps |
| CPU time | 725.7 seconds |
| Started | Oct 15 10:37:38 PM UTC 24 |
| Finished | Oct 15 10:49:54 PM UTC 24 |
| Peak memory | 675764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142889702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.3142889702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.950645652 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 3449419880 ps |
| CPU time | 502.27 seconds |
| Started | Oct 15 10:37:58 PM UTC 24 |
| Finished | Oct 15 10:46:27 PM UTC 24 |
| Peak memory | 673952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950645652 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_alert_handler_lpg_s leep_mode_alerts.950645652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1997275097 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 3774582352 ps |
| CPU time | 373.88 seconds |
| Started | Oct 15 10:40:01 PM UTC 24 |
| Finished | Oct 15 10:46:20 PM UTC 24 |
| Peak memory | 673648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997275097 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1997275097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.3451212320 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 4845297172 ps |
| CPU time | 533.77 seconds |
| Started | Oct 15 10:40:17 PM UTC 24 |
| Finished | Oct 15 10:49:18 PM UTC 24 |
| Peak memory | 675896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451212320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.3451212320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3182184232 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 3481371800 ps |
| CPU time | 415.26 seconds |
| Started | Oct 15 10:40:18 PM UTC 24 |
| Finished | Oct 15 10:47:20 PM UTC 24 |
| Peak memory | 673640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182184232 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3182184232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1086030753 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 3927185800 ps |
| CPU time | 390.96 seconds |
| Started | Oct 15 10:41:56 PM UTC 24 |
| Finished | Oct 15 10:48:32 PM UTC 24 |
| Peak memory | 673712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086030753 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1086030753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.398366835 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 3794780414 ps |
| CPU time | 321.56 seconds |
| Started | Oct 15 10:41:37 PM UTC 24 |
| Finished | Oct 15 10:47:04 PM UTC 24 |
| Peak memory | 673904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398366835 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_alert_handler_lpg_s leep_mode_alerts.398366835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1911288685 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 4606625506 ps |
| CPU time | 443.3 seconds |
| Started | Oct 15 10:42:09 PM UTC 24 |
| Finished | Oct 15 10:49:39 PM UTC 24 |
| Peak memory | 673788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911288685 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1911288685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.3962169476 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 6501245002 ps |
| CPU time | 766.96 seconds |
| Started | Oct 15 10:42:15 PM UTC 24 |
| Finished | Oct 15 10:55:12 PM UTC 24 |
| Peak memory | 675692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962169476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.3962169476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1197410477 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 3739890344 ps |
| CPU time | 389.69 seconds |
| Started | Oct 15 10:42:15 PM UTC 24 |
| Finished | Oct 15 10:48:51 PM UTC 24 |
| Peak memory | 673712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197410477 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1197410477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.3526116750 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 5111219180 ps |
| CPU time | 586.73 seconds |
| Started | Oct 15 10:42:40 PM UTC 24 |
| Finished | Oct 15 10:52:35 PM UTC 24 |
| Peak memory | 675748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526116750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.3526116750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3366383931 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 3360424784 ps |
| CPU time | 362.82 seconds |
| Started | Oct 15 10:45:04 PM UTC 24 |
| Finished | Oct 15 10:51:13 PM UTC 24 |
| Peak memory | 673956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366383931 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3366383931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.2307870351 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 4999225228 ps |
| CPU time | 512.26 seconds |
| Started | Oct 15 10:46:44 PM UTC 24 |
| Finished | Oct 15 10:55:24 PM UTC 24 |
| Peak memory | 675928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307870351 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.2307870351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.1327665551 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 5500540812 ps |
| CPU time | 587.31 seconds |
| Started | Oct 15 10:03:34 PM UTC 24 |
| Finished | Oct 15 10:13:30 PM UTC 24 |
| Peak memory | 675688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327665551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.1327665551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.170880096 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 3394074142 ps |
| CPU time | 387.63 seconds |
| Started | Oct 15 10:47:23 PM UTC 24 |
| Finished | Oct 15 10:53:56 PM UTC 24 |
| Peak memory | 673812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170880096 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_alert_handler_lpg_s leep_mode_alerts.170880096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3148506608 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 3681629514 ps |
| CPU time | 352.38 seconds |
| Started | Oct 15 10:49:57 PM UTC 24 |
| Finished | Oct 15 10:55:55 PM UTC 24 |
| Peak memory | 674020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148506608 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3148506608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2264518898 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 2997541648 ps |
| CPU time | 286.44 seconds |
| Started | Oct 15 10:54:42 PM UTC 24 |
| Finished | Oct 15 10:59:33 PM UTC 24 |
| Peak memory | 673892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264518898 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2264518898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.3150889338 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 5142531482 ps |
| CPU time | 585.6 seconds |
| Started | Oct 15 10:53:51 PM UTC 24 |
| Finished | Oct 15 11:03:44 PM UTC 24 |
| Peak memory | 675700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150889338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.3150889338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.812938731 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 5861313928 ps |
| CPU time | 555.6 seconds |
| Started | Oct 15 10:53:37 PM UTC 24 |
| Finished | Oct 15 11:03:00 PM UTC 24 |
| Peak memory | 675744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812938731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.812938731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.1119243745 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 5811576496 ps |
| CPU time | 604.08 seconds |
| Started | Oct 15 10:54:17 PM UTC 24 |
| Finished | Oct 15 11:04:30 PM UTC 24 |
| Peak memory | 675880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119243745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.1119243745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.939306642 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 3626442388 ps |
| CPU time | 362.43 seconds |
| Started | Oct 15 10:58:22 PM UTC 24 |
| Finished | Oct 15 11:04:30 PM UTC 24 |
| Peak memory | 673796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939306642 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_alert_handler_lpg_s leep_mode_alerts.939306642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.399483852 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 4946909864 ps |
| CPU time | 577.64 seconds |
| Started | Oct 15 10:58:03 PM UTC 24 |
| Finished | Oct 15 11:07:49 PM UTC 24 |
| Peak memory | 675944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399483852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.399483852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.458649141 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 4386852500 ps |
| CPU time | 506.09 seconds |
| Started | Oct 15 10:58:01 PM UTC 24 |
| Finished | Oct 15 11:06:34 PM UTC 24 |
| Peak memory | 675704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458649141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.458649141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.1294446426 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 5677287428 ps |
| CPU time | 555.95 seconds |
| Started | Oct 15 11:01:08 PM UTC 24 |
| Finished | Oct 15 11:10:31 PM UTC 24 |
| Peak memory | 675684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294446426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.1294446426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2543311347 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 4202946462 ps |
| CPU time | 319.57 seconds |
| Started | Oct 15 11:04:11 PM UTC 24 |
| Finished | Oct 15 11:09:35 PM UTC 24 |
| Peak memory | 673860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543311347 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2543311347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.3243796038 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 4907967456 ps |
| CPU time | 471.37 seconds |
| Started | Oct 15 11:04:56 PM UTC 24 |
| Finished | Oct 15 11:12:54 PM UTC 24 |
| Peak memory | 675948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243796038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.3243796038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3846036497 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 4316701992 ps |
| CPU time | 322.13 seconds |
| Started | Oct 15 11:07:01 PM UTC 24 |
| Finished | Oct 15 11:12:28 PM UTC 24 |
| Peak memory | 673644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846036497 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3846036497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.888964536 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 5083316670 ps |
| CPU time | 396.59 seconds |
| Started | Oct 15 11:06:11 PM UTC 24 |
| Finished | Oct 15 11:12:53 PM UTC 24 |
| Peak memory | 675904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888964536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.888964536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.4290475739 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 5459391000 ps |
| CPU time | 466.81 seconds |
| Started | Oct 15 11:07:02 PM UTC 24 |
| Finished | Oct 15 11:14:54 PM UTC 24 |
| Peak memory | 676012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290475739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.4290475739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.22062186 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2907071833 ps |
| CPU time | 128.11 seconds |
| Started | Oct 15 08:33:31 PM UTC 24 |
| Finished | Oct 15 08:35:42 PM UTC 24 |
| Peak memory | 641176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_ access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=22062186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.22062186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.119125465 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 5178678662 ps |
| CPU time | 404.82 seconds |
| Started | Oct 15 08:18:39 PM UTC 24 |
| Finished | Oct 15 08:25:30 PM UTC 24 |
| Peak memory | 627504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119125465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.119125465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.4177952935 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 6451639128 ps |
| CPU time | 667.45 seconds |
| Started | Oct 15 02:51:01 PM UTC 24 |
| Finished | Oct 15 03:02:18 PM UTC 24 |
| Peak memory | 617120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177952935 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.4177952935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4182468640 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 5608468136 ps |
| CPU time | 448.75 seconds |
| Started | Oct 15 05:32:55 PM UTC 24 |
| Finished | Oct 15 05:40:30 PM UTC 24 |
| Peak memory | 627608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182468640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4182468640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_rst_inputs.4138400627 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 19891290262 ps |
| CPU time | 3086.2 seconds |
| Started | Oct 15 05:40:56 PM UTC 24 |
| Finished | Oct 15 06:33:00 PM UTC 24 |
| Peak memory | 629944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_ images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138400627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_input s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.4138400627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.2161020547 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 5112469568 ps |
| CPU time | 577 seconds |
| Started | Oct 15 10:30:39 PM UTC 24 |
| Finished | Oct 15 10:40:24 PM UTC 24 |
| Peak memory | 627780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161020547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.2161020547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.3382468684 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 10797182808 ps |
| CPU time | 2231.56 seconds |
| Started | Oct 15 05:14:45 PM UTC 24 |
| Finished | Oct 15 05:52:25 PM UTC 24 |
| Peak memory | 627632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382468684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sidel oad_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.3382468684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2513960201 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 7308844687 ps |
| CPU time | 493.9 seconds |
| Started | Oct 15 04:57:25 PM UTC 24 |
| Finished | Oct 15 05:05:46 PM UTC 24 |
| Peak memory | 627564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2513960201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_pwrmgr_full_aon_reset.2513960201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.63589624 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 4238507717 ps |
| CPU time | 434.37 seconds |
| Started | Oct 15 05:33:40 PM UTC 24 |
| Finished | Oct 15 05:41:01 PM UTC 24 |
| Peak memory | 641548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_han dler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=63589624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escal ation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.63589624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2454839893 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 3252116030 ps |
| CPU time | 335.12 seconds |
| Started | Oct 15 04:49:27 PM UTC 24 |
| Finished | Oct 15 04:55:07 PM UTC 24 |
| Peak memory | 625736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2454839893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_flash_ctrl_idle_low_power.2454839893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2501257628 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 21976366520 ps |
| CPU time | 1577.1 seconds |
| Started | Oct 15 05:32:00 PM UTC 24 |
| Finished | Oct 15 05:58:36 PM UTC 24 |
| Peak memory | 627424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501257628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2501257628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.3829108913 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 3398006514 ps |
| CPU time | 269.55 seconds |
| Started | Oct 15 02:36:00 PM UTC 24 |
| Finished | Oct 15 02:40:33 PM UTC 24 |
| Peak memory | 615188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829108913 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.3829108913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.604594041 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 11413100153 ps |
| CPU time | 475.84 seconds |
| Started | Oct 15 03:00:27 PM UTC 24 |
| Finished | Oct 15 03:08:29 PM UTC 24 |
| Peak memory | 594152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604594041 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.604594041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1985247024 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 4746690771 ps |
| CPU time | 468.62 seconds |
| Started | Oct 15 06:55:05 PM UTC 24 |
| Finished | Oct 15 07:03:01 PM UTC 24 |
| Peak memory | 637672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985247024 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1985247024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.1196680088 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4046627264 ps |
| CPU time | 436.45 seconds |
| Started | Oct 15 08:25:19 PM UTC 24 |
| Finished | Oct 15 08:32:41 PM UTC 24 |
| Peak memory | 625636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1196680088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_gpio.1196680088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_gpio/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.3285089516 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 3181097990 ps |
| CPU time | 284.38 seconds |
| Started | Oct 15 05:12:53 PM UTC 24 |
| Finished | Oct 15 05:17:41 PM UTC 24 |
| Peak memory | 625244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3285089516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_hmac_enc_idle.3285089516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2939280831 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 7184082404 ps |
| CPU time | 315.78 seconds |
| Started | Oct 15 04:59:57 PM UTC 24 |
| Finished | Oct 15 05:05:18 PM UTC 24 |
| Peak memory | 633540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939280831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2939280831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.833078192 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 18778914097 ps |
| CPU time | 1964.78 seconds |
| Started | Oct 15 05:38:42 PM UTC 24 |
| Finished | Oct 15 06:11:51 PM UTC 24 |
| Peak memory | 632084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_buil d_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833078192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.833078192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.1234712438 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 18485953748 ps |
| CPU time | 5030.34 seconds |
| Started | Oct 15 05:14:46 PM UTC 24 |
| Finished | Oct 15 06:39:35 PM UTC 24 |
| Peak memory | 629940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234712438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.1234712438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.1851917788 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 4347828670 ps |
| CPU time | 557.63 seconds |
| Started | Oct 15 05:30:40 PM UTC 24 |
| Finished | Oct 15 05:40:06 PM UTC 24 |
| Peak memory | 627224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851917788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_l c_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.1851917788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.3472654868 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 4863094112 ps |
| CPU time | 564.1 seconds |
| Started | Oct 15 05:39:18 PM UTC 24 |
| Finished | Oct 15 05:48:50 PM UTC 24 |
| Peak memory | 625236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472654868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_power_idle_load.3472654868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.3227658147 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 7900403312 ps |
| CPU time | 794.67 seconds |
| Started | Oct 15 05:19:23 PM UTC 24 |
| Finished | Oct 15 05:32:49 PM UTC 24 |
| Peak memory | 627428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3227658147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.3227658147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.3428243165 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 15962295662 ps |
| CPU time | 624.18 seconds |
| Started | Oct 15 02:35:39 PM UTC 24 |
| Finished | Oct 15 02:46:11 PM UTC 24 |
| Peak memory | 594228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428243165 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3428243165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.2962897092 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 126884575 ps |
| CPU time | 17.54 seconds |
| Started | Oct 15 02:35:38 PM UTC 24 |
| Finished | Oct 15 02:35:56 PM UTC 24 |
| Peak memory | 593752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962897092 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2962897092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.4098126740 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 7841197988 ps |
| CPU time | 325.31 seconds |
| Started | Oct 15 02:37:32 PM UTC 24 |
| Finished | Oct 15 02:43:02 PM UTC 24 |
| Peak memory | 594032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098126740 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.4098126740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.2439822474 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 7059373675 ps |
| CPU time | 266.66 seconds |
| Started | Oct 15 02:58:46 PM UTC 24 |
| Finished | Oct 15 03:03:17 PM UTC 24 |
| Peak memory | 593752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439822474 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2439822474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.2934392937 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 4767897981 ps |
| CPU time | 367.76 seconds |
| Started | Oct 15 02:59:08 PM UTC 24 |
| Finished | Oct 15 03:05:21 PM UTC 24 |
| Peak memory | 619308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934392937 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.2934392937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.199508307 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 3739626745 ps |
| CPU time | 339.06 seconds |
| Started | Oct 15 03:05:55 PM UTC 24 |
| Finished | Oct 15 03:11:39 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199508307 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.199508307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.401370608 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 13336161161 ps |
| CPU time | 551.85 seconds |
| Started | Oct 15 02:40:42 PM UTC 24 |
| Finished | Oct 15 02:50:01 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401370608 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.401370608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.437916660 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 3143582280 ps |
| CPU time | 186.4 seconds |
| Started | Oct 15 03:20:14 PM UTC 24 |
| Finished | Oct 15 03:23:23 PM UTC 24 |
| Peak memory | 619016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437916660 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.437916660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.3963597407 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 11155253730 ps |
| CPU time | 412.04 seconds |
| Started | Oct 15 03:21:26 PM UTC 24 |
| Finished | Oct 15 03:28:24 PM UTC 24 |
| Peak memory | 594020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963597407 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3963597407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.2663529854 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 22808954414 ps |
| CPU time | 748.78 seconds |
| Started | Oct 15 03:36:35 PM UTC 24 |
| Finished | Oct 15 03:49:13 PM UTC 24 |
| Peak memory | 594144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663529854 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2663529854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/33.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.2810520147 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 11562578896 ps |
| CPU time | 421.9 seconds |
| Started | Oct 15 03:41:46 PM UTC 24 |
| Finished | Oct 15 03:48:54 PM UTC 24 |
| Peak memory | 594024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810520147 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2810520147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/38.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.2427263513 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 13131884673 ps |
| CPU time | 474.38 seconds |
| Started | Oct 15 03:57:02 PM UTC 24 |
| Finished | Oct 15 04:05:03 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427263513 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.2427263513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/53.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.610477052 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 2588677483 ps |
| CPU time | 97.43 seconds |
| Started | Oct 15 04:01:55 PM UTC 24 |
| Finished | Oct 15 04:03:35 PM UTC 24 |
| Peak memory | 593732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610477052 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.610477052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/58.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1906069546 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 4473717800 ps |
| CPU time | 646.88 seconds |
| Started | Oct 15 04:50:27 PM UTC 24 |
| Finished | Oct 15 05:01:23 PM UTC 24 |
| Peak memory | 625544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1906069546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.1906069546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2403313520 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4263016416 ps |
| CPU time | 397.99 seconds |
| Started | Oct 15 05:31:05 PM UTC 24 |
| Finished | Oct 15 05:37:48 PM UTC 24 |
| Peak memory | 625236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=2403313520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_pwrmgr_lowpower_cancel.2403313520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2631940540 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 4734318388 ps |
| CPU time | 784.89 seconds |
| Started | Oct 15 05:03:31 PM UTC 24 |
| Finished | Oct 15 05:16:46 PM UTC 24 |
| Peak memory | 627520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631940540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.2631940540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.3381313723 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 4439079444 ps |
| CPU time | 547.38 seconds |
| Started | Oct 15 06:56:40 PM UTC 24 |
| Finished | Oct 15 07:05:55 PM UTC 24 |
| Peak memory | 627608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3381313723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.3381313723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.1338689358 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 3940066490 ps |
| CPU time | 471.12 seconds |
| Started | Oct 15 08:20:39 PM UTC 24 |
| Finished | Oct 15 08:28:38 PM UTC 24 |
| Peak memory | 627360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1338689358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.1338689358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.3949024433 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 6170759029 ps |
| CPU time | 411.93 seconds |
| Started | Oct 15 07:55:38 PM UTC 24 |
| Finished | Oct 15 08:02:36 PM UTC 24 |
| Peak memory | 642228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949024433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_tap_straps_rma.3949024433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.1085338609 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 5246808187 ps |
| CPU time | 234.56 seconds |
| Started | Oct 15 02:35:45 PM UTC 24 |
| Finished | Oct 15 02:39:43 PM UTC 24 |
| Peak memory | 678568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085338609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_reset.1085338609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.3040524989 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 41143602472 ps |
| CPU time | 12656.9 seconds |
| Started | Oct 15 05:11:22 PM UTC 24 |
| Finished | Oct 15 08:44:51 PM UTC 24 |
| Peak memory | 630448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3040524989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_csrng_edn_concurrency.3040524989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3295385573 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 4855291304 ps |
| CPU time | 487.15 seconds |
| Started | Oct 15 05:11:59 PM UTC 24 |
| Finished | Oct 15 05:20:13 PM UTC 24 |
| Peak memory | 627524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295385573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src _fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.3295385573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.2339833587 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 2720957780 ps |
| CPU time | 464.08 seconds |
| Started | Oct 15 05:10:02 PM UTC 24 |
| Finished | Oct 15 05:17:53 PM UTC 24 |
| Peak memory | 625360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_ device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339833587 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_boot_mode.2339833587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.2576956708 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 2581722988 ps |
| CPU time | 257.06 seconds |
| Started | Oct 15 04:49:10 PM UTC 24 |
| Finished | Oct 15 04:53:32 PM UTC 24 |
| Peak memory | 625476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2576956708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_concurrency.2576956708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_inject_scramble_seed.3876849537 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 67957306943 ps |
| CPU time | 16465.5 seconds |
| Started | Oct 15 04:50:32 PM UTC 24 |
| Finished | Oct 15 09:28:20 PM UTC 24 |
| Peak memory | 644504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=1 50_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876849537 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.3876849537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3817941680 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 2605915664 ps |
| CPU time | 225.71 seconds |
| Started | Oct 15 09:30:35 PM UTC 24 |
| Finished | Oct 15 09:34:24 PM UTC 24 |
| Peak memory | 627488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_ima ges=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3817941680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_gli tch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.3817941680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1458593946 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 24150173960 ps |
| CPU time | 7529.22 seconds |
| Started | Oct 15 05:47:09 PM UTC 24 |
| Finished | Oct 15 07:54:08 PM UTC 24 |
| Peak memory | 628100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458593946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1458593946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.1523825251 |
| Short name | T2918 |
| Test name | |
| Test status | |
| Simulation time | 64530245625 ps |
| CPU time | 10618.2 seconds |
| Started | Oct 15 02:35:31 PM UTC 24 |
| Finished | Oct 15 05:34:34 PM UTC 24 |
| Peak memory | 654828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1523825251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_ csr_aliasing.1523825251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.1648433276 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 14392453800 ps |
| CPU time | 1429.5 seconds |
| Started | Oct 15 02:35:31 PM UTC 24 |
| Finished | Oct 15 02:59:36 PM UTC 24 |
| Peak memory | 613136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1648433276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.chip_csr_bit_bash.1648433276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.2485968885 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 10918588008 ps |
| CPU time | 760.98 seconds |
| Started | Oct 15 02:35:48 PM UTC 24 |
| Finished | Oct 15 02:48:39 PM UTC 24 |
| Peak memory | 668616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2485968885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.chip_csr_mem_rw_with_rand_reset.2485968885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.1300601798 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 5081857256 ps |
| CPU time | 179.33 seconds |
| Started | Oct 15 02:35:35 PM UTC 24 |
| Finished | Oct 15 02:38:37 PM UTC 24 |
| Peak memory | 604784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300601798 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.1300601798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1420867645 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 12826377455 ps |
| CPU time | 669.03 seconds |
| Started | Oct 15 02:35:31 PM UTC 24 |
| Finished | Oct 15 02:46:49 PM UTC 24 |
| Peak memory | 604432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_c pu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1420867645 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. chip_rv_dm_lc_disabled.1420867645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.1600214059 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 33979069606 ps |
| CPU time | 3908.16 seconds |
| Started | Oct 15 02:35:32 PM UTC 24 |
| Finished | Oct 15 03:41:24 PM UTC 24 |
| Peak memory | 611968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1600214059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.chip_same_csr_outstanding.1600214059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1996709499 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 460225407 ps |
| CPU time | 20.66 seconds |
| Started | Oct 15 02:35:40 PM UTC 24 |
| Finished | Oct 15 02:36:02 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996709499 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.1996709499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.1937604364 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 246105473 ps |
| CPU time | 23.97 seconds |
| Started | Oct 15 02:35:34 PM UTC 24 |
| Finished | Oct 15 02:35:59 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937604364 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.1937604364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.3667233011 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 45854686166 ps |
| CPU time | 576.6 seconds |
| Started | Oct 15 02:35:35 PM UTC 24 |
| Finished | Oct 15 02:45:19 PM UTC 24 |
| Peak memory | 593876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667233011 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3667233011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.831781322 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 36320605370 ps |
| CPU time | 509.14 seconds |
| Started | Oct 15 02:35:36 PM UTC 24 |
| Finished | Oct 15 02:44:12 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831781322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.831781322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.144280168 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 587961240 ps |
| CPU time | 41.09 seconds |
| Started | Oct 15 02:35:38 PM UTC 24 |
| Finished | Oct 15 02:36:20 PM UTC 24 |
| Peak memory | 593904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144280168 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.144280168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.3820958803 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 4352658284 ps |
| CPU time | 41.77 seconds |
| Started | Oct 15 02:35:36 PM UTC 24 |
| Finished | Oct 15 02:36:19 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820958803 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3820958803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.214340773 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 6564972312 ps |
| CPU time | 92.14 seconds |
| Started | Oct 15 02:35:34 PM UTC 24 |
| Finished | Oct 15 02:37:08 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214340773 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.214340773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1295054350 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 46894930 ps |
| CPU time | 6.89 seconds |
| Started | Oct 15 02:35:34 PM UTC 24 |
| Finished | Oct 15 02:35:42 PM UTC 24 |
| Peak memory | 591820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295054350 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1295054350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3704600559 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 91059401 ps |
| CPU time | 32.26 seconds |
| Started | Oct 15 02:35:43 PM UTC 24 |
| Finished | Oct 15 02:36:17 PM UTC 24 |
| Peak memory | 593724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704600559 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.3704600559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.96174530 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 13436627037 ps |
| CPU time | 1154.26 seconds |
| Started | Oct 15 02:35:58 PM UTC 24 |
| Finished | Oct 15 02:55:25 PM UTC 24 |
| Peak memory | 614864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=96174530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.96174530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3527250003 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 12454951820 ps |
| CPU time | 945.38 seconds |
| Started | Oct 15 02:37:56 PM UTC 24 |
| Finished | Oct 15 02:53:54 PM UTC 24 |
| Peak memory | 662332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3527250003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.chip_csr_mem_rw_with_rand_reset.3527250003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.454435975 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 4269006573 ps |
| CPU time | 339.85 seconds |
| Started | Oct 15 02:37:48 PM UTC 24 |
| Finished | Oct 15 02:43:33 PM UTC 24 |
| Peak memory | 615060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454435975 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.454435975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.3206134075 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 4589390918 ps |
| CPU time | 129.6 seconds |
| Started | Oct 15 02:36:11 PM UTC 24 |
| Finished | Oct 15 02:38:23 PM UTC 24 |
| Peak memory | 604792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206134075 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.3206134075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_prim_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1983175253 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 20691476187 ps |
| CPU time | 958.94 seconds |
| Started | Oct 15 02:36:20 PM UTC 24 |
| Finished | Oct 15 02:52:30 PM UTC 24 |
| Peak memory | 604720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_c pu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1983175253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. chip_rv_dm_lc_disabled.1983175253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.147958393 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 14914968292 ps |
| CPU time | 2359.38 seconds |
| Started | Oct 15 02:36:05 PM UTC 24 |
| Finished | Oct 15 03:15:53 PM UTC 24 |
| Peak memory | 609108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=147958393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.chip_same_csr_outstanding.147958393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1632968768 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 907553941 ps |
| CPU time | 37.94 seconds |
| Started | Oct 15 02:37:11 PM UTC 24 |
| Finished | Oct 15 02:37:51 PM UTC 24 |
| Peak memory | 593688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632968768 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1632968768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.112429211 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 843115901 ps |
| CPU time | 35.65 seconds |
| Started | Oct 15 02:36:57 PM UTC 24 |
| Finished | Oct 15 02:37:35 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112429211 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.112429211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.1235338693 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 286035274 ps |
| CPU time | 19.23 seconds |
| Started | Oct 15 02:36:25 PM UTC 24 |
| Finished | Oct 15 02:36:45 PM UTC 24 |
| Peak memory | 594124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235338693 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.1235338693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.2503038513 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 3268653597 ps |
| CPU time | 65.72 seconds |
| Started | Oct 15 02:36:45 PM UTC 24 |
| Finished | Oct 15 02:37:52 PM UTC 24 |
| Peak memory | 591912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503038513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2503038513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.849563140 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 346158484 ps |
| CPU time | 36.26 seconds |
| Started | Oct 15 02:36:29 PM UTC 24 |
| Finished | Oct 15 02:37:07 PM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849563140 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.849563140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.2587145476 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 194504519 ps |
| CPU time | 7.8 seconds |
| Started | Oct 15 02:36:17 PM UTC 24 |
| Finished | Oct 15 02:36:26 PM UTC 24 |
| Peak memory | 591840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587145476 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2587145476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.2759213920 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 8143532255 ps |
| CPU time | 98.6 seconds |
| Started | Oct 15 02:36:26 PM UTC 24 |
| Finished | Oct 15 02:38:06 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759213920 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2759213920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1760641400 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 4792593548 ps |
| CPU time | 114.74 seconds |
| Started | Oct 15 02:36:28 PM UTC 24 |
| Finished | Oct 15 02:38:25 PM UTC 24 |
| Peak memory | 591696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760641400 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1760641400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.605005905 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 55837671 ps |
| CPU time | 8.9 seconds |
| Started | Oct 15 02:36:24 PM UTC 24 |
| Finished | Oct 15 02:36:34 PM UTC 24 |
| Peak memory | 591760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605005905 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.605005905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.2975095113 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 2025272449 ps |
| CPU time | 90.6 seconds |
| Started | Oct 15 02:37:15 PM UTC 24 |
| Finished | Oct 15 02:38:48 PM UTC 24 |
| Peak memory | 594056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975095113 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2975095113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.1063905248 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 370123124 ps |
| CPU time | 27.35 seconds |
| Started | Oct 15 02:37:00 PM UTC 24 |
| Finished | Oct 15 02:37:29 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063905248 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1063905248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.716394922 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 5701010550 ps |
| CPU time | 521.25 seconds |
| Started | Oct 15 02:58:57 PM UTC 24 |
| Finished | Oct 15 03:07:46 PM UTC 24 |
| Peak memory | 656072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=716394922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.716394922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.2126712918 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 3628211696 ps |
| CPU time | 344.15 seconds |
| Started | Oct 15 02:58:50 PM UTC 24 |
| Finished | Oct 15 03:04:39 PM UTC 24 |
| Peak memory | 615128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126712918 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.2126712918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.590535679 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 15841163272 ps |
| CPU time | 1711.29 seconds |
| Started | Oct 15 02:57:09 PM UTC 24 |
| Finished | Oct 15 03:26:01 PM UTC 24 |
| Peak memory | 608784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=590535679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 10.chip_same_csr_outstanding.590535679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.4017564249 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 401782111 ps |
| CPU time | 35.63 seconds |
| Started | Oct 15 02:57:50 PM UTC 24 |
| Finished | Oct 15 02:58:27 PM UTC 24 |
| Peak memory | 594112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017564249 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.4017564249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2367494868 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 24094111397 ps |
| CPU time | 377.39 seconds |
| Started | Oct 15 02:57:55 PM UTC 24 |
| Finished | Oct 15 03:04:17 PM UTC 24 |
| Peak memory | 594112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367494868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_dev ice_slow_rsp.2367494868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3562138454 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 915252477 ps |
| CPU time | 41.21 seconds |
| Started | Oct 15 02:58:31 PM UTC 24 |
| Finished | Oct 15 02:59:14 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562138454 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3562138454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.3457536851 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 2645806317 ps |
| CPU time | 103.8 seconds |
| Started | Oct 15 02:58:14 PM UTC 24 |
| Finished | Oct 15 03:00:00 PM UTC 24 |
| Peak memory | 593876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457536851 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3457536851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.4240891337 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 774511342 ps |
| CPU time | 40.9 seconds |
| Started | Oct 15 02:57:28 PM UTC 24 |
| Finished | Oct 15 02:58:11 PM UTC 24 |
| Peak memory | 593672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240891337 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.4240891337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.1669920869 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 43801081415 ps |
| CPU time | 432 seconds |
| Started | Oct 15 02:57:47 PM UTC 24 |
| Finished | Oct 15 03:05:04 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669920869 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1669920869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.3282095709 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 13218632765 ps |
| CPU time | 247.85 seconds |
| Started | Oct 15 02:57:49 PM UTC 24 |
| Finished | Oct 15 03:02:00 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282095709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3282095709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.3004907555 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 592724770 ps |
| CPU time | 72.07 seconds |
| Started | Oct 15 02:57:37 PM UTC 24 |
| Finished | Oct 15 02:58:51 PM UTC 24 |
| Peak memory | 593812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004907555 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3004907555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.1536244087 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 252883541 ps |
| CPU time | 23.06 seconds |
| Started | Oct 15 02:58:11 PM UTC 24 |
| Finished | Oct 15 02:58:35 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536244087 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1536244087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.3188952761 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 37221495 ps |
| CPU time | 8.13 seconds |
| Started | Oct 15 02:57:16 PM UTC 24 |
| Finished | Oct 15 02:57:25 PM UTC 24 |
| Peak memory | 591740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188952761 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3188952761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.1138510700 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 4475276551 ps |
| CPU time | 61.63 seconds |
| Started | Oct 15 02:57:23 PM UTC 24 |
| Finished | Oct 15 02:58:26 PM UTC 24 |
| Peak memory | 591684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138510700 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1138510700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.4007004014 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 6264126951 ps |
| CPU time | 121.32 seconds |
| Started | Oct 15 02:57:26 PM UTC 24 |
| Finished | Oct 15 02:59:30 PM UTC 24 |
| Peak memory | 591824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007004014 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.4007004014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2973766029 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 55322175 ps |
| CPU time | 7.53 seconds |
| Started | Oct 15 02:57:20 PM UTC 24 |
| Finished | Oct 15 02:57:29 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973766029 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2973766029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.1473014365 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 2237342671 ps |
| CPU time | 192.64 seconds |
| Started | Oct 15 02:58:36 PM UTC 24 |
| Finished | Oct 15 03:01:52 PM UTC 24 |
| Peak memory | 594016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473014365 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1473014365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2125832180 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 198916390 ps |
| CPU time | 48.81 seconds |
| Started | Oct 15 02:58:39 PM UTC 24 |
| Finished | Oct 15 02:59:30 PM UTC 24 |
| Peak memory | 593728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125832180 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.2125832180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.1613697302 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 745127398 ps |
| CPU time | 39.66 seconds |
| Started | Oct 15 02:58:21 PM UTC 24 |
| Finished | Oct 15 02:59:03 PM UTC 24 |
| Peak memory | 593824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613697302 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1613697302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.3058070470 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 8566657763 ps |
| CPU time | 783.4 seconds |
| Started | Oct 15 03:00:47 PM UTC 24 |
| Finished | Oct 15 03:14:00 PM UTC 24 |
| Peak memory | 668360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3058070470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 11.chip_csr_mem_rw_with_rand_reset.3058070470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.3882765001 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 5779993325 ps |
| CPU time | 615.89 seconds |
| Started | Oct 15 03:00:45 PM UTC 24 |
| Finished | Oct 15 03:11:09 PM UTC 24 |
| Peak memory | 617092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882765001 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.3882765001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.1098331793 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 14679927492 ps |
| CPU time | 1860.57 seconds |
| Started | Oct 15 02:58:56 PM UTC 24 |
| Finished | Oct 15 03:30:21 PM UTC 24 |
| Peak memory | 609004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1098331793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.chip_same_csr_outstanding.1098331793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.3718732176 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 1100509596 ps |
| CPU time | 50.99 seconds |
| Started | Oct 15 02:59:58 PM UTC 24 |
| Finished | Oct 15 03:00:50 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718732176 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3718732176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3698069791 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 53494571893 ps |
| CPU time | 935.29 seconds |
| Started | Oct 15 02:59:57 PM UTC 24 |
| Finished | Oct 15 03:15:43 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698069791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_dev ice_slow_rsp.3698069791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2485518472 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 814817054 ps |
| CPU time | 33.77 seconds |
| Started | Oct 15 03:00:19 PM UTC 24 |
| Finished | Oct 15 03:00:55 PM UTC 24 |
| Peak memory | 593816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485518472 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2485518472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.2083884726 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 105481426 ps |
| CPU time | 14.07 seconds |
| Started | Oct 15 03:00:03 PM UTC 24 |
| Finished | Oct 15 03:00:20 PM UTC 24 |
| Peak memory | 593824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083884726 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2083884726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.969172512 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 339844987 ps |
| CPU time | 42.44 seconds |
| Started | Oct 15 02:59:31 PM UTC 24 |
| Finished | Oct 15 03:00:15 PM UTC 24 |
| Peak memory | 594064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969172512 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.969172512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.53743191 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 25520751681 ps |
| CPU time | 231.3 seconds |
| Started | Oct 15 02:59:40 PM UTC 24 |
| Finished | Oct 15 03:03:35 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53743191 -asse rt nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.53743191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.3480960862 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 14183013279 ps |
| CPU time | 273.27 seconds |
| Started | Oct 15 02:59:50 PM UTC 24 |
| Finished | Oct 15 03:04:27 PM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480960862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3480960862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.725858902 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 218125306 ps |
| CPU time | 20.72 seconds |
| Started | Oct 15 02:59:38 PM UTC 24 |
| Finished | Oct 15 03:00:00 PM UTC 24 |
| Peak memory | 593992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725858902 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.725858902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.1739568913 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 1132194103 ps |
| CPU time | 49.24 seconds |
| Started | Oct 15 03:00:03 PM UTC 24 |
| Finished | Oct 15 03:00:55 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739568913 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1739568913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.4265274145 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 40871846 ps |
| CPU time | 8.45 seconds |
| Started | Oct 15 02:59:18 PM UTC 24 |
| Finished | Oct 15 02:59:27 PM UTC 24 |
| Peak memory | 591736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265274145 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.4265274145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.2270221344 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 7014792971 ps |
| CPU time | 85.59 seconds |
| Started | Oct 15 02:59:31 PM UTC 24 |
| Finished | Oct 15 03:00:58 PM UTC 24 |
| Peak memory | 591760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270221344 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2270221344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3893243787 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 2623931853 ps |
| CPU time | 36.84 seconds |
| Started | Oct 15 02:59:34 PM UTC 24 |
| Finished | Oct 15 03:00:12 PM UTC 24 |
| Peak memory | 591684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893243787 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3893243787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.763086505 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 43511337 ps |
| CPU time | 8.6 seconds |
| Started | Oct 15 02:59:30 PM UTC 24 |
| Finished | Oct 15 02:59:40 PM UTC 24 |
| Peak memory | 591792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763086505 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.763086505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.4040651302 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 10033806046 ps |
| CPU time | 367.09 seconds |
| Started | Oct 15 03:00:39 PM UTC 24 |
| Finished | Oct 15 03:06:52 PM UTC 24 |
| Peak memory | 594184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040651302 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.4040651302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3292614211 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 1884692233 ps |
| CPU time | 274.28 seconds |
| Started | Oct 15 03:00:36 PM UTC 24 |
| Finished | Oct 15 03:05:15 PM UTC 24 |
| Peak memory | 593984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292614211 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.3292614211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1999558532 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 66565803 ps |
| CPU time | 18.91 seconds |
| Started | Oct 15 03:00:42 PM UTC 24 |
| Finished | Oct 15 03:01:02 PM UTC 24 |
| Peak memory | 593668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999558532 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.1999558532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.1005605891 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 294027376 ps |
| CPU time | 18.67 seconds |
| Started | Oct 15 03:00:05 PM UTC 24 |
| Finished | Oct 15 03:00:25 PM UTC 24 |
| Peak memory | 593808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005605891 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1005605891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.999197778 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 5614611168 ps |
| CPU time | 465.64 seconds |
| Started | Oct 15 03:03:46 PM UTC 24 |
| Finished | Oct 15 03:11:38 PM UTC 24 |
| Peak memory | 662216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=999197778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.999197778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.2687690473 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 4447582746 ps |
| CPU time | 386.53 seconds |
| Started | Oct 15 03:03:47 PM UTC 24 |
| Finished | Oct 15 03:10:19 PM UTC 24 |
| Peak memory | 615156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687690473 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.2687690473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.2579065877 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 27188077878 ps |
| CPU time | 4078.45 seconds |
| Started | Oct 15 03:01:17 PM UTC 24 |
| Finished | Oct 15 04:10:02 PM UTC 24 |
| Peak memory | 612096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2579065877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.chip_same_csr_outstanding.2579065877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.1921903601 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 3092923750 ps |
| CPU time | 212.16 seconds |
| Started | Oct 15 03:01:22 PM UTC 24 |
| Finished | Oct 15 03:04:57 PM UTC 24 |
| Peak memory | 619244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921903601 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.1921903601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.2326247711 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1952792966 ps |
| CPU time | 91.09 seconds |
| Started | Oct 15 03:02:18 PM UTC 24 |
| Finished | Oct 15 03:03:51 PM UTC 24 |
| Peak memory | 593692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326247711 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2326247711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.185886403 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 464055961 ps |
| CPU time | 27.9 seconds |
| Started | Oct 15 03:03:41 PM UTC 24 |
| Finished | Oct 15 03:04:10 PM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185886403 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.185886403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.1738088735 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 175384453 ps |
| CPU time | 11.6 seconds |
| Started | Oct 15 03:03:07 PM UTC 24 |
| Finished | Oct 15 03:03:20 PM UTC 24 |
| Peak memory | 591632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738088735 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1738088735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.1758576076 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 1474342307 ps |
| CPU time | 76.42 seconds |
| Started | Oct 15 03:01:59 PM UTC 24 |
| Finished | Oct 15 03:03:17 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758576076 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.1758576076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.942017784 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 19897246000 ps |
| CPU time | 248.07 seconds |
| Started | Oct 15 03:02:04 PM UTC 24 |
| Finished | Oct 15 03:06:16 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942017784 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.942017784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.1131839287 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 27105639399 ps |
| CPU time | 534.02 seconds |
| Started | Oct 15 03:02:05 PM UTC 24 |
| Finished | Oct 15 03:11:06 PM UTC 24 |
| Peak memory | 594152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131839287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.1131839287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.742608945 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 436274545 ps |
| CPU time | 37.92 seconds |
| Started | Oct 15 03:02:02 PM UTC 24 |
| Finished | Oct 15 03:02:41 PM UTC 24 |
| Peak memory | 593816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742608945 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.742608945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.2617276912 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 575944225 ps |
| CPU time | 58.41 seconds |
| Started | Oct 15 03:02:44 PM UTC 24 |
| Finished | Oct 15 03:03:44 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617276912 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.2617276912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.2552806905 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 48357350 ps |
| CPU time | 9.24 seconds |
| Started | Oct 15 03:01:21 PM UTC 24 |
| Finished | Oct 15 03:01:32 PM UTC 24 |
| Peak memory | 591744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552806905 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2552806905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.2595063547 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 9157219269 ps |
| CPU time | 112.43 seconds |
| Started | Oct 15 03:01:28 PM UTC 24 |
| Finished | Oct 15 03:03:23 PM UTC 24 |
| Peak memory | 591920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595063547 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2595063547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1208164924 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 5093806491 ps |
| CPU time | 78.6 seconds |
| Started | Oct 15 03:01:29 PM UTC 24 |
| Finished | Oct 15 03:02:49 PM UTC 24 |
| Peak memory | 591944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208164924 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1208164924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.490301704 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 42832127 ps |
| CPU time | 8.53 seconds |
| Started | Oct 15 03:01:25 PM UTC 24 |
| Finished | Oct 15 03:01:35 PM UTC 24 |
| Peak memory | 591772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490301704 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.490301704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.1072926205 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 10622268389 ps |
| CPU time | 399.26 seconds |
| Started | Oct 15 03:03:42 PM UTC 24 |
| Finished | Oct 15 03:10:27 PM UTC 24 |
| Peak memory | 594052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072926205 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1072926205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.1223834731 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 248560961 ps |
| CPU time | 28.62 seconds |
| Started | Oct 15 03:03:48 PM UTC 24 |
| Finished | Oct 15 03:04:18 PM UTC 24 |
| Peak memory | 593672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223834731 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1223834731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1959181662 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 374433953 ps |
| CPU time | 226.93 seconds |
| Started | Oct 15 03:03:43 PM UTC 24 |
| Finished | Oct 15 03:07:34 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959181662 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.1959181662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1569927737 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 565351045 ps |
| CPU time | 168.76 seconds |
| Started | Oct 15 03:03:48 PM UTC 24 |
| Finished | Oct 15 03:06:39 PM UTC 24 |
| Peak memory | 593728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569927737 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.1569927737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.2429665201 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 70705074 ps |
| CPU time | 6.32 seconds |
| Started | Oct 15 03:03:16 PM UTC 24 |
| Finished | Oct 15 03:03:23 PM UTC 24 |
| Peak memory | 592076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429665201 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2429665201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.911186139 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 9076467195 ps |
| CPU time | 862.38 seconds |
| Started | Oct 15 03:06:08 PM UTC 24 |
| Finished | Oct 15 03:20:42 PM UTC 24 |
| Peak memory | 668416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=911186139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.911186139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.3682422813 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 5520035388 ps |
| CPU time | 521.9 seconds |
| Started | Oct 15 03:06:03 PM UTC 24 |
| Finished | Oct 15 03:14:52 PM UTC 24 |
| Peak memory | 614924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682422813 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.3682422813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.3743674932 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 15196755777 ps |
| CPU time | 1912.57 seconds |
| Started | Oct 15 03:03:58 PM UTC 24 |
| Finished | Oct 15 03:36:13 PM UTC 24 |
| Peak memory | 608964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3743674932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.chip_same_csr_outstanding.3743674932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2377448916 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 23380199911 ps |
| CPU time | 434.73 seconds |
| Started | Oct 15 03:05:04 PM UTC 24 |
| Finished | Oct 15 03:12:25 PM UTC 24 |
| Peak memory | 593864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377448916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_dev ice_slow_rsp.2377448916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3199977924 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 55786628 ps |
| CPU time | 12.28 seconds |
| Started | Oct 15 03:05:31 PM UTC 24 |
| Finished | Oct 15 03:05:45 PM UTC 24 |
| Peak memory | 593748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199977924 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.3199977924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.1896913099 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 1128553512 ps |
| CPU time | 43.09 seconds |
| Started | Oct 15 03:05:20 PM UTC 24 |
| Finished | Oct 15 03:06:04 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896913099 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1896913099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.2000384417 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 105486057 ps |
| CPU time | 15.97 seconds |
| Started | Oct 15 03:04:44 PM UTC 24 |
| Finished | Oct 15 03:05:01 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000384417 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.2000384417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.24463891 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 36319454974 ps |
| CPU time | 340.04 seconds |
| Started | Oct 15 03:04:50 PM UTC 24 |
| Finished | Oct 15 03:10:34 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24463891 -asse rt nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.24463891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.3675796261 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 16279501801 ps |
| CPU time | 232.1 seconds |
| Started | Oct 15 03:04:53 PM UTC 24 |
| Finished | Oct 15 03:08:49 PM UTC 24 |
| Peak memory | 593740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675796261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.3675796261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.2822136880 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 534026444 ps |
| CPU time | 53.32 seconds |
| Started | Oct 15 03:04:46 PM UTC 24 |
| Finished | Oct 15 03:05:41 PM UTC 24 |
| Peak memory | 593688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822136880 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.2822136880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.664015620 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 171685923 ps |
| CPU time | 11.63 seconds |
| Started | Oct 15 03:05:23 PM UTC 24 |
| Finished | Oct 15 03:05:36 PM UTC 24 |
| Peak memory | 591752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664015620 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.664015620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.2657891547 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 203102676 ps |
| CPU time | 13.37 seconds |
| Started | Oct 15 03:04:09 PM UTC 24 |
| Finished | Oct 15 03:04:23 PM UTC 24 |
| Peak memory | 591744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657891547 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2657891547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.3607987900 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 5564277015 ps |
| CPU time | 72.49 seconds |
| Started | Oct 15 03:04:37 PM UTC 24 |
| Finished | Oct 15 03:05:51 PM UTC 24 |
| Peak memory | 591756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607987900 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3607987900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1275882981 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 4640368191 ps |
| CPU time | 80.78 seconds |
| Started | Oct 15 03:04:43 PM UTC 24 |
| Finished | Oct 15 03:06:05 PM UTC 24 |
| Peak memory | 591824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275882981 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1275882981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3185674912 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 36275348 ps |
| CPU time | 8.73 seconds |
| Started | Oct 15 03:04:19 PM UTC 24 |
| Finished | Oct 15 03:04:29 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185674912 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.3185674912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.597515003 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 1159437737 ps |
| CPU time | 106.18 seconds |
| Started | Oct 15 03:05:42 PM UTC 24 |
| Finished | Oct 15 03:07:30 PM UTC 24 |
| Peak memory | 593732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597515003 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.597515003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.1326859303 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 4862204122 ps |
| CPU time | 217.62 seconds |
| Started | Oct 15 03:05:47 PM UTC 24 |
| Finished | Oct 15 03:09:29 PM UTC 24 |
| Peak memory | 594156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326859303 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1326859303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.2236251780 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 331497998 ps |
| CPU time | 48.98 seconds |
| Started | Oct 15 03:05:28 PM UTC 24 |
| Finished | Oct 15 03:06:19 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236251780 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2236251780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.2129997500 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 6808664170 ps |
| CPU time | 453.03 seconds |
| Started | Oct 15 03:08:35 PM UTC 24 |
| Finished | Oct 15 03:16:14 PM UTC 24 |
| Peak memory | 654152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2129997500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 14.chip_csr_mem_rw_with_rand_reset.2129997500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.505456491 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 5557795228 ps |
| CPU time | 566.34 seconds |
| Started | Oct 15 03:08:32 PM UTC 24 |
| Finished | Oct 15 03:18:06 PM UTC 24 |
| Peak memory | 617156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505456491 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.505456491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.1176035963 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 16277555067 ps |
| CPU time | 1734.64 seconds |
| Started | Oct 15 03:06:11 PM UTC 24 |
| Finished | Oct 15 03:35:27 PM UTC 24 |
| Peak memory | 609000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1176035963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.chip_same_csr_outstanding.1176035963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.2901552940 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 3167268954 ps |
| CPU time | 210.47 seconds |
| Started | Oct 15 03:06:17 PM UTC 24 |
| Finished | Oct 15 03:09:51 PM UTC 24 |
| Peak memory | 614932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901552940 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.2901552940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.3972992667 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 2065806614 ps |
| CPU time | 113.19 seconds |
| Started | Oct 15 03:07:04 PM UTC 24 |
| Finished | Oct 15 03:08:59 PM UTC 24 |
| Peak memory | 593692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972992667 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.3972992667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1112842940 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 28459294066 ps |
| CPU time | 400.04 seconds |
| Started | Oct 15 03:07:14 PM UTC 24 |
| Finished | Oct 15 03:13:59 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112842940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_dev ice_slow_rsp.1112842940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.1806612504 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 366826264 ps |
| CPU time | 25.57 seconds |
| Started | Oct 15 03:07:49 PM UTC 24 |
| Finished | Oct 15 03:08:16 PM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806612504 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.1806612504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.147724291 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 443381840 ps |
| CPU time | 48.73 seconds |
| Started | Oct 15 03:07:35 PM UTC 24 |
| Finished | Oct 15 03:08:25 PM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147724291 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.147724291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.1792031676 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 711176377 ps |
| CPU time | 36.39 seconds |
| Started | Oct 15 03:06:48 PM UTC 24 |
| Finished | Oct 15 03:07:26 PM UTC 24 |
| Peak memory | 594060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792031676 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.1792031676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.3869254133 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 14032943145 ps |
| CPU time | 130.97 seconds |
| Started | Oct 15 03:07:04 PM UTC 24 |
| Finished | Oct 15 03:09:17 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869254133 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3869254133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.1224203074 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 7107921411 ps |
| CPU time | 125.59 seconds |
| Started | Oct 15 03:07:06 PM UTC 24 |
| Finished | Oct 15 03:09:14 PM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224203074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1224203074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.683861576 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 258328856 ps |
| CPU time | 25.09 seconds |
| Started | Oct 15 03:06:43 PM UTC 24 |
| Finished | Oct 15 03:07:09 PM UTC 24 |
| Peak memory | 593824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683861576 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.683861576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.3151323335 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 1084117682 ps |
| CPU time | 36.15 seconds |
| Started | Oct 15 03:07:27 PM UTC 24 |
| Finished | Oct 15 03:08:05 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151323335 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3151323335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.3568761433 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 157682170 ps |
| CPU time | 10.58 seconds |
| Started | Oct 15 03:06:27 PM UTC 24 |
| Finished | Oct 15 03:06:38 PM UTC 24 |
| Peak memory | 591612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568761433 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3568761433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.1408063879 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 9699420480 ps |
| CPU time | 105.68 seconds |
| Started | Oct 15 03:06:40 PM UTC 24 |
| Finished | Oct 15 03:08:28 PM UTC 24 |
| Peak memory | 592132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408063879 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1408063879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.344265545 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 6163782120 ps |
| CPU time | 96.25 seconds |
| Started | Oct 15 03:06:46 PM UTC 24 |
| Finished | Oct 15 03:08:24 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344265545 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.344265545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.240339710 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 42022175 ps |
| CPU time | 7.74 seconds |
| Started | Oct 15 03:06:32 PM UTC 24 |
| Finished | Oct 15 03:06:41 PM UTC 24 |
| Peak memory | 591700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240339710 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.240339710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.3311358701 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 2233742539 ps |
| CPU time | 202.61 seconds |
| Started | Oct 15 03:07:54 PM UTC 24 |
| Finished | Oct 15 03:11:21 PM UTC 24 |
| Peak memory | 593976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311358701 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3311358701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.1475296853 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 2782313000 ps |
| CPU time | 195.54 seconds |
| Started | Oct 15 03:07:58 PM UTC 24 |
| Finished | Oct 15 03:11:17 PM UTC 24 |
| Peak memory | 594024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475296853 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1475296853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3298353582 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 1210100767 ps |
| CPU time | 311.88 seconds |
| Started | Oct 15 03:07:55 PM UTC 24 |
| Finished | Oct 15 03:13:12 PM UTC 24 |
| Peak memory | 593728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298353582 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.3298353582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3840724346 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 73488247 ps |
| CPU time | 23.07 seconds |
| Started | Oct 15 03:08:12 PM UTC 24 |
| Finished | Oct 15 03:08:37 PM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840724346 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.3840724346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.2351145391 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 116610405 ps |
| CPU time | 22.12 seconds |
| Started | Oct 15 03:07:44 PM UTC 24 |
| Finished | Oct 15 03:08:08 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351145391 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2351145391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.3671607902 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 7139011656 ps |
| CPU time | 551.12 seconds |
| Started | Oct 15 03:10:35 PM UTC 24 |
| Finished | Oct 15 03:19:53 PM UTC 24 |
| Peak memory | 657988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3671607902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 15.chip_csr_mem_rw_with_rand_reset.3671607902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.3095065219 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 4296962104 ps |
| CPU time | 273.49 seconds |
| Started | Oct 15 03:10:25 PM UTC 24 |
| Finished | Oct 15 03:15:03 PM UTC 24 |
| Peak memory | 615304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095065219 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.3095065219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.3971207508 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 15749404118 ps |
| CPU time | 1896.13 seconds |
| Started | Oct 15 03:08:42 PM UTC 24 |
| Finished | Oct 15 03:40:40 PM UTC 24 |
| Peak memory | 608784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3971207508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.chip_same_csr_outstanding.3971207508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.224558455 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 1160414685 ps |
| CPU time | 102.49 seconds |
| Started | Oct 15 03:09:26 PM UTC 24 |
| Finished | Oct 15 03:11:10 PM UTC 24 |
| Peak memory | 593944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224558455 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.224558455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.605023003 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 12258907063 ps |
| CPU time | 214.46 seconds |
| Started | Oct 15 03:09:25 PM UTC 24 |
| Finished | Oct 15 03:13:03 PM UTC 24 |
| Peak memory | 593980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605023003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_devi ce_slow_rsp.605023003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.3371907125 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 955279891 ps |
| CPU time | 47.86 seconds |
| Started | Oct 15 03:09:45 PM UTC 24 |
| Finished | Oct 15 03:10:34 PM UTC 24 |
| Peak memory | 593892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371907125 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.3371907125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.1768666195 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 1023421842 ps |
| CPU time | 40.13 seconds |
| Started | Oct 15 03:09:39 PM UTC 24 |
| Finished | Oct 15 03:10:20 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768666195 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1768666195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.1416275778 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 269996949 ps |
| CPU time | 23.59 seconds |
| Started | Oct 15 03:08:55 PM UTC 24 |
| Finished | Oct 15 03:09:20 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416275778 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.1416275778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.550123788 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 17178106509 ps |
| CPU time | 164.31 seconds |
| Started | Oct 15 03:09:15 PM UTC 24 |
| Finished | Oct 15 03:12:02 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550123788 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.550123788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.2165487949 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 22298068277 ps |
| CPU time | 319.54 seconds |
| Started | Oct 15 03:09:16 PM UTC 24 |
| Finished | Oct 15 03:14:40 PM UTC 24 |
| Peak memory | 594088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165487949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.2165487949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.2440466966 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 180847181 ps |
| CPU time | 19.73 seconds |
| Started | Oct 15 03:09:03 PM UTC 24 |
| Finished | Oct 15 03:09:23 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440466966 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.2440466966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.1626207478 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 825097666 ps |
| CPU time | 24.72 seconds |
| Started | Oct 15 03:09:38 PM UTC 24 |
| Finished | Oct 15 03:10:04 PM UTC 24 |
| Peak memory | 593660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626207478 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1626207478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.3645437194 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 52313442 ps |
| CPU time | 7.05 seconds |
| Started | Oct 15 03:08:45 PM UTC 24 |
| Finished | Oct 15 03:08:53 PM UTC 24 |
| Peak memory | 591876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645437194 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3645437194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.228557966 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 8706772068 ps |
| CPU time | 83.51 seconds |
| Started | Oct 15 03:08:52 PM UTC 24 |
| Finished | Oct 15 03:10:17 PM UTC 24 |
| Peak memory | 591684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228557966 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.228557966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2775235611 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 5313481801 ps |
| CPU time | 105.83 seconds |
| Started | Oct 15 03:08:52 PM UTC 24 |
| Finished | Oct 15 03:10:40 PM UTC 24 |
| Peak memory | 591944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775235611 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2775235611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.1993553881 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 51185474 ps |
| CPU time | 7.06 seconds |
| Started | Oct 15 03:08:50 PM UTC 24 |
| Finished | Oct 15 03:08:58 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993553881 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1993553881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.3541664037 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 5540544980 ps |
| CPU time | 197.05 seconds |
| Started | Oct 15 03:09:46 PM UTC 24 |
| Finished | Oct 15 03:13:07 PM UTC 24 |
| Peak memory | 593784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541664037 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3541664037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.2866596990 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 14483066846 ps |
| CPU time | 559.95 seconds |
| Started | Oct 15 03:09:56 PM UTC 24 |
| Finished | Oct 15 03:19:23 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866596990 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2866596990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.1611037126 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 5971238302 ps |
| CPU time | 382.04 seconds |
| Started | Oct 15 03:09:49 PM UTC 24 |
| Finished | Oct 15 03:16:17 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611037126 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.1611037126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.3321242855 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 593908976 ps |
| CPU time | 25.71 seconds |
| Started | Oct 15 03:09:40 PM UTC 24 |
| Finished | Oct 15 03:10:07 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321242855 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3321242855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.4274126040 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 5850160521 ps |
| CPU time | 515 seconds |
| Started | Oct 15 03:12:26 PM UTC 24 |
| Finished | Oct 15 03:21:08 PM UTC 24 |
| Peak memory | 658188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=4274126040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 16.chip_csr_mem_rw_with_rand_reset.4274126040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.2459106369 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 5536424064 ps |
| CPU time | 558.63 seconds |
| Started | Oct 15 03:12:15 PM UTC 24 |
| Finished | Oct 15 03:21:41 PM UTC 24 |
| Peak memory | 615184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459106369 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.2459106369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.4069654572 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 27748001421 ps |
| CPU time | 3796.29 seconds |
| Started | Oct 15 03:10:42 PM UTC 24 |
| Finished | Oct 15 04:14:44 PM UTC 24 |
| Peak memory | 612032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=4069654572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.chip_same_csr_outstanding.4069654572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.3114269556 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 3861602707 ps |
| CPU time | 187.43 seconds |
| Started | Oct 15 03:10:47 PM UTC 24 |
| Finished | Oct 15 03:13:57 PM UTC 24 |
| Peak memory | 615080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114269556 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.3114269556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.2977872360 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 2389413004 ps |
| CPU time | 113.06 seconds |
| Started | Oct 15 03:11:33 PM UTC 24 |
| Finished | Oct 15 03:13:28 PM UTC 24 |
| Peak memory | 593984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977872360 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2977872360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1094898002 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 14475292815 ps |
| CPU time | 245.32 seconds |
| Started | Oct 15 03:11:33 PM UTC 24 |
| Finished | Oct 15 03:15:42 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094898002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_dev ice_slow_rsp.1094898002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.2217761246 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 987084607 ps |
| CPU time | 35.06 seconds |
| Started | Oct 15 03:11:44 PM UTC 24 |
| Finished | Oct 15 03:12:20 PM UTC 24 |
| Peak memory | 593672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217761246 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.2217761246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.21919235 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 463071495 ps |
| CPU time | 22.27 seconds |
| Started | Oct 15 03:11:42 PM UTC 24 |
| Finished | Oct 15 03:12:06 PM UTC 24 |
| Peak memory | 593816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21919235 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.21919235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.1749868855 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 96537783 ps |
| CPU time | 18.88 seconds |
| Started | Oct 15 03:10:59 PM UTC 24 |
| Finished | Oct 15 03:11:19 PM UTC 24 |
| Peak memory | 594024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749868855 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.1749868855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.3423250566 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 48819656456 ps |
| CPU time | 456.57 seconds |
| Started | Oct 15 03:11:23 PM UTC 24 |
| Finished | Oct 15 03:19:05 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423250566 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3423250566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.1512454539 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 23824186930 ps |
| CPU time | 428.12 seconds |
| Started | Oct 15 03:11:26 PM UTC 24 |
| Finished | Oct 15 03:18:39 PM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512454539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1512454539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.2302898272 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 131147086 ps |
| CPU time | 19.38 seconds |
| Started | Oct 15 03:11:07 PM UTC 24 |
| Finished | Oct 15 03:11:28 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302898272 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.2302898272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.614336978 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 2047718073 ps |
| CPU time | 65.1 seconds |
| Started | Oct 15 03:11:36 PM UTC 24 |
| Finished | Oct 15 03:12:43 PM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614336978 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.614336978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.3281432823 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 171669713 ps |
| CPU time | 8.95 seconds |
| Started | Oct 15 03:10:46 PM UTC 24 |
| Finished | Oct 15 03:10:56 PM UTC 24 |
| Peak memory | 591692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281432823 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3281432823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.3971496638 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 9754306549 ps |
| CPU time | 139.03 seconds |
| Started | Oct 15 03:10:53 PM UTC 24 |
| Finished | Oct 15 03:13:15 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971496638 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3971496638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.4115358101 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 4605575156 ps |
| CPU time | 72.43 seconds |
| Started | Oct 15 03:11:01 PM UTC 24 |
| Finished | Oct 15 03:12:16 PM UTC 24 |
| Peak memory | 592136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115358101 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.4115358101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.2495715217 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 58186314 ps |
| CPU time | 10.65 seconds |
| Started | Oct 15 03:10:47 PM UTC 24 |
| Finished | Oct 15 03:10:59 PM UTC 24 |
| Peak memory | 591756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495715217 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2495715217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.2573457949 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2609037657 ps |
| CPU time | 284.41 seconds |
| Started | Oct 15 03:11:50 PM UTC 24 |
| Finished | Oct 15 03:16:39 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573457949 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.2573457949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.2639182894 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 7723344311 ps |
| CPU time | 329.06 seconds |
| Started | Oct 15 03:12:01 PM UTC 24 |
| Finished | Oct 15 03:17:35 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639182894 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2639182894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.2102591441 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 976020339 ps |
| CPU time | 167.69 seconds |
| Started | Oct 15 03:12:04 PM UTC 24 |
| Finished | Oct 15 03:14:54 PM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102591441 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.2102591441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.3719894796 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 324462528 ps |
| CPU time | 44.89 seconds |
| Started | Oct 15 03:11:45 PM UTC 24 |
| Finished | Oct 15 03:12:32 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719894796 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3719894796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.3026199789 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 6494460250 ps |
| CPU time | 470.97 seconds |
| Started | Oct 15 03:14:25 PM UTC 24 |
| Finished | Oct 15 03:22:23 PM UTC 24 |
| Peak memory | 658228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3026199789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 17.chip_csr_mem_rw_with_rand_reset.3026199789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.954120051 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 4171455932 ps |
| CPU time | 316.54 seconds |
| Started | Oct 15 03:14:26 PM UTC 24 |
| Finished | Oct 15 03:19:47 PM UTC 24 |
| Peak memory | 615120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954120051 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.954120051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.728425858 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 29395314408 ps |
| CPU time | 4328.93 seconds |
| Started | Oct 15 03:12:33 PM UTC 24 |
| Finished | Oct 15 04:25:33 PM UTC 24 |
| Peak memory | 611816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=728425858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 17.chip_same_csr_outstanding.728425858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.2895110137 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 3788870810 ps |
| CPU time | 306.94 seconds |
| Started | Oct 15 03:12:32 PM UTC 24 |
| Finished | Oct 15 03:17:43 PM UTC 24 |
| Peak memory | 614932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895110137 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.2895110137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.3799183598 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 1301864729 ps |
| CPU time | 93.17 seconds |
| Started | Oct 15 03:13:27 PM UTC 24 |
| Finished | Oct 15 03:15:02 PM UTC 24 |
| Peak memory | 593700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799183598 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.3799183598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.953828357 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 50232632716 ps |
| CPU time | 846.96 seconds |
| Started | Oct 15 03:13:31 PM UTC 24 |
| Finished | Oct 15 03:27:49 PM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953828357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_devi ce_slow_rsp.953828357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2600995808 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 265903717 ps |
| CPU time | 34.94 seconds |
| Started | Oct 15 03:13:54 PM UTC 24 |
| Finished | Oct 15 03:14:30 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600995808 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.2600995808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.3694295970 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 292736353 ps |
| CPU time | 26.32 seconds |
| Started | Oct 15 03:13:39 PM UTC 24 |
| Finished | Oct 15 03:14:06 PM UTC 24 |
| Peak memory | 593808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694295970 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3694295970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.2800003126 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 1523571248 ps |
| CPU time | 68.86 seconds |
| Started | Oct 15 03:13:07 PM UTC 24 |
| Finished | Oct 15 03:14:17 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800003126 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.2800003126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.1920517792 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 5033849621 ps |
| CPU time | 52.55 seconds |
| Started | Oct 15 03:13:18 PM UTC 24 |
| Finished | Oct 15 03:14:12 PM UTC 24 |
| Peak memory | 591696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920517792 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.1920517792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.901373216 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 22448870955 ps |
| CPU time | 363.03 seconds |
| Started | Oct 15 03:13:21 PM UTC 24 |
| Finished | Oct 15 03:19:29 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901373216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.901373216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.3207935950 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 607809218 ps |
| CPU time | 56.24 seconds |
| Started | Oct 15 03:13:17 PM UTC 24 |
| Finished | Oct 15 03:14:15 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207935950 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3207935950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.808220022 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 895843941 ps |
| CPU time | 23.69 seconds |
| Started | Oct 15 03:13:24 PM UTC 24 |
| Finished | Oct 15 03:13:49 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808220022 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.808220022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.3046839604 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 188139007 ps |
| CPU time | 8.75 seconds |
| Started | Oct 15 03:12:42 PM UTC 24 |
| Finished | Oct 15 03:12:52 PM UTC 24 |
| Peak memory | 591608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046839604 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3046839604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.415081461 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 6675418146 ps |
| CPU time | 88.15 seconds |
| Started | Oct 15 03:12:51 PM UTC 24 |
| Finished | Oct 15 03:14:21 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415081461 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.415081461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.2381548448 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 5368339546 ps |
| CPU time | 79.94 seconds |
| Started | Oct 15 03:12:58 PM UTC 24 |
| Finished | Oct 15 03:14:20 PM UTC 24 |
| Peak memory | 591684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381548448 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2381548448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.3255546880 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 50761175 ps |
| CPU time | 6.14 seconds |
| Started | Oct 15 03:12:46 PM UTC 24 |
| Finished | Oct 15 03:12:53 PM UTC 24 |
| Peak memory | 591616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255546880 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3255546880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.866184671 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 1882445635 ps |
| CPU time | 204.72 seconds |
| Started | Oct 15 03:14:24 PM UTC 24 |
| Finished | Oct 15 03:17:53 PM UTC 24 |
| Peak memory | 594116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866184671 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.866184671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.1976505793 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 9071977844 ps |
| CPU time | 374.12 seconds |
| Started | Oct 15 03:14:14 PM UTC 24 |
| Finished | Oct 15 03:20:33 PM UTC 24 |
| Peak memory | 594028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976505793 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.1976505793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.2363953689 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 4799673639 ps |
| CPU time | 292.94 seconds |
| Started | Oct 15 03:14:24 PM UTC 24 |
| Finished | Oct 15 03:19:22 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363953689 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.2363953689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.548011207 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 103461399 ps |
| CPU time | 15.51 seconds |
| Started | Oct 15 03:13:42 PM UTC 24 |
| Finished | Oct 15 03:13:58 PM UTC 24 |
| Peak memory | 593676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548011207 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.548011207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.3852389740 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 5756135628 ps |
| CPU time | 479.19 seconds |
| Started | Oct 15 03:16:15 PM UTC 24 |
| Finished | Oct 15 03:24:21 PM UTC 24 |
| Peak memory | 652036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3852389740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 18.chip_csr_mem_rw_with_rand_reset.3852389740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.333487202 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 4618232863 ps |
| CPU time | 364.47 seconds |
| Started | Oct 15 03:16:10 PM UTC 24 |
| Finished | Oct 15 03:22:20 PM UTC 24 |
| Peak memory | 615244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333487202 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.333487202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.3377722798 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 16663112620 ps |
| CPU time | 1833.36 seconds |
| Started | Oct 15 03:14:31 PM UTC 24 |
| Finished | Oct 15 03:45:25 PM UTC 24 |
| Peak memory | 609064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3377722798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.chip_same_csr_outstanding.3377722798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.598729985 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 3824621413 ps |
| CPU time | 295.96 seconds |
| Started | Oct 15 03:14:38 PM UTC 24 |
| Finished | Oct 15 03:19:39 PM UTC 24 |
| Peak memory | 614924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598729985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.598729985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.207886458 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 707429258 ps |
| CPU time | 27.1 seconds |
| Started | Oct 15 03:15:20 PM UTC 24 |
| Finished | Oct 15 03:15:48 PM UTC 24 |
| Peak memory | 594048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207886458 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.207886458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2318640518 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 176435930 ps |
| CPU time | 28.01 seconds |
| Started | Oct 15 03:15:40 PM UTC 24 |
| Finished | Oct 15 03:16:09 PM UTC 24 |
| Peak memory | 593676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318640518 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.2318640518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.1999022632 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 86916046 ps |
| CPU time | 15.1 seconds |
| Started | Oct 15 03:15:29 PM UTC 24 |
| Finished | Oct 15 03:15:45 PM UTC 24 |
| Peak memory | 593672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999022632 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1999022632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.2249142136 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 280390036 ps |
| CPU time | 26.52 seconds |
| Started | Oct 15 03:14:57 PM UTC 24 |
| Finished | Oct 15 03:15:24 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249142136 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.2249142136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.2843459967 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 27088921177 ps |
| CPU time | 387.1 seconds |
| Started | Oct 15 03:15:17 PM UTC 24 |
| Finished | Oct 15 03:21:49 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843459967 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2843459967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.165741445 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 19207671612 ps |
| CPU time | 267.34 seconds |
| Started | Oct 15 03:15:17 PM UTC 24 |
| Finished | Oct 15 03:19:48 PM UTC 24 |
| Peak memory | 593740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165741445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.165741445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.671379885 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 183888951 ps |
| CPU time | 24.96 seconds |
| Started | Oct 15 03:15:07 PM UTC 24 |
| Finished | Oct 15 03:15:33 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671379885 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.671379885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.4166948735 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 2041868208 ps |
| CPU time | 54.17 seconds |
| Started | Oct 15 03:15:21 PM UTC 24 |
| Finished | Oct 15 03:16:17 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166948735 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.4166948735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.565912474 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 44150602 ps |
| CPU time | 9.11 seconds |
| Started | Oct 15 03:14:41 PM UTC 24 |
| Finished | Oct 15 03:14:51 PM UTC 24 |
| Peak memory | 591608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565912474 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.565912474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.2579292654 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 8577754856 ps |
| CPU time | 93.76 seconds |
| Started | Oct 15 03:14:46 PM UTC 24 |
| Finished | Oct 15 03:16:22 PM UTC 24 |
| Peak memory | 592068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579292654 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2579292654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.1333703727 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 6425939681 ps |
| CPU time | 108.59 seconds |
| Started | Oct 15 03:14:48 PM UTC 24 |
| Finished | Oct 15 03:16:39 PM UTC 24 |
| Peak memory | 591824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333703727 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1333703727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1555541524 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 47473200 ps |
| CPU time | 9.36 seconds |
| Started | Oct 15 03:14:44 PM UTC 24 |
| Finished | Oct 15 03:14:54 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555541524 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1555541524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.4092503568 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 4693016956 ps |
| CPU time | 207.96 seconds |
| Started | Oct 15 03:15:51 PM UTC 24 |
| Finished | Oct 15 03:19:22 PM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092503568 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.4092503568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.266247514 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 596466990 ps |
| CPU time | 192.93 seconds |
| Started | Oct 15 03:16:01 PM UTC 24 |
| Finished | Oct 15 03:19:18 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266247514 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.266247514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.3757664711 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 5328173229 ps |
| CPU time | 364.55 seconds |
| Started | Oct 15 03:16:09 PM UTC 24 |
| Finished | Oct 15 03:22:20 PM UTC 24 |
| Peak memory | 594008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757664711 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.3757664711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.1206229008 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 150027973 ps |
| CPU time | 26.06 seconds |
| Started | Oct 15 03:15:30 PM UTC 24 |
| Finished | Oct 15 03:15:58 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206229008 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1206229008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.2526853413 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 5999851244 ps |
| CPU time | 423.83 seconds |
| Started | Oct 15 03:18:52 PM UTC 24 |
| Finished | Oct 15 03:26:02 PM UTC 24 |
| Peak memory | 657988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2526853413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 19.chip_csr_mem_rw_with_rand_reset.2526853413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.2887223096 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 6140552144 ps |
| CPU time | 684.74 seconds |
| Started | Oct 15 03:18:47 PM UTC 24 |
| Finished | Oct 15 03:30:21 PM UTC 24 |
| Peak memory | 617292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887223096 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.2887223096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.2714577357 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 31825138652 ps |
| CPU time | 3576.98 seconds |
| Started | Oct 15 03:16:19 PM UTC 24 |
| Finished | Oct 15 04:16:37 PM UTC 24 |
| Peak memory | 611816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2714577357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.chip_same_csr_outstanding.2714577357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.4198028274 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 3734286258 ps |
| CPU time | 275.91 seconds |
| Started | Oct 15 03:16:24 PM UTC 24 |
| Finished | Oct 15 03:21:04 PM UTC 24 |
| Peak memory | 619028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198028274 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.4198028274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.148040680 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 2434137104 ps |
| CPU time | 130.97 seconds |
| Started | Oct 15 03:17:17 PM UTC 24 |
| Finished | Oct 15 03:19:30 PM UTC 24 |
| Peak memory | 593892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148040680 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.148040680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2154220635 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 23819757835 ps |
| CPU time | 381.08 seconds |
| Started | Oct 15 03:17:48 PM UTC 24 |
| Finished | Oct 15 03:24:14 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154220635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_dev ice_slow_rsp.2154220635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.1512300392 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 49733429 ps |
| CPU time | 9.74 seconds |
| Started | Oct 15 03:18:10 PM UTC 24 |
| Finished | Oct 15 03:18:21 PM UTC 24 |
| Peak memory | 593676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512300392 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.1512300392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.1182159813 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 557615246 ps |
| CPU time | 56.29 seconds |
| Started | Oct 15 03:18:01 PM UTC 24 |
| Finished | Oct 15 03:19:00 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182159813 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1182159813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.3115200121 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 401920598 ps |
| CPU time | 48.93 seconds |
| Started | Oct 15 03:16:49 PM UTC 24 |
| Finished | Oct 15 03:17:40 PM UTC 24 |
| Peak memory | 594024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115200121 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.3115200121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.3089890128 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 22304755266 ps |
| CPU time | 222.81 seconds |
| Started | Oct 15 03:17:06 PM UTC 24 |
| Finished | Oct 15 03:20:52 PM UTC 24 |
| Peak memory | 594092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089890128 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3089890128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.2911423253 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 20797192701 ps |
| CPU time | 322.53 seconds |
| Started | Oct 15 03:17:16 PM UTC 24 |
| Finished | Oct 15 03:22:43 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911423253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2911423253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.3493187579 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 86136103 ps |
| CPU time | 15.85 seconds |
| Started | Oct 15 03:17:06 PM UTC 24 |
| Finished | Oct 15 03:17:23 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493187579 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.3493187579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.3090774535 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 302932515 ps |
| CPU time | 32.39 seconds |
| Started | Oct 15 03:18:02 PM UTC 24 |
| Finished | Oct 15 03:18:36 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090774535 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3090774535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.2467963710 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 173755317 ps |
| CPU time | 12.1 seconds |
| Started | Oct 15 03:16:37 PM UTC 24 |
| Finished | Oct 15 03:16:50 PM UTC 24 |
| Peak memory | 591604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467963710 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2467963710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.1030010639 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 7896065494 ps |
| CPU time | 125.46 seconds |
| Started | Oct 15 03:16:44 PM UTC 24 |
| Finished | Oct 15 03:18:52 PM UTC 24 |
| Peak memory | 592068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030010639 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1030010639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2673437810 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 6596696107 ps |
| CPU time | 91.82 seconds |
| Started | Oct 15 03:16:43 PM UTC 24 |
| Finished | Oct 15 03:18:17 PM UTC 24 |
| Peak memory | 591824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673437810 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2673437810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.3423833159 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 53988395 ps |
| CPU time | 9.34 seconds |
| Started | Oct 15 03:16:40 PM UTC 24 |
| Finished | Oct 15 03:16:50 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423833159 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3423833159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.932851876 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 4391939450 ps |
| CPU time | 233.84 seconds |
| Started | Oct 15 03:18:19 PM UTC 24 |
| Finished | Oct 15 03:22:17 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932851876 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.932851876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.3347566238 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 234616248 ps |
| CPU time | 27.81 seconds |
| Started | Oct 15 03:18:31 PM UTC 24 |
| Finished | Oct 15 03:19:01 PM UTC 24 |
| Peak memory | 593824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347566238 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3347566238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.144711670 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 181774617 ps |
| CPU time | 124.52 seconds |
| Started | Oct 15 03:18:21 PM UTC 24 |
| Finished | Oct 15 03:20:28 PM UTC 24 |
| Peak memory | 593944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144711670 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.144711670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.1691030373 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 259360395 ps |
| CPU time | 85.89 seconds |
| Started | Oct 15 03:18:44 PM UTC 24 |
| Finished | Oct 15 03:20:12 PM UTC 24 |
| Peak memory | 593728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691030373 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.1691030373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.2459034561 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 1166416026 ps |
| CPU time | 70.42 seconds |
| Started | Oct 15 03:18:06 PM UTC 24 |
| Finished | Oct 15 03:19:18 PM UTC 24 |
| Peak memory | 594048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459034561 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2459034561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_aliasing.4280350965 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 34912443576 ps |
| CPU time | 5737.2 seconds |
| Started | Oct 15 02:38:12 PM UTC 24 |
| Finished | Oct 15 04:14:55 PM UTC 24 |
| Peak memory | 616068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4280350965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_ csr_aliasing.4280350965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.2813843011 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 31300760939 ps |
| CPU time | 3322.11 seconds |
| Started | Oct 15 02:38:02 PM UTC 24 |
| Finished | Oct 15 03:34:04 PM UTC 24 |
| Peak memory | 615008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2813843011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.chip_csr_bit_bash.2813843011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.3226680087 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 6534532812 ps |
| CPU time | 522.09 seconds |
| Started | Oct 15 02:41:09 PM UTC 24 |
| Finished | Oct 15 02:49:59 PM UTC 24 |
| Peak memory | 654148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3226680087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.chip_csr_mem_rw_with_rand_reset.3226680087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.4206679641 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 6011972136 ps |
| CPU time | 247.82 seconds |
| Started | Oct 15 02:38:23 PM UTC 24 |
| Finished | Oct 15 02:42:35 PM UTC 24 |
| Peak memory | 604556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206679641 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.4206679641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_prim_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.1144241178 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 19061772721 ps |
| CPU time | 598.65 seconds |
| Started | Oct 15 02:38:33 PM UTC 24 |
| Finished | Oct 15 02:48:39 PM UTC 24 |
| Peak memory | 604424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_c pu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1144241178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. chip_rv_dm_lc_disabled.1144241178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.1175948277 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 14775355353 ps |
| CPU time | 1833.6 seconds |
| Started | Oct 15 02:38:16 PM UTC 24 |
| Finished | Oct 15 03:09:11 PM UTC 24 |
| Peak memory | 608788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1175948277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.chip_same_csr_outstanding.1175948277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.4285018930 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 4965945540 ps |
| CPU time | 547.95 seconds |
| Started | Oct 15 02:38:16 PM UTC 24 |
| Finished | Oct 15 02:47:31 PM UTC 24 |
| Peak memory | 619144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285018930 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.4285018930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.2492898320 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 266857780 ps |
| CPU time | 17.86 seconds |
| Started | Oct 15 02:39:25 PM UTC 24 |
| Finished | Oct 15 02:39:44 PM UTC 24 |
| Peak memory | 591632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492898320 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2492898320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.3281541039 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 147043130 ps |
| CPU time | 24.46 seconds |
| Started | Oct 15 02:40:30 PM UTC 24 |
| Finished | Oct 15 02:40:56 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281541039 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3281541039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.3050251005 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 556560754 ps |
| CPU time | 43.2 seconds |
| Started | Oct 15 02:40:10 PM UTC 24 |
| Finished | Oct 15 02:40:54 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050251005 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3050251005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.332674546 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 1550015705 ps |
| CPU time | 63.35 seconds |
| Started | Oct 15 02:39:04 PM UTC 24 |
| Finished | Oct 15 02:40:09 PM UTC 24 |
| Peak memory | 593676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332674546 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.332674546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.3023167311 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 5698980684 ps |
| CPU time | 76.17 seconds |
| Started | Oct 15 02:39:27 PM UTC 24 |
| Finished | Oct 15 02:40:45 PM UTC 24 |
| Peak memory | 591828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023167311 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3023167311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.2942080484 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 21210621814 ps |
| CPU time | 403.94 seconds |
| Started | Oct 15 02:39:25 PM UTC 24 |
| Finished | Oct 15 02:46:14 PM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942080484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2942080484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.876951803 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 408305682 ps |
| CPU time | 50.23 seconds |
| Started | Oct 15 02:39:12 PM UTC 24 |
| Finished | Oct 15 02:40:04 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876951803 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.876951803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.2882889184 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 74607680 ps |
| CPU time | 10.83 seconds |
| Started | Oct 15 02:40:10 PM UTC 24 |
| Finished | Oct 15 02:40:22 PM UTC 24 |
| Peak memory | 593812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882889184 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2882889184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.526007793 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 50428942 ps |
| CPU time | 9.38 seconds |
| Started | Oct 15 02:38:49 PM UTC 24 |
| Finished | Oct 15 02:39:00 PM UTC 24 |
| Peak memory | 591608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526007793 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.526007793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.3370923679 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 8925552191 ps |
| CPU time | 86.65 seconds |
| Started | Oct 15 02:38:52 PM UTC 24 |
| Finished | Oct 15 02:40:20 PM UTC 24 |
| Peak memory | 591800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370923679 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3370923679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.2330656185 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 4170531030 ps |
| CPU time | 58.29 seconds |
| Started | Oct 15 02:39:05 PM UTC 24 |
| Finished | Oct 15 02:40:04 PM UTC 24 |
| Peak memory | 591916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330656185 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2330656185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.1276965142 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 39609665 ps |
| CPU time | 9.39 seconds |
| Started | Oct 15 02:38:51 PM UTC 24 |
| Finished | Oct 15 02:39:01 PM UTC 24 |
| Peak memory | 591692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276965142 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.1276965142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.2347353174 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 9349337320 ps |
| CPU time | 358.67 seconds |
| Started | Oct 15 02:40:32 PM UTC 24 |
| Finished | Oct 15 02:46:36 PM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347353174 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2347353174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.2283195393 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 57578577 ps |
| CPU time | 30.17 seconds |
| Started | Oct 15 02:40:33 PM UTC 24 |
| Finished | Oct 15 02:41:04 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283195393 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.2283195393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.1709693008 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 8068861382 ps |
| CPU time | 319.49 seconds |
| Started | Oct 15 02:40:46 PM UTC 24 |
| Finished | Oct 15 02:46:10 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709693008 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.1709693008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.1127888717 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 924964023 ps |
| CPU time | 51.85 seconds |
| Started | Oct 15 02:40:15 PM UTC 24 |
| Finished | Oct 15 02:41:08 PM UTC 24 |
| Peak memory | 593808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127888717 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1127888717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.1507688988 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 5046639226 ps |
| CPU time | 351.29 seconds |
| Started | Oct 15 03:19:02 PM UTC 24 |
| Finished | Oct 15 03:24:58 PM UTC 24 |
| Peak memory | 614928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507688988 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.1507688988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.2041661914 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 360141170 ps |
| CPU time | 20.25 seconds |
| Started | Oct 15 03:19:49 PM UTC 24 |
| Finished | Oct 15 03:20:10 PM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041661914 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.2041661914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.3188732904 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 13846426398 ps |
| CPU time | 220.46 seconds |
| Started | Oct 15 03:19:49 PM UTC 24 |
| Finished | Oct 15 03:23:33 PM UTC 24 |
| Peak memory | 593616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188732904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_dev ice_slow_rsp.3188732904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.2276872110 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 802463785 ps |
| CPU time | 32.54 seconds |
| Started | Oct 15 03:19:53 PM UTC 24 |
| Finished | Oct 15 03:20:27 PM UTC 24 |
| Peak memory | 593900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276872110 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.2276872110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.3273032558 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 614741495 ps |
| CPU time | 66.21 seconds |
| Started | Oct 15 03:19:53 PM UTC 24 |
| Finished | Oct 15 03:21:01 PM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273032558 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3273032558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.4169089918 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 253720514 ps |
| CPU time | 11.72 seconds |
| Started | Oct 15 03:19:33 PM UTC 24 |
| Finished | Oct 15 03:19:46 PM UTC 24 |
| Peak memory | 591624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169089918 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.4169089918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.1805407157 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 11979663325 ps |
| CPU time | 103.5 seconds |
| Started | Oct 15 03:19:45 PM UTC 24 |
| Finished | Oct 15 03:21:31 PM UTC 24 |
| Peak memory | 594084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805407157 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1805407157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.3887162803 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 24547445880 ps |
| CPU time | 337.98 seconds |
| Started | Oct 15 03:19:44 PM UTC 24 |
| Finished | Oct 15 03:25:27 PM UTC 24 |
| Peak memory | 593888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887162803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3887162803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.4233879018 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 520329683 ps |
| CPU time | 57.03 seconds |
| Started | Oct 15 03:19:45 PM UTC 24 |
| Finished | Oct 15 03:20:43 PM UTC 24 |
| Peak memory | 593812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233879018 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.4233879018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.2591290606 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 1035578247 ps |
| CPU time | 40.21 seconds |
| Started | Oct 15 03:19:50 PM UTC 24 |
| Finished | Oct 15 03:20:32 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591290606 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2591290606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.1896160133 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 234220935 ps |
| CPU time | 13.22 seconds |
| Started | Oct 15 03:19:06 PM UTC 24 |
| Finished | Oct 15 03:19:20 PM UTC 24 |
| Peak memory | 591912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896160133 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1896160133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.2924677903 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 8825806449 ps |
| CPU time | 96.74 seconds |
| Started | Oct 15 03:19:26 PM UTC 24 |
| Finished | Oct 15 03:21:05 PM UTC 24 |
| Peak memory | 591760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924677903 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2924677903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.1695201862 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 3331345797 ps |
| CPU time | 46.43 seconds |
| Started | Oct 15 03:19:27 PM UTC 24 |
| Finished | Oct 15 03:20:15 PM UTC 24 |
| Peak memory | 591832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695201862 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1695201862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.3037900781 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 54411021 ps |
| CPU time | 9.97 seconds |
| Started | Oct 15 03:19:20 PM UTC 24 |
| Finished | Oct 15 03:19:31 PM UTC 24 |
| Peak memory | 591872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037900781 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3037900781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.4277988676 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 5048305416 ps |
| CPU time | 174.88 seconds |
| Started | Oct 15 03:20:02 PM UTC 24 |
| Finished | Oct 15 03:22:59 PM UTC 24 |
| Peak memory | 593976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277988676 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.4277988676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.582635147 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 263012618 ps |
| CPU time | 36.02 seconds |
| Started | Oct 15 03:20:05 PM UTC 24 |
| Finished | Oct 15 03:20:42 PM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582635147 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.582635147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.1567159321 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 311867447 ps |
| CPU time | 86.6 seconds |
| Started | Oct 15 03:20:05 PM UTC 24 |
| Finished | Oct 15 03:21:34 PM UTC 24 |
| Peak memory | 593720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567159321 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.1567159321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.1331203121 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 2135203892 ps |
| CPU time | 214.83 seconds |
| Started | Oct 15 03:20:07 PM UTC 24 |
| Finished | Oct 15 03:23:45 PM UTC 24 |
| Peak memory | 593732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331203121 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.1331203121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.3784665427 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 1175147695 ps |
| CPU time | 58.83 seconds |
| Started | Oct 15 03:19:56 PM UTC 24 |
| Finished | Oct 15 03:20:56 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784665427 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3784665427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/20.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.649725305 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 337964736 ps |
| CPU time | 22.11 seconds |
| Started | Oct 15 03:20:53 PM UTC 24 |
| Finished | Oct 15 03:21:17 PM UTC 24 |
| Peak memory | 593816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649725305 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.649725305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.441226921 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 1310707414 ps |
| CPU time | 52.42 seconds |
| Started | Oct 15 03:21:10 PM UTC 24 |
| Finished | Oct 15 03:22:04 PM UTC 24 |
| Peak memory | 593772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441226921 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.441226921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.3461774019 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 1579097758 ps |
| CPU time | 54.68 seconds |
| Started | Oct 15 03:21:07 PM UTC 24 |
| Finished | Oct 15 03:22:03 PM UTC 24 |
| Peak memory | 594024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461774019 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3461774019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.2275455212 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 1000903945 ps |
| CPU time | 48.54 seconds |
| Started | Oct 15 03:20:40 PM UTC 24 |
| Finished | Oct 15 03:21:30 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275455212 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.2275455212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.207428714 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 57417753797 ps |
| CPU time | 498.57 seconds |
| Started | Oct 15 03:20:52 PM UTC 24 |
| Finished | Oct 15 03:29:17 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207428714 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.207428714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.621796116 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 24738705654 ps |
| CPU time | 428.32 seconds |
| Started | Oct 15 03:20:53 PM UTC 24 |
| Finished | Oct 15 03:28:07 PM UTC 24 |
| Peak memory | 593984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621796116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.621796116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.2398141280 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 515426712 ps |
| CPU time | 46.37 seconds |
| Started | Oct 15 03:20:50 PM UTC 24 |
| Finished | Oct 15 03:21:38 PM UTC 24 |
| Peak memory | 593688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398141280 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.2398141280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.3262234308 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 276283445 ps |
| CPU time | 24.69 seconds |
| Started | Oct 15 03:20:59 PM UTC 24 |
| Finished | Oct 15 03:21:25 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262234308 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3262234308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.3754405688 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 145491799 ps |
| CPU time | 11.22 seconds |
| Started | Oct 15 03:20:14 PM UTC 24 |
| Finished | Oct 15 03:20:26 PM UTC 24 |
| Peak memory | 591948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754405688 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.3754405688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.2818852378 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 7541813080 ps |
| CPU time | 72.41 seconds |
| Started | Oct 15 03:20:37 PM UTC 24 |
| Finished | Oct 15 03:21:51 PM UTC 24 |
| Peak memory | 591816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818852378 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2818852378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.3019096891 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 3482846955 ps |
| CPU time | 55.28 seconds |
| Started | Oct 15 03:20:34 PM UTC 24 |
| Finished | Oct 15 03:21:31 PM UTC 24 |
| Peak memory | 591888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019096891 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3019096891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.1175495321 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 54165175 ps |
| CPU time | 6.54 seconds |
| Started | Oct 15 03:20:16 PM UTC 24 |
| Finished | Oct 15 03:20:23 PM UTC 24 |
| Peak memory | 591876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175495321 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.1175495321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.1213321808 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 3631144980 ps |
| CPU time | 313.53 seconds |
| Started | Oct 15 03:21:19 PM UTC 24 |
| Finished | Oct 15 03:26:38 PM UTC 24 |
| Peak memory | 594168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213321808 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1213321808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.1774854627 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 1674883239 ps |
| CPU time | 176 seconds |
| Started | Oct 15 03:21:23 PM UTC 24 |
| Finished | Oct 15 03:24:22 PM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774854627 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.1774854627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.3106042153 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 119134521 ps |
| CPU time | 36.79 seconds |
| Started | Oct 15 03:21:26 PM UTC 24 |
| Finished | Oct 15 03:22:04 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106042153 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.3106042153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.3237596572 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 331718626 ps |
| CPU time | 38.8 seconds |
| Started | Oct 15 03:21:10 PM UTC 24 |
| Finished | Oct 15 03:21:50 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237596572 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3237596572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/21.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.2403122577 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 3063527241 ps |
| CPU time | 96.27 seconds |
| Started | Oct 15 03:21:32 PM UTC 24 |
| Finished | Oct 15 03:23:10 PM UTC 24 |
| Peak memory | 615068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403122577 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.2403122577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.2964069375 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 1407789501 ps |
| CPU time | 69.25 seconds |
| Started | Oct 15 03:22:04 PM UTC 24 |
| Finished | Oct 15 03:23:15 PM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964069375 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.2964069375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.38648798 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 35860802404 ps |
| CPU time | 486.97 seconds |
| Started | Oct 15 03:22:05 PM UTC 24 |
| Finished | Oct 15 03:30:18 PM UTC 24 |
| Peak memory | 593748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38648798 -assert n opostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_devic e_slow_rsp.38648798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1670405863 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 1057447461 ps |
| CPU time | 51.19 seconds |
| Started | Oct 15 03:22:15 PM UTC 24 |
| Finished | Oct 15 03:23:08 PM UTC 24 |
| Peak memory | 594016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670405863 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.1670405863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.266042148 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 159683375 ps |
| CPU time | 14.16 seconds |
| Started | Oct 15 03:22:13 PM UTC 24 |
| Finished | Oct 15 03:22:28 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266042148 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.266042148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.1950945754 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 1598102958 ps |
| CPU time | 56.25 seconds |
| Started | Oct 15 03:21:54 PM UTC 24 |
| Finished | Oct 15 03:22:52 PM UTC 24 |
| Peak memory | 594064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950945754 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.1950945754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.1989040642 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 53351539569 ps |
| CPU time | 569.37 seconds |
| Started | Oct 15 03:22:00 PM UTC 24 |
| Finished | Oct 15 03:31:36 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989040642 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1989040642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.1909400160 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 24945211387 ps |
| CPU time | 403.9 seconds |
| Started | Oct 15 03:22:01 PM UTC 24 |
| Finished | Oct 15 03:28:51 PM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909400160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1909400160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.1114766870 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 149772667 ps |
| CPU time | 21.2 seconds |
| Started | Oct 15 03:21:56 PM UTC 24 |
| Finished | Oct 15 03:22:19 PM UTC 24 |
| Peak memory | 593676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114766870 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.1114766870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.1945775385 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 942370052 ps |
| CPU time | 29.4 seconds |
| Started | Oct 15 03:22:09 PM UTC 24 |
| Finished | Oct 15 03:22:40 PM UTC 24 |
| Peak memory | 593808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945775385 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1945775385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.577318555 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 48678798 ps |
| CPU time | 9.54 seconds |
| Started | Oct 15 03:21:34 PM UTC 24 |
| Finished | Oct 15 03:21:45 PM UTC 24 |
| Peak memory | 591844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577318555 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.577318555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.341228197 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 10345439584 ps |
| CPU time | 106.4 seconds |
| Started | Oct 15 03:21:50 PM UTC 24 |
| Finished | Oct 15 03:23:38 PM UTC 24 |
| Peak memory | 591940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341228197 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.341228197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.664611953 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 5670092651 ps |
| CPU time | 92.21 seconds |
| Started | Oct 15 03:21:54 PM UTC 24 |
| Finished | Oct 15 03:23:29 PM UTC 24 |
| Peak memory | 591756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664611953 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.664611953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.1876053864 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 45195208 ps |
| CPU time | 9.17 seconds |
| Started | Oct 15 03:21:43 PM UTC 24 |
| Finished | Oct 15 03:21:54 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876053864 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1876053864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.473382257 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 1604667607 ps |
| CPU time | 136.02 seconds |
| Started | Oct 15 03:22:21 PM UTC 24 |
| Finished | Oct 15 03:24:40 PM UTC 24 |
| Peak memory | 593864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473382257 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.473382257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.1094757506 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 658498691 ps |
| CPU time | 216.76 seconds |
| Started | Oct 15 03:22:17 PM UTC 24 |
| Finished | Oct 15 03:25:57 PM UTC 24 |
| Peak memory | 593984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094757506 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.1094757506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.982181314 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 66401852 ps |
| CPU time | 31.13 seconds |
| Started | Oct 15 03:22:25 PM UTC 24 |
| Finished | Oct 15 03:22:58 PM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982181314 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.982181314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.3163688082 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 77769906 ps |
| CPU time | 9.64 seconds |
| Started | Oct 15 03:22:16 PM UTC 24 |
| Finished | Oct 15 03:22:27 PM UTC 24 |
| Peak memory | 592036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163688082 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3163688082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/22.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.3329584504 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 3519129412 ps |
| CPU time | 197.55 seconds |
| Started | Oct 15 03:22:25 PM UTC 24 |
| Finished | Oct 15 03:25:45 PM UTC 24 |
| Peak memory | 619272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329584504 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.3329584504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.4226391496 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 3263629324 ps |
| CPU time | 186.54 seconds |
| Started | Oct 15 03:22:51 PM UTC 24 |
| Finished | Oct 15 03:26:01 PM UTC 24 |
| Peak memory | 593892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226391496 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.4226391496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2510901069 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 59682726362 ps |
| CPU time | 885.18 seconds |
| Started | Oct 15 03:22:55 PM UTC 24 |
| Finished | Oct 15 03:37:51 PM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510901069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_dev ice_slow_rsp.2510901069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.3418099070 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 900161428 ps |
| CPU time | 38.43 seconds |
| Started | Oct 15 03:23:18 PM UTC 24 |
| Finished | Oct 15 03:23:58 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418099070 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.3418099070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.3652394594 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 394609213 ps |
| CPU time | 17.41 seconds |
| Started | Oct 15 03:23:02 PM UTC 24 |
| Finished | Oct 15 03:23:21 PM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652394594 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3652394594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.1785390849 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 68994753 ps |
| CPU time | 9.24 seconds |
| Started | Oct 15 03:22:46 PM UTC 24 |
| Finished | Oct 15 03:22:56 PM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785390849 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.1785390849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.12724825 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 21972460166 ps |
| CPU time | 235.7 seconds |
| Started | Oct 15 03:22:46 PM UTC 24 |
| Finished | Oct 15 03:26:46 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12724825 -asse rt nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.12724825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.4093512999 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 10428078683 ps |
| CPU time | 197.84 seconds |
| Started | Oct 15 03:22:48 PM UTC 24 |
| Finished | Oct 15 03:26:09 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093512999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.4093512999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.2573469606 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 40755059 ps |
| CPU time | 9.14 seconds |
| Started | Oct 15 03:22:44 PM UTC 24 |
| Finished | Oct 15 03:22:55 PM UTC 24 |
| Peak memory | 591520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573469606 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.2573469606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.3246405183 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 258547932 ps |
| CPU time | 30.44 seconds |
| Started | Oct 15 03:22:59 PM UTC 24 |
| Finished | Oct 15 03:23:32 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246405183 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3246405183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.3554533734 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 45592557 ps |
| CPU time | 5.88 seconds |
| Started | Oct 15 03:22:26 PM UTC 24 |
| Finished | Oct 15 03:22:32 PM UTC 24 |
| Peak memory | 591804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554533734 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3554533734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.3998215717 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 6190662980 ps |
| CPU time | 63.89 seconds |
| Started | Oct 15 03:22:44 PM UTC 24 |
| Finished | Oct 15 03:23:50 PM UTC 24 |
| Peak memory | 591836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998215717 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.3998215717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.1557086888 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 4242689268 ps |
| CPU time | 68.49 seconds |
| Started | Oct 15 03:22:46 PM UTC 24 |
| Finished | Oct 15 03:23:56 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557086888 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1557086888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.38208234 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 47730690 ps |
| CPU time | 9.2 seconds |
| Started | Oct 15 03:22:44 PM UTC 24 |
| Finished | Oct 15 03:22:55 PM UTC 24 |
| Peak memory | 591864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38208234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.38208234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.3372273089 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 171463863 ps |
| CPU time | 24.19 seconds |
| Started | Oct 15 03:23:19 PM UTC 24 |
| Finished | Oct 15 03:23:44 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372273089 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3372273089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.260728188 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 14484074875 ps |
| CPU time | 546.98 seconds |
| Started | Oct 15 03:23:21 PM UTC 24 |
| Finished | Oct 15 03:32:35 PM UTC 24 |
| Peak memory | 593992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260728188 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.260728188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.2421575717 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 1916392946 ps |
| CPU time | 387.09 seconds |
| Started | Oct 15 03:23:21 PM UTC 24 |
| Finished | Oct 15 03:29:54 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421575717 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.2421575717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.2636353155 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 758275463 ps |
| CPU time | 31 seconds |
| Started | Oct 15 03:23:09 PM UTC 24 |
| Finished | Oct 15 03:23:41 PM UTC 24 |
| Peak memory | 593824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636353155 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2636353155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.3579641330 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 4924327632 ps |
| CPU time | 370.93 seconds |
| Started | Oct 15 03:23:23 PM UTC 24 |
| Finished | Oct 15 03:29:39 PM UTC 24 |
| Peak memory | 619028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579641330 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.3579641330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.451374315 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 982964107 ps |
| CPU time | 89.72 seconds |
| Started | Oct 15 03:24:05 PM UTC 24 |
| Finished | Oct 15 03:25:37 PM UTC 24 |
| Peak memory | 594112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451374315 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.451374315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.1102721507 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 810538373 ps |
| CPU time | 47.81 seconds |
| Started | Oct 15 03:24:12 PM UTC 24 |
| Finished | Oct 15 03:25:02 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102721507 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.1102721507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.3424844609 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 168059265 ps |
| CPU time | 17.99 seconds |
| Started | Oct 15 03:24:10 PM UTC 24 |
| Finished | Oct 15 03:24:29 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424844609 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3424844609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.3516801842 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 899069043 ps |
| CPU time | 36.53 seconds |
| Started | Oct 15 03:23:51 PM UTC 24 |
| Finished | Oct 15 03:24:28 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516801842 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.3516801842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.4017965258 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 40308641707 ps |
| CPU time | 457.71 seconds |
| Started | Oct 15 03:23:58 PM UTC 24 |
| Finished | Oct 15 03:31:42 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017965258 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.4017965258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.2771307944 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 21222150238 ps |
| CPU time | 322.7 seconds |
| Started | Oct 15 03:24:00 PM UTC 24 |
| Finished | Oct 15 03:29:27 PM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771307944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2771307944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.505938055 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 467544020 ps |
| CPU time | 40.63 seconds |
| Started | Oct 15 03:23:55 PM UTC 24 |
| Finished | Oct 15 03:24:37 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505938055 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.505938055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.1749707994 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 454723317 ps |
| CPU time | 36.64 seconds |
| Started | Oct 15 03:24:09 PM UTC 24 |
| Finished | Oct 15 03:24:47 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749707994 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1749707994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.2985812580 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 191929781 ps |
| CPU time | 9.91 seconds |
| Started | Oct 15 03:23:32 PM UTC 24 |
| Finished | Oct 15 03:23:43 PM UTC 24 |
| Peak memory | 591612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985812580 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2985812580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.756581763 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 6364550413 ps |
| CPU time | 59.53 seconds |
| Started | Oct 15 03:23:38 PM UTC 24 |
| Finished | Oct 15 03:24:39 PM UTC 24 |
| Peak memory | 591940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756581763 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.756581763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.3998785047 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 2803393369 ps |
| CPU time | 58.48 seconds |
| Started | Oct 15 03:23:45 PM UTC 24 |
| Finished | Oct 15 03:24:45 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998785047 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3998785047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.1549768199 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 44455074 ps |
| CPU time | 9 seconds |
| Started | Oct 15 03:23:34 PM UTC 24 |
| Finished | Oct 15 03:23:45 PM UTC 24 |
| Peak memory | 591756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549768199 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1549768199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.3760172723 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 15976307037 ps |
| CPU time | 555.73 seconds |
| Started | Oct 15 03:24:16 PM UTC 24 |
| Finished | Oct 15 03:33:39 PM UTC 24 |
| Peak memory | 594028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760172723 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3760172723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.3110987605 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 598678582 ps |
| CPU time | 59.83 seconds |
| Started | Oct 15 03:24:23 PM UTC 24 |
| Finished | Oct 15 03:25:25 PM UTC 24 |
| Peak memory | 593984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110987605 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3110987605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.2677906189 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 21458661987 ps |
| CPU time | 920.63 seconds |
| Started | Oct 15 03:24:41 PM UTC 24 |
| Finished | Oct 15 03:40:13 PM UTC 24 |
| Peak memory | 598108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677906189 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.2677906189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.1356602587 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 780691300 ps |
| CPU time | 31.99 seconds |
| Started | Oct 15 03:24:10 PM UTC 24 |
| Finished | Oct 15 03:24:44 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356602587 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1356602587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/24.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.1779770359 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 2780448950 ps |
| CPU time | 107.04 seconds |
| Started | Oct 15 03:24:45 PM UTC 24 |
| Finished | Oct 15 03:26:34 PM UTC 24 |
| Peak memory | 619080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779770359 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.1779770359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.3737682202 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 822844343 ps |
| CPU time | 70.77 seconds |
| Started | Oct 15 03:25:14 PM UTC 24 |
| Finished | Oct 15 03:26:26 PM UTC 24 |
| Peak memory | 593692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737682202 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3737682202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.1103678490 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 49405133622 ps |
| CPU time | 743.73 seconds |
| Started | Oct 15 03:25:25 PM UTC 24 |
| Finished | Oct 15 03:37:58 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103678490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_dev ice_slow_rsp.1103678490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.2211334232 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 232816376 ps |
| CPU time | 23.72 seconds |
| Started | Oct 15 03:25:52 PM UTC 24 |
| Finished | Oct 15 03:26:17 PM UTC 24 |
| Peak memory | 593904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211334232 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.2211334232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.1621176005 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 446135615 ps |
| CPU time | 48.76 seconds |
| Started | Oct 15 03:25:28 PM UTC 24 |
| Finished | Oct 15 03:26:18 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621176005 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1621176005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.3886527282 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 635513651 ps |
| CPU time | 75.36 seconds |
| Started | Oct 15 03:25:06 PM UTC 24 |
| Finished | Oct 15 03:26:24 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886527282 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.3886527282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.541088374 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 60189176797 ps |
| CPU time | 574.02 seconds |
| Started | Oct 15 03:25:10 PM UTC 24 |
| Finished | Oct 15 03:34:51 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541088374 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.541088374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.2269528965 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 8296327976 ps |
| CPU time | 135.41 seconds |
| Started | Oct 15 03:25:08 PM UTC 24 |
| Finished | Oct 15 03:27:26 PM UTC 24 |
| Peak memory | 594112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269528965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2269528965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.2275920396 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 310098596 ps |
| CPU time | 32.04 seconds |
| Started | Oct 15 03:25:05 PM UTC 24 |
| Finished | Oct 15 03:25:38 PM UTC 24 |
| Peak memory | 593688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275920396 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2275920396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.582048843 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 433508783 ps |
| CPU time | 31.96 seconds |
| Started | Oct 15 03:25:25 PM UTC 24 |
| Finished | Oct 15 03:25:58 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582048843 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.582048843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.4049444682 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 49967617 ps |
| CPU time | 9.83 seconds |
| Started | Oct 15 03:24:48 PM UTC 24 |
| Finished | Oct 15 03:24:59 PM UTC 24 |
| Peak memory | 591892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049444682 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.4049444682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.1518447547 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 9505109956 ps |
| CPU time | 116.47 seconds |
| Started | Oct 15 03:24:56 PM UTC 24 |
| Finished | Oct 15 03:26:55 PM UTC 24 |
| Peak memory | 591924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518447547 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1518447547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.568792738 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 5107527970 ps |
| CPU time | 67.09 seconds |
| Started | Oct 15 03:25:02 PM UTC 24 |
| Finished | Oct 15 03:26:11 PM UTC 24 |
| Peak memory | 591816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568792738 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.568792738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.2062051383 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 58883039 ps |
| CPU time | 7.86 seconds |
| Started | Oct 15 03:24:56 PM UTC 24 |
| Finished | Oct 15 03:25:05 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062051383 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2062051383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.3635283159 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 7979575972 ps |
| CPU time | 312.44 seconds |
| Started | Oct 15 03:25:53 PM UTC 24 |
| Finished | Oct 15 03:31:09 PM UTC 24 |
| Peak memory | 594032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635283159 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3635283159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.564224597 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 6987994091 ps |
| CPU time | 232.23 seconds |
| Started | Oct 15 03:26:05 PM UTC 24 |
| Finished | Oct 15 03:30:01 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564224597 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.564224597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.688448254 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 275866052 ps |
| CPU time | 124.55 seconds |
| Started | Oct 15 03:26:02 PM UTC 24 |
| Finished | Oct 15 03:28:09 PM UTC 24 |
| Peak memory | 593728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688448254 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.688448254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.1332641478 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 330502622 ps |
| CPU time | 101.03 seconds |
| Started | Oct 15 03:26:13 PM UTC 24 |
| Finished | Oct 15 03:27:56 PM UTC 24 |
| Peak memory | 593728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332641478 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.1332641478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.3268488979 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 55641631 ps |
| CPU time | 13.41 seconds |
| Started | Oct 15 03:25:32 PM UTC 24 |
| Finished | Oct 15 03:25:46 PM UTC 24 |
| Peak memory | 593900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268488979 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3268488979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/25.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.2439856623 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 3481396096 ps |
| CPU time | 197.98 seconds |
| Started | Oct 15 03:26:12 PM UTC 24 |
| Finished | Oct 15 03:29:33 PM UTC 24 |
| Peak memory | 619308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439856623 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.2439856623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.1257755104 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 646844431 ps |
| CPU time | 56.17 seconds |
| Started | Oct 15 03:26:46 PM UTC 24 |
| Finished | Oct 15 03:27:44 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257755104 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.1257755104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.364947806 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 68072860029 ps |
| CPU time | 1040.06 seconds |
| Started | Oct 15 03:26:51 PM UTC 24 |
| Finished | Oct 15 03:44:23 PM UTC 24 |
| Peak memory | 594004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364947806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_devi ce_slow_rsp.364947806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.3872923995 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 403766918 ps |
| CPU time | 21.47 seconds |
| Started | Oct 15 03:27:02 PM UTC 24 |
| Finished | Oct 15 03:27:24 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872923995 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3872923995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.1055052493 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 1155534372 ps |
| CPU time | 51.25 seconds |
| Started | Oct 15 03:27:01 PM UTC 24 |
| Finished | Oct 15 03:27:54 PM UTC 24 |
| Peak memory | 593672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055052493 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1055052493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.1473717916 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 1385100525 ps |
| CPU time | 49.08 seconds |
| Started | Oct 15 03:26:28 PM UTC 24 |
| Finished | Oct 15 03:27:19 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473717916 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.1473717916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.1034938266 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 19294547061 ps |
| CPU time | 201.35 seconds |
| Started | Oct 15 03:26:38 PM UTC 24 |
| Finished | Oct 15 03:30:02 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034938266 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1034938266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.1599018517 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 27345772817 ps |
| CPU time | 415.56 seconds |
| Started | Oct 15 03:26:40 PM UTC 24 |
| Finished | Oct 15 03:33:41 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599018517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1599018517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.2526472558 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 609313633 ps |
| CPU time | 52.27 seconds |
| Started | Oct 15 03:26:35 PM UTC 24 |
| Finished | Oct 15 03:27:28 PM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526472558 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.2526472558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.2286536437 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 168520532 ps |
| CPU time | 18.86 seconds |
| Started | Oct 15 03:26:51 PM UTC 24 |
| Finished | Oct 15 03:27:11 PM UTC 24 |
| Peak memory | 593668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286536437 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2286536437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.2854003317 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 154077527 ps |
| CPU time | 11.31 seconds |
| Started | Oct 15 03:26:23 PM UTC 24 |
| Finished | Oct 15 03:26:36 PM UTC 24 |
| Peak memory | 591932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854003317 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2854003317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.4049799130 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 8194618420 ps |
| CPU time | 99.78 seconds |
| Started | Oct 15 03:26:27 PM UTC 24 |
| Finished | Oct 15 03:28:09 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049799130 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.4049799130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.1976804444 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 4363041343 ps |
| CPU time | 73.15 seconds |
| Started | Oct 15 03:26:26 PM UTC 24 |
| Finished | Oct 15 03:27:41 PM UTC 24 |
| Peak memory | 591824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976804444 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1976804444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.2397236097 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 44350379 ps |
| CPU time | 8.18 seconds |
| Started | Oct 15 03:26:25 PM UTC 24 |
| Finished | Oct 15 03:26:34 PM UTC 24 |
| Peak memory | 591616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397236097 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.2397236097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.1300175963 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 2319927189 ps |
| CPU time | 215.67 seconds |
| Started | Oct 15 03:27:04 PM UTC 24 |
| Finished | Oct 15 03:30:43 PM UTC 24 |
| Peak memory | 594032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300175963 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1300175963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.1797869459 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 23052200162 ps |
| CPU time | 788.03 seconds |
| Started | Oct 15 03:27:21 PM UTC 24 |
| Finished | Oct 15 03:40:39 PM UTC 24 |
| Peak memory | 593992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797869459 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1797869459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.3038772150 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 6810756 ps |
| CPU time | 11.55 seconds |
| Started | Oct 15 03:27:13 PM UTC 24 |
| Finished | Oct 15 03:27:25 PM UTC 24 |
| Peak memory | 591784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038772150 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.3038772150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3643095090 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 782288772 ps |
| CPU time | 144.39 seconds |
| Started | Oct 15 03:27:38 PM UTC 24 |
| Finished | Oct 15 03:30:05 PM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643095090 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.3643095090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.4009319624 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 236229604 ps |
| CPU time | 33.75 seconds |
| Started | Oct 15 03:26:59 PM UTC 24 |
| Finished | Oct 15 03:27:34 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009319624 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.4009319624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/26.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.4233302357 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 3501513085 ps |
| CPU time | 269.46 seconds |
| Started | Oct 15 03:27:41 PM UTC 24 |
| Finished | Oct 15 03:32:15 PM UTC 24 |
| Peak memory | 619156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233302357 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.4233302357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.1652531616 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 2409179020 ps |
| CPU time | 119.27 seconds |
| Started | Oct 15 03:28:15 PM UTC 24 |
| Finished | Oct 15 03:30:17 PM UTC 24 |
| Peak memory | 593884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652531616 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1652531616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.2903063472 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 21075829426 ps |
| CPU time | 320.35 seconds |
| Started | Oct 15 03:28:21 PM UTC 24 |
| Finished | Oct 15 03:33:45 PM UTC 24 |
| Peak memory | 593992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903063472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_dev ice_slow_rsp.2903063472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.2898683715 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 869705183 ps |
| CPU time | 46.07 seconds |
| Started | Oct 15 03:28:35 PM UTC 24 |
| Finished | Oct 15 03:29:22 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898683715 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.2898683715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.228174905 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 803306047 ps |
| CPU time | 26.94 seconds |
| Started | Oct 15 03:28:22 PM UTC 24 |
| Finished | Oct 15 03:28:50 PM UTC 24 |
| Peak memory | 593824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228174905 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.228174905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.3283537269 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 512571734 ps |
| CPU time | 50.23 seconds |
| Started | Oct 15 03:27:53 PM UTC 24 |
| Finished | Oct 15 03:28:45 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283537269 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.3283537269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.299551345 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 20552406543 ps |
| CPU time | 199.14 seconds |
| Started | Oct 15 03:28:04 PM UTC 24 |
| Finished | Oct 15 03:31:27 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299551345 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.299551345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.981334744 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 11535736479 ps |
| CPU time | 182.15 seconds |
| Started | Oct 15 03:28:06 PM UTC 24 |
| Finished | Oct 15 03:31:11 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981334744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.981334744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.2235701338 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 154128173 ps |
| CPU time | 22.14 seconds |
| Started | Oct 15 03:28:01 PM UTC 24 |
| Finished | Oct 15 03:28:25 PM UTC 24 |
| Peak memory | 593808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235701338 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2235701338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.2103736706 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 849350200 ps |
| CPU time | 26.71 seconds |
| Started | Oct 15 03:28:19 PM UTC 24 |
| Finished | Oct 15 03:28:47 PM UTC 24 |
| Peak memory | 593808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103736706 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2103736706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.1414807084 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 48660360 ps |
| CPU time | 8.69 seconds |
| Started | Oct 15 03:27:44 PM UTC 24 |
| Finished | Oct 15 03:27:54 PM UTC 24 |
| Peak memory | 591612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414807084 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1414807084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.3695041093 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 8214511683 ps |
| CPU time | 90.48 seconds |
| Started | Oct 15 03:27:52 PM UTC 24 |
| Finished | Oct 15 03:29:24 PM UTC 24 |
| Peak memory | 591816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695041093 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3695041093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.1551718037 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 5692005332 ps |
| CPU time | 101 seconds |
| Started | Oct 15 03:27:53 PM UTC 24 |
| Finished | Oct 15 03:29:36 PM UTC 24 |
| Peak memory | 591824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551718037 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1551718037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.71296855 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 48008890 ps |
| CPU time | 6.62 seconds |
| Started | Oct 15 03:27:48 PM UTC 24 |
| Finished | Oct 15 03:27:56 PM UTC 24 |
| Peak memory | 591624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71296855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.71296855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.2033613782 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 14735936629 ps |
| CPU time | 485.42 seconds |
| Started | Oct 15 03:28:34 PM UTC 24 |
| Finished | Oct 15 03:36:45 PM UTC 24 |
| Peak memory | 594032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033613782 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2033613782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.2704470344 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 69007632 ps |
| CPU time | 10.35 seconds |
| Started | Oct 15 03:28:49 PM UTC 24 |
| Finished | Oct 15 03:29:00 PM UTC 24 |
| Peak memory | 591612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704470344 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2704470344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.1923526891 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 5278254331 ps |
| CPU time | 473.62 seconds |
| Started | Oct 15 03:28:32 PM UTC 24 |
| Finished | Oct 15 03:36:32 PM UTC 24 |
| Peak memory | 594028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923526891 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.1923526891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.4177076786 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 4565994838 ps |
| CPU time | 294.12 seconds |
| Started | Oct 15 03:28:51 PM UTC 24 |
| Finished | Oct 15 03:33:49 PM UTC 24 |
| Peak memory | 593976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177076786 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.4177076786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.1757160377 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 1380318220 ps |
| CPU time | 78.43 seconds |
| Started | Oct 15 03:28:23 PM UTC 24 |
| Finished | Oct 15 03:29:43 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757160377 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1757160377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.2770683422 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 3370989094 ps |
| CPU time | 138.51 seconds |
| Started | Oct 15 03:29:11 PM UTC 24 |
| Finished | Oct 15 03:31:31 PM UTC 24 |
| Peak memory | 619180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770683422 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.2770683422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.2426625825 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 1264813397 ps |
| CPU time | 88.44 seconds |
| Started | Oct 15 03:29:49 PM UTC 24 |
| Finished | Oct 15 03:31:20 PM UTC 24 |
| Peak memory | 593692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426625825 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.2426625825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.3797101082 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 31694008499 ps |
| CPU time | 489.75 seconds |
| Started | Oct 15 03:29:52 PM UTC 24 |
| Finished | Oct 15 03:38:08 PM UTC 24 |
| Peak memory | 593740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797101082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_dev ice_slow_rsp.3797101082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.1391916192 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 23497583 ps |
| CPU time | 7.84 seconds |
| Started | Oct 15 03:30:06 PM UTC 24 |
| Finished | Oct 15 03:30:15 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391916192 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.1391916192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.3358475944 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 1680871070 ps |
| CPU time | 62.83 seconds |
| Started | Oct 15 03:29:58 PM UTC 24 |
| Finished | Oct 15 03:31:03 PM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358475944 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3358475944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.1381248412 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 1533227073 ps |
| CPU time | 59.66 seconds |
| Started | Oct 15 03:29:43 PM UTC 24 |
| Finished | Oct 15 03:30:45 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381248412 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.1381248412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.2207391125 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 25233875042 ps |
| CPU time | 316.27 seconds |
| Started | Oct 15 03:29:49 PM UTC 24 |
| Finished | Oct 15 03:35:10 PM UTC 24 |
| Peak memory | 593900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207391125 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2207391125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.2816816343 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 22805252080 ps |
| CPU time | 387.39 seconds |
| Started | Oct 15 03:29:48 PM UTC 24 |
| Finished | Oct 15 03:36:21 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816816343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2816816343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.1734360111 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 518497340 ps |
| CPU time | 46.97 seconds |
| Started | Oct 15 03:29:47 PM UTC 24 |
| Finished | Oct 15 03:30:35 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734360111 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.1734360111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.2649699981 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 2450196341 ps |
| CPU time | 66.66 seconds |
| Started | Oct 15 03:29:55 PM UTC 24 |
| Finished | Oct 15 03:31:03 PM UTC 24 |
| Peak memory | 594048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649699981 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2649699981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.1502631809 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 41116043 ps |
| CPU time | 9.4 seconds |
| Started | Oct 15 03:29:12 PM UTC 24 |
| Finished | Oct 15 03:29:23 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502631809 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1502631809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.1404832250 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 7397977341 ps |
| CPU time | 111.5 seconds |
| Started | Oct 15 03:29:15 PM UTC 24 |
| Finished | Oct 15 03:31:09 PM UTC 24 |
| Peak memory | 591940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404832250 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1404832250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.2414033438 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 5648912466 ps |
| CPU time | 99.81 seconds |
| Started | Oct 15 03:29:27 PM UTC 24 |
| Finished | Oct 15 03:31:09 PM UTC 24 |
| Peak memory | 591824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414033438 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2414033438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1032678261 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 46365992 ps |
| CPU time | 9.07 seconds |
| Started | Oct 15 03:29:15 PM UTC 24 |
| Finished | Oct 15 03:29:26 PM UTC 24 |
| Peak memory | 591756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032678261 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1032678261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.2390638997 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 3119663668 ps |
| CPU time | 295.87 seconds |
| Started | Oct 15 03:30:07 PM UTC 24 |
| Finished | Oct 15 03:35:07 PM UTC 24 |
| Peak memory | 594040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390638997 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2390638997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.3412541627 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 1102801465 ps |
| CPU time | 53.08 seconds |
| Started | Oct 15 03:30:25 PM UTC 24 |
| Finished | Oct 15 03:31:19 PM UTC 24 |
| Peak memory | 594056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412541627 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3412541627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.3389894241 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 195980108 ps |
| CPU time | 183.51 seconds |
| Started | Oct 15 03:30:21 PM UTC 24 |
| Finished | Oct 15 03:33:28 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389894241 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.3389894241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.631930998 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 238050709 ps |
| CPU time | 84.23 seconds |
| Started | Oct 15 03:30:25 PM UTC 24 |
| Finished | Oct 15 03:31:52 PM UTC 24 |
| Peak memory | 593724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631930998 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.631930998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.4100748401 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 262540017 ps |
| CPU time | 30.29 seconds |
| Started | Oct 15 03:29:59 PM UTC 24 |
| Finished | Oct 15 03:30:31 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100748401 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.4100748401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.646822294 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 3683451839 ps |
| CPU time | 219.82 seconds |
| Started | Oct 15 03:30:32 PM UTC 24 |
| Finished | Oct 15 03:34:15 PM UTC 24 |
| Peak memory | 619152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646822294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.646822294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.893588012 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 920885830 ps |
| CPU time | 66.45 seconds |
| Started | Oct 15 03:31:05 PM UTC 24 |
| Finished | Oct 15 03:32:13 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893588012 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.893588012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.151817916 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 928256460 ps |
| CPU time | 35.75 seconds |
| Started | Oct 15 03:31:34 PM UTC 24 |
| Finished | Oct 15 03:32:11 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151817916 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.151817916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.3859196736 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 1031159946 ps |
| CPU time | 43.45 seconds |
| Started | Oct 15 03:31:28 PM UTC 24 |
| Finished | Oct 15 03:32:13 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859196736 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3859196736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.4074897820 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 2071850848 ps |
| CPU time | 66.1 seconds |
| Started | Oct 15 03:30:46 PM UTC 24 |
| Finished | Oct 15 03:31:54 PM UTC 24 |
| Peak memory | 593672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074897820 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.4074897820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.1563152563 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 33329488040 ps |
| CPU time | 307.79 seconds |
| Started | Oct 15 03:31:01 PM UTC 24 |
| Finished | Oct 15 03:36:13 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563152563 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1563152563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.3439971004 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 20937895907 ps |
| CPU time | 292.38 seconds |
| Started | Oct 15 03:31:09 PM UTC 24 |
| Finished | Oct 15 03:36:05 PM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439971004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3439971004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.2761556859 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 597816015 ps |
| CPU time | 62.19 seconds |
| Started | Oct 15 03:30:54 PM UTC 24 |
| Finished | Oct 15 03:31:58 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761556859 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.2761556859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.1946714488 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 295816128 ps |
| CPU time | 12.57 seconds |
| Started | Oct 15 03:31:22 PM UTC 24 |
| Finished | Oct 15 03:31:36 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946714488 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1946714488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.1136545726 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 169073850 ps |
| CPU time | 10.82 seconds |
| Started | Oct 15 03:30:43 PM UTC 24 |
| Finished | Oct 15 03:30:55 PM UTC 24 |
| Peak memory | 591984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136545726 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.1136545726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.1782706230 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 10280914139 ps |
| CPU time | 118.01 seconds |
| Started | Oct 15 03:30:45 PM UTC 24 |
| Finished | Oct 15 03:32:45 PM UTC 24 |
| Peak memory | 591940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782706230 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1782706230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.2198069732 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 5791134935 ps |
| CPU time | 125.57 seconds |
| Started | Oct 15 03:30:47 PM UTC 24 |
| Finished | Oct 15 03:32:55 PM UTC 24 |
| Peak memory | 591880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198069732 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.2198069732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.3314232866 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 43136230 ps |
| CPU time | 8.31 seconds |
| Started | Oct 15 03:30:43 PM UTC 24 |
| Finished | Oct 15 03:30:52 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314232866 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.3314232866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.1130674388 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1283910581 ps |
| CPU time | 108.2 seconds |
| Started | Oct 15 03:31:32 PM UTC 24 |
| Finished | Oct 15 03:33:22 PM UTC 24 |
| Peak memory | 593976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130674388 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1130674388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.1176065931 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 6069032755 ps |
| CPU time | 254.97 seconds |
| Started | Oct 15 03:31:37 PM UTC 24 |
| Finished | Oct 15 03:35:56 PM UTC 24 |
| Peak memory | 593976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176065931 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1176065931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.198300839 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 1635114281 ps |
| CPU time | 340.29 seconds |
| Started | Oct 15 03:31:44 PM UTC 24 |
| Finished | Oct 15 03:37:29 PM UTC 24 |
| Peak memory | 594004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198300839 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.198300839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.3654881942 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 1149660437 ps |
| CPU time | 49.37 seconds |
| Started | Oct 15 03:31:28 PM UTC 24 |
| Finished | Oct 15 03:32:19 PM UTC 24 |
| Peak memory | 594048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654881942 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3654881942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.2135492636 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 30966313512 ps |
| CPU time | 3471.62 seconds |
| Started | Oct 15 02:41:10 PM UTC 24 |
| Finished | Oct 15 03:39:43 PM UTC 24 |
| Peak memory | 615120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2135492636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.chip_csr_bit_bash.2135492636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.2922385414 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 4240700432 ps |
| CPU time | 180.83 seconds |
| Started | Oct 15 02:43:11 PM UTC 24 |
| Finished | Oct 15 02:46:15 PM UTC 24 |
| Peak memory | 678624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922385414 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_reset.2922385414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.4046567460 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 9471434456 ps |
| CPU time | 815.44 seconds |
| Started | Oct 15 02:43:25 PM UTC 24 |
| Finished | Oct 15 02:57:10 PM UTC 24 |
| Peak memory | 666516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=4046567460 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.chip_csr_mem_rw_with_rand_reset.4046567460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.1507717828 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 4255279740 ps |
| CPU time | 399.8 seconds |
| Started | Oct 15 02:43:14 PM UTC 24 |
| Finished | Oct 15 02:50:00 PM UTC 24 |
| Peak memory | 615192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507717828 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.1507717828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.4009070900 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 3593760297 ps |
| CPU time | 261.84 seconds |
| Started | Oct 15 02:41:20 PM UTC 24 |
| Finished | Oct 15 02:45:45 PM UTC 24 |
| Peak memory | 619396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009070900 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.4009070900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.134072331 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 1385019011 ps |
| CPU time | 70.99 seconds |
| Started | Oct 15 02:41:57 PM UTC 24 |
| Finished | Oct 15 02:43:10 PM UTC 24 |
| Peak memory | 593944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134072331 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.134072331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3207984540 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 67039245263 ps |
| CPU time | 1072.54 seconds |
| Started | Oct 15 02:42:13 PM UTC 24 |
| Finished | Oct 15 03:00:19 PM UTC 24 |
| Peak memory | 593740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207984540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_devi ce_slow_rsp.3207984540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.4148935189 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 1110136073 ps |
| CPU time | 52 seconds |
| Started | Oct 15 02:42:31 PM UTC 24 |
| Finished | Oct 15 02:43:25 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148935189 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.4148935189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.3815906772 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 225133900 ps |
| CPU time | 20.57 seconds |
| Started | Oct 15 02:42:23 PM UTC 24 |
| Finished | Oct 15 02:42:44 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815906772 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3815906772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.3026862603 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1895617554 ps |
| CPU time | 59.81 seconds |
| Started | Oct 15 02:41:32 PM UTC 24 |
| Finished | Oct 15 02:42:33 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026862603 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.3026862603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.513400156 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 48904492517 ps |
| CPU time | 520.27 seconds |
| Started | Oct 15 02:41:31 PM UTC 24 |
| Finished | Oct 15 02:50:18 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513400156 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.513400156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.1229001012 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 14513368020 ps |
| CPU time | 203.26 seconds |
| Started | Oct 15 02:41:55 PM UTC 24 |
| Finished | Oct 15 02:45:22 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229001012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1229001012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.2795418646 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 232764465 ps |
| CPU time | 31.12 seconds |
| Started | Oct 15 02:41:29 PM UTC 24 |
| Finished | Oct 15 02:42:02 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795418646 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2795418646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.1501300648 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 128911176 ps |
| CPU time | 16.61 seconds |
| Started | Oct 15 02:42:16 PM UTC 24 |
| Finished | Oct 15 02:42:34 PM UTC 24 |
| Peak memory | 593748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501300648 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1501300648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.1334886032 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 55961728 ps |
| CPU time | 9.83 seconds |
| Started | Oct 15 02:41:20 PM UTC 24 |
| Finished | Oct 15 02:41:30 PM UTC 24 |
| Peak memory | 591844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334886032 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.1334886032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.3010227807 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 10017859725 ps |
| CPU time | 102.92 seconds |
| Started | Oct 15 02:41:23 PM UTC 24 |
| Finished | Oct 15 02:43:08 PM UTC 24 |
| Peak memory | 592048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010227807 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3010227807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.3883322517 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 5270563745 ps |
| CPU time | 87.54 seconds |
| Started | Oct 15 02:41:30 PM UTC 24 |
| Finished | Oct 15 02:43:00 PM UTC 24 |
| Peak memory | 591696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883322517 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3883322517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.3131924468 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 36182546 ps |
| CPU time | 7.98 seconds |
| Started | Oct 15 02:41:19 PM UTC 24 |
| Finished | Oct 15 02:41:28 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131924468 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3131924468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.2654056990 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 4496023438 ps |
| CPU time | 162.27 seconds |
| Started | Oct 15 02:43:00 PM UTC 24 |
| Finished | Oct 15 02:45:46 PM UTC 24 |
| Peak memory | 593892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654056990 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2654056990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.3191078155 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 231548044 ps |
| CPU time | 98.77 seconds |
| Started | Oct 15 02:43:00 PM UTC 24 |
| Finished | Oct 15 02:44:41 PM UTC 24 |
| Peak memory | 593984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191078155 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.3191078155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.847134791 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 2010187311 ps |
| CPU time | 258.37 seconds |
| Started | Oct 15 02:43:01 PM UTC 24 |
| Finished | Oct 15 02:47:24 PM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847134791 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.847134791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.3490405431 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 163604135 ps |
| CPU time | 28.43 seconds |
| Started | Oct 15 02:42:30 PM UTC 24 |
| Finished | Oct 15 02:42:59 PM UTC 24 |
| Peak memory | 593916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490405431 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3490405431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.524224263 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 19322345 ps |
| CPU time | 6.56 seconds |
| Started | Oct 15 03:32:23 PM UTC 24 |
| Finished | Oct 15 03:32:31 PM UTC 24 |
| Peak memory | 591640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524224263 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.524224263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/30.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.3388696431 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 40293406846 ps |
| CPU time | 628.23 seconds |
| Started | Oct 15 03:32:24 PM UTC 24 |
| Finished | Oct 15 03:43:00 PM UTC 24 |
| Peak memory | 593992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388696431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_dev ice_slow_rsp.3388696431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.2990509880 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 666298526 ps |
| CPU time | 33.54 seconds |
| Started | Oct 15 03:32:39 PM UTC 24 |
| Finished | Oct 15 03:33:14 PM UTC 24 |
| Peak memory | 593676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990509880 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.2990509880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.835884270 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 110448235 ps |
| CPU time | 12.69 seconds |
| Started | Oct 15 03:32:39 PM UTC 24 |
| Finished | Oct 15 03:32:53 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835884270 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.835884270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/30.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.944430789 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 1988795530 ps |
| CPU time | 87.93 seconds |
| Started | Oct 15 03:32:01 PM UTC 24 |
| Finished | Oct 15 03:33:31 PM UTC 24 |
| Peak memory | 593980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944430789 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.944430789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/30.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.4259002758 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 52106177313 ps |
| CPU time | 527.83 seconds |
| Started | Oct 15 03:32:19 PM UTC 24 |
| Finished | Oct 15 03:41:14 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259002758 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.4259002758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/30.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.1986136616 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 3307989303 ps |
| CPU time | 48.74 seconds |
| Started | Oct 15 03:32:21 PM UTC 24 |
| Finished | Oct 15 03:33:11 PM UTC 24 |
| Peak memory | 591772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986136616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1986136616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/30.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.3656514874 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 436308013 ps |
| CPU time | 49.98 seconds |
| Started | Oct 15 03:32:07 PM UTC 24 |
| Finished | Oct 15 03:32:59 PM UTC 24 |
| Peak memory | 593816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656514874 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.3656514874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/30.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.3373818717 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 96205037 ps |
| CPU time | 13.39 seconds |
| Started | Oct 15 03:32:27 PM UTC 24 |
| Finished | Oct 15 03:32:42 PM UTC 24 |
| Peak memory | 593668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373818717 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3373818717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/30.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.2734790805 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 145435126 ps |
| CPU time | 10.91 seconds |
| Started | Oct 15 03:31:44 PM UTC 24 |
| Finished | Oct 15 03:31:56 PM UTC 24 |
| Peak memory | 591884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734790805 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2734790805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/30.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.1961777878 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 7337640103 ps |
| CPU time | 79.84 seconds |
| Started | Oct 15 03:31:57 PM UTC 24 |
| Finished | Oct 15 03:33:19 PM UTC 24 |
| Peak memory | 591940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961777878 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1961777878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/30.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.3063273465 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 4849666252 ps |
| CPU time | 63.26 seconds |
| Started | Oct 15 03:31:59 PM UTC 24 |
| Finished | Oct 15 03:33:04 PM UTC 24 |
| Peak memory | 591824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063273465 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3063273465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2131392126 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 51290667 ps |
| CPU time | 9.64 seconds |
| Started | Oct 15 03:31:51 PM UTC 24 |
| Finished | Oct 15 03:32:01 PM UTC 24 |
| Peak memory | 591860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131392126 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2131392126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/30.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.205175431 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 18435420742 ps |
| CPU time | 671.23 seconds |
| Started | Oct 15 03:32:41 PM UTC 24 |
| Finished | Oct 15 03:44:01 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205175431 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.205175431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/30.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.812884198 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 6319657091 ps |
| CPU time | 189.12 seconds |
| Started | Oct 15 03:32:56 PM UTC 24 |
| Finished | Oct 15 03:36:08 PM UTC 24 |
| Peak memory | 594004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812884198 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.812884198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/30.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.224935658 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 4549264234 ps |
| CPU time | 300.98 seconds |
| Started | Oct 15 03:32:42 PM UTC 24 |
| Finished | Oct 15 03:37:47 PM UTC 24 |
| Peak memory | 594152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224935658 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.224935658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.33766363 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 810151022 ps |
| CPU time | 362.01 seconds |
| Started | Oct 15 03:33:02 PM UTC 24 |
| Finished | Oct 15 03:39:10 PM UTC 24 |
| Peak memory | 593892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33766363 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.33766363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.235244894 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 697457125 ps |
| CPU time | 39.78 seconds |
| Started | Oct 15 03:32:38 PM UTC 24 |
| Finished | Oct 15 03:33:20 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235244894 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.235244894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/30.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.2235211823 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 272337089 ps |
| CPU time | 20.35 seconds |
| Started | Oct 15 03:33:40 PM UTC 24 |
| Finished | Oct 15 03:34:02 PM UTC 24 |
| Peak memory | 593692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235211823 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2235211823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/31.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.2350383688 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 42089439764 ps |
| CPU time | 691.04 seconds |
| Started | Oct 15 03:33:45 PM UTC 24 |
| Finished | Oct 15 03:45:25 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350383688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_dev ice_slow_rsp.2350383688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.2284713639 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 710217860 ps |
| CPU time | 36.07 seconds |
| Started | Oct 15 03:33:42 PM UTC 24 |
| Finished | Oct 15 03:34:20 PM UTC 24 |
| Peak memory | 594096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284713639 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2284713639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.1978159221 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 1619918727 ps |
| CPU time | 59.96 seconds |
| Started | Oct 15 03:33:46 PM UTC 24 |
| Finished | Oct 15 03:34:47 PM UTC 24 |
| Peak memory | 593912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978159221 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1978159221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/31.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.90087109 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 257838097 ps |
| CPU time | 25.51 seconds |
| Started | Oct 15 03:33:22 PM UTC 24 |
| Finished | Oct 15 03:33:49 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90087109 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.90087109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/31.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.1938528626 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 30321814711 ps |
| CPU time | 315.61 seconds |
| Started | Oct 15 03:33:31 PM UTC 24 |
| Finished | Oct 15 03:38:51 PM UTC 24 |
| Peak memory | 594092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938528626 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1938528626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/31.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.1802812747 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 5142615056 ps |
| CPU time | 77.39 seconds |
| Started | Oct 15 03:33:39 PM UTC 24 |
| Finished | Oct 15 03:34:58 PM UTC 24 |
| Peak memory | 591908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802812747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1802812747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/31.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.1762438343 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 569034903 ps |
| CPU time | 48.92 seconds |
| Started | Oct 15 03:33:24 PM UTC 24 |
| Finished | Oct 15 03:34:14 PM UTC 24 |
| Peak memory | 594052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762438343 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.1762438343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/31.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.821100155 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 1615108759 ps |
| CPU time | 44.38 seconds |
| Started | Oct 15 03:33:44 PM UTC 24 |
| Finished | Oct 15 03:34:30 PM UTC 24 |
| Peak memory | 594068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821100155 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.821100155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/31.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.2467615347 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 141453988 ps |
| CPU time | 10.08 seconds |
| Started | Oct 15 03:33:08 PM UTC 24 |
| Finished | Oct 15 03:33:19 PM UTC 24 |
| Peak memory | 591612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467615347 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2467615347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/31.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.1009361527 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 7781482044 ps |
| CPU time | 86.63 seconds |
| Started | Oct 15 03:33:18 PM UTC 24 |
| Finished | Oct 15 03:34:47 PM UTC 24 |
| Peak memory | 591940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009361527 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1009361527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/31.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.2580679711 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 5012997546 ps |
| CPU time | 109.53 seconds |
| Started | Oct 15 03:33:20 PM UTC 24 |
| Finished | Oct 15 03:35:12 PM UTC 24 |
| Peak memory | 591696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580679711 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2580679711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.2084858155 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 40494641 ps |
| CPU time | 8.85 seconds |
| Started | Oct 15 03:33:10 PM UTC 24 |
| Finished | Oct 15 03:33:20 PM UTC 24 |
| Peak memory | 591616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084858155 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.2084858155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/31.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.746682820 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 924350316 ps |
| CPU time | 85.64 seconds |
| Started | Oct 15 03:33:54 PM UTC 24 |
| Finished | Oct 15 03:35:22 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746682820 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.746682820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/31.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.2754893109 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 3270442014 ps |
| CPU time | 240.21 seconds |
| Started | Oct 15 03:34:03 PM UTC 24 |
| Finished | Oct 15 03:38:06 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754893109 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2754893109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/31.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.181185901 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 923214873 ps |
| CPU time | 145.84 seconds |
| Started | Oct 15 03:33:56 PM UTC 24 |
| Finished | Oct 15 03:36:25 PM UTC 24 |
| Peak memory | 593724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181185901 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.181185901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.1746443126 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 835317532 ps |
| CPU time | 141.96 seconds |
| Started | Oct 15 03:34:04 PM UTC 24 |
| Finished | Oct 15 03:36:28 PM UTC 24 |
| Peak memory | 593860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746443126 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.1746443126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.877379128 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 178801224 ps |
| CPU time | 9.14 seconds |
| Started | Oct 15 03:33:44 PM UTC 24 |
| Finished | Oct 15 03:33:54 PM UTC 24 |
| Peak memory | 591776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877379128 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.877379128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/31.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.2774071319 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 3061100945 ps |
| CPU time | 142.81 seconds |
| Started | Oct 15 03:34:42 PM UTC 24 |
| Finished | Oct 15 03:37:08 PM UTC 24 |
| Peak memory | 593752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774071319 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2774071319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/32.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.254931710 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 43170081949 ps |
| CPU time | 615.55 seconds |
| Started | Oct 15 03:34:48 PM UTC 24 |
| Finished | Oct 15 03:45:11 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254931710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_devi ce_slow_rsp.254931710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.508476688 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 339876602 ps |
| CPU time | 21.41 seconds |
| Started | Oct 15 03:35:15 PM UTC 24 |
| Finished | Oct 15 03:35:37 PM UTC 24 |
| Peak memory | 593956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508476688 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.508476688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.3003807561 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 1124721235 ps |
| CPU time | 43.29 seconds |
| Started | Oct 15 03:34:52 PM UTC 24 |
| Finished | Oct 15 03:35:36 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003807561 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.3003807561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/32.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.1367965653 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 294432366 ps |
| CPU time | 27.31 seconds |
| Started | Oct 15 03:34:27 PM UTC 24 |
| Finished | Oct 15 03:34:56 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367965653 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.1367965653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/32.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.1920736490 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 13398330704 ps |
| CPU time | 133.56 seconds |
| Started | Oct 15 03:34:41 PM UTC 24 |
| Finished | Oct 15 03:36:57 PM UTC 24 |
| Peak memory | 594096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920736490 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1920736490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/32.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.968529657 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 27495802205 ps |
| CPU time | 459.97 seconds |
| Started | Oct 15 03:34:35 PM UTC 24 |
| Finished | Oct 15 03:42:21 PM UTC 24 |
| Peak memory | 593976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968529657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.968529657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/32.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.4169887818 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 353533001 ps |
| CPU time | 41.94 seconds |
| Started | Oct 15 03:34:30 PM UTC 24 |
| Finished | Oct 15 03:35:13 PM UTC 24 |
| Peak memory | 593808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169887818 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.4169887818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/32.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.2194789558 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 1468442079 ps |
| CPU time | 46.56 seconds |
| Started | Oct 15 03:34:48 PM UTC 24 |
| Finished | Oct 15 03:35:36 PM UTC 24 |
| Peak memory | 593668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194789558 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2194789558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/32.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.4006791560 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 49488550 ps |
| CPU time | 9.14 seconds |
| Started | Oct 15 03:34:10 PM UTC 24 |
| Finished | Oct 15 03:34:21 PM UTC 24 |
| Peak memory | 591740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006791560 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.4006791560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/32.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.3110596836 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 9913146669 ps |
| CPU time | 153.4 seconds |
| Started | Oct 15 03:34:17 PM UTC 24 |
| Finished | Oct 15 03:36:53 PM UTC 24 |
| Peak memory | 592068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110596836 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3110596836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/32.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.932425640 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 3797249701 ps |
| CPU time | 64.92 seconds |
| Started | Oct 15 03:34:17 PM UTC 24 |
| Finished | Oct 15 03:35:24 PM UTC 24 |
| Peak memory | 591904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932425640 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.932425640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.3005991619 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 49808220 ps |
| CPU time | 9.2 seconds |
| Started | Oct 15 03:34:14 PM UTC 24 |
| Finished | Oct 15 03:34:24 PM UTC 24 |
| Peak memory | 591768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005991619 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.3005991619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/32.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.2956028499 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 3569841029 ps |
| CPU time | 298.1 seconds |
| Started | Oct 15 03:35:13 PM UTC 24 |
| Finished | Oct 15 03:40:16 PM UTC 24 |
| Peak memory | 593988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956028499 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2956028499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/32.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.297033934 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 7040245286 ps |
| CPU time | 232.45 seconds |
| Started | Oct 15 03:35:24 PM UTC 24 |
| Finished | Oct 15 03:39:20 PM UTC 24 |
| Peak memory | 594120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297033934 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.297033934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/32.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.3633999161 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 6249467295 ps |
| CPU time | 547.89 seconds |
| Started | Oct 15 03:35:17 PM UTC 24 |
| Finished | Oct 15 03:44:33 PM UTC 24 |
| Peak memory | 593860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633999161 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.3633999161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.3469868131 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 904839521 ps |
| CPU time | 254.91 seconds |
| Started | Oct 15 03:35:24 PM UTC 24 |
| Finished | Oct 15 03:39:44 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469868131 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.3469868131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.38432613 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 44201307 ps |
| CPU time | 11.18 seconds |
| Started | Oct 15 03:34:57 PM UTC 24 |
| Finished | Oct 15 03:35:09 PM UTC 24 |
| Peak memory | 591812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38432613 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.38432613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/32.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.854571305 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 415374396 ps |
| CPU time | 40.13 seconds |
| Started | Oct 15 03:36:03 PM UTC 24 |
| Finished | Oct 15 03:36:45 PM UTC 24 |
| Peak memory | 593692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854571305 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.854571305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/33.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.4167619800 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 26344195288 ps |
| CPU time | 364.67 seconds |
| Started | Oct 15 03:36:00 PM UTC 24 |
| Finished | Oct 15 03:42:09 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167619800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_dev ice_slow_rsp.4167619800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.3902981238 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 239571933 ps |
| CPU time | 35.79 seconds |
| Started | Oct 15 03:36:19 PM UTC 24 |
| Finished | Oct 15 03:36:56 PM UTC 24 |
| Peak memory | 593984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902981238 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3902981238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.820967764 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 2453431489 ps |
| CPU time | 90.6 seconds |
| Started | Oct 15 03:36:14 PM UTC 24 |
| Finished | Oct 15 03:37:47 PM UTC 24 |
| Peak memory | 593984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820967764 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.820967764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/33.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.891699572 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 87819753 ps |
| CPU time | 9.59 seconds |
| Started | Oct 15 03:35:41 PM UTC 24 |
| Finished | Oct 15 03:35:52 PM UTC 24 |
| Peak memory | 592008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891699572 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.891699572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/33.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.3887321709 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 10764609185 ps |
| CPU time | 114.31 seconds |
| Started | Oct 15 03:35:47 PM UTC 24 |
| Finished | Oct 15 03:37:44 PM UTC 24 |
| Peak memory | 593816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887321709 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3887321709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/33.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.4282854505 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 18485170808 ps |
| CPU time | 322.76 seconds |
| Started | Oct 15 03:35:54 PM UTC 24 |
| Finished | Oct 15 03:41:22 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282854505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.4282854505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/33.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.3317332839 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 583994600 ps |
| CPU time | 57.61 seconds |
| Started | Oct 15 03:35:49 PM UTC 24 |
| Finished | Oct 15 03:36:48 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317332839 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.3317332839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/33.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.1974684923 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 1706268050 ps |
| CPU time | 65.65 seconds |
| Started | Oct 15 03:36:05 PM UTC 24 |
| Finished | Oct 15 03:37:12 PM UTC 24 |
| Peak memory | 593860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974684923 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1974684923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/33.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.1543625207 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 235277779 ps |
| CPU time | 13.73 seconds |
| Started | Oct 15 03:35:34 PM UTC 24 |
| Finished | Oct 15 03:35:49 PM UTC 24 |
| Peak memory | 591612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543625207 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1543625207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/33.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.367489827 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 8278975189 ps |
| CPU time | 77.68 seconds |
| Started | Oct 15 03:35:35 PM UTC 24 |
| Finished | Oct 15 03:36:55 PM UTC 24 |
| Peak memory | 591940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367489827 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.367489827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/33.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.3795215314 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 4729665937 ps |
| CPU time | 88.5 seconds |
| Started | Oct 15 03:35:33 PM UTC 24 |
| Finished | Oct 15 03:37:04 PM UTC 24 |
| Peak memory | 591816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795215314 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3795215314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.1699097676 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 47719041 ps |
| CPU time | 7.96 seconds |
| Started | Oct 15 03:35:37 PM UTC 24 |
| Finished | Oct 15 03:35:47 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699097676 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.1699097676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/33.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.149723875 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 7447860676 ps |
| CPU time | 329.27 seconds |
| Started | Oct 15 03:36:23 PM UTC 24 |
| Finished | Oct 15 03:41:57 PM UTC 24 |
| Peak memory | 594056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149723875 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.149723875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/33.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3232453764 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 199963983 ps |
| CPU time | 117.08 seconds |
| Started | Oct 15 03:36:31 PM UTC 24 |
| Finished | Oct 15 03:38:30 PM UTC 24 |
| Peak memory | 593976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232453764 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.3232453764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.3938295025 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 249629143 ps |
| CPU time | 55 seconds |
| Started | Oct 15 03:36:36 PM UTC 24 |
| Finished | Oct 15 03:37:33 PM UTC 24 |
| Peak memory | 593944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938295025 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.3938295025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.206351212 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 663326709 ps |
| CPU time | 29.69 seconds |
| Started | Oct 15 03:36:16 PM UTC 24 |
| Finished | Oct 15 03:36:47 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206351212 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.206351212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/33.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.1190293425 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 288011629 ps |
| CPU time | 39.1 seconds |
| Started | Oct 15 03:37:12 PM UTC 24 |
| Finished | Oct 15 03:37:53 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190293425 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1190293425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/34.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.318839320 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 13783686274 ps |
| CPU time | 190.43 seconds |
| Started | Oct 15 03:37:14 PM UTC 24 |
| Finished | Oct 15 03:40:27 PM UTC 24 |
| Peak memory | 593880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318839320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_devi ce_slow_rsp.318839320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.2743579057 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 246467225 ps |
| CPU time | 25.83 seconds |
| Started | Oct 15 03:37:20 PM UTC 24 |
| Finished | Oct 15 03:37:47 PM UTC 24 |
| Peak memory | 593816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743579057 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.2743579057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.1513793609 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 2372282034 ps |
| CPU time | 73.62 seconds |
| Started | Oct 15 03:37:17 PM UTC 24 |
| Finished | Oct 15 03:38:32 PM UTC 24 |
| Peak memory | 594012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513793609 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1513793609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/34.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.1448836748 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 112900367 ps |
| CPU time | 14.92 seconds |
| Started | Oct 15 03:36:54 PM UTC 24 |
| Finished | Oct 15 03:37:10 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448836748 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.1448836748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/34.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.3974023397 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 41766139312 ps |
| CPU time | 482.29 seconds |
| Started | Oct 15 03:37:09 PM UTC 24 |
| Finished | Oct 15 03:45:18 PM UTC 24 |
| Peak memory | 594004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974023397 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3974023397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/34.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.3696489649 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 11084331511 ps |
| CPU time | 171.54 seconds |
| Started | Oct 15 03:37:11 PM UTC 24 |
| Finished | Oct 15 03:40:05 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696489649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.3696489649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/34.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.1029497748 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 533683349 ps |
| CPU time | 45.5 seconds |
| Started | Oct 15 03:36:59 PM UTC 24 |
| Finished | Oct 15 03:37:46 PM UTC 24 |
| Peak memory | 593748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029497748 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.1029497748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/34.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.3641125408 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 373413959 ps |
| CPU time | 17.47 seconds |
| Started | Oct 15 03:37:13 PM UTC 24 |
| Finished | Oct 15 03:37:32 PM UTC 24 |
| Peak memory | 593660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641125408 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3641125408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/34.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.1362628563 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 53139368 ps |
| CPU time | 7.95 seconds |
| Started | Oct 15 03:36:36 PM UTC 24 |
| Finished | Oct 15 03:36:45 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362628563 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1362628563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/34.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.2725932584 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 7664543661 ps |
| CPU time | 86.22 seconds |
| Started | Oct 15 03:36:48 PM UTC 24 |
| Finished | Oct 15 03:38:16 PM UTC 24 |
| Peak memory | 591696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725932584 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2725932584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/34.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.1596524262 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 6303517513 ps |
| CPU time | 103.48 seconds |
| Started | Oct 15 03:36:50 PM UTC 24 |
| Finished | Oct 15 03:38:36 PM UTC 24 |
| Peak memory | 591832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596524262 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1596524262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.3548272262 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 41400396 ps |
| CPU time | 5.98 seconds |
| Started | Oct 15 03:36:42 PM UTC 24 |
| Finished | Oct 15 03:36:49 PM UTC 24 |
| Peak memory | 591836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548272262 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3548272262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/34.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.1255132894 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 1857113469 ps |
| CPU time | 174.4 seconds |
| Started | Oct 15 03:37:24 PM UTC 24 |
| Finished | Oct 15 03:40:22 PM UTC 24 |
| Peak memory | 593740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255132894 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1255132894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/34.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.2515492685 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 10421371671 ps |
| CPU time | 327.53 seconds |
| Started | Oct 15 03:37:30 PM UTC 24 |
| Finished | Oct 15 03:43:02 PM UTC 24 |
| Peak memory | 593976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515492685 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2515492685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/34.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.3340916271 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 493041648 ps |
| CPU time | 174.51 seconds |
| Started | Oct 15 03:37:23 PM UTC 24 |
| Finished | Oct 15 03:40:21 PM UTC 24 |
| Peak memory | 593728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340916271 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.3340916271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.3512840071 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 1868850794 ps |
| CPU time | 278.15 seconds |
| Started | Oct 15 03:37:34 PM UTC 24 |
| Finished | Oct 15 03:42:16 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512840071 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.3512840071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.3623986144 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 891415706 ps |
| CPU time | 42.44 seconds |
| Started | Oct 15 03:37:20 PM UTC 24 |
| Finished | Oct 15 03:38:04 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623986144 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3623986144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/34.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.4236878709 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 750102623 ps |
| CPU time | 42.46 seconds |
| Started | Oct 15 03:38:10 PM UTC 24 |
| Finished | Oct 15 03:38:54 PM UTC 24 |
| Peak memory | 594044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236878709 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.4236878709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/35.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.605402911 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 61471224187 ps |
| CPU time | 948.87 seconds |
| Started | Oct 15 03:38:12 PM UTC 24 |
| Finished | Oct 15 03:54:12 PM UTC 24 |
| Peak memory | 593884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605402911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_devi ce_slow_rsp.605402911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.2774068480 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 227123353 ps |
| CPU time | 25.89 seconds |
| Started | Oct 15 03:38:15 PM UTC 24 |
| Finished | Oct 15 03:38:43 PM UTC 24 |
| Peak memory | 593676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774068480 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.2774068480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.3331246601 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 388877486 ps |
| CPU time | 15.27 seconds |
| Started | Oct 15 03:38:15 PM UTC 24 |
| Finished | Oct 15 03:38:31 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331246601 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3331246601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/35.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.3030458033 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 2572682005 ps |
| CPU time | 98.91 seconds |
| Started | Oct 15 03:37:57 PM UTC 24 |
| Finished | Oct 15 03:39:39 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030458033 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.3030458033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/35.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.4149899573 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 29193720194 ps |
| CPU time | 269.69 seconds |
| Started | Oct 15 03:38:12 PM UTC 24 |
| Finished | Oct 15 03:42:46 PM UTC 24 |
| Peak memory | 593864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149899573 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.4149899573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/35.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.1714755248 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 16786591064 ps |
| CPU time | 253.67 seconds |
| Started | Oct 15 03:38:10 PM UTC 24 |
| Finished | Oct 15 03:42:28 PM UTC 24 |
| Peak memory | 593552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714755248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1714755248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/35.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.2547883432 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 253380759 ps |
| CPU time | 22.63 seconds |
| Started | Oct 15 03:38:08 PM UTC 24 |
| Finished | Oct 15 03:38:32 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547883432 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.2547883432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/35.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.1701837884 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 295717728 ps |
| CPU time | 22.25 seconds |
| Started | Oct 15 03:38:14 PM UTC 24 |
| Finished | Oct 15 03:38:37 PM UTC 24 |
| Peak memory | 593888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701837884 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1701837884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/35.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.1344775564 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 202190471 ps |
| CPU time | 12.43 seconds |
| Started | Oct 15 03:37:37 PM UTC 24 |
| Finished | Oct 15 03:37:51 PM UTC 24 |
| Peak memory | 591804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344775564 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1344775564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/35.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.850931203 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 8722600887 ps |
| CPU time | 75.98 seconds |
| Started | Oct 15 03:37:54 PM UTC 24 |
| Finished | Oct 15 03:39:12 PM UTC 24 |
| Peak memory | 591940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850931203 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.850931203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/35.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.1670687032 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 6071921084 ps |
| CPU time | 102.3 seconds |
| Started | Oct 15 03:37:58 PM UTC 24 |
| Finished | Oct 15 03:39:43 PM UTC 24 |
| Peak memory | 591880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670687032 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1670687032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.1711906365 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 43484848 ps |
| CPU time | 8.86 seconds |
| Started | Oct 15 03:37:39 PM UTC 24 |
| Finished | Oct 15 03:37:49 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711906365 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1711906365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/35.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.1657589560 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 2938996206 ps |
| CPU time | 111.87 seconds |
| Started | Oct 15 03:38:33 PM UTC 24 |
| Finished | Oct 15 03:40:27 PM UTC 24 |
| Peak memory | 593748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657589560 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1657589560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/35.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1535167971 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 2460229986 ps |
| CPU time | 330.37 seconds |
| Started | Oct 15 03:38:27 PM UTC 24 |
| Finished | Oct 15 03:44:03 PM UTC 24 |
| Peak memory | 594028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535167971 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.1535167971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3505512299 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 527321260 ps |
| CPU time | 262.08 seconds |
| Started | Oct 15 03:38:34 PM UTC 24 |
| Finished | Oct 15 03:43:00 PM UTC 24 |
| Peak memory | 593916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505512299 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.3505512299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.3474780887 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 729455189 ps |
| CPU time | 42.67 seconds |
| Started | Oct 15 03:38:14 PM UTC 24 |
| Finished | Oct 15 03:38:58 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474780887 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3474780887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/35.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.2738819842 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 1528642628 ps |
| CPU time | 57.94 seconds |
| Started | Oct 15 03:39:18 PM UTC 24 |
| Finished | Oct 15 03:40:17 PM UTC 24 |
| Peak memory | 593692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738819842 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.2738819842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/36.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.284246181 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 21193490719 ps |
| CPU time | 354.8 seconds |
| Started | Oct 15 03:39:18 PM UTC 24 |
| Finished | Oct 15 03:45:17 PM UTC 24 |
| Peak memory | 593748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284246181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_devi ce_slow_rsp.284246181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.440022584 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 819100726 ps |
| CPU time | 43.73 seconds |
| Started | Oct 15 03:39:38 PM UTC 24 |
| Finished | Oct 15 03:40:23 PM UTC 24 |
| Peak memory | 594064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440022584 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.440022584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.2983561439 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 1303072766 ps |
| CPU time | 48.86 seconds |
| Started | Oct 15 03:39:24 PM UTC 24 |
| Finished | Oct 15 03:40:14 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983561439 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2983561439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/36.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.2002125756 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 284354038 ps |
| CPU time | 13.97 seconds |
| Started | Oct 15 03:38:59 PM UTC 24 |
| Finished | Oct 15 03:39:14 PM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002125756 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.2002125756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/36.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.2416943150 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 17303783483 ps |
| CPU time | 178.3 seconds |
| Started | Oct 15 03:39:03 PM UTC 24 |
| Finished | Oct 15 03:42:04 PM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416943150 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2416943150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/36.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.269185006 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 31890163022 ps |
| CPU time | 469.89 seconds |
| Started | Oct 15 03:39:06 PM UTC 24 |
| Finished | Oct 15 03:47:02 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269185006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.269185006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/36.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.2101527600 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 597553147 ps |
| CPU time | 45.49 seconds |
| Started | Oct 15 03:39:02 PM UTC 24 |
| Finished | Oct 15 03:39:49 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101527600 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2101527600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/36.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.238307541 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 212214458 ps |
| CPU time | 22.09 seconds |
| Started | Oct 15 03:39:20 PM UTC 24 |
| Finished | Oct 15 03:39:43 PM UTC 24 |
| Peak memory | 593676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238307541 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.238307541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/36.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.2637350906 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 51084516 ps |
| CPU time | 9.67 seconds |
| Started | Oct 15 03:38:41 PM UTC 24 |
| Finished | Oct 15 03:38:52 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637350906 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2637350906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/36.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.824023840 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 9001686295 ps |
| CPU time | 91.8 seconds |
| Started | Oct 15 03:38:58 PM UTC 24 |
| Finished | Oct 15 03:40:32 PM UTC 24 |
| Peak memory | 591872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824023840 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.824023840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/36.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.711296791 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 5479113710 ps |
| CPU time | 80.59 seconds |
| Started | Oct 15 03:38:58 PM UTC 24 |
| Finished | Oct 15 03:40:21 PM UTC 24 |
| Peak memory | 591904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711296791 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.711296791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.1827261703 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 39724691 ps |
| CPU time | 8.6 seconds |
| Started | Oct 15 03:38:55 PM UTC 24 |
| Finished | Oct 15 03:39:05 PM UTC 24 |
| Peak memory | 591812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827261703 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1827261703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/36.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.3550898829 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 10839020208 ps |
| CPU time | 330.87 seconds |
| Started | Oct 15 03:39:39 PM UTC 24 |
| Finished | Oct 15 03:45:14 PM UTC 24 |
| Peak memory | 594044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550898829 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3550898829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/36.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.132961417 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 709528743 ps |
| CPU time | 71.24 seconds |
| Started | Oct 15 03:39:48 PM UTC 24 |
| Finished | Oct 15 03:41:01 PM UTC 24 |
| Peak memory | 593812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132961417 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.132961417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/36.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.217044399 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 5931338767 ps |
| CPU time | 430.63 seconds |
| Started | Oct 15 03:39:40 PM UTC 24 |
| Finished | Oct 15 03:46:56 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217044399 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.217044399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.1127711153 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 74968780 ps |
| CPU time | 8.42 seconds |
| Started | Oct 15 03:39:33 PM UTC 24 |
| Finished | Oct 15 03:39:42 PM UTC 24 |
| Peak memory | 591888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127711153 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1127711153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/36.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.2798105554 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 510888073 ps |
| CPU time | 45.98 seconds |
| Started | Oct 15 03:40:41 PM UTC 24 |
| Finished | Oct 15 03:41:28 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798105554 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.2798105554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/37.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.1237083927 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 40329944749 ps |
| CPU time | 583.7 seconds |
| Started | Oct 15 03:40:41 PM UTC 24 |
| Finished | Oct 15 03:50:32 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237083927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_dev ice_slow_rsp.1237083927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.115544719 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 96047598 ps |
| CPU time | 14.81 seconds |
| Started | Oct 15 03:40:46 PM UTC 24 |
| Finished | Oct 15 03:41:02 PM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115544719 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.115544719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.3808991649 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 219863627 ps |
| CPU time | 18.6 seconds |
| Started | Oct 15 03:40:43 PM UTC 24 |
| Finished | Oct 15 03:41:03 PM UTC 24 |
| Peak memory | 594020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808991649 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3808991649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/37.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.4142484079 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 562182670 ps |
| CPU time | 51.43 seconds |
| Started | Oct 15 03:40:07 PM UTC 24 |
| Finished | Oct 15 03:41:01 PM UTC 24 |
| Peak memory | 593912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142484079 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.4142484079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/37.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.3051893981 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 53945375108 ps |
| CPU time | 632.39 seconds |
| Started | Oct 15 03:40:28 PM UTC 24 |
| Finished | Oct 15 03:51:09 PM UTC 24 |
| Peak memory | 594008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051893981 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3051893981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/37.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.141726780 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 23975306453 ps |
| CPU time | 397.8 seconds |
| Started | Oct 15 03:40:39 PM UTC 24 |
| Finished | Oct 15 03:47:22 PM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141726780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.141726780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/37.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.3804902694 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 165423530 ps |
| CPU time | 15.65 seconds |
| Started | Oct 15 03:40:15 PM UTC 24 |
| Finished | Oct 15 03:40:32 PM UTC 24 |
| Peak memory | 593880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804902694 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3804902694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/37.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.2555483431 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 1649988806 ps |
| CPU time | 63.35 seconds |
| Started | Oct 15 03:40:41 PM UTC 24 |
| Finished | Oct 15 03:41:46 PM UTC 24 |
| Peak memory | 593808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555483431 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2555483431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/37.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.1654380663 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 231268292 ps |
| CPU time | 13.79 seconds |
| Started | Oct 15 03:40:05 PM UTC 24 |
| Finished | Oct 15 03:40:20 PM UTC 24 |
| Peak memory | 591616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654380663 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1654380663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/37.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.256315371 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 8636052301 ps |
| CPU time | 86.27 seconds |
| Started | Oct 15 03:40:09 PM UTC 24 |
| Finished | Oct 15 03:41:37 PM UTC 24 |
| Peak memory | 592068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256315371 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.256315371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/37.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.1302879775 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 4012980638 ps |
| CPU time | 59.8 seconds |
| Started | Oct 15 03:40:08 PM UTC 24 |
| Finished | Oct 15 03:41:10 PM UTC 24 |
| Peak memory | 591824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302879775 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1302879775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.1840307398 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 39107627 ps |
| CPU time | 8.51 seconds |
| Started | Oct 15 03:40:08 PM UTC 24 |
| Finished | Oct 15 03:40:18 PM UTC 24 |
| Peak memory | 591764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840307398 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.1840307398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/37.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.946636098 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 1287138505 ps |
| CPU time | 104.66 seconds |
| Started | Oct 15 03:40:47 PM UTC 24 |
| Finished | Oct 15 03:42:34 PM UTC 24 |
| Peak memory | 594068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946636098 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.946636098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/37.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.765981687 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 1315307138 ps |
| CPU time | 105.01 seconds |
| Started | Oct 15 03:40:48 PM UTC 24 |
| Finished | Oct 15 03:42:35 PM UTC 24 |
| Peak memory | 593736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765981687 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.765981687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/37.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.1167430365 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 530381149 ps |
| CPU time | 312.35 seconds |
| Started | Oct 15 03:40:46 PM UTC 24 |
| Finished | Oct 15 03:46:03 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167430365 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.1167430365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.1523882006 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 6628759327 ps |
| CPU time | 391.16 seconds |
| Started | Oct 15 03:40:50 PM UTC 24 |
| Finished | Oct 15 03:47:27 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523882006 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.1523882006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.3767131356 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 131427190 ps |
| CPU time | 22.54 seconds |
| Started | Oct 15 03:40:42 PM UTC 24 |
| Finished | Oct 15 03:41:05 PM UTC 24 |
| Peak memory | 593840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767131356 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3767131356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/37.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.2767569446 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 1236047845 ps |
| CPU time | 88.66 seconds |
| Started | Oct 15 03:41:27 PM UTC 24 |
| Finished | Oct 15 03:42:57 PM UTC 24 |
| Peak memory | 594012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767569446 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.2767569446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/38.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.3452971280 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 142682577 ps |
| CPU time | 18.03 seconds |
| Started | Oct 15 03:41:36 PM UTC 24 |
| Finished | Oct 15 03:41:55 PM UTC 24 |
| Peak memory | 594044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452971280 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3452971280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.1005076813 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 618664286 ps |
| CPU time | 54.79 seconds |
| Started | Oct 15 03:41:30 PM UTC 24 |
| Finished | Oct 15 03:42:26 PM UTC 24 |
| Peak memory | 594016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005076813 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1005076813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/38.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.1585673803 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 138370386 ps |
| CPU time | 10.71 seconds |
| Started | Oct 15 03:41:06 PM UTC 24 |
| Finished | Oct 15 03:41:17 PM UTC 24 |
| Peak memory | 591760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585673803 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.1585673803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/38.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.1846668514 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 44058382255 ps |
| CPU time | 411.32 seconds |
| Started | Oct 15 03:41:29 PM UTC 24 |
| Finished | Oct 15 03:48:25 PM UTC 24 |
| Peak memory | 593876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846668514 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1846668514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/38.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.118304894 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 20830935687 ps |
| CPU time | 292.64 seconds |
| Started | Oct 15 03:41:26 PM UTC 24 |
| Finished | Oct 15 03:46:23 PM UTC 24 |
| Peak memory | 593884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118304894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.118304894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/38.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.3361359522 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 321124365 ps |
| CPU time | 27.98 seconds |
| Started | Oct 15 03:41:03 PM UTC 24 |
| Finished | Oct 15 03:41:32 PM UTC 24 |
| Peak memory | 593764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361359522 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.3361359522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/38.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.4189868931 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 1447625098 ps |
| CPU time | 47.26 seconds |
| Started | Oct 15 03:41:28 PM UTC 24 |
| Finished | Oct 15 03:42:17 PM UTC 24 |
| Peak memory | 593808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189868931 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.4189868931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/38.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.821018534 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 38177446 ps |
| CPU time | 6.5 seconds |
| Started | Oct 15 03:40:53 PM UTC 24 |
| Finished | Oct 15 03:41:00 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821018534 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.821018534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/38.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.2560658177 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 5878062606 ps |
| CPU time | 63.93 seconds |
| Started | Oct 15 03:40:57 PM UTC 24 |
| Finished | Oct 15 03:42:03 PM UTC 24 |
| Peak memory | 591916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560658177 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2560658177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/38.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.2755338161 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 4227688723 ps |
| CPU time | 73.07 seconds |
| Started | Oct 15 03:40:56 PM UTC 24 |
| Finished | Oct 15 03:42:11 PM UTC 24 |
| Peak memory | 591940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755338161 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2755338161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.2437889311 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 52324570 ps |
| CPU time | 6.39 seconds |
| Started | Oct 15 03:40:53 PM UTC 24 |
| Finished | Oct 15 03:41:01 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437889311 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2437889311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/38.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.909635809 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 2230429160 ps |
| CPU time | 241.91 seconds |
| Started | Oct 15 03:41:41 PM UTC 24 |
| Finished | Oct 15 03:45:48 PM UTC 24 |
| Peak memory | 594024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909635809 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.909635809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/38.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.2645417992 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 30524197 ps |
| CPU time | 15.08 seconds |
| Started | Oct 15 03:41:45 PM UTC 24 |
| Finished | Oct 15 03:42:01 PM UTC 24 |
| Peak memory | 591812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645417992 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.2645417992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.1008175871 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 154566759 ps |
| CPU time | 35.59 seconds |
| Started | Oct 15 03:41:49 PM UTC 24 |
| Finished | Oct 15 03:42:27 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008175871 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.1008175871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.2384382207 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 90045899 ps |
| CPU time | 16.61 seconds |
| Started | Oct 15 03:41:31 PM UTC 24 |
| Finished | Oct 15 03:41:49 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384382207 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.2384382207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/38.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.1884179661 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 3180362285 ps |
| CPU time | 125.97 seconds |
| Started | Oct 15 03:42:26 PM UTC 24 |
| Finished | Oct 15 03:44:35 PM UTC 24 |
| Peak memory | 593752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884179661 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.1884179661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/39.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.3285239460 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 11842982785 ps |
| CPU time | 163.26 seconds |
| Started | Oct 15 03:42:29 PM UTC 24 |
| Finished | Oct 15 03:45:15 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285239460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_dev ice_slow_rsp.3285239460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.1340340300 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 1262794114 ps |
| CPU time | 57.7 seconds |
| Started | Oct 15 03:42:37 PM UTC 24 |
| Finished | Oct 15 03:43:37 PM UTC 24 |
| Peak memory | 593676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340340300 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.1340340300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.1124454598 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 2378789404 ps |
| CPU time | 79.17 seconds |
| Started | Oct 15 03:42:33 PM UTC 24 |
| Finished | Oct 15 03:43:53 PM UTC 24 |
| Peak memory | 593892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124454598 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1124454598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/39.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.1251409241 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 807412213 ps |
| CPU time | 31.58 seconds |
| Started | Oct 15 03:42:16 PM UTC 24 |
| Finished | Oct 15 03:42:49 PM UTC 24 |
| Peak memory | 594084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251409241 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.1251409241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/39.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.1227157222 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 31432403376 ps |
| CPU time | 337.93 seconds |
| Started | Oct 15 03:42:24 PM UTC 24 |
| Finished | Oct 15 03:48:07 PM UTC 24 |
| Peak memory | 594092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227157222 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1227157222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/39.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.4010668795 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 29984047985 ps |
| CPU time | 431.92 seconds |
| Started | Oct 15 03:42:26 PM UTC 24 |
| Finished | Oct 15 03:49:43 PM UTC 24 |
| Peak memory | 594152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010668795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.4010668795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/39.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.3239416318 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 258245208 ps |
| CPU time | 22.54 seconds |
| Started | Oct 15 03:42:20 PM UTC 24 |
| Finished | Oct 15 03:42:44 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239416318 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.3239416318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/39.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.3587941969 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 241953017 ps |
| CPU time | 19.24 seconds |
| Started | Oct 15 03:42:32 PM UTC 24 |
| Finished | Oct 15 03:42:52 PM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587941969 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3587941969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/39.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.3875426930 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 147226767 ps |
| CPU time | 11.21 seconds |
| Started | Oct 15 03:41:54 PM UTC 24 |
| Finished | Oct 15 03:42:07 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875426930 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3875426930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/39.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.3227504020 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 9321243238 ps |
| CPU time | 84.33 seconds |
| Started | Oct 15 03:42:04 PM UTC 24 |
| Finished | Oct 15 03:43:31 PM UTC 24 |
| Peak memory | 592048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227504020 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3227504020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/39.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1248471082 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 4506498558 ps |
| CPU time | 64.14 seconds |
| Started | Oct 15 03:42:12 PM UTC 24 |
| Finished | Oct 15 03:43:17 PM UTC 24 |
| Peak memory | 592072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248471082 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1248471082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.441562963 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 57951181 ps |
| CPU time | 8.22 seconds |
| Started | Oct 15 03:42:00 PM UTC 24 |
| Finished | Oct 15 03:42:09 PM UTC 24 |
| Peak memory | 592048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441562963 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.441562963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/39.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.1090515397 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 9901670194 ps |
| CPU time | 294.93 seconds |
| Started | Oct 15 03:42:42 PM UTC 24 |
| Finished | Oct 15 03:47:41 PM UTC 24 |
| Peak memory | 594044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090515397 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1090515397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/39.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.2150964257 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 344683537 ps |
| CPU time | 24.1 seconds |
| Started | Oct 15 03:42:48 PM UTC 24 |
| Finished | Oct 15 03:43:13 PM UTC 24 |
| Peak memory | 594108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150964257 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2150964257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/39.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.3371473885 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 133417490 ps |
| CPU time | 23.53 seconds |
| Started | Oct 15 03:42:42 PM UTC 24 |
| Finished | Oct 15 03:43:06 PM UTC 24 |
| Peak memory | 593728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371473885 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.3371473885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.2166621472 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 7488334160 ps |
| CPU time | 767.09 seconds |
| Started | Oct 15 03:42:50 PM UTC 24 |
| Finished | Oct 15 03:55:47 PM UTC 24 |
| Peak memory | 598104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166621472 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.2166621472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.2360428870 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 24954094 ps |
| CPU time | 7.37 seconds |
| Started | Oct 15 03:42:37 PM UTC 24 |
| Finished | Oct 15 03:42:45 PM UTC 24 |
| Peak memory | 591632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360428870 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2360428870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/39.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.263025203 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 13969947818 ps |
| CPU time | 1528.47 seconds |
| Started | Oct 15 02:43:27 PM UTC 24 |
| Finished | Oct 15 03:09:13 PM UTC 24 |
| Peak memory | 615144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=263025203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.chip_csr_bit_bash.263025203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.914236984 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 4875458080 ps |
| CPU time | 250.14 seconds |
| Started | Oct 15 02:46:15 PM UTC 24 |
| Finished | Oct 15 02:50:29 PM UTC 24 |
| Peak memory | 678412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914236984 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_reset.914236984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.3496066123 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 10534005558 ps |
| CPU time | 998.67 seconds |
| Started | Oct 15 02:46:27 PM UTC 24 |
| Finished | Oct 15 03:03:18 PM UTC 24 |
| Peak memory | 668236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3496066123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.chip_csr_mem_rw_with_rand_reset.3496066123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.3929903910 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 6360720823 ps |
| CPU time | 757.72 seconds |
| Started | Oct 15 02:46:17 PM UTC 24 |
| Finished | Oct 15 02:59:04 PM UTC 24 |
| Peak memory | 617244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929903910 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.3929903910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.3436145455 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 14858367659 ps |
| CPU time | 1658.1 seconds |
| Started | Oct 15 02:43:34 PM UTC 24 |
| Finished | Oct 15 03:11:32 PM UTC 24 |
| Peak memory | 608916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3436145455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.chip_same_csr_outstanding.3436145455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.1259236638 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 1564157721 ps |
| CPU time | 69.01 seconds |
| Started | Oct 15 02:44:39 PM UTC 24 |
| Finished | Oct 15 02:45:50 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259236638 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.1259236638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.4122771346 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 53785990484 ps |
| CPU time | 734.28 seconds |
| Started | Oct 15 02:44:57 PM UTC 24 |
| Finished | Oct 15 02:57:20 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122771346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_devi ce_slow_rsp.4122771346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.3435902402 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 960911342 ps |
| CPU time | 51.98 seconds |
| Started | Oct 15 02:45:43 PM UTC 24 |
| Finished | Oct 15 02:46:37 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435902402 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3435902402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.3372291526 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 387762847 ps |
| CPU time | 17.83 seconds |
| Started | Oct 15 02:45:31 PM UTC 24 |
| Finished | Oct 15 02:45:50 PM UTC 24 |
| Peak memory | 593676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372291526 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3372291526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.2884699151 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 1501941782 ps |
| CPU time | 56.61 seconds |
| Started | Oct 15 02:44:14 PM UTC 24 |
| Finished | Oct 15 02:45:12 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884699151 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.2884699151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.2638842106 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 18087067219 ps |
| CPU time | 204.62 seconds |
| Started | Oct 15 02:44:23 PM UTC 24 |
| Finished | Oct 15 02:47:51 PM UTC 24 |
| Peak memory | 594132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638842106 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2638842106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.1771591452 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 21540921606 ps |
| CPU time | 356.02 seconds |
| Started | Oct 15 02:44:27 PM UTC 24 |
| Finished | Oct 15 02:50:28 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771591452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1771591452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.3283910137 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 429389018 ps |
| CPU time | 48.74 seconds |
| Started | Oct 15 02:44:14 PM UTC 24 |
| Finished | Oct 15 02:45:04 PM UTC 24 |
| Peak memory | 594064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283910137 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.3283910137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.3812361079 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 2612277876 ps |
| CPU time | 96.76 seconds |
| Started | Oct 15 02:45:08 PM UTC 24 |
| Finished | Oct 15 02:46:47 PM UTC 24 |
| Peak memory | 594016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812361079 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3812361079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.2467758391 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 51335017 ps |
| CPU time | 6.53 seconds |
| Started | Oct 15 02:43:39 PM UTC 24 |
| Finished | Oct 15 02:43:47 PM UTC 24 |
| Peak memory | 591736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467758391 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2467758391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.198468444 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 8311402761 ps |
| CPU time | 93.77 seconds |
| Started | Oct 15 02:43:59 PM UTC 24 |
| Finished | Oct 15 02:45:34 PM UTC 24 |
| Peak memory | 592044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198468444 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.198468444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.1570590969 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 5078856422 ps |
| CPU time | 119.46 seconds |
| Started | Oct 15 02:44:09 PM UTC 24 |
| Finished | Oct 15 02:46:11 PM UTC 24 |
| Peak memory | 592072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570590969 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1570590969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.554515486 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 45037408 ps |
| CPU time | 9.16 seconds |
| Started | Oct 15 02:43:50 PM UTC 24 |
| Finished | Oct 15 02:44:00 PM UTC 24 |
| Peak memory | 591828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554515486 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.554515486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.2642398390 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 4141514901 ps |
| CPU time | 388.93 seconds |
| Started | Oct 15 02:45:46 PM UTC 24 |
| Finished | Oct 15 02:52:21 PM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642398390 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2642398390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.1049546085 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 6716813080 ps |
| CPU time | 227.77 seconds |
| Started | Oct 15 02:46:12 PM UTC 24 |
| Finished | Oct 15 02:50:03 PM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049546085 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1049546085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.681149008 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 108212306 ps |
| CPU time | 58.87 seconds |
| Started | Oct 15 02:46:01 PM UTC 24 |
| Finished | Oct 15 02:47:02 PM UTC 24 |
| Peak memory | 593992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681149008 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.681149008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.1674724425 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 12494595142 ps |
| CPU time | 546.88 seconds |
| Started | Oct 15 02:46:12 PM UTC 24 |
| Finished | Oct 15 02:55:26 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674724425 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.1674724425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.188249142 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 585923089 ps |
| CPU time | 28.7 seconds |
| Started | Oct 15 02:45:37 PM UTC 24 |
| Finished | Oct 15 02:46:07 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188249142 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.188249142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.3808123954 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 321949735 ps |
| CPU time | 30.46 seconds |
| Started | Oct 15 03:43:15 PM UTC 24 |
| Finished | Oct 15 03:43:47 PM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808123954 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3808123954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/40.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3798616567 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 45579012918 ps |
| CPU time | 653.53 seconds |
| Started | Oct 15 03:43:20 PM UTC 24 |
| Finished | Oct 15 03:54:22 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798616567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_dev ice_slow_rsp.3798616567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.760051946 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 117256743 ps |
| CPU time | 17.55 seconds |
| Started | Oct 15 03:43:23 PM UTC 24 |
| Finished | Oct 15 03:43:42 PM UTC 24 |
| Peak memory | 593880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760051946 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.760051946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.415255845 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 59334790 ps |
| CPU time | 11.27 seconds |
| Started | Oct 15 03:43:21 PM UTC 24 |
| Finished | Oct 15 03:43:34 PM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415255845 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.415255845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/40.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.2443349838 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 1863082405 ps |
| CPU time | 74.29 seconds |
| Started | Oct 15 03:43:06 PM UTC 24 |
| Finished | Oct 15 03:44:23 PM UTC 24 |
| Peak memory | 593860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443349838 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.2443349838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/40.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.2479599431 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 52441559786 ps |
| CPU time | 691.66 seconds |
| Started | Oct 15 03:43:10 PM UTC 24 |
| Finished | Oct 15 03:54:51 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479599431 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2479599431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/40.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.3952691319 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 23203770082 ps |
| CPU time | 360.66 seconds |
| Started | Oct 15 03:43:11 PM UTC 24 |
| Finished | Oct 15 03:49:17 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952691319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3952691319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/40.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.3693954614 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 350956755 ps |
| CPU time | 30.99 seconds |
| Started | Oct 15 03:43:09 PM UTC 24 |
| Finished | Oct 15 03:43:42 PM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693954614 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.3693954614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/40.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.4004884222 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 136568286 ps |
| CPU time | 10.68 seconds |
| Started | Oct 15 03:43:19 PM UTC 24 |
| Finished | Oct 15 03:43:31 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004884222 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.4004884222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/40.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.2094042612 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 38770924 ps |
| CPU time | 8.78 seconds |
| Started | Oct 15 03:42:50 PM UTC 24 |
| Finished | Oct 15 03:42:59 PM UTC 24 |
| Peak memory | 591940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094042612 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2094042612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/40.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.20348665 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 6337019191 ps |
| CPU time | 68.87 seconds |
| Started | Oct 15 03:43:01 PM UTC 24 |
| Finished | Oct 15 03:44:11 PM UTC 24 |
| Peak memory | 591832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20348665 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.20348665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/40.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.2975718118 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 5736732491 ps |
| CPU time | 94.97 seconds |
| Started | Oct 15 03:43:00 PM UTC 24 |
| Finished | Oct 15 03:44:37 PM UTC 24 |
| Peak memory | 592012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975718118 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2975718118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.2688929976 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 38907544 ps |
| CPU time | 6.79 seconds |
| Started | Oct 15 03:42:53 PM UTC 24 |
| Finished | Oct 15 03:43:01 PM UTC 24 |
| Peak memory | 590812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688929976 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.2688929976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/40.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.3171302036 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 7537949185 ps |
| CPU time | 243.17 seconds |
| Started | Oct 15 03:43:26 PM UTC 24 |
| Finished | Oct 15 03:47:33 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171302036 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3171302036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/40.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.311346156 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 10852774480 ps |
| CPU time | 399.15 seconds |
| Started | Oct 15 03:43:32 PM UTC 24 |
| Finished | Oct 15 03:50:17 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311346156 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.311346156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/40.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.2290711108 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 71741232 ps |
| CPU time | 31.09 seconds |
| Started | Oct 15 03:43:29 PM UTC 24 |
| Finished | Oct 15 03:44:01 PM UTC 24 |
| Peak memory | 593724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290711108 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.2290711108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.870510393 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 450411282 ps |
| CPU time | 195.13 seconds |
| Started | Oct 15 03:43:38 PM UTC 24 |
| Finished | Oct 15 03:46:56 PM UTC 24 |
| Peak memory | 594148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870510393 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.870510393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.3744542784 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 703164347 ps |
| CPU time | 44.59 seconds |
| Started | Oct 15 03:43:28 PM UTC 24 |
| Finished | Oct 15 03:44:14 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744542784 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3744542784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/40.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.3970794140 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 2053464497 ps |
| CPU time | 89.08 seconds |
| Started | Oct 15 03:44:17 PM UTC 24 |
| Finished | Oct 15 03:45:48 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970794140 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.3970794140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/41.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2374863763 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 60894706980 ps |
| CPU time | 854.65 seconds |
| Started | Oct 15 03:44:21 PM UTC 24 |
| Finished | Oct 15 03:58:45 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374863763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_dev ice_slow_rsp.2374863763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.3633580871 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 22854056 ps |
| CPU time | 7.48 seconds |
| Started | Oct 15 03:44:34 PM UTC 24 |
| Finished | Oct 15 03:44:42 PM UTC 24 |
| Peak memory | 591756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633580871 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.3633580871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.3230014448 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 653601513 ps |
| CPU time | 25.82 seconds |
| Started | Oct 15 03:44:27 PM UTC 24 |
| Finished | Oct 15 03:44:54 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230014448 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3230014448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/41.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.54551863 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 557409101 ps |
| CPU time | 46.12 seconds |
| Started | Oct 15 03:44:04 PM UTC 24 |
| Finished | Oct 15 03:44:51 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54551863 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.54551863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/41.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.3157274922 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 40718741781 ps |
| CPU time | 523.49 seconds |
| Started | Oct 15 03:44:09 PM UTC 24 |
| Finished | Oct 15 03:52:59 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157274922 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3157274922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/41.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.1333108830 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 1941980295 ps |
| CPU time | 35.75 seconds |
| Started | Oct 15 03:44:15 PM UTC 24 |
| Finished | Oct 15 03:44:52 PM UTC 24 |
| Peak memory | 591828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333108830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1333108830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/41.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.2649342776 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 303938534 ps |
| CPU time | 27.14 seconds |
| Started | Oct 15 03:44:06 PM UTC 24 |
| Finished | Oct 15 03:44:35 PM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649342776 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.2649342776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/41.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.1444592787 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 2527612189 ps |
| CPU time | 98 seconds |
| Started | Oct 15 03:44:27 PM UTC 24 |
| Finished | Oct 15 03:46:07 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444592787 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1444592787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/41.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.2002034001 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 246207709 ps |
| CPU time | 10.23 seconds |
| Started | Oct 15 03:43:39 PM UTC 24 |
| Finished | Oct 15 03:43:50 PM UTC 24 |
| Peak memory | 591732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002034001 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2002034001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/41.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.2207307759 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 9439751618 ps |
| CPU time | 102.94 seconds |
| Started | Oct 15 03:43:56 PM UTC 24 |
| Finished | Oct 15 03:45:41 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207307759 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2207307759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/41.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.1789992579 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 4038264290 ps |
| CPU time | 51.59 seconds |
| Started | Oct 15 03:43:59 PM UTC 24 |
| Finished | Oct 15 03:44:52 PM UTC 24 |
| Peak memory | 591944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789992579 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1789992579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.2299516837 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 43834821 ps |
| CPU time | 8.97 seconds |
| Started | Oct 15 03:43:56 PM UTC 24 |
| Finished | Oct 15 03:44:06 PM UTC 24 |
| Peak memory | 591756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299516837 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2299516837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/41.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.1691858588 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 377773010 ps |
| CPU time | 17.61 seconds |
| Started | Oct 15 03:44:37 PM UTC 24 |
| Finished | Oct 15 03:44:55 PM UTC 24 |
| Peak memory | 594028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691858588 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1691858588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/41.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.398982888 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 5874276497 ps |
| CPU time | 222.84 seconds |
| Started | Oct 15 03:44:51 PM UTC 24 |
| Finished | Oct 15 03:48:37 PM UTC 24 |
| Peak memory | 593748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398982888 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.398982888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/41.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3301361949 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 119709709 ps |
| CPU time | 30.28 seconds |
| Started | Oct 15 03:44:41 PM UTC 24 |
| Finished | Oct 15 03:45:13 PM UTC 24 |
| Peak memory | 593952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301361949 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.3301361949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.606555814 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 470541925 ps |
| CPU time | 166.29 seconds |
| Started | Oct 15 03:44:47 PM UTC 24 |
| Finished | Oct 15 03:47:37 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606555814 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.606555814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.2535156047 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 265707680 ps |
| CPU time | 35.52 seconds |
| Started | Oct 15 03:44:29 PM UTC 24 |
| Finished | Oct 15 03:45:06 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535156047 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2535156047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/41.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.3822330099 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 108524178 ps |
| CPU time | 14.23 seconds |
| Started | Oct 15 03:45:20 PM UTC 24 |
| Finished | Oct 15 03:45:35 PM UTC 24 |
| Peak memory | 591832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822330099 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3822330099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/42.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.1620053976 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 71915811046 ps |
| CPU time | 1092.81 seconds |
| Started | Oct 15 03:45:23 PM UTC 24 |
| Finished | Oct 15 04:03:49 PM UTC 24 |
| Peak memory | 593888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620053976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_dev ice_slow_rsp.1620053976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.4294764102 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 840813660 ps |
| CPU time | 39.94 seconds |
| Started | Oct 15 03:45:40 PM UTC 24 |
| Finished | Oct 15 03:46:21 PM UTC 24 |
| Peak memory | 593876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294764102 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.4294764102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.1713954416 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 604374001 ps |
| CPU time | 56.48 seconds |
| Started | Oct 15 03:45:36 PM UTC 24 |
| Finished | Oct 15 03:46:34 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713954416 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1713954416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/42.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.1392510896 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 484662658 ps |
| CPU time | 23.11 seconds |
| Started | Oct 15 03:45:06 PM UTC 24 |
| Finished | Oct 15 03:45:31 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392510896 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.1392510896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/42.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.4121296699 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 10652917523 ps |
| CPU time | 103.88 seconds |
| Started | Oct 15 03:45:17 PM UTC 24 |
| Finished | Oct 15 03:47:03 PM UTC 24 |
| Peak memory | 594156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121296699 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.4121296699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/42.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.1496834118 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 29748795674 ps |
| CPU time | 460.54 seconds |
| Started | Oct 15 03:45:18 PM UTC 24 |
| Finished | Oct 15 03:53:05 PM UTC 24 |
| Peak memory | 593984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496834118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1496834118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/42.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.3570320663 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 555018179 ps |
| CPU time | 52.31 seconds |
| Started | Oct 15 03:45:18 PM UTC 24 |
| Finished | Oct 15 03:46:12 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570320663 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.3570320663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/42.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.731818995 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 1477986886 ps |
| CPU time | 41.27 seconds |
| Started | Oct 15 03:45:33 PM UTC 24 |
| Finished | Oct 15 03:46:15 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731818995 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.731818995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/42.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.1861429983 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 179683939 ps |
| CPU time | 11.82 seconds |
| Started | Oct 15 03:44:59 PM UTC 24 |
| Finished | Oct 15 03:45:12 PM UTC 24 |
| Peak memory | 591736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861429983 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1861429983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/42.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.842137853 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 8364723977 ps |
| CPU time | 117.53 seconds |
| Started | Oct 15 03:45:00 PM UTC 24 |
| Finished | Oct 15 03:47:00 PM UTC 24 |
| Peak memory | 591928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842137853 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.842137853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/42.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.2680674884 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 3803975739 ps |
| CPU time | 57.83 seconds |
| Started | Oct 15 03:45:02 PM UTC 24 |
| Finished | Oct 15 03:46:01 PM UTC 24 |
| Peak memory | 591888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680674884 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.2680674884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.1942907053 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 60568482 ps |
| CPU time | 10.24 seconds |
| Started | Oct 15 03:45:02 PM UTC 24 |
| Finished | Oct 15 03:45:13 PM UTC 24 |
| Peak memory | 591880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942907053 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.1942907053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/42.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.3917978775 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 2426393066 ps |
| CPU time | 182.45 seconds |
| Started | Oct 15 03:45:37 PM UTC 24 |
| Finished | Oct 15 03:48:43 PM UTC 24 |
| Peak memory | 593952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917978775 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3917978775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/42.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.4164385918 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 3606617365 ps |
| CPU time | 120.49 seconds |
| Started | Oct 15 03:45:37 PM UTC 24 |
| Finished | Oct 15 03:47:40 PM UTC 24 |
| Peak memory | 593988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164385918 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.4164385918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/42.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2874860152 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 6935899207 ps |
| CPU time | 398.4 seconds |
| Started | Oct 15 03:45:40 PM UTC 24 |
| Finished | Oct 15 03:52:23 PM UTC 24 |
| Peak memory | 594044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874860152 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.2874860152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.1908002325 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 3166608660 ps |
| CPU time | 320.99 seconds |
| Started | Oct 15 03:45:39 PM UTC 24 |
| Finished | Oct 15 03:51:05 PM UTC 24 |
| Peak memory | 594016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908002325 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.1908002325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.2022289147 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 1074723671 ps |
| CPU time | 60.33 seconds |
| Started | Oct 15 03:45:36 PM UTC 24 |
| Finished | Oct 15 03:46:38 PM UTC 24 |
| Peak memory | 593672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022289147 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2022289147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/42.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.1904042308 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 3131713490 ps |
| CPU time | 115.82 seconds |
| Started | Oct 15 03:46:20 PM UTC 24 |
| Finished | Oct 15 03:48:18 PM UTC 24 |
| Peak memory | 593756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904042308 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.1904042308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/43.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.4046249540 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 274560129 ps |
| CPU time | 27.32 seconds |
| Started | Oct 15 03:46:39 PM UTC 24 |
| Finished | Oct 15 03:47:08 PM UTC 24 |
| Peak memory | 593752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046249540 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.4046249540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.837642033 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 39064401 ps |
| CPU time | 8.61 seconds |
| Started | Oct 15 03:46:26 PM UTC 24 |
| Finished | Oct 15 03:46:36 PM UTC 24 |
| Peak memory | 591632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837642033 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.837642033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/43.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.1854953722 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 2116728388 ps |
| CPU time | 91.31 seconds |
| Started | Oct 15 03:45:59 PM UTC 24 |
| Finished | Oct 15 03:47:32 PM UTC 24 |
| Peak memory | 593808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854953722 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.1854953722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/43.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.956103041 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 34728557289 ps |
| CPU time | 370.13 seconds |
| Started | Oct 15 03:46:13 PM UTC 24 |
| Finished | Oct 15 03:52:28 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956103041 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.956103041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/43.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.3926149595 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 10540454773 ps |
| CPU time | 170.85 seconds |
| Started | Oct 15 03:46:08 PM UTC 24 |
| Finished | Oct 15 03:49:03 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926149595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3926149595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/43.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.3435831469 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 311846356 ps |
| CPU time | 36 seconds |
| Started | Oct 15 03:46:05 PM UTC 24 |
| Finished | Oct 15 03:46:42 PM UTC 24 |
| Peak memory | 594020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435831469 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.3435831469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/43.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.1656021069 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 1746193216 ps |
| CPU time | 58.88 seconds |
| Started | Oct 15 03:46:24 PM UTC 24 |
| Finished | Oct 15 03:47:25 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656021069 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1656021069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/43.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.4037310212 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 168180851 ps |
| CPU time | 11.55 seconds |
| Started | Oct 15 03:45:41 PM UTC 24 |
| Finished | Oct 15 03:45:54 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037310212 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.4037310212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/43.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.3009899563 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 7711663457 ps |
| CPU time | 109.03 seconds |
| Started | Oct 15 03:45:49 PM UTC 24 |
| Finished | Oct 15 03:47:40 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009899563 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3009899563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/43.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.2928696094 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 5044309277 ps |
| CPU time | 73.1 seconds |
| Started | Oct 15 03:45:58 PM UTC 24 |
| Finished | Oct 15 03:47:13 PM UTC 24 |
| Peak memory | 591880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928696094 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2928696094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.3229272676 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 46047469 ps |
| CPU time | 8 seconds |
| Started | Oct 15 03:45:50 PM UTC 24 |
| Finished | Oct 15 03:45:59 PM UTC 24 |
| Peak memory | 591744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229272676 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3229272676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/43.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.2184035568 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 10128259173 ps |
| CPU time | 354.86 seconds |
| Started | Oct 15 03:46:42 PM UTC 24 |
| Finished | Oct 15 03:52:42 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184035568 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2184035568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/43.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.1697865785 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 11585797127 ps |
| CPU time | 390.35 seconds |
| Started | Oct 15 03:46:48 PM UTC 24 |
| Finished | Oct 15 03:53:24 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697865785 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1697865785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/43.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.3206890448 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 103379406 ps |
| CPU time | 127.5 seconds |
| Started | Oct 15 03:46:48 PM UTC 24 |
| Finished | Oct 15 03:48:58 PM UTC 24 |
| Peak memory | 593728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206890448 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.3206890448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.2559514075 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 5970817795 ps |
| CPU time | 637.63 seconds |
| Started | Oct 15 03:47:01 PM UTC 24 |
| Finished | Oct 15 03:57:47 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559514075 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.2559514075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.213670602 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 86656668 ps |
| CPU time | 8.46 seconds |
| Started | Oct 15 03:46:30 PM UTC 24 |
| Finished | Oct 15 03:46:40 PM UTC 24 |
| Peak memory | 591776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213670602 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.213670602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/43.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.3721975140 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 305675886 ps |
| CPU time | 31.33 seconds |
| Started | Oct 15 03:47:25 PM UTC 24 |
| Finished | Oct 15 03:47:57 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721975140 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.3721975140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/44.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1108819018 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 52381827716 ps |
| CPU time | 812.87 seconds |
| Started | Oct 15 03:47:33 PM UTC 24 |
| Finished | Oct 15 04:01:16 PM UTC 24 |
| Peak memory | 593916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108819018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_dev ice_slow_rsp.1108819018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.3586889016 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 212161737 ps |
| CPU time | 24.51 seconds |
| Started | Oct 15 03:47:46 PM UTC 24 |
| Finished | Oct 15 03:48:12 PM UTC 24 |
| Peak memory | 593860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586889016 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.3586889016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.3316295350 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 2012191581 ps |
| CPU time | 58.53 seconds |
| Started | Oct 15 03:47:42 PM UTC 24 |
| Finished | Oct 15 03:48:42 PM UTC 24 |
| Peak memory | 593808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316295350 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3316295350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/44.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.1379238216 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 274441337 ps |
| CPU time | 26.86 seconds |
| Started | Oct 15 03:47:22 PM UTC 24 |
| Finished | Oct 15 03:47:50 PM UTC 24 |
| Peak memory | 593860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379238216 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.1379238216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/44.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.1240653341 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 20979590407 ps |
| CPU time | 199.93 seconds |
| Started | Oct 15 03:47:21 PM UTC 24 |
| Finished | Oct 15 03:50:44 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240653341 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1240653341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/44.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.2059801314 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 2410112159 ps |
| CPU time | 47.71 seconds |
| Started | Oct 15 03:47:26 PM UTC 24 |
| Finished | Oct 15 03:48:15 PM UTC 24 |
| Peak memory | 591832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059801314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2059801314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/44.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.935415953 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 278145787 ps |
| CPU time | 28.7 seconds |
| Started | Oct 15 03:47:25 PM UTC 24 |
| Finished | Oct 15 03:47:55 PM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935415953 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.935415953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/44.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.1409086964 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 1856593517 ps |
| CPU time | 64.74 seconds |
| Started | Oct 15 03:47:38 PM UTC 24 |
| Finished | Oct 15 03:48:44 PM UTC 24 |
| Peak memory | 593808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409086964 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1409086964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/44.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.4054231501 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 48806191 ps |
| CPU time | 9.62 seconds |
| Started | Oct 15 03:47:04 PM UTC 24 |
| Finished | Oct 15 03:47:14 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054231501 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.4054231501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/44.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.1532646854 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 7087354364 ps |
| CPU time | 108.24 seconds |
| Started | Oct 15 03:47:05 PM UTC 24 |
| Finished | Oct 15 03:48:55 PM UTC 24 |
| Peak memory | 591888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532646854 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1532646854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/44.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.848269647 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 4009713029 ps |
| CPU time | 67.92 seconds |
| Started | Oct 15 03:47:08 PM UTC 24 |
| Finished | Oct 15 03:48:18 PM UTC 24 |
| Peak memory | 591936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848269647 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.848269647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.1429586207 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 48887558 ps |
| CPU time | 9.02 seconds |
| Started | Oct 15 03:47:05 PM UTC 24 |
| Finished | Oct 15 03:47:15 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429586207 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.1429586207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/44.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.3350881673 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 2303785570 ps |
| CPU time | 232.21 seconds |
| Started | Oct 15 03:47:47 PM UTC 24 |
| Finished | Oct 15 03:51:43 PM UTC 24 |
| Peak memory | 594164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350881673 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3350881673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/44.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.2397489058 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 2684625117 ps |
| CPU time | 215.69 seconds |
| Started | Oct 15 03:47:51 PM UTC 24 |
| Finished | Oct 15 03:51:31 PM UTC 24 |
| Peak memory | 594052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397489058 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2397489058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/44.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.3229597025 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 1930685645 ps |
| CPU time | 207.45 seconds |
| Started | Oct 15 03:47:54 PM UTC 24 |
| Finished | Oct 15 03:51:25 PM UTC 24 |
| Peak memory | 593728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229597025 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.3229597025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.2650466583 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 155932712 ps |
| CPU time | 81.62 seconds |
| Started | Oct 15 03:47:59 PM UTC 24 |
| Finished | Oct 15 03:49:23 PM UTC 24 |
| Peak memory | 593720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650466583 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.2650466583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.2196741507 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 260913055 ps |
| CPU time | 33.36 seconds |
| Started | Oct 15 03:47:41 PM UTC 24 |
| Finished | Oct 15 03:48:16 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196741507 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2196741507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/44.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.139042364 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 169295384 ps |
| CPU time | 11.51 seconds |
| Started | Oct 15 03:48:33 PM UTC 24 |
| Finished | Oct 15 03:48:46 PM UTC 24 |
| Peak memory | 591876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139042364 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.139042364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/45.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.1668880483 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 36919864305 ps |
| CPU time | 573.24 seconds |
| Started | Oct 15 03:48:33 PM UTC 24 |
| Finished | Oct 15 03:58:14 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668880483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_dev ice_slow_rsp.1668880483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.4229861557 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 249692302 ps |
| CPU time | 17.2 seconds |
| Started | Oct 15 03:48:39 PM UTC 24 |
| Finished | Oct 15 03:48:58 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229861557 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.4229861557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.2399718373 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 1209842252 ps |
| CPU time | 49.09 seconds |
| Started | Oct 15 03:48:40 PM UTC 24 |
| Finished | Oct 15 03:49:31 PM UTC 24 |
| Peak memory | 593824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399718373 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2399718373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/45.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.710730224 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 62455563 ps |
| CPU time | 11.94 seconds |
| Started | Oct 15 03:48:15 PM UTC 24 |
| Finished | Oct 15 03:48:28 PM UTC 24 |
| Peak memory | 593824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710730224 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.710730224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/45.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.668674451 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 12852792833 ps |
| CPU time | 138.38 seconds |
| Started | Oct 15 03:48:22 PM UTC 24 |
| Finished | Oct 15 03:50:43 PM UTC 24 |
| Peak memory | 593944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668674451 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.668674451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/45.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.2854029505 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 25962913838 ps |
| CPU time | 358.14 seconds |
| Started | Oct 15 03:48:24 PM UTC 24 |
| Finished | Oct 15 03:54:27 PM UTC 24 |
| Peak memory | 593748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854029505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2854029505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/45.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.4083093267 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 455006489 ps |
| CPU time | 47.54 seconds |
| Started | Oct 15 03:48:17 PM UTC 24 |
| Finished | Oct 15 03:49:06 PM UTC 24 |
| Peak memory | 594020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083093267 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.4083093267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/45.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.3432292059 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 354972946 ps |
| CPU time | 25.35 seconds |
| Started | Oct 15 03:48:38 PM UTC 24 |
| Finished | Oct 15 03:49:05 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432292059 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3432292059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/45.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.1996773957 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 44907479 ps |
| CPU time | 6.2 seconds |
| Started | Oct 15 03:48:00 PM UTC 24 |
| Finished | Oct 15 03:48:07 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996773957 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1996773957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/45.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.1269107361 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 7355116246 ps |
| CPU time | 71.61 seconds |
| Started | Oct 15 03:48:08 PM UTC 24 |
| Finished | Oct 15 03:49:21 PM UTC 24 |
| Peak memory | 591856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269107361 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1269107361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/45.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.2708531712 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 2954549333 ps |
| CPU time | 46.15 seconds |
| Started | Oct 15 03:48:04 PM UTC 24 |
| Finished | Oct 15 03:48:52 PM UTC 24 |
| Peak memory | 591824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708531712 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.2708531712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.2455487486 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 42442453 ps |
| CPU time | 8.67 seconds |
| Started | Oct 15 03:48:03 PM UTC 24 |
| Finished | Oct 15 03:48:13 PM UTC 24 |
| Peak memory | 591764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455487486 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.2455487486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/45.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.4116141168 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 1160322732 ps |
| CPU time | 111.5 seconds |
| Started | Oct 15 03:48:45 PM UTC 24 |
| Finished | Oct 15 03:50:39 PM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116141168 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.4116141168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/45.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.4089800375 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 9149372387 ps |
| CPU time | 305.13 seconds |
| Started | Oct 15 03:48:48 PM UTC 24 |
| Finished | Oct 15 03:53:58 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089800375 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.4089800375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/45.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3067980872 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 11360763711 ps |
| CPU time | 601.76 seconds |
| Started | Oct 15 03:48:42 PM UTC 24 |
| Finished | Oct 15 03:58:51 PM UTC 24 |
| Peak memory | 594028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067980872 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.3067980872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.3959619488 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 3645438553 ps |
| CPU time | 142.14 seconds |
| Started | Oct 15 03:48:54 PM UTC 24 |
| Finished | Oct 15 03:51:19 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959619488 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.3959619488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.3143237493 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 329292991 ps |
| CPU time | 44.55 seconds |
| Started | Oct 15 03:48:42 PM UTC 24 |
| Finished | Oct 15 03:49:28 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143237493 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3143237493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/45.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.2721576770 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 3320718313 ps |
| CPU time | 154.35 seconds |
| Started | Oct 15 03:49:22 PM UTC 24 |
| Finished | Oct 15 03:52:00 PM UTC 24 |
| Peak memory | 593984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721576770 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2721576770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/46.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.104344557 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 57859656685 ps |
| CPU time | 869.21 seconds |
| Started | Oct 15 03:49:25 PM UTC 24 |
| Finished | Oct 15 04:04:05 PM UTC 24 |
| Peak memory | 593884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104344557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_devi ce_slow_rsp.104344557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.3714717606 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 1250383409 ps |
| CPU time | 50.03 seconds |
| Started | Oct 15 03:49:33 PM UTC 24 |
| Finished | Oct 15 03:50:24 PM UTC 24 |
| Peak memory | 594016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714717606 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.3714717606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.3621210661 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 66902551 ps |
| CPU time | 11.77 seconds |
| Started | Oct 15 03:49:30 PM UTC 24 |
| Finished | Oct 15 03:49:43 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621210661 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.3621210661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/46.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.1824498855 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 598534479 ps |
| CPU time | 54.39 seconds |
| Started | Oct 15 03:49:14 PM UTC 24 |
| Finished | Oct 15 03:50:10 PM UTC 24 |
| Peak memory | 593912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824498855 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.1824498855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/46.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.2967632734 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 28556976481 ps |
| CPU time | 289.56 seconds |
| Started | Oct 15 03:49:20 PM UTC 24 |
| Finished | Oct 15 03:54:13 PM UTC 24 |
| Peak memory | 594120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967632734 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2967632734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/46.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.1880309221 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 23276729319 ps |
| CPU time | 383.19 seconds |
| Started | Oct 15 03:49:21 PM UTC 24 |
| Finished | Oct 15 03:55:49 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880309221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1880309221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/46.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.1014797316 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 202342849 ps |
| CPU time | 26.86 seconds |
| Started | Oct 15 03:49:17 PM UTC 24 |
| Finished | Oct 15 03:49:46 PM UTC 24 |
| Peak memory | 594128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014797316 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.1014797316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/46.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.2375750309 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 173558544 ps |
| CPU time | 17.76 seconds |
| Started | Oct 15 03:49:29 PM UTC 24 |
| Finished | Oct 15 03:49:48 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375750309 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2375750309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/46.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.1416851156 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 141769910 ps |
| CPU time | 10.65 seconds |
| Started | Oct 15 03:49:02 PM UTC 24 |
| Finished | Oct 15 03:49:13 PM UTC 24 |
| Peak memory | 591740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416851156 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1416851156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/46.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.4069226410 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 7027999152 ps |
| CPU time | 104.36 seconds |
| Started | Oct 15 03:49:11 PM UTC 24 |
| Finished | Oct 15 03:50:58 PM UTC 24 |
| Peak memory | 591816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069226410 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.4069226410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/46.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.543012724 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 4458721334 ps |
| CPU time | 72.77 seconds |
| Started | Oct 15 03:49:11 PM UTC 24 |
| Finished | Oct 15 03:50:25 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543012724 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.543012724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.548871102 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 37196730 ps |
| CPU time | 8.57 seconds |
| Started | Oct 15 03:49:10 PM UTC 24 |
| Finished | Oct 15 03:49:20 PM UTC 24 |
| Peak memory | 591852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548871102 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.548871102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/46.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.3866446243 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 2068760635 ps |
| CPU time | 175.72 seconds |
| Started | Oct 15 03:49:40 PM UTC 24 |
| Finished | Oct 15 03:52:39 PM UTC 24 |
| Peak memory | 593788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866446243 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3866446243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/46.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.3640244351 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 1167887470 ps |
| CPU time | 118.19 seconds |
| Started | Oct 15 03:49:45 PM UTC 24 |
| Finished | Oct 15 03:51:46 PM UTC 24 |
| Peak memory | 593916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640244351 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.3640244351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/46.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.1438950367 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 300481273 ps |
| CPU time | 121.28 seconds |
| Started | Oct 15 03:49:43 PM UTC 24 |
| Finished | Oct 15 03:51:47 PM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438950367 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.1438950367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.3005167581 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 1247439592 ps |
| CPU time | 235.02 seconds |
| Started | Oct 15 03:49:45 PM UTC 24 |
| Finished | Oct 15 03:53:44 PM UTC 24 |
| Peak memory | 593952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005167581 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.3005167581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.971228783 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 221739860 ps |
| CPU time | 34.79 seconds |
| Started | Oct 15 03:49:32 PM UTC 24 |
| Finished | Oct 15 03:50:09 PM UTC 24 |
| Peak memory | 593916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971228783 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.971228783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/46.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.812791271 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 830391584 ps |
| CPU time | 71.62 seconds |
| Started | Oct 15 03:50:28 PM UTC 24 |
| Finished | Oct 15 03:51:41 PM UTC 24 |
| Peak memory | 593692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812791271 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.812791271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/47.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.354370477 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 55753797652 ps |
| CPU time | 801.32 seconds |
| Started | Oct 15 03:50:29 PM UTC 24 |
| Finished | Oct 15 04:04:00 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354370477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_devi ce_slow_rsp.354370477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.3096454966 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 202744321 ps |
| CPU time | 22.83 seconds |
| Started | Oct 15 03:50:50 PM UTC 24 |
| Finished | Oct 15 03:51:14 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096454966 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.3096454966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.1314896062 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 1751345570 ps |
| CPU time | 47.48 seconds |
| Started | Oct 15 03:50:32 PM UTC 24 |
| Finished | Oct 15 03:51:21 PM UTC 24 |
| Peak memory | 593824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314896062 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1314896062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/47.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.1605338737 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 1544497852 ps |
| CPU time | 53.06 seconds |
| Started | Oct 15 03:50:09 PM UTC 24 |
| Finished | Oct 15 03:51:04 PM UTC 24 |
| Peak memory | 593740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605338737 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.1605338737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/47.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.783593266 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 42429381447 ps |
| CPU time | 449 seconds |
| Started | Oct 15 03:50:14 PM UTC 24 |
| Finished | Oct 15 03:57:49 PM UTC 24 |
| Peak memory | 594016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783593266 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.783593266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/47.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.3300937728 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 10772540225 ps |
| CPU time | 226.31 seconds |
| Started | Oct 15 03:50:10 PM UTC 24 |
| Finished | Oct 15 03:54:00 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300937728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3300937728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/47.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.3123808006 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 236857238 ps |
| CPU time | 29.29 seconds |
| Started | Oct 15 03:50:09 PM UTC 24 |
| Finished | Oct 15 03:50:40 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123808006 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.3123808006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/47.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.913790602 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 464068914 ps |
| CPU time | 14.4 seconds |
| Started | Oct 15 03:50:29 PM UTC 24 |
| Finished | Oct 15 03:50:45 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913790602 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.913790602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/47.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.1297857919 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 260616801 ps |
| CPU time | 14.57 seconds |
| Started | Oct 15 03:49:50 PM UTC 24 |
| Finished | Oct 15 03:50:06 PM UTC 24 |
| Peak memory | 591876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297857919 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1297857919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/47.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.324540053 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 8734502677 ps |
| CPU time | 79.43 seconds |
| Started | Oct 15 03:49:55 PM UTC 24 |
| Finished | Oct 15 03:51:17 PM UTC 24 |
| Peak memory | 591940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324540053 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.324540053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/47.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.3085511735 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 5379851181 ps |
| CPU time | 82.14 seconds |
| Started | Oct 15 03:50:07 PM UTC 24 |
| Finished | Oct 15 03:51:31 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085511735 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3085511735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.3464178200 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 37846869 ps |
| CPU time | 8.42 seconds |
| Started | Oct 15 03:49:51 PM UTC 24 |
| Finished | Oct 15 03:50:00 PM UTC 24 |
| Peak memory | 591764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464178200 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.3464178200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/47.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.2153122111 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 6279311210 ps |
| CPU time | 253.02 seconds |
| Started | Oct 15 03:50:49 PM UTC 24 |
| Finished | Oct 15 03:55:06 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153122111 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2153122111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/47.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.3157912917 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 8983949185 ps |
| CPU time | 288.69 seconds |
| Started | Oct 15 03:51:05 PM UTC 24 |
| Finished | Oct 15 03:55:57 PM UTC 24 |
| Peak memory | 593912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157912917 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3157912917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/47.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.3974832101 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 2933514870 ps |
| CPU time | 414.7 seconds |
| Started | Oct 15 03:50:56 PM UTC 24 |
| Finished | Oct 15 03:57:57 PM UTC 24 |
| Peak memory | 594044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974832101 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.3974832101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.3817447658 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 255734480 ps |
| CPU time | 68.95 seconds |
| Started | Oct 15 03:51:04 PM UTC 24 |
| Finished | Oct 15 03:52:15 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817447658 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.3817447658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.3433781982 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 173198410 ps |
| CPU time | 12.88 seconds |
| Started | Oct 15 03:50:39 PM UTC 24 |
| Finished | Oct 15 03:50:53 PM UTC 24 |
| Peak memory | 591772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433781982 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3433781982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/47.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.1274400436 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 716326259 ps |
| CPU time | 31.58 seconds |
| Started | Oct 15 03:51:40 PM UTC 24 |
| Finished | Oct 15 03:52:13 PM UTC 24 |
| Peak memory | 593692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274400436 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.1274400436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/48.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.3435577736 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 50031930783 ps |
| CPU time | 782.81 seconds |
| Started | Oct 15 03:51:41 PM UTC 24 |
| Finished | Oct 15 04:04:54 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435577736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_dev ice_slow_rsp.3435577736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.2315038409 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 135062730 ps |
| CPU time | 21.07 seconds |
| Started | Oct 15 03:51:45 PM UTC 24 |
| Finished | Oct 15 03:52:07 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315038409 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.2315038409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.2890536183 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 213583177 ps |
| CPU time | 12.53 seconds |
| Started | Oct 15 03:51:47 PM UTC 24 |
| Finished | Oct 15 03:52:00 PM UTC 24 |
| Peak memory | 593916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890536183 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2890536183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/48.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.1689397093 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 1366213493 ps |
| CPU time | 53.37 seconds |
| Started | Oct 15 03:51:25 PM UTC 24 |
| Finished | Oct 15 03:52:20 PM UTC 24 |
| Peak memory | 594020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689397093 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.1689397093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/48.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.308152066 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 22960065266 ps |
| CPU time | 261.05 seconds |
| Started | Oct 15 03:51:31 PM UTC 24 |
| Finished | Oct 15 03:55:56 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308152066 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.308152066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/48.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.3576512302 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 24442931838 ps |
| CPU time | 349.69 seconds |
| Started | Oct 15 03:51:32 PM UTC 24 |
| Finished | Oct 15 03:57:27 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576512302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3576512302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/48.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.3265557071 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 572512132 ps |
| CPU time | 57.02 seconds |
| Started | Oct 15 03:51:29 PM UTC 24 |
| Finished | Oct 15 03:52:28 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265557071 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.3265557071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/48.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.1832678207 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 2558857708 ps |
| CPU time | 93.08 seconds |
| Started | Oct 15 03:51:44 PM UTC 24 |
| Finished | Oct 15 03:53:20 PM UTC 24 |
| Peak memory | 593988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832678207 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1832678207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/48.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.2332716232 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 209078419 ps |
| CPU time | 12.84 seconds |
| Started | Oct 15 03:51:07 PM UTC 24 |
| Finished | Oct 15 03:51:21 PM UTC 24 |
| Peak memory | 591612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332716232 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2332716232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/48.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.364044645 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 9756350656 ps |
| CPU time | 112.02 seconds |
| Started | Oct 15 03:51:10 PM UTC 24 |
| Finished | Oct 15 03:53:04 PM UTC 24 |
| Peak memory | 591940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364044645 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.364044645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/48.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.4159716639 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 4562338209 ps |
| CPU time | 55.98 seconds |
| Started | Oct 15 03:51:18 PM UTC 24 |
| Finished | Oct 15 03:52:15 PM UTC 24 |
| Peak memory | 591684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159716639 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.4159716639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.163806365 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 52474022 ps |
| CPU time | 9.21 seconds |
| Started | Oct 15 03:51:11 PM UTC 24 |
| Finished | Oct 15 03:51:21 PM UTC 24 |
| Peak memory | 591796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163806365 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.163806365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/48.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.2944837116 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 20722303750 ps |
| CPU time | 762.92 seconds |
| Started | Oct 15 03:51:51 PM UTC 24 |
| Finished | Oct 15 04:04:44 PM UTC 24 |
| Peak memory | 594028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944837116 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2944837116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/48.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.2116634413 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 7642118667 ps |
| CPU time | 299.14 seconds |
| Started | Oct 15 03:51:57 PM UTC 24 |
| Finished | Oct 15 03:57:01 PM UTC 24 |
| Peak memory | 593976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116634413 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2116634413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/48.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.4101704025 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 78579915 ps |
| CPU time | 32.28 seconds |
| Started | Oct 15 03:51:52 PM UTC 24 |
| Finished | Oct 15 03:52:26 PM UTC 24 |
| Peak memory | 593904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101704025 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.4101704025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.2145214845 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 7174604173 ps |
| CPU time | 427.9 seconds |
| Started | Oct 15 03:52:06 PM UTC 24 |
| Finished | Oct 15 03:59:20 PM UTC 24 |
| Peak memory | 594140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145214845 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.2145214845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.3723827839 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 195695005 ps |
| CPU time | 15.44 seconds |
| Started | Oct 15 03:51:43 PM UTC 24 |
| Finished | Oct 15 03:51:59 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723827839 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3723827839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/48.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.467219648 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 1312269245 ps |
| CPU time | 69.11 seconds |
| Started | Oct 15 03:52:43 PM UTC 24 |
| Finished | Oct 15 03:53:53 PM UTC 24 |
| Peak memory | 594120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467219648 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.467219648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/49.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.1646381059 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 53910862365 ps |
| CPU time | 779.17 seconds |
| Started | Oct 15 03:52:40 PM UTC 24 |
| Finished | Oct 15 04:05:49 PM UTC 24 |
| Peak memory | 594012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646381059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_dev ice_slow_rsp.1646381059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.621179901 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 788169704 ps |
| CPU time | 42.63 seconds |
| Started | Oct 15 03:52:47 PM UTC 24 |
| Finished | Oct 15 03:53:31 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621179901 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.621179901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.3379164048 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 1444740662 ps |
| CPU time | 64.61 seconds |
| Started | Oct 15 03:52:43 PM UTC 24 |
| Finished | Oct 15 03:53:49 PM UTC 24 |
| Peak memory | 593816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379164048 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3379164048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/49.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.3114629044 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 560155534 ps |
| CPU time | 25.13 seconds |
| Started | Oct 15 03:52:25 PM UTC 24 |
| Finished | Oct 15 03:52:52 PM UTC 24 |
| Peak memory | 593884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114629044 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.3114629044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/49.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.2639823643 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 38569976566 ps |
| CPU time | 367.4 seconds |
| Started | Oct 15 03:52:33 PM UTC 24 |
| Finished | Oct 15 03:58:45 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639823643 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2639823643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/49.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.1740963134 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 13452538708 ps |
| CPU time | 193.51 seconds |
| Started | Oct 15 03:52:39 PM UTC 24 |
| Finished | Oct 15 03:55:56 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740963134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1740963134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/49.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.376399108 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 499965456 ps |
| CPU time | 45.78 seconds |
| Started | Oct 15 03:52:28 PM UTC 24 |
| Finished | Oct 15 03:53:15 PM UTC 24 |
| Peak memory | 593916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376399108 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.376399108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/49.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.3438279471 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 1263723774 ps |
| CPU time | 38.07 seconds |
| Started | Oct 15 03:52:43 PM UTC 24 |
| Finished | Oct 15 03:53:22 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438279471 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3438279471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/49.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.1653167389 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 198656915 ps |
| CPU time | 9.08 seconds |
| Started | Oct 15 03:52:09 PM UTC 24 |
| Finished | Oct 15 03:52:19 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653167389 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1653167389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/49.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.94154745 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 9100542116 ps |
| CPU time | 90.63 seconds |
| Started | Oct 15 03:52:09 PM UTC 24 |
| Finished | Oct 15 03:53:41 PM UTC 24 |
| Peak memory | 591904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94154745 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.94154745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/49.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.3243721488 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 4018515878 ps |
| CPU time | 72.17 seconds |
| Started | Oct 15 03:52:26 PM UTC 24 |
| Finished | Oct 15 03:53:40 PM UTC 24 |
| Peak memory | 591760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243721488 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3243721488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3863399295 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 48909608 ps |
| CPU time | 8.35 seconds |
| Started | Oct 15 03:52:11 PM UTC 24 |
| Finished | Oct 15 03:52:21 PM UTC 24 |
| Peak memory | 591756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863399295 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3863399295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/49.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.1292033381 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 1748022015 ps |
| CPU time | 77.67 seconds |
| Started | Oct 15 03:52:50 PM UTC 24 |
| Finished | Oct 15 03:54:10 PM UTC 24 |
| Peak memory | 593956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292033381 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1292033381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/49.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.204163270 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 2813239551 ps |
| CPU time | 93 seconds |
| Started | Oct 15 03:52:54 PM UTC 24 |
| Finished | Oct 15 03:54:30 PM UTC 24 |
| Peak memory | 593860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204163270 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.204163270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/49.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.876312609 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 46906608 ps |
| CPU time | 28.96 seconds |
| Started | Oct 15 03:52:53 PM UTC 24 |
| Finished | Oct 15 03:53:24 PM UTC 24 |
| Peak memory | 591672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876312609 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.876312609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.626393761 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 1796191002 ps |
| CPU time | 96.25 seconds |
| Started | Oct 15 03:53:06 PM UTC 24 |
| Finished | Oct 15 03:54:44 PM UTC 24 |
| Peak memory | 593732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626393761 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.626393761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.3225463427 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 1112065228 ps |
| CPU time | 47.34 seconds |
| Started | Oct 15 03:52:48 PM UTC 24 |
| Finished | Oct 15 03:53:37 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225463427 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3225463427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/49.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.3518693770 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 5533937477 ps |
| CPU time | 497.32 seconds |
| Started | Oct 15 02:48:19 PM UTC 24 |
| Finished | Oct 15 02:56:42 PM UTC 24 |
| Peak memory | 660044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3518693770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 5.chip_csr_mem_rw_with_rand_reset.3518693770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.1744484876 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 4272667850 ps |
| CPU time | 439.3 seconds |
| Started | Oct 15 02:48:18 PM UTC 24 |
| Finished | Oct 15 02:55:43 PM UTC 24 |
| Peak memory | 617116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744484876 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.1744484876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.1092411072 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 15910574352 ps |
| CPU time | 1963.85 seconds |
| Started | Oct 15 02:46:35 PM UTC 24 |
| Finished | Oct 15 03:19:41 PM UTC 24 |
| Peak memory | 608788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1092411072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.chip_same_csr_outstanding.1092411072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.4131737279 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 682738668 ps |
| CPU time | 40.57 seconds |
| Started | Oct 15 02:47:09 PM UTC 24 |
| Finished | Oct 15 02:47:51 PM UTC 24 |
| Peak memory | 594072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131737279 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.4131737279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1557678197 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 56248416324 ps |
| CPU time | 854.04 seconds |
| Started | Oct 15 02:47:12 PM UTC 24 |
| Finished | Oct 15 03:01:36 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557678197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_devi ce_slow_rsp.1557678197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.221781192 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 189733041 ps |
| CPU time | 14.01 seconds |
| Started | Oct 15 02:47:44 PM UTC 24 |
| Finished | Oct 15 02:47:59 PM UTC 24 |
| Peak memory | 591616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221781192 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.221781192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.1571830488 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 289297394 ps |
| CPU time | 33.01 seconds |
| Started | Oct 15 02:47:17 PM UTC 24 |
| Finished | Oct 15 02:47:51 PM UTC 24 |
| Peak memory | 594020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571830488 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1571830488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.2321559493 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 92641721 ps |
| CPU time | 15.39 seconds |
| Started | Oct 15 02:47:03 PM UTC 24 |
| Finished | Oct 15 02:47:19 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321559493 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.2321559493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.1283127390 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 32924257733 ps |
| CPU time | 294.45 seconds |
| Started | Oct 15 02:47:05 PM UTC 24 |
| Finished | Oct 15 02:52:03 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283127390 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1283127390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.2946857349 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 3591612800 ps |
| CPU time | 81.75 seconds |
| Started | Oct 15 02:47:07 PM UTC 24 |
| Finished | Oct 15 02:48:31 PM UTC 24 |
| Peak memory | 591912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946857349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2946857349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.4272735108 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 93863800 ps |
| CPU time | 15.63 seconds |
| Started | Oct 15 02:47:02 PM UTC 24 |
| Finished | Oct 15 02:47:19 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272735108 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.4272735108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.3711463231 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 1397695596 ps |
| CPU time | 63.17 seconds |
| Started | Oct 15 02:47:11 PM UTC 24 |
| Finished | Oct 15 02:48:16 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711463231 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3711463231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.1507612436 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 135325240 ps |
| CPU time | 7.22 seconds |
| Started | Oct 15 02:46:36 PM UTC 24 |
| Finished | Oct 15 02:46:44 PM UTC 24 |
| Peak memory | 591968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507612436 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1507612436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.3708437834 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 8788759652 ps |
| CPU time | 131.33 seconds |
| Started | Oct 15 02:46:40 PM UTC 24 |
| Finished | Oct 15 02:48:54 PM UTC 24 |
| Peak memory | 592052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708437834 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3708437834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.1417734542 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 4720329357 ps |
| CPU time | 76.34 seconds |
| Started | Oct 15 02:46:52 PM UTC 24 |
| Finished | Oct 15 02:48:11 PM UTC 24 |
| Peak memory | 591696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417734542 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1417734542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.3283496629 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 46232938 ps |
| CPU time | 9.14 seconds |
| Started | Oct 15 02:46:35 PM UTC 24 |
| Finished | Oct 15 02:46:45 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283496629 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.3283496629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.2663995794 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2375032168 ps |
| CPU time | 319.85 seconds |
| Started | Oct 15 02:47:45 PM UTC 24 |
| Finished | Oct 15 02:53:10 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663995794 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2663995794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.1447832428 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 4432612714 ps |
| CPU time | 159.8 seconds |
| Started | Oct 15 02:47:57 PM UTC 24 |
| Finished | Oct 15 02:50:40 PM UTC 24 |
| Peak memory | 593752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447832428 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.1447832428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.345691854 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 637713140 ps |
| CPU time | 137.13 seconds |
| Started | Oct 15 02:48:17 PM UTC 24 |
| Finished | Oct 15 02:50:37 PM UTC 24 |
| Peak memory | 593724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345691854 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.345691854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.3082214641 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 1088475402 ps |
| CPU time | 42.15 seconds |
| Started | Oct 15 02:47:29 PM UTC 24 |
| Finished | Oct 15 02:48:12 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082214641 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3082214641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.3070725600 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 3713567725 ps |
| CPU time | 160.72 seconds |
| Started | Oct 15 03:53:50 PM UTC 24 |
| Finished | Oct 15 03:56:33 PM UTC 24 |
| Peak memory | 594176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070725600 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device.3070725600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/50.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.3995723492 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 40497012354 ps |
| CPU time | 831.52 seconds |
| Started | Oct 15 03:53:51 PM UTC 24 |
| Finished | Oct 15 04:07:53 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995723492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_dev ice_slow_rsp.3995723492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.562213505 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 945339341 ps |
| CPU time | 49.15 seconds |
| Started | Oct 15 03:54:04 PM UTC 24 |
| Finished | Oct 15 03:54:55 PM UTC 24 |
| Peak memory | 593976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562213505 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_addr.562213505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.2395261420 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 2443897570 ps |
| CPU time | 115.2 seconds |
| Started | Oct 15 03:53:53 PM UTC 24 |
| Finished | Oct 15 03:55:50 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395261420 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.2395261420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/50.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.2830285542 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 128020902 ps |
| CPU time | 11.34 seconds |
| Started | Oct 15 03:53:33 PM UTC 24 |
| Finished | Oct 15 03:53:45 PM UTC 24 |
| Peak memory | 591768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830285542 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.2830285542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/50.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.3472823643 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 4931117756 ps |
| CPU time | 54.46 seconds |
| Started | Oct 15 03:53:46 PM UTC 24 |
| Finished | Oct 15 03:54:42 PM UTC 24 |
| Peak memory | 592024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472823643 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.3472823643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/50.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.2711526148 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 6669132963 ps |
| CPU time | 91.46 seconds |
| Started | Oct 15 03:53:51 PM UTC 24 |
| Finished | Oct 15 03:55:24 PM UTC 24 |
| Peak memory | 594088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711526148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.2711526148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/50.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.755987501 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 69573335 ps |
| CPU time | 12.83 seconds |
| Started | Oct 15 03:53:40 PM UTC 24 |
| Finished | Oct 15 03:53:54 PM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755987501 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_delays.755987501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/50.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.3409121721 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 193621234 ps |
| CPU time | 23.37 seconds |
| Started | Oct 15 03:53:49 PM UTC 24 |
| Finished | Oct 15 03:54:13 PM UTC 24 |
| Peak memory | 594060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409121721 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.3409121721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/50.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.3948361322 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 230817888 ps |
| CPU time | 13.7 seconds |
| Started | Oct 15 03:53:08 PM UTC 24 |
| Finished | Oct 15 03:53:23 PM UTC 24 |
| Peak memory | 591612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948361322 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.3948361322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/50.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.3129281154 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 5704894759 ps |
| CPU time | 63 seconds |
| Started | Oct 15 03:53:26 PM UTC 24 |
| Finished | Oct 15 03:54:31 PM UTC 24 |
| Peak memory | 591816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129281154 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.3129281154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/50.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.2674914705 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 4935411938 ps |
| CPU time | 75.64 seconds |
| Started | Oct 15 03:53:28 PM UTC 24 |
| Finished | Oct 15 03:54:45 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674914705 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.2674914705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.497140910 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 42163402 ps |
| CPU time | 6.91 seconds |
| Started | Oct 15 03:53:17 PM UTC 24 |
| Finished | Oct 15 03:53:25 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497140910 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delays.497140910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/50.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.2264759927 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 4620595263 ps |
| CPU time | 150.26 seconds |
| Started | Oct 15 03:54:07 PM UTC 24 |
| Finished | Oct 15 03:56:40 PM UTC 24 |
| Peak memory | 593780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264759927 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.2264759927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/50.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.1581111373 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 3403524372 ps |
| CPU time | 107.94 seconds |
| Started | Oct 15 03:54:09 PM UTC 24 |
| Finished | Oct 15 03:55:59 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581111373 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.1581111373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/50.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.3544768127 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 1386237384 ps |
| CPU time | 205.78 seconds |
| Started | Oct 15 03:54:04 PM UTC 24 |
| Finished | Oct 15 03:57:33 PM UTC 24 |
| Peak memory | 593780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544768127 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_rand_reset.3544768127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.3835636720 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 2486378266 ps |
| CPU time | 216.42 seconds |
| Started | Oct 15 03:54:10 PM UTC 24 |
| Finished | Oct 15 03:57:50 PM UTC 24 |
| Peak memory | 594004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835636720 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_reset_error.3835636720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.2693664766 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 78457072 ps |
| CPU time | 15.3 seconds |
| Started | Oct 15 03:53:59 PM UTC 24 |
| Finished | Oct 15 03:54:15 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693664766 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.2693664766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/50.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.2927998485 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 801765759 ps |
| CPU time | 59.02 seconds |
| Started | Oct 15 03:54:40 PM UTC 24 |
| Finished | Oct 15 03:55:41 PM UTC 24 |
| Peak memory | 593884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927998485 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device.2927998485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/51.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2233153859 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 13806154745 ps |
| CPU time | 223.53 seconds |
| Started | Oct 15 03:54:40 PM UTC 24 |
| Finished | Oct 15 03:58:27 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233153859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_dev ice_slow_rsp.2233153859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.1520471243 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 49520437 ps |
| CPU time | 8.14 seconds |
| Started | Oct 15 03:54:52 PM UTC 24 |
| Finished | Oct 15 03:55:01 PM UTC 24 |
| Peak memory | 591820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520471243 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_addr.1520471243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.1415272221 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 830331775 ps |
| CPU time | 29.37 seconds |
| Started | Oct 15 03:54:45 PM UTC 24 |
| Finished | Oct 15 03:55:16 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415272221 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.1415272221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/51.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.1077849866 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 1933527870 ps |
| CPU time | 70.68 seconds |
| Started | Oct 15 03:54:23 PM UTC 24 |
| Finished | Oct 15 03:55:35 PM UTC 24 |
| Peak memory | 594128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077849866 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.1077849866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/51.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.1560165530 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 51097571984 ps |
| CPU time | 556.6 seconds |
| Started | Oct 15 03:54:35 PM UTC 24 |
| Finished | Oct 15 04:03:59 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560165530 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.1560165530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/51.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.2412040629 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 37606527194 ps |
| CPU time | 509.05 seconds |
| Started | Oct 15 03:54:37 PM UTC 24 |
| Finished | Oct 15 04:03:13 PM UTC 24 |
| Peak memory | 594152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412040629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.2412040629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/51.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.3816826154 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 308505303 ps |
| CPU time | 39.08 seconds |
| Started | Oct 15 03:54:31 PM UTC 24 |
| Finished | Oct 15 03:55:12 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816826154 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_delays.3816826154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/51.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.2285350677 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 760229887 ps |
| CPU time | 31.72 seconds |
| Started | Oct 15 03:54:45 PM UTC 24 |
| Finished | Oct 15 03:55:18 PM UTC 24 |
| Peak memory | 593904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285350677 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.2285350677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/51.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.2001477090 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 43345078 ps |
| CPU time | 7.02 seconds |
| Started | Oct 15 03:54:17 PM UTC 24 |
| Finished | Oct 15 03:54:25 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001477090 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.2001477090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/51.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.772716694 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 8286283783 ps |
| CPU time | 76.73 seconds |
| Started | Oct 15 03:54:22 PM UTC 24 |
| Finished | Oct 15 03:55:40 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772716694 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.772716694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/51.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.4148649990 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 4130358925 ps |
| CPU time | 60.51 seconds |
| Started | Oct 15 03:54:24 PM UTC 24 |
| Finished | Oct 15 03:55:26 PM UTC 24 |
| Peak memory | 591872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148649990 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.4148649990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.2380127788 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 59975582 ps |
| CPU time | 10.04 seconds |
| Started | Oct 15 03:54:19 PM UTC 24 |
| Finished | Oct 15 03:54:30 PM UTC 24 |
| Peak memory | 591752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380127788 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delays.2380127788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/51.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.2763222245 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 14849665245 ps |
| CPU time | 484.51 seconds |
| Started | Oct 15 03:54:54 PM UTC 24 |
| Finished | Oct 15 04:03:05 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763222245 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.2763222245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/51.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.1361782611 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 3299360010 ps |
| CPU time | 233.35 seconds |
| Started | Oct 15 03:55:10 PM UTC 24 |
| Finished | Oct 15 03:59:07 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361782611 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.1361782611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/51.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.3757364792 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 107173422 ps |
| CPU time | 55.56 seconds |
| Started | Oct 15 03:54:59 PM UTC 24 |
| Finished | Oct 15 03:55:56 PM UTC 24 |
| Peak memory | 591916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757364792 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_rand_reset.3757364792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.2130342626 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 74921368 ps |
| CPU time | 37.05 seconds |
| Started | Oct 15 03:55:11 PM UTC 24 |
| Finished | Oct 15 03:55:49 PM UTC 24 |
| Peak memory | 593720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130342626 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_reset_error.2130342626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.655241962 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 237596516 ps |
| CPU time | 34.23 seconds |
| Started | Oct 15 03:54:51 PM UTC 24 |
| Finished | Oct 15 03:55:27 PM UTC 24 |
| Peak memory | 593824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655241962 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.655241962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/51.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.3004182223 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 2523247280 ps |
| CPU time | 102.62 seconds |
| Started | Oct 15 03:55:46 PM UTC 24 |
| Finished | Oct 15 03:57:31 PM UTC 24 |
| Peak memory | 594112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004182223 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device.3004182223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/52.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.987119446 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 30417301406 ps |
| CPU time | 460.51 seconds |
| Started | Oct 15 03:55:49 PM UTC 24 |
| Finished | Oct 15 04:03:35 PM UTC 24 |
| Peak memory | 594004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987119446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_devi ce_slow_rsp.987119446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.1056415505 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 603708832 ps |
| CPU time | 33 seconds |
| Started | Oct 15 03:56:00 PM UTC 24 |
| Finished | Oct 15 03:56:34 PM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056415505 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_addr.1056415505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.3606359997 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 222501651 ps |
| CPU time | 11.14 seconds |
| Started | Oct 15 03:55:53 PM UTC 24 |
| Finished | Oct 15 03:56:05 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606359997 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.3606359997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/52.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.322178084 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 536775058 ps |
| CPU time | 56.22 seconds |
| Started | Oct 15 03:55:32 PM UTC 24 |
| Finished | Oct 15 03:56:30 PM UTC 24 |
| Peak memory | 593812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322178084 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.322178084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/52.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.1841728522 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 48065614521 ps |
| CPU time | 483.73 seconds |
| Started | Oct 15 03:55:43 PM UTC 24 |
| Finished | Oct 15 04:03:53 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841728522 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.1841728522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/52.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.1138704755 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 28267963394 ps |
| CPU time | 385.99 seconds |
| Started | Oct 15 03:55:44 PM UTC 24 |
| Finished | Oct 15 04:02:15 PM UTC 24 |
| Peak memory | 594088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138704755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.1138704755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/52.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.569061590 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 374356724 ps |
| CPU time | 36.93 seconds |
| Started | Oct 15 03:55:37 PM UTC 24 |
| Finished | Oct 15 03:56:15 PM UTC 24 |
| Peak memory | 593916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569061590 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_delays.569061590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/52.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.1213179103 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 475919565 ps |
| CPU time | 18.5 seconds |
| Started | Oct 15 03:55:51 PM UTC 24 |
| Finished | Oct 15 03:56:11 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213179103 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.1213179103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/52.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.2300906337 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 201975555 ps |
| CPU time | 8.6 seconds |
| Started | Oct 15 03:55:12 PM UTC 24 |
| Finished | Oct 15 03:55:22 PM UTC 24 |
| Peak memory | 591740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300906337 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.2300906337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/52.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.4170995682 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 8353536239 ps |
| CPU time | 125 seconds |
| Started | Oct 15 03:55:22 PM UTC 24 |
| Finished | Oct 15 03:57:30 PM UTC 24 |
| Peak memory | 591696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170995682 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.4170995682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/52.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.2773576943 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 5251978041 ps |
| CPU time | 75.25 seconds |
| Started | Oct 15 03:55:26 PM UTC 24 |
| Finished | Oct 15 03:56:43 PM UTC 24 |
| Peak memory | 591824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773576943 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.2773576943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.2919661164 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 55050122 ps |
| CPU time | 7.24 seconds |
| Started | Oct 15 03:55:18 PM UTC 24 |
| Finished | Oct 15 03:55:26 PM UTC 24 |
| Peak memory | 591756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919661164 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delays.2919661164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/52.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.264136263 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 1082105730 ps |
| CPU time | 74.2 seconds |
| Started | Oct 15 03:56:04 PM UTC 24 |
| Finished | Oct 15 03:57:20 PM UTC 24 |
| Peak memory | 593732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264136263 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.264136263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/52.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.2176875270 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 8786628854 ps |
| CPU time | 299.98 seconds |
| Started | Oct 15 03:56:15 PM UTC 24 |
| Finished | Oct 15 04:01:19 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176875270 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.2176875270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/52.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.2009991929 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 281786259 ps |
| CPU time | 106.74 seconds |
| Started | Oct 15 03:56:04 PM UTC 24 |
| Finished | Oct 15 03:57:53 PM UTC 24 |
| Peak memory | 593956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009991929 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_rand_reset.2009991929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.2158137598 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 343054717 ps |
| CPU time | 123.2 seconds |
| Started | Oct 15 03:56:17 PM UTC 24 |
| Finished | Oct 15 03:58:22 PM UTC 24 |
| Peak memory | 594080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158137598 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_reset_error.2158137598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.691263039 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 56241208 ps |
| CPU time | 12.28 seconds |
| Started | Oct 15 03:55:50 PM UTC 24 |
| Finished | Oct 15 03:56:03 PM UTC 24 |
| Peak memory | 593812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691263039 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.691263039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/52.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.3262103491 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 28648604 ps |
| CPU time | 9.35 seconds |
| Started | Oct 15 03:56:29 PM UTC 24 |
| Finished | Oct 15 03:56:39 PM UTC 24 |
| Peak memory | 593692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262103491 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device.3262103491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/53.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.3549765102 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 5922257713 ps |
| CPU time | 117.27 seconds |
| Started | Oct 15 03:56:32 PM UTC 24 |
| Finished | Oct 15 03:58:31 PM UTC 24 |
| Peak memory | 594116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549765102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_dev ice_slow_rsp.3549765102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.2174412657 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 1090224865 ps |
| CPU time | 55.19 seconds |
| Started | Oct 15 03:56:53 PM UTC 24 |
| Finished | Oct 15 03:57:50 PM UTC 24 |
| Peak memory | 593876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174412657 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_addr.2174412657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.291905696 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 2114052023 ps |
| CPU time | 70.92 seconds |
| Started | Oct 15 03:56:43 PM UTC 24 |
| Finished | Oct 15 03:57:55 PM UTC 24 |
| Peak memory | 593676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291905696 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.291905696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/53.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.997466132 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 442486379 ps |
| CPU time | 42.47 seconds |
| Started | Oct 15 03:56:23 PM UTC 24 |
| Finished | Oct 15 03:57:07 PM UTC 24 |
| Peak memory | 594052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997466132 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.997466132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/53.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.1580241137 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 22189578625 ps |
| CPU time | 317.23 seconds |
| Started | Oct 15 03:56:26 PM UTC 24 |
| Finished | Oct 15 04:01:48 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580241137 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.1580241137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/53.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.710843742 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 32451678632 ps |
| CPU time | 570.13 seconds |
| Started | Oct 15 03:56:29 PM UTC 24 |
| Finished | Oct 15 04:06:06 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710843742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.710843742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/53.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.3510306279 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 524300410 ps |
| CPU time | 53.69 seconds |
| Started | Oct 15 03:56:22 PM UTC 24 |
| Finished | Oct 15 03:57:18 PM UTC 24 |
| Peak memory | 594064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510306279 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_delays.3510306279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/53.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.1333195336 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 393558794 ps |
| CPU time | 14.98 seconds |
| Started | Oct 15 03:56:38 PM UTC 24 |
| Finished | Oct 15 03:56:54 PM UTC 24 |
| Peak memory | 594064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333195336 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.1333195336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/53.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.2733890907 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 173396340 ps |
| CPU time | 10.41 seconds |
| Started | Oct 15 03:56:14 PM UTC 24 |
| Finished | Oct 15 03:56:25 PM UTC 24 |
| Peak memory | 591868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733890907 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.2733890907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/53.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.3774461500 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 10133286113 ps |
| CPU time | 105.01 seconds |
| Started | Oct 15 03:56:21 PM UTC 24 |
| Finished | Oct 15 03:58:08 PM UTC 24 |
| Peak memory | 591888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774461500 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.3774461500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/53.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.4033946100 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 3981555832 ps |
| CPU time | 56.49 seconds |
| Started | Oct 15 03:56:20 PM UTC 24 |
| Finished | Oct 15 03:57:18 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033946100 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.4033946100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.1036225580 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 44860050 ps |
| CPU time | 9.37 seconds |
| Started | Oct 15 03:56:16 PM UTC 24 |
| Finished | Oct 15 03:56:27 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036225580 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delays.1036225580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/53.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.1063452093 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 3230912892 ps |
| CPU time | 145.82 seconds |
| Started | Oct 15 03:56:57 PM UTC 24 |
| Finished | Oct 15 03:59:26 PM UTC 24 |
| Peak memory | 593788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063452093 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.1063452093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/53.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.1602881268 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 32870258 ps |
| CPU time | 89.86 seconds |
| Started | Oct 15 03:57:01 PM UTC 24 |
| Finished | Oct 15 03:58:33 PM UTC 24 |
| Peak memory | 594172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602881268 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_rand_reset.1602881268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2529772210 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 3141045287 ps |
| CPU time | 426.83 seconds |
| Started | Oct 15 03:57:07 PM UTC 24 |
| Finished | Oct 15 04:04:19 PM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529772210 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_reset_error.2529772210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.213553933 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 424138838 ps |
| CPU time | 29.04 seconds |
| Started | Oct 15 03:56:50 PM UTC 24 |
| Finished | Oct 15 03:57:21 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213553933 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.213553933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/53.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.4248394558 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 1213176370 ps |
| CPU time | 52.83 seconds |
| Started | Oct 15 03:57:46 PM UTC 24 |
| Finished | Oct 15 03:58:41 PM UTC 24 |
| Peak memory | 593688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248394558 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device.4248394558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/54.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.2472695230 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 32124896516 ps |
| CPU time | 457.64 seconds |
| Started | Oct 15 03:57:46 PM UTC 24 |
| Finished | Oct 15 04:05:30 PM UTC 24 |
| Peak memory | 593984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472695230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_dev ice_slow_rsp.2472695230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.203157231 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 1044637072 ps |
| CPU time | 39.48 seconds |
| Started | Oct 15 03:57:53 PM UTC 24 |
| Finished | Oct 15 03:58:34 PM UTC 24 |
| Peak memory | 593748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203157231 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_addr.203157231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.2295748259 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 1594995165 ps |
| CPU time | 50.31 seconds |
| Started | Oct 15 03:57:50 PM UTC 24 |
| Finished | Oct 15 03:58:43 PM UTC 24 |
| Peak memory | 593672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295748259 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.2295748259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/54.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.2852263455 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 528967960 ps |
| CPU time | 49.92 seconds |
| Started | Oct 15 03:57:34 PM UTC 24 |
| Finished | Oct 15 03:58:25 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852263455 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.2852263455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/54.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.1065937427 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 6356537986 ps |
| CPU time | 80.66 seconds |
| Started | Oct 15 03:57:44 PM UTC 24 |
| Finished | Oct 15 03:59:07 PM UTC 24 |
| Peak memory | 591832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065937427 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.1065937427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/54.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.3554125870 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 14189880836 ps |
| CPU time | 207.29 seconds |
| Started | Oct 15 03:57:44 PM UTC 24 |
| Finished | Oct 15 04:01:14 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554125870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.3554125870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/54.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.3327928002 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 319459809 ps |
| CPU time | 25.39 seconds |
| Started | Oct 15 03:57:43 PM UTC 24 |
| Finished | Oct 15 03:58:10 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327928002 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_delays.3327928002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/54.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.1352727315 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 806747144 ps |
| CPU time | 24.85 seconds |
| Started | Oct 15 03:57:46 PM UTC 24 |
| Finished | Oct 15 03:58:12 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352727315 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.1352727315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/54.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.3035650024 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 56076474 ps |
| CPU time | 10.12 seconds |
| Started | Oct 15 03:57:07 PM UTC 24 |
| Finished | Oct 15 03:57:19 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035650024 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.3035650024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/54.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.2631914598 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 8964962923 ps |
| CPU time | 122.72 seconds |
| Started | Oct 15 03:57:22 PM UTC 24 |
| Finished | Oct 15 03:59:27 PM UTC 24 |
| Peak memory | 591816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631914598 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.2631914598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/54.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.1380639532 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 5849159934 ps |
| CPU time | 125.65 seconds |
| Started | Oct 15 03:57:28 PM UTC 24 |
| Finished | Oct 15 03:59:37 PM UTC 24 |
| Peak memory | 591824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380639532 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.1380639532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.51129877 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 53689314 ps |
| CPU time | 9.18 seconds |
| Started | Oct 15 03:57:11 PM UTC 24 |
| Finished | Oct 15 03:57:21 PM UTC 24 |
| Peak memory | 591864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51129877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delays.51129877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/54.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.3381314761 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 7984250955 ps |
| CPU time | 282.43 seconds |
| Started | Oct 15 03:57:58 PM UTC 24 |
| Finished | Oct 15 04:02:45 PM UTC 24 |
| Peak memory | 593980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381314761 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.3381314761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/54.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.2593775556 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 3520850679 ps |
| CPU time | 258.57 seconds |
| Started | Oct 15 03:58:13 PM UTC 24 |
| Finished | Oct 15 04:02:36 PM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593775556 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.2593775556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/54.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.2547690589 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 9304292060 ps |
| CPU time | 522.31 seconds |
| Started | Oct 15 03:58:13 PM UTC 24 |
| Finished | Oct 15 04:07:02 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547690589 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_rand_reset.2547690589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.1474267139 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 433833677 ps |
| CPU time | 97.82 seconds |
| Started | Oct 15 03:58:14 PM UTC 24 |
| Finished | Oct 15 03:59:54 PM UTC 24 |
| Peak memory | 593732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474267139 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_reset_error.1474267139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.536638388 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 200799723 ps |
| CPU time | 35.51 seconds |
| Started | Oct 15 03:57:55 PM UTC 24 |
| Finished | Oct 15 03:58:32 PM UTC 24 |
| Peak memory | 593824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536638388 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.536638388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/54.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.1537781323 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 290285052 ps |
| CPU time | 34.92 seconds |
| Started | Oct 15 03:58:44 PM UTC 24 |
| Finished | Oct 15 03:59:20 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537781323 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device.1537781323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/55.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.996886352 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 89132484146 ps |
| CPU time | 1282.49 seconds |
| Started | Oct 15 03:58:46 PM UTC 24 |
| Finished | Oct 15 04:20:24 PM UTC 24 |
| Peak memory | 596780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996886352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_devi ce_slow_rsp.996886352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.2064585767 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 918201316 ps |
| CPU time | 35.4 seconds |
| Started | Oct 15 03:58:54 PM UTC 24 |
| Finished | Oct 15 03:59:31 PM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064585767 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_addr.2064585767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.3478631033 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 482691326 ps |
| CPU time | 37.26 seconds |
| Started | Oct 15 03:58:53 PM UTC 24 |
| Finished | Oct 15 03:59:31 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478631033 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.3478631033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/55.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.2224661989 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 1995173383 ps |
| CPU time | 76.41 seconds |
| Started | Oct 15 03:58:29 PM UTC 24 |
| Finished | Oct 15 03:59:48 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224661989 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.2224661989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/55.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.386596023 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 45267398077 ps |
| CPU time | 450.86 seconds |
| Started | Oct 15 03:58:38 PM UTC 24 |
| Finished | Oct 15 04:06:14 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386596023 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.386596023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/55.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.2759404117 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 9564888888 ps |
| CPU time | 136.42 seconds |
| Started | Oct 15 03:58:37 PM UTC 24 |
| Finished | Oct 15 04:00:56 PM UTC 24 |
| Peak memory | 594088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759404117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.2759404117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/55.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.1728432357 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 511081874 ps |
| CPU time | 40.16 seconds |
| Started | Oct 15 03:58:35 PM UTC 24 |
| Finished | Oct 15 03:59:16 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728432357 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_delays.1728432357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/55.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.2233719714 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 353074730 ps |
| CPU time | 18.93 seconds |
| Started | Oct 15 03:58:53 PM UTC 24 |
| Finished | Oct 15 03:59:13 PM UTC 24 |
| Peak memory | 593788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233719714 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.2233719714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/55.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.3491261354 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 192815937 ps |
| CPU time | 12.52 seconds |
| Started | Oct 15 03:58:13 PM UTC 24 |
| Finished | Oct 15 03:58:27 PM UTC 24 |
| Peak memory | 591872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491261354 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.3491261354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/55.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.3900180657 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 6213536088 ps |
| CPU time | 62.86 seconds |
| Started | Oct 15 03:58:21 PM UTC 24 |
| Finished | Oct 15 03:59:25 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900180657 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.3900180657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/55.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.1894446075 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 3910585815 ps |
| CPU time | 59.39 seconds |
| Started | Oct 15 03:58:24 PM UTC 24 |
| Finished | Oct 15 03:59:25 PM UTC 24 |
| Peak memory | 591880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894446075 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.1894446075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.2663035336 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 40452053 ps |
| CPU time | 5.53 seconds |
| Started | Oct 15 03:58:16 PM UTC 24 |
| Finished | Oct 15 03:58:23 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663035336 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delays.2663035336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/55.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.167261299 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 1724614957 ps |
| CPU time | 150.95 seconds |
| Started | Oct 15 03:58:58 PM UTC 24 |
| Finished | Oct 15 04:01:32 PM UTC 24 |
| Peak memory | 593736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167261299 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.167261299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/55.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.2722929576 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 485877991 ps |
| CPU time | 46.54 seconds |
| Started | Oct 15 03:58:53 PM UTC 24 |
| Finished | Oct 15 03:59:41 PM UTC 24 |
| Peak memory | 593908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722929576 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.2722929576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/55.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.3584961795 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 7284350 ps |
| CPU time | 34.3 seconds |
| Started | Oct 15 03:58:57 PM UTC 24 |
| Finished | Oct 15 03:59:32 PM UTC 24 |
| Peak memory | 593668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584961795 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_rand_reset.3584961795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.2564657997 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 406351848 ps |
| CPU time | 132.74 seconds |
| Started | Oct 15 03:59:06 PM UTC 24 |
| Finished | Oct 15 04:01:21 PM UTC 24 |
| Peak memory | 593732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564657997 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_reset_error.2564657997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.602514545 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 319991199 ps |
| CPU time | 36.32 seconds |
| Started | Oct 15 03:58:51 PM UTC 24 |
| Finished | Oct 15 03:59:29 PM UTC 24 |
| Peak memory | 593824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602514545 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.602514545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/55.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.110046754 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 687362850 ps |
| CPU time | 35.88 seconds |
| Started | Oct 15 03:59:42 PM UTC 24 |
| Finished | Oct 15 04:00:20 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110046754 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device.110046754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/56.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.931491657 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 51173263403 ps |
| CPU time | 875.85 seconds |
| Started | Oct 15 03:59:45 PM UTC 24 |
| Finished | Oct 15 04:14:31 PM UTC 24 |
| Peak memory | 594004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931491657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_devi ce_slow_rsp.931491657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.2368590039 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 643565417 ps |
| CPU time | 39.39 seconds |
| Started | Oct 15 03:59:49 PM UTC 24 |
| Finished | Oct 15 04:00:30 PM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368590039 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_addr.2368590039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.1856662201 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 468920984 ps |
| CPU time | 38.98 seconds |
| Started | Oct 15 03:59:44 PM UTC 24 |
| Finished | Oct 15 04:00:25 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856662201 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.1856662201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/56.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.2940692756 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 976984248 ps |
| CPU time | 40 seconds |
| Started | Oct 15 03:59:33 PM UTC 24 |
| Finished | Oct 15 04:00:14 PM UTC 24 |
| Peak memory | 593884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940692756 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.2940692756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/56.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.2452523068 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 47474734362 ps |
| CPU time | 455.5 seconds |
| Started | Oct 15 03:59:34 PM UTC 24 |
| Finished | Oct 15 04:07:15 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452523068 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.2452523068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/56.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.1589000900 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 22947688554 ps |
| CPU time | 356.87 seconds |
| Started | Oct 15 03:59:37 PM UTC 24 |
| Finished | Oct 15 04:05:40 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589000900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.1589000900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/56.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.3711479863 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 317721229 ps |
| CPU time | 29.07 seconds |
| Started | Oct 15 03:59:34 PM UTC 24 |
| Finished | Oct 15 04:00:05 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711479863 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_delays.3711479863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/56.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.3588136839 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 2518410716 ps |
| CPU time | 90.15 seconds |
| Started | Oct 15 03:59:44 PM UTC 24 |
| Finished | Oct 15 04:01:16 PM UTC 24 |
| Peak memory | 594100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588136839 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.3588136839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/56.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.3213356911 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 186712872 ps |
| CPU time | 12.21 seconds |
| Started | Oct 15 03:59:08 PM UTC 24 |
| Finished | Oct 15 03:59:21 PM UTC 24 |
| Peak memory | 591892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213356911 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.3213356911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/56.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.3416264423 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 6569615427 ps |
| CPU time | 68.08 seconds |
| Started | Oct 15 03:59:08 PM UTC 24 |
| Finished | Oct 15 04:00:18 PM UTC 24 |
| Peak memory | 591880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416264423 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.3416264423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/56.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.1444514211 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 5159836102 ps |
| CPU time | 94.87 seconds |
| Started | Oct 15 03:59:19 PM UTC 24 |
| Finished | Oct 15 04:00:56 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444514211 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.1444514211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.2897531019 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 49851182 ps |
| CPU time | 9.83 seconds |
| Started | Oct 15 03:59:12 PM UTC 24 |
| Finished | Oct 15 03:59:23 PM UTC 24 |
| Peak memory | 591756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897531019 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delays.2897531019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/56.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.3452112393 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 15172999003 ps |
| CPU time | 576.39 seconds |
| Started | Oct 15 03:59:51 PM UTC 24 |
| Finished | Oct 15 04:09:35 PM UTC 24 |
| Peak memory | 594240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452112393 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.3452112393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/56.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.315928382 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 1191867320 ps |
| CPU time | 51.28 seconds |
| Started | Oct 15 03:59:49 PM UTC 24 |
| Finished | Oct 15 04:00:42 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315928382 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.315928382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/56.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.3642086240 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 2265774199 ps |
| CPU time | 282.64 seconds |
| Started | Oct 15 03:59:48 PM UTC 24 |
| Finished | Oct 15 04:04:35 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642086240 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_rand_reset.3642086240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.2712842158 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 92388505 ps |
| CPU time | 32.3 seconds |
| Started | Oct 15 03:59:53 PM UTC 24 |
| Finished | Oct 15 04:00:27 PM UTC 24 |
| Peak memory | 593720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712842158 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_reset_error.2712842158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.175133730 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 143771009 ps |
| CPU time | 25.41 seconds |
| Started | Oct 15 03:59:50 PM UTC 24 |
| Finished | Oct 15 04:00:17 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175133730 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.175133730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/56.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.170753600 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 1154306685 ps |
| CPU time | 87.16 seconds |
| Started | Oct 15 04:00:30 PM UTC 24 |
| Finished | Oct 15 04:01:59 PM UTC 24 |
| Peak memory | 594076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170753600 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device.170753600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/57.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.1588322795 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 33591949857 ps |
| CPU time | 450.76 seconds |
| Started | Oct 15 04:00:34 PM UTC 24 |
| Finished | Oct 15 04:08:10 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588322795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_dev ice_slow_rsp.1588322795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.153676838 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 1033583539 ps |
| CPU time | 38.81 seconds |
| Started | Oct 15 04:00:44 PM UTC 24 |
| Finished | Oct 15 04:01:24 PM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153676838 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_addr.153676838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.1159439894 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 692572358 ps |
| CPU time | 29.53 seconds |
| Started | Oct 15 04:00:42 PM UTC 24 |
| Finished | Oct 15 04:01:13 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159439894 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.1159439894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/57.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.425493873 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 244375220 ps |
| CPU time | 30.51 seconds |
| Started | Oct 15 04:00:00 PM UTC 24 |
| Finished | Oct 15 04:00:37 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425493873 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.425493873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/57.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.175354206 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 37521469292 ps |
| CPU time | 344.08 seconds |
| Started | Oct 15 04:00:21 PM UTC 24 |
| Finished | Oct 15 04:06:09 PM UTC 24 |
| Peak memory | 594188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175354206 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.175354206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/57.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.4257211033 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 14390223920 ps |
| CPU time | 200.35 seconds |
| Started | Oct 15 04:00:30 PM UTC 24 |
| Finished | Oct 15 04:03:53 PM UTC 24 |
| Peak memory | 594088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257211033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.4257211033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/57.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.124611927 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 489223999 ps |
| CPU time | 44.42 seconds |
| Started | Oct 15 04:00:14 PM UTC 24 |
| Finished | Oct 15 04:01:00 PM UTC 24 |
| Peak memory | 593812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124611927 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_delays.124611927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/57.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.1890715608 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 132277554 ps |
| CPU time | 16.81 seconds |
| Started | Oct 15 04:00:39 PM UTC 24 |
| Finished | Oct 15 04:00:57 PM UTC 24 |
| Peak memory | 594064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890715608 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.1890715608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/57.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.142135874 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 163631765 ps |
| CPU time | 8.99 seconds |
| Started | Oct 15 03:59:58 PM UTC 24 |
| Finished | Oct 15 04:00:08 PM UTC 24 |
| Peak memory | 591612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142135874 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.142135874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/57.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.1145097788 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 8613802034 ps |
| CPU time | 88.37 seconds |
| Started | Oct 15 03:59:57 PM UTC 24 |
| Finished | Oct 15 04:01:27 PM UTC 24 |
| Peak memory | 591940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145097788 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.1145097788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/57.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.2576136003 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 5230361415 ps |
| CPU time | 97.7 seconds |
| Started | Oct 15 04:00:01 PM UTC 24 |
| Finished | Oct 15 04:01:45 PM UTC 24 |
| Peak memory | 591920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576136003 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.2576136003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.780406207 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 55188486 ps |
| CPU time | 9.6 seconds |
| Started | Oct 15 03:59:56 PM UTC 24 |
| Finished | Oct 15 04:00:06 PM UTC 24 |
| Peak memory | 591696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780406207 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delays.780406207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/57.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.258619549 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 5828472684 ps |
| CPU time | 199.97 seconds |
| Started | Oct 15 04:00:56 PM UTC 24 |
| Finished | Oct 15 04:04:19 PM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258619549 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.258619549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/57.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.577264984 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 7415223 ps |
| CPU time | 25.24 seconds |
| Started | Oct 15 04:00:55 PM UTC 24 |
| Finished | Oct 15 04:01:22 PM UTC 24 |
| Peak memory | 591548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577264984 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_rand_reset.577264984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.3882534582 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 6498734908 ps |
| CPU time | 305.86 seconds |
| Started | Oct 15 04:01:03 PM UTC 24 |
| Finished | Oct 15 04:06:13 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882534582 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_reset_error.3882534582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.3215130895 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 32909452 ps |
| CPU time | 10.01 seconds |
| Started | Oct 15 04:00:43 PM UTC 24 |
| Finished | Oct 15 04:00:54 PM UTC 24 |
| Peak memory | 591632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215130895 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.3215130895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/57.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.2287229980 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 327283264 ps |
| CPU time | 21.09 seconds |
| Started | Oct 15 04:01:37 PM UTC 24 |
| Finished | Oct 15 04:01:59 PM UTC 24 |
| Peak memory | 593760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287229980 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device.2287229980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/58.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3262761917 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 17341212164 ps |
| CPU time | 274.41 seconds |
| Started | Oct 15 04:01:43 PM UTC 24 |
| Finished | Oct 15 04:06:21 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262761917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_dev ice_slow_rsp.3262761917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.1891396377 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 151169522 ps |
| CPU time | 20.2 seconds |
| Started | Oct 15 04:01:47 PM UTC 24 |
| Finished | Oct 15 04:02:08 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891396377 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_addr.1891396377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.4251064923 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 914997537 ps |
| CPU time | 38.97 seconds |
| Started | Oct 15 04:01:45 PM UTC 24 |
| Finished | Oct 15 04:02:25 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251064923 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.4251064923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/58.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.1893496875 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 647697596 ps |
| CPU time | 34.71 seconds |
| Started | Oct 15 04:01:23 PM UTC 24 |
| Finished | Oct 15 04:02:00 PM UTC 24 |
| Peak memory | 594052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893496875 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.1893496875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/58.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.3110717874 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 55950824874 ps |
| CPU time | 520.12 seconds |
| Started | Oct 15 04:01:31 PM UTC 24 |
| Finished | Oct 15 04:10:17 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110717874 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.3110717874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/58.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.3456602181 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 37377125906 ps |
| CPU time | 544.35 seconds |
| Started | Oct 15 04:01:36 PM UTC 24 |
| Finished | Oct 15 04:10:47 PM UTC 24 |
| Peak memory | 593748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456602181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.3456602181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/58.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.611148499 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 462607469 ps |
| CPU time | 41.78 seconds |
| Started | Oct 15 04:01:27 PM UTC 24 |
| Finished | Oct 15 04:02:10 PM UTC 24 |
| Peak memory | 593988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611148499 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_delays.611148499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/58.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.1436546015 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 569301511 ps |
| CPU time | 26.65 seconds |
| Started | Oct 15 04:01:43 PM UTC 24 |
| Finished | Oct 15 04:02:11 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436546015 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.1436546015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/58.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.1722843908 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 136076516 ps |
| CPU time | 10.2 seconds |
| Started | Oct 15 04:01:08 PM UTC 24 |
| Finished | Oct 15 04:01:20 PM UTC 24 |
| Peak memory | 591884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722843908 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.1722843908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/58.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.1070677292 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 9191938767 ps |
| CPU time | 144.96 seconds |
| Started | Oct 15 04:01:22 PM UTC 24 |
| Finished | Oct 15 04:03:50 PM UTC 24 |
| Peak memory | 591836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070677292 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.1070677292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/58.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.3473340447 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 5641186523 ps |
| CPU time | 72.97 seconds |
| Started | Oct 15 04:01:21 PM UTC 24 |
| Finished | Oct 15 04:02:36 PM UTC 24 |
| Peak memory | 591952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473340447 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.3473340447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.3630489528 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 57434558 ps |
| CPU time | 8.87 seconds |
| Started | Oct 15 04:01:22 PM UTC 24 |
| Finished | Oct 15 04:01:32 PM UTC 24 |
| Peak memory | 591820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630489528 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delays.3630489528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/58.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.2460139139 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 5660237305 ps |
| CPU time | 206.55 seconds |
| Started | Oct 15 04:01:50 PM UTC 24 |
| Finished | Oct 15 04:05:20 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460139139 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.2460139139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/58.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.160907950 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 66674176 ps |
| CPU time | 49.99 seconds |
| Started | Oct 15 04:01:49 PM UTC 24 |
| Finished | Oct 15 04:02:40 PM UTC 24 |
| Peak memory | 591804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160907950 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_rand_reset.160907950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.2089673892 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 7191346498 ps |
| CPU time | 512.58 seconds |
| Started | Oct 15 04:01:59 PM UTC 24 |
| Finished | Oct 15 04:10:39 PM UTC 24 |
| Peak memory | 594012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089673892 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_reset_error.2089673892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.2950243585 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 37838490 ps |
| CPU time | 10.49 seconds |
| Started | Oct 15 04:01:45 PM UTC 24 |
| Finished | Oct 15 04:01:57 PM UTC 24 |
| Peak memory | 591772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950243585 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.2950243585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/58.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.3284121878 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 509906866 ps |
| CPU time | 44.4 seconds |
| Started | Oct 15 04:02:36 PM UTC 24 |
| Finished | Oct 15 04:03:22 PM UTC 24 |
| Peak memory | 593764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284121878 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device.3284121878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/59.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.890007035 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 66357413315 ps |
| CPU time | 1184.51 seconds |
| Started | Oct 15 04:02:38 PM UTC 24 |
| Finished | Oct 15 04:22:37 PM UTC 24 |
| Peak memory | 597036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890007035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_devi ce_slow_rsp.890007035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3526571590 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 774176840 ps |
| CPU time | 39.84 seconds |
| Started | Oct 15 04:02:47 PM UTC 24 |
| Finished | Oct 15 04:03:28 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526571590 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_addr.3526571590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.3011250565 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 114047585 ps |
| CPU time | 13.24 seconds |
| Started | Oct 15 04:02:40 PM UTC 24 |
| Finished | Oct 15 04:02:55 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011250565 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.3011250565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/59.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.1491512584 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 1347780885 ps |
| CPU time | 63.26 seconds |
| Started | Oct 15 04:02:26 PM UTC 24 |
| Finished | Oct 15 04:03:31 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491512584 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.1491512584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/59.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.338488458 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 31741928446 ps |
| CPU time | 365.59 seconds |
| Started | Oct 15 04:02:26 PM UTC 24 |
| Finished | Oct 15 04:08:36 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338488458 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.338488458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/59.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.2152834926 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 35613534452 ps |
| CPU time | 573.56 seconds |
| Started | Oct 15 04:02:31 PM UTC 24 |
| Finished | Oct 15 04:12:12 PM UTC 24 |
| Peak memory | 593880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152834926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.2152834926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/59.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.3190623779 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 191602358 ps |
| CPU time | 26.07 seconds |
| Started | Oct 15 04:02:26 PM UTC 24 |
| Finished | Oct 15 04:02:53 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190623779 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_delays.3190623779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/59.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.3467472749 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 2537875479 ps |
| CPU time | 69.68 seconds |
| Started | Oct 15 04:02:36 PM UTC 24 |
| Finished | Oct 15 04:03:47 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467472749 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.3467472749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/59.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.650309464 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 240653691 ps |
| CPU time | 13.82 seconds |
| Started | Oct 15 04:01:58 PM UTC 24 |
| Finished | Oct 15 04:02:13 PM UTC 24 |
| Peak memory | 591612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650309464 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.650309464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/59.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.878349511 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 8426506181 ps |
| CPU time | 97.4 seconds |
| Started | Oct 15 04:02:15 PM UTC 24 |
| Finished | Oct 15 04:03:55 PM UTC 24 |
| Peak memory | 591824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878349511 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.878349511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/59.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.44654629 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 3590186075 ps |
| CPU time | 47.97 seconds |
| Started | Oct 15 04:02:22 PM UTC 24 |
| Finished | Oct 15 04:03:12 PM UTC 24 |
| Peak memory | 591924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44654629 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.44654629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.86015499 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 50817141 ps |
| CPU time | 9.68 seconds |
| Started | Oct 15 04:02:11 PM UTC 24 |
| Finished | Oct 15 04:02:21 PM UTC 24 |
| Peak memory | 591624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86015499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delays.86015499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/59.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.4121177342 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 3605774293 ps |
| CPU time | 159.82 seconds |
| Started | Oct 15 04:02:49 PM UTC 24 |
| Finished | Oct 15 04:05:32 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121177342 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.4121177342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/59.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.373621456 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 5473710397 ps |
| CPU time | 209.74 seconds |
| Started | Oct 15 04:03:04 PM UTC 24 |
| Finished | Oct 15 04:06:37 PM UTC 24 |
| Peak memory | 594092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373621456 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.373621456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/59.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.2255886365 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 8234889151 ps |
| CPU time | 459.61 seconds |
| Started | Oct 15 04:03:03 PM UTC 24 |
| Finished | Oct 15 04:10:49 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255886365 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_rand_reset.2255886365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1959865320 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 12853429463 ps |
| CPU time | 660.35 seconds |
| Started | Oct 15 04:03:05 PM UTC 24 |
| Finished | Oct 15 04:14:13 PM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959865320 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_reset_error.1959865320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.1065394949 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 1113774455 ps |
| CPU time | 47.29 seconds |
| Started | Oct 15 04:02:40 PM UTC 24 |
| Finished | Oct 15 04:03:29 PM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065394949 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.1065394949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/59.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.2493010865 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 12354036356 ps |
| CPU time | 943.09 seconds |
| Started | Oct 15 02:51:07 PM UTC 24 |
| Finished | Oct 15 03:07:03 PM UTC 24 |
| Peak memory | 654152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2493010865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 6.chip_csr_mem_rw_with_rand_reset.2493010865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.1072358418 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 28761022116 ps |
| CPU time | 4192.64 seconds |
| Started | Oct 15 02:48:25 PM UTC 24 |
| Finished | Oct 15 03:59:08 PM UTC 24 |
| Peak memory | 611972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1072358418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.chip_same_csr_outstanding.1072358418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.36965200 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 3877344285 ps |
| CPU time | 403.06 seconds |
| Started | Oct 15 02:48:37 PM UTC 24 |
| Finished | Oct 15 02:55:26 PM UTC 24 |
| Peak memory | 619184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36965200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.36965200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.3320663689 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 884555438 ps |
| CPU time | 86.56 seconds |
| Started | Oct 15 02:49:45 PM UTC 24 |
| Finished | Oct 15 02:51:13 PM UTC 24 |
| Peak memory | 593944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320663689 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.3320663689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.3301728044 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 30757327462 ps |
| CPU time | 498.76 seconds |
| Started | Oct 15 02:50:05 PM UTC 24 |
| Finished | Oct 15 02:58:30 PM UTC 24 |
| Peak memory | 593740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301728044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_devi ce_slow_rsp.3301728044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3007864206 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 1113662064 ps |
| CPU time | 61.03 seconds |
| Started | Oct 15 02:50:30 PM UTC 24 |
| Finished | Oct 15 02:51:33 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007864206 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3007864206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.2407055037 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 1755724634 ps |
| CPU time | 64.04 seconds |
| Started | Oct 15 02:50:25 PM UTC 24 |
| Finished | Oct 15 02:51:31 PM UTC 24 |
| Peak memory | 593816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407055037 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2407055037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.2986722587 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 217475966 ps |
| CPU time | 11.48 seconds |
| Started | Oct 15 02:49:05 PM UTC 24 |
| Finished | Oct 15 02:49:18 PM UTC 24 |
| Peak memory | 593816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986722587 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.2986722587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.2080288698 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 22516292048 ps |
| CPU time | 228.96 seconds |
| Started | Oct 15 02:49:20 PM UTC 24 |
| Finished | Oct 15 02:53:13 PM UTC 24 |
| Peak memory | 593876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080288698 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2080288698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.837572786 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 6366428633 ps |
| CPU time | 100.98 seconds |
| Started | Oct 15 02:49:20 PM UTC 24 |
| Finished | Oct 15 02:51:03 PM UTC 24 |
| Peak memory | 594008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837572786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.837572786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.1635664869 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 161859645 ps |
| CPU time | 22.56 seconds |
| Started | Oct 15 02:49:14 PM UTC 24 |
| Finished | Oct 15 02:49:37 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635664869 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1635664869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.1914039832 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 711847387 ps |
| CPU time | 29.5 seconds |
| Started | Oct 15 02:50:25 PM UTC 24 |
| Finished | Oct 15 02:50:56 PM UTC 24 |
| Peak memory | 593664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914039832 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.1914039832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.3925046028 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 168847677 ps |
| CPU time | 8.19 seconds |
| Started | Oct 15 02:48:39 PM UTC 24 |
| Finished | Oct 15 02:48:48 PM UTC 24 |
| Peak memory | 591608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925046028 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3925046028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.1527406560 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 7775439798 ps |
| CPU time | 108.96 seconds |
| Started | Oct 15 02:48:57 PM UTC 24 |
| Finished | Oct 15 02:50:48 PM UTC 24 |
| Peak memory | 591932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527406560 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1527406560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.1886445928 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 5825031348 ps |
| CPU time | 108.52 seconds |
| Started | Oct 15 02:49:02 PM UTC 24 |
| Finished | Oct 15 02:50:52 PM UTC 24 |
| Peak memory | 591888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886445928 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1886445928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.4109298087 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 45180618 ps |
| CPU time | 9.45 seconds |
| Started | Oct 15 02:48:43 PM UTC 24 |
| Finished | Oct 15 02:48:54 PM UTC 24 |
| Peak memory | 591768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109298087 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.4109298087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.3439348033 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 6408678 ps |
| CPU time | 5.69 seconds |
| Started | Oct 15 02:50:42 PM UTC 24 |
| Finished | Oct 15 02:50:49 PM UTC 24 |
| Peak memory | 581288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439348033 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3439348033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.2403134458 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 8131670078 ps |
| CPU time | 316.17 seconds |
| Started | Oct 15 02:50:53 PM UTC 24 |
| Finished | Oct 15 02:56:15 PM UTC 24 |
| Peak memory | 593908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403134458 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.2403134458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.757943572 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 278740382 ps |
| CPU time | 136.08 seconds |
| Started | Oct 15 02:50:43 PM UTC 24 |
| Finished | Oct 15 02:53:02 PM UTC 24 |
| Peak memory | 593740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757943572 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.757943572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1568782698 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 3008325139 ps |
| CPU time | 255.77 seconds |
| Started | Oct 15 02:50:57 PM UTC 24 |
| Finished | Oct 15 02:55:16 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568782698 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.1568782698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.3682469533 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 254358988 ps |
| CPU time | 15.96 seconds |
| Started | Oct 15 02:50:26 PM UTC 24 |
| Finished | Oct 15 02:50:43 PM UTC 24 |
| Peak memory | 593916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682469533 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3682469533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.3961890375 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 773164922 ps |
| CPU time | 77.33 seconds |
| Started | Oct 15 04:03:50 PM UTC 24 |
| Finished | Oct 15 04:05:10 PM UTC 24 |
| Peak memory | 593764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961890375 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device.3961890375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/60.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.264968141 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 65283866385 ps |
| CPU time | 1035.65 seconds |
| Started | Oct 15 04:03:55 PM UTC 24 |
| Finished | Oct 15 04:21:23 PM UTC 24 |
| Peak memory | 593912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264968141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_devi ce_slow_rsp.264968141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.4221043169 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 260159126 ps |
| CPU time | 31.97 seconds |
| Started | Oct 15 04:03:58 PM UTC 24 |
| Finished | Oct 15 04:04:32 PM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221043169 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_addr.4221043169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.3166972580 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 946793595 ps |
| CPU time | 29.28 seconds |
| Started | Oct 15 04:03:54 PM UTC 24 |
| Finished | Oct 15 04:04:25 PM UTC 24 |
| Peak memory | 593864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166972580 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.3166972580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/60.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.472057301 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 505967852 ps |
| CPU time | 57.21 seconds |
| Started | Oct 15 04:03:39 PM UTC 24 |
| Finished | Oct 15 04:04:37 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472057301 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.472057301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/60.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.1831065409 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 42918350037 ps |
| CPU time | 441.81 seconds |
| Started | Oct 15 04:03:47 PM UTC 24 |
| Finished | Oct 15 04:11:14 PM UTC 24 |
| Peak memory | 593748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831065409 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.1831065409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/60.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.4064741627 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 31715639886 ps |
| CPU time | 448.27 seconds |
| Started | Oct 15 04:03:44 PM UTC 24 |
| Finished | Oct 15 04:11:18 PM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064741627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.4064741627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/60.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.2634264528 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 235492288 ps |
| CPU time | 31.48 seconds |
| Started | Oct 15 04:03:38 PM UTC 24 |
| Finished | Oct 15 04:04:11 PM UTC 24 |
| Peak memory | 593812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634264528 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_delays.2634264528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/60.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.3906767576 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 71592007 ps |
| CPU time | 8.22 seconds |
| Started | Oct 15 04:03:54 PM UTC 24 |
| Finished | Oct 15 04:04:04 PM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906767576 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.3906767576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/60.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.4156402566 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 148923953 ps |
| CPU time | 10.51 seconds |
| Started | Oct 15 04:03:10 PM UTC 24 |
| Finished | Oct 15 04:03:22 PM UTC 24 |
| Peak memory | 591876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156402566 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.4156402566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/60.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.2876602061 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 7920096032 ps |
| CPU time | 87.15 seconds |
| Started | Oct 15 04:03:21 PM UTC 24 |
| Finished | Oct 15 04:04:50 PM UTC 24 |
| Peak memory | 591932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876602061 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.2876602061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/60.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.3212502604 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 6760155916 ps |
| CPU time | 93.81 seconds |
| Started | Oct 15 04:03:32 PM UTC 24 |
| Finished | Oct 15 04:05:08 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212502604 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.3212502604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.1907901231 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 42691402 ps |
| CPU time | 8.6 seconds |
| Started | Oct 15 04:03:22 PM UTC 24 |
| Finished | Oct 15 04:03:32 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907901231 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delays.1907901231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/60.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.4055769514 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 4169115810 ps |
| CPU time | 159.77 seconds |
| Started | Oct 15 04:04:12 PM UTC 24 |
| Finished | Oct 15 04:06:55 PM UTC 24 |
| Peak memory | 593824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055769514 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.4055769514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/60.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.794927129 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 4873721364 ps |
| CPU time | 146.79 seconds |
| Started | Oct 15 04:04:15 PM UTC 24 |
| Finished | Oct 15 04:06:45 PM UTC 24 |
| Peak memory | 594068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794927129 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.794927129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/60.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.3014969071 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 2109256881 ps |
| CPU time | 213.91 seconds |
| Started | Oct 15 04:04:17 PM UTC 24 |
| Finished | Oct 15 04:07:54 PM UTC 24 |
| Peak memory | 593732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014969071 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_reset_error.3014969071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.1712302443 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 198928577 ps |
| CPU time | 29.24 seconds |
| Started | Oct 15 04:03:58 PM UTC 24 |
| Finished | Oct 15 04:04:29 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712302443 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.1712302443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/60.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.1185945887 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 1912884492 ps |
| CPU time | 71.24 seconds |
| Started | Oct 15 04:04:43 PM UTC 24 |
| Finished | Oct 15 04:05:56 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185945887 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device.1185945887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/61.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.2778553366 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 23755151982 ps |
| CPU time | 449.73 seconds |
| Started | Oct 15 04:04:46 PM UTC 24 |
| Finished | Oct 15 04:12:22 PM UTC 24 |
| Peak memory | 593888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778553366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_dev ice_slow_rsp.2778553366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.1234806262 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 1076066412 ps |
| CPU time | 42.65 seconds |
| Started | Oct 15 04:04:56 PM UTC 24 |
| Finished | Oct 15 04:05:40 PM UTC 24 |
| Peak memory | 594060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234806262 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_addr.1234806262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.4097818708 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 899631602 ps |
| CPU time | 44.98 seconds |
| Started | Oct 15 04:04:50 PM UTC 24 |
| Finished | Oct 15 04:05:37 PM UTC 24 |
| Peak memory | 593892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097818708 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.4097818708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/61.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.3578926578 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 2023381583 ps |
| CPU time | 74.71 seconds |
| Started | Oct 15 04:04:27 PM UTC 24 |
| Finished | Oct 15 04:05:44 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578926578 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.3578926578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/61.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.1724693090 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 37937130280 ps |
| CPU time | 413.94 seconds |
| Started | Oct 15 04:04:36 PM UTC 24 |
| Finished | Oct 15 04:11:36 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724693090 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.1724693090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/61.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.518485698 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 6325965099 ps |
| CPU time | 97.91 seconds |
| Started | Oct 15 04:04:42 PM UTC 24 |
| Finished | Oct 15 04:06:22 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518485698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.518485698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/61.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.757765543 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 38476064 ps |
| CPU time | 7.51 seconds |
| Started | Oct 15 04:04:28 PM UTC 24 |
| Finished | Oct 15 04:04:38 PM UTC 24 |
| Peak memory | 591708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757765543 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_delays.757765543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/61.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.3901026026 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 1502118786 ps |
| CPU time | 47.25 seconds |
| Started | Oct 15 04:04:51 PM UTC 24 |
| Finished | Oct 15 04:05:40 PM UTC 24 |
| Peak memory | 594052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901026026 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.3901026026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/61.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.1587397536 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 45808420 ps |
| CPU time | 9 seconds |
| Started | Oct 15 04:04:16 PM UTC 24 |
| Finished | Oct 15 04:04:26 PM UTC 24 |
| Peak memory | 591996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587397536 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.1587397536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/61.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.3905898564 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 8398473569 ps |
| CPU time | 104.86 seconds |
| Started | Oct 15 04:04:24 PM UTC 24 |
| Finished | Oct 15 04:06:11 PM UTC 24 |
| Peak memory | 591932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905898564 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.3905898564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/61.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.3142113754 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 5826941006 ps |
| CPU time | 81.6 seconds |
| Started | Oct 15 04:04:26 PM UTC 24 |
| Finished | Oct 15 04:05:50 PM UTC 24 |
| Peak memory | 592064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142113754 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.3142113754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.2707979867 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 50546573 ps |
| CPU time | 6.67 seconds |
| Started | Oct 15 04:04:16 PM UTC 24 |
| Finished | Oct 15 04:04:24 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707979867 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delays.2707979867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/61.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.2315239480 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 4015835453 ps |
| CPU time | 162.74 seconds |
| Started | Oct 15 04:04:56 PM UTC 24 |
| Finished | Oct 15 04:07:42 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315239480 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.2315239480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/61.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.3035745463 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 3050895426 ps |
| CPU time | 216.87 seconds |
| Started | Oct 15 04:05:04 PM UTC 24 |
| Finished | Oct 15 04:08:44 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035745463 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.3035745463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/61.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.3551522504 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 19552878726 ps |
| CPU time | 1086.01 seconds |
| Started | Oct 15 04:05:01 PM UTC 24 |
| Finished | Oct 15 04:23:20 PM UTC 24 |
| Peak memory | 596592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551522504 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_rand_reset.3551522504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.2644458673 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 200769016 ps |
| CPU time | 71.32 seconds |
| Started | Oct 15 04:05:04 PM UTC 24 |
| Finished | Oct 15 04:06:17 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644458673 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_reset_error.2644458673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.1779560222 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 56446585 ps |
| CPU time | 13.11 seconds |
| Started | Oct 15 04:04:51 PM UTC 24 |
| Finished | Oct 15 04:05:05 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779560222 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.1779560222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/61.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.474617427 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 1762175500 ps |
| CPU time | 79.52 seconds |
| Started | Oct 15 04:05:46 PM UTC 24 |
| Finished | Oct 15 04:07:08 PM UTC 24 |
| Peak memory | 593944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474617427 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device.474617427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/62.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.1520440349 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 37277030131 ps |
| CPU time | 558.08 seconds |
| Started | Oct 15 04:05:54 PM UTC 24 |
| Finished | Oct 15 04:15:19 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520440349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_dev ice_slow_rsp.1520440349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.304154042 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 1043281544 ps |
| CPU time | 48.71 seconds |
| Started | Oct 15 04:06:00 PM UTC 24 |
| Finished | Oct 15 04:06:51 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304154042 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_addr.304154042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.3103497705 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 451251206 ps |
| CPU time | 43.88 seconds |
| Started | Oct 15 04:05:59 PM UTC 24 |
| Finished | Oct 15 04:06:45 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103497705 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.3103497705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/62.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.1529069037 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 1789984310 ps |
| CPU time | 72.47 seconds |
| Started | Oct 15 04:05:32 PM UTC 24 |
| Finished | Oct 15 04:06:46 PM UTC 24 |
| Peak memory | 593900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529069037 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.1529069037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/62.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.2357792984 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 30513293017 ps |
| CPU time | 306.88 seconds |
| Started | Oct 15 04:05:36 PM UTC 24 |
| Finished | Oct 15 04:10:47 PM UTC 24 |
| Peak memory | 593284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357792984 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.2357792984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/62.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.3576706874 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 14279784993 ps |
| CPU time | 226.42 seconds |
| Started | Oct 15 04:05:44 PM UTC 24 |
| Finished | Oct 15 04:09:34 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576706874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.3576706874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/62.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.2759701427 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 409276430 ps |
| CPU time | 37.18 seconds |
| Started | Oct 15 04:05:36 PM UTC 24 |
| Finished | Oct 15 04:06:14 PM UTC 24 |
| Peak memory | 593208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759701427 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_delays.2759701427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/62.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.2828817676 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 909445459 ps |
| CPU time | 38.32 seconds |
| Started | Oct 15 04:05:55 PM UTC 24 |
| Finished | Oct 15 04:06:34 PM UTC 24 |
| Peak memory | 593668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828817676 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.2828817676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/62.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.2462902614 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 159962046 ps |
| CPU time | 9.19 seconds |
| Started | Oct 15 04:05:06 PM UTC 24 |
| Finished | Oct 15 04:05:16 PM UTC 24 |
| Peak memory | 591740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462902614 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.2462902614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/62.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.1858430081 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 9102692880 ps |
| CPU time | 100.98 seconds |
| Started | Oct 15 04:05:21 PM UTC 24 |
| Finished | Oct 15 04:07:04 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858430081 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.1858430081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/62.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.3326583875 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 4693921351 ps |
| CPU time | 69.45 seconds |
| Started | Oct 15 04:05:30 PM UTC 24 |
| Finished | Oct 15 04:06:41 PM UTC 24 |
| Peak memory | 591952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326583875 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.3326583875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.3316806163 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 54115376 ps |
| CPU time | 9.31 seconds |
| Started | Oct 15 04:05:18 PM UTC 24 |
| Finished | Oct 15 04:05:28 PM UTC 24 |
| Peak memory | 591756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316806163 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delays.3316806163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/62.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.1471701963 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 4754402026 ps |
| CPU time | 160.56 seconds |
| Started | Oct 15 04:06:07 PM UTC 24 |
| Finished | Oct 15 04:08:50 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471701963 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.1471701963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/62.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.1479744551 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 11144013706 ps |
| CPU time | 386.87 seconds |
| Started | Oct 15 04:06:09 PM UTC 24 |
| Finished | Oct 15 04:12:41 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479744551 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.1479744551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/62.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.3278554191 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 5876942257 ps |
| CPU time | 854.7 seconds |
| Started | Oct 15 04:06:07 PM UTC 24 |
| Finished | Oct 15 04:20:33 PM UTC 24 |
| Peak memory | 594024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278554191 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_rand_reset.3278554191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.4234857365 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 837058064 ps |
| CPU time | 97.36 seconds |
| Started | Oct 15 04:06:16 PM UTC 24 |
| Finished | Oct 15 04:07:55 PM UTC 24 |
| Peak memory | 593956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234857365 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_reset_error.4234857365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.2628156090 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 1117437764 ps |
| CPU time | 51.08 seconds |
| Started | Oct 15 04:06:01 PM UTC 24 |
| Finished | Oct 15 04:06:54 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628156090 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.2628156090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/62.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.1321052464 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 2434156586 ps |
| CPU time | 122.24 seconds |
| Started | Oct 15 04:06:44 PM UTC 24 |
| Finished | Oct 15 04:08:49 PM UTC 24 |
| Peak memory | 593988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321052464 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device.1321052464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/63.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1262122324 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 49245445826 ps |
| CPU time | 696.36 seconds |
| Started | Oct 15 04:06:46 PM UTC 24 |
| Finished | Oct 15 04:18:31 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262122324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_dev ice_slow_rsp.1262122324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.1095441790 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 175372543 ps |
| CPU time | 10.58 seconds |
| Started | Oct 15 04:07:01 PM UTC 24 |
| Finished | Oct 15 04:07:13 PM UTC 24 |
| Peak memory | 591700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095441790 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_addr.1095441790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.1835038135 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 2432535812 ps |
| CPU time | 74.9 seconds |
| Started | Oct 15 04:06:50 PM UTC 24 |
| Finished | Oct 15 04:08:07 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835038135 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.1835038135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/63.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.3427754244 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 280522900 ps |
| CPU time | 26.57 seconds |
| Started | Oct 15 04:06:36 PM UTC 24 |
| Finished | Oct 15 04:07:04 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427754244 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.3427754244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/63.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.75597916 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 23847762989 ps |
| CPU time | 217.23 seconds |
| Started | Oct 15 04:06:41 PM UTC 24 |
| Finished | Oct 15 04:10:21 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75597916 -asse rt nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.75597916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/63.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.1376742895 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 9342442835 ps |
| CPU time | 172.26 seconds |
| Started | Oct 15 04:06:42 PM UTC 24 |
| Finished | Oct 15 04:09:37 PM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376742895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.1376742895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/63.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.1462781111 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 318335670 ps |
| CPU time | 28.37 seconds |
| Started | Oct 15 04:06:39 PM UTC 24 |
| Finished | Oct 15 04:07:08 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462781111 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_delays.1462781111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/63.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.450567638 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 1668644989 ps |
| CPU time | 52.39 seconds |
| Started | Oct 15 04:06:49 PM UTC 24 |
| Finished | Oct 15 04:07:43 PM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450567638 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.450567638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/63.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.2649262457 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 52330957 ps |
| CPU time | 7.92 seconds |
| Started | Oct 15 04:06:14 PM UTC 24 |
| Finished | Oct 15 04:06:23 PM UTC 24 |
| Peak memory | 591608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649262457 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.2649262457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/63.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.3444249262 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 7517898040 ps |
| CPU time | 83.41 seconds |
| Started | Oct 15 04:06:30 PM UTC 24 |
| Finished | Oct 15 04:07:56 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444249262 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.3444249262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/63.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.865273466 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 4853800626 ps |
| CPU time | 88.16 seconds |
| Started | Oct 15 04:06:31 PM UTC 24 |
| Finished | Oct 15 04:08:01 PM UTC 24 |
| Peak memory | 591820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865273466 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.865273466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.127997879 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 47931771 ps |
| CPU time | 9.47 seconds |
| Started | Oct 15 04:06:23 PM UTC 24 |
| Finished | Oct 15 04:06:33 PM UTC 24 |
| Peak memory | 591624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127997879 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delays.127997879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/63.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.2968909728 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 4415403574 ps |
| CPU time | 156.52 seconds |
| Started | Oct 15 04:07:03 PM UTC 24 |
| Finished | Oct 15 04:09:42 PM UTC 24 |
| Peak memory | 594036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968909728 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.2968909728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/63.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.570968946 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 21476567899 ps |
| CPU time | 670.77 seconds |
| Started | Oct 15 04:07:10 PM UTC 24 |
| Finished | Oct 15 04:18:29 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570968946 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.570968946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/63.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.1319103613 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 602359578 ps |
| CPU time | 154.89 seconds |
| Started | Oct 15 04:07:08 PM UTC 24 |
| Finished | Oct 15 04:09:45 PM UTC 24 |
| Peak memory | 593956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319103613 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_rand_reset.1319103613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3181388984 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 410740875 ps |
| CPU time | 155.37 seconds |
| Started | Oct 15 04:07:10 PM UTC 24 |
| Finished | Oct 15 04:09:48 PM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181388984 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_reset_error.3181388984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.3363495751 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 272705642 ps |
| CPU time | 33.36 seconds |
| Started | Oct 15 04:07:00 PM UTC 24 |
| Finished | Oct 15 04:07:35 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363495751 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.3363495751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/63.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.3152057234 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 3880724115 ps |
| CPU time | 149.1 seconds |
| Started | Oct 15 04:07:35 PM UTC 24 |
| Finished | Oct 15 04:10:07 PM UTC 24 |
| Peak memory | 593984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152057234 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device.3152057234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/64.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.3614819840 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 36446124473 ps |
| CPU time | 559.93 seconds |
| Started | Oct 15 04:07:38 PM UTC 24 |
| Finished | Oct 15 04:17:05 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614819840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_dev ice_slow_rsp.3614819840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.957760653 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 150294245 ps |
| CPU time | 10.25 seconds |
| Started | Oct 15 04:07:51 PM UTC 24 |
| Finished | Oct 15 04:08:02 PM UTC 24 |
| Peak memory | 591896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957760653 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_addr.957760653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.671961757 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 569676615 ps |
| CPU time | 27.44 seconds |
| Started | Oct 15 04:07:43 PM UTC 24 |
| Finished | Oct 15 04:08:12 PM UTC 24 |
| Peak memory | 593676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671961757 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.671961757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/64.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.3818949783 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 2589669636 ps |
| CPU time | 97.24 seconds |
| Started | Oct 15 04:07:27 PM UTC 24 |
| Finished | Oct 15 04:09:06 PM UTC 24 |
| Peak memory | 593736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818949783 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.3818949783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/64.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.3908090571 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 38886017447 ps |
| CPU time | 376.82 seconds |
| Started | Oct 15 04:07:28 PM UTC 24 |
| Finished | Oct 15 04:13:50 PM UTC 24 |
| Peak memory | 594044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908090571 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.3908090571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/64.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.414598093 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 19501702728 ps |
| CPU time | 306.43 seconds |
| Started | Oct 15 04:07:34 PM UTC 24 |
| Finished | Oct 15 04:12:45 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414598093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.414598093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/64.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.3588949368 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 543558547 ps |
| CPU time | 55.34 seconds |
| Started | Oct 15 04:07:26 PM UTC 24 |
| Finished | Oct 15 04:08:23 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588949368 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_delays.3588949368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/64.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.3475778755 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 500520657 ps |
| CPU time | 20.91 seconds |
| Started | Oct 15 04:07:41 PM UTC 24 |
| Finished | Oct 15 04:08:03 PM UTC 24 |
| Peak memory | 593756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475778755 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.3475778755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/64.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.1155288287 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 42929066 ps |
| CPU time | 8.08 seconds |
| Started | Oct 15 04:07:11 PM UTC 24 |
| Finished | Oct 15 04:07:21 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155288287 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.1155288287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/64.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.91698613 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 9023842434 ps |
| CPU time | 97.05 seconds |
| Started | Oct 15 04:07:19 PM UTC 24 |
| Finished | Oct 15 04:08:58 PM UTC 24 |
| Peak memory | 591948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91698613 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.91698613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/64.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.1207226964 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 4257481189 ps |
| CPU time | 87.25 seconds |
| Started | Oct 15 04:07:20 PM UTC 24 |
| Finished | Oct 15 04:08:50 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207226964 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.1207226964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.207321273 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 47672181 ps |
| CPU time | 7.12 seconds |
| Started | Oct 15 04:07:16 PM UTC 24 |
| Finished | Oct 15 04:07:24 PM UTC 24 |
| Peak memory | 591880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207321273 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delays.207321273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/64.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.1807438251 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 16633773773 ps |
| CPU time | 637.91 seconds |
| Started | Oct 15 04:07:59 PM UTC 24 |
| Finished | Oct 15 04:18:46 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807438251 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.1807438251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/64.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.206720891 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 3797093751 ps |
| CPU time | 131.04 seconds |
| Started | Oct 15 04:08:10 PM UTC 24 |
| Finished | Oct 15 04:10:23 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206720891 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.206720891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/64.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.3566293393 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 128331063 ps |
| CPU time | 68.68 seconds |
| Started | Oct 15 04:08:09 PM UTC 24 |
| Finished | Oct 15 04:09:19 PM UTC 24 |
| Peak memory | 593732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566293393 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_rand_reset.3566293393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.2476582374 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 195733707 ps |
| CPU time | 35.42 seconds |
| Started | Oct 15 04:08:16 PM UTC 24 |
| Finished | Oct 15 04:08:53 PM UTC 24 |
| Peak memory | 593712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476582374 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_reset_error.2476582374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.2246742879 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 502259507 ps |
| CPU time | 31.09 seconds |
| Started | Oct 15 04:07:47 PM UTC 24 |
| Finished | Oct 15 04:08:19 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246742879 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.2246742879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/64.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.320490724 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 737494749 ps |
| CPU time | 50.9 seconds |
| Started | Oct 15 04:08:39 PM UTC 24 |
| Finished | Oct 15 04:09:31 PM UTC 24 |
| Peak memory | 593764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320490724 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device.320490724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/65.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.1125998443 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 47114303968 ps |
| CPU time | 717.85 seconds |
| Started | Oct 15 04:08:44 PM UTC 24 |
| Finished | Oct 15 04:20:51 PM UTC 24 |
| Peak memory | 594012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125998443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_dev ice_slow_rsp.1125998443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.364957528 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 1377857610 ps |
| CPU time | 59.63 seconds |
| Started | Oct 15 04:08:56 PM UTC 24 |
| Finished | Oct 15 04:09:58 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364957528 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_addr.364957528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.3081620132 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 1803464056 ps |
| CPU time | 53.65 seconds |
| Started | Oct 15 04:08:54 PM UTC 24 |
| Finished | Oct 15 04:09:49 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081620132 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.3081620132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/65.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.2095984121 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 1309473762 ps |
| CPU time | 45.16 seconds |
| Started | Oct 15 04:08:26 PM UTC 24 |
| Finished | Oct 15 04:09:13 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095984121 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.2095984121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/65.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.4206199802 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 54925948316 ps |
| CPU time | 674.18 seconds |
| Started | Oct 15 04:08:33 PM UTC 24 |
| Finished | Oct 15 04:19:55 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206199802 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.4206199802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/65.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.141881913 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 33549674200 ps |
| CPU time | 657.89 seconds |
| Started | Oct 15 04:08:34 PM UTC 24 |
| Finished | Oct 15 04:19:40 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141881913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.141881913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/65.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.1299311766 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 46251257 ps |
| CPU time | 10.02 seconds |
| Started | Oct 15 04:08:29 PM UTC 24 |
| Finished | Oct 15 04:08:40 PM UTC 24 |
| Peak memory | 591636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299311766 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_delays.1299311766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/65.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.730417428 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 975456609 ps |
| CPU time | 28.35 seconds |
| Started | Oct 15 04:08:50 PM UTC 24 |
| Finished | Oct 15 04:09:21 PM UTC 24 |
| Peak memory | 593728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730417428 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.730417428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/65.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.2315336906 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 205622324 ps |
| CPU time | 8.4 seconds |
| Started | Oct 15 04:08:18 PM UTC 24 |
| Finished | Oct 15 04:08:27 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315336906 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.2315336906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/65.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.2555843006 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 9245009199 ps |
| CPU time | 82.77 seconds |
| Started | Oct 15 04:08:23 PM UTC 24 |
| Finished | Oct 15 04:09:47 PM UTC 24 |
| Peak memory | 591940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555843006 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.2555843006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/65.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.762917512 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 5686887021 ps |
| CPU time | 93.27 seconds |
| Started | Oct 15 04:08:27 PM UTC 24 |
| Finished | Oct 15 04:10:02 PM UTC 24 |
| Peak memory | 591900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762917512 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.762917512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.1708159009 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 43089208 ps |
| CPU time | 6.53 seconds |
| Started | Oct 15 04:08:21 PM UTC 24 |
| Finished | Oct 15 04:08:29 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708159009 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delays.1708159009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/65.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.2043481794 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 11836579263 ps |
| CPU time | 447.55 seconds |
| Started | Oct 15 04:09:03 PM UTC 24 |
| Finished | Oct 15 04:16:36 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043481794 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.2043481794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/65.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.2980004820 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 7893350212 ps |
| CPU time | 274.58 seconds |
| Started | Oct 15 04:09:08 PM UTC 24 |
| Finished | Oct 15 04:13:47 PM UTC 24 |
| Peak memory | 594000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980004820 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.2980004820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/65.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.2751375717 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 361331865 ps |
| CPU time | 115.05 seconds |
| Started | Oct 15 04:09:12 PM UTC 24 |
| Finished | Oct 15 04:11:10 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751375717 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_reset_error.2751375717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.3030943157 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 1415735727 ps |
| CPU time | 57.57 seconds |
| Started | Oct 15 04:08:49 PM UTC 24 |
| Finished | Oct 15 04:09:48 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030943157 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.3030943157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/65.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.1734337485 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 659042057 ps |
| CPU time | 68.45 seconds |
| Started | Oct 15 04:09:50 PM UTC 24 |
| Finished | Oct 15 04:11:00 PM UTC 24 |
| Peak memory | 593892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734337485 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device.1734337485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/66.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.671281422 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 32976687131 ps |
| CPU time | 583.24 seconds |
| Started | Oct 15 04:09:49 PM UTC 24 |
| Finished | Oct 15 04:19:40 PM UTC 24 |
| Peak memory | 594132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671281422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_devi ce_slow_rsp.671281422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.2457380043 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 1232798540 ps |
| CPU time | 45.9 seconds |
| Started | Oct 15 04:10:00 PM UTC 24 |
| Finished | Oct 15 04:10:48 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457380043 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_addr.2457380043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.397109768 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 290058746 ps |
| CPU time | 25.42 seconds |
| Started | Oct 15 04:09:58 PM UTC 24 |
| Finished | Oct 15 04:10:25 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397109768 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.397109768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/66.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.1510425882 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 176360835 ps |
| CPU time | 17.03 seconds |
| Started | Oct 15 04:09:32 PM UTC 24 |
| Finished | Oct 15 04:09:51 PM UTC 24 |
| Peak memory | 593808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510425882 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.1510425882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/66.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.2059089859 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 5902142746 ps |
| CPU time | 60.04 seconds |
| Started | Oct 15 04:09:46 PM UTC 24 |
| Finished | Oct 15 04:10:48 PM UTC 24 |
| Peak memory | 591692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059089859 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.2059089859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/66.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.594532547 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 10220427820 ps |
| CPU time | 142.04 seconds |
| Started | Oct 15 04:09:47 PM UTC 24 |
| Finished | Oct 15 04:12:12 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594532547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.594532547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/66.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.3610831409 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 454557101 ps |
| CPU time | 38.57 seconds |
| Started | Oct 15 04:09:39 PM UTC 24 |
| Finished | Oct 15 04:10:19 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610831409 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_delays.3610831409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/66.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.1271710523 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 510200924 ps |
| CPU time | 35.27 seconds |
| Started | Oct 15 04:09:55 PM UTC 24 |
| Finished | Oct 15 04:10:31 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271710523 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.1271710523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/66.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.1393027725 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 51214076 ps |
| CPU time | 8.77 seconds |
| Started | Oct 15 04:09:15 PM UTC 24 |
| Finished | Oct 15 04:09:25 PM UTC 24 |
| Peak memory | 591616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393027725 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.1393027725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/66.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.966693584 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 9877018103 ps |
| CPU time | 104.9 seconds |
| Started | Oct 15 04:09:16 PM UTC 24 |
| Finished | Oct 15 04:11:02 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966693584 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.966693584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/66.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.279479124 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 5837633176 ps |
| CPU time | 86.01 seconds |
| Started | Oct 15 04:09:25 PM UTC 24 |
| Finished | Oct 15 04:10:53 PM UTC 24 |
| Peak memory | 591832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279479124 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.279479124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.376395680 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 49115569 ps |
| CPU time | 7.49 seconds |
| Started | Oct 15 04:09:15 PM UTC 24 |
| Finished | Oct 15 04:09:24 PM UTC 24 |
| Peak memory | 591856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376395680 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delays.376395680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/66.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.1712545345 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 9592689545 ps |
| CPU time | 312.74 seconds |
| Started | Oct 15 04:10:07 PM UTC 24 |
| Finished | Oct 15 04:15:24 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712545345 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.1712545345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/66.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.3840338051 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 3019263145 ps |
| CPU time | 214.85 seconds |
| Started | Oct 15 04:10:09 PM UTC 24 |
| Finished | Oct 15 04:13:47 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840338051 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.3840338051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/66.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.3230988378 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 3964985604 ps |
| CPU time | 483.88 seconds |
| Started | Oct 15 04:10:10 PM UTC 24 |
| Finished | Oct 15 04:18:20 PM UTC 24 |
| Peak memory | 594028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230988378 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_rand_reset.3230988378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.3979908108 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 9539257584 ps |
| CPU time | 502.48 seconds |
| Started | Oct 15 04:10:10 PM UTC 24 |
| Finished | Oct 15 04:18:39 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979908108 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_reset_error.3979908108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.4249628026 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 275224278 ps |
| CPU time | 16.49 seconds |
| Started | Oct 15 04:10:02 PM UTC 24 |
| Finished | Oct 15 04:10:20 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249628026 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.4249628026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/66.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.1712743685 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 3422294336 ps |
| CPU time | 128.91 seconds |
| Started | Oct 15 04:10:45 PM UTC 24 |
| Finished | Oct 15 04:12:57 PM UTC 24 |
| Peak memory | 593756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712743685 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device.1712743685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/67.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.638341490 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 17529719097 ps |
| CPU time | 331.62 seconds |
| Started | Oct 15 04:10:47 PM UTC 24 |
| Finished | Oct 15 04:16:23 PM UTC 24 |
| Peak memory | 594016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638341490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_devi ce_slow_rsp.638341490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.2516572423 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 1124340536 ps |
| CPU time | 46.79 seconds |
| Started | Oct 15 04:10:51 PM UTC 24 |
| Finished | Oct 15 04:11:39 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516572423 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_addr.2516572423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.238500841 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 210812043 ps |
| CPU time | 24.97 seconds |
| Started | Oct 15 04:10:48 PM UTC 24 |
| Finished | Oct 15 04:11:14 PM UTC 24 |
| Peak memory | 593884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238500841 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.238500841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/67.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.3308792975 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 1349469714 ps |
| CPU time | 46.89 seconds |
| Started | Oct 15 04:10:28 PM UTC 24 |
| Finished | Oct 15 04:11:16 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308792975 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.3308792975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/67.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.3620507965 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 42944680670 ps |
| CPU time | 394.33 seconds |
| Started | Oct 15 04:10:33 PM UTC 24 |
| Finished | Oct 15 04:17:12 PM UTC 24 |
| Peak memory | 593884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620507965 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.3620507965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/67.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.2873630527 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 15786424795 ps |
| CPU time | 228.1 seconds |
| Started | Oct 15 04:10:45 PM UTC 24 |
| Finished | Oct 15 04:14:37 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873630527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.2873630527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/67.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.3628045941 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 637433171 ps |
| CPU time | 55.86 seconds |
| Started | Oct 15 04:10:26 PM UTC 24 |
| Finished | Oct 15 04:11:24 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628045941 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_delays.3628045941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/67.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.2573640733 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 1282055571 ps |
| CPU time | 36.51 seconds |
| Started | Oct 15 04:10:48 PM UTC 24 |
| Finished | Oct 15 04:11:26 PM UTC 24 |
| Peak memory | 593860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573640733 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.2573640733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/67.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.2169123524 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 42671725 ps |
| CPU time | 8.84 seconds |
| Started | Oct 15 04:10:11 PM UTC 24 |
| Finished | Oct 15 04:10:21 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169123524 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.2169123524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/67.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.1303407190 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 9157914829 ps |
| CPU time | 86.65 seconds |
| Started | Oct 15 04:10:11 PM UTC 24 |
| Finished | Oct 15 04:11:39 PM UTC 24 |
| Peak memory | 591940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303407190 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.1303407190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/67.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.3775886811 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 4005843126 ps |
| CPU time | 61.45 seconds |
| Started | Oct 15 04:10:24 PM UTC 24 |
| Finished | Oct 15 04:11:27 PM UTC 24 |
| Peak memory | 591684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775886811 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.3775886811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.3514505345 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 36606413 ps |
| CPU time | 8.4 seconds |
| Started | Oct 15 04:10:11 PM UTC 24 |
| Finished | Oct 15 04:10:21 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514505345 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delays.3514505345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/67.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.706137365 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 5729743658 ps |
| CPU time | 229.34 seconds |
| Started | Oct 15 04:10:50 PM UTC 24 |
| Finished | Oct 15 04:14:44 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706137365 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.706137365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/67.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.496477443 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 3415366750 ps |
| CPU time | 268.46 seconds |
| Started | Oct 15 04:11:03 PM UTC 24 |
| Finished | Oct 15 04:15:35 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496477443 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.496477443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/67.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.4136963132 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 6320504915 ps |
| CPU time | 270.81 seconds |
| Started | Oct 15 04:10:56 PM UTC 24 |
| Finished | Oct 15 04:15:31 PM UTC 24 |
| Peak memory | 593980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136963132 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_rand_reset.4136963132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.2584979444 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 722252096 ps |
| CPU time | 273.13 seconds |
| Started | Oct 15 04:11:08 PM UTC 24 |
| Finished | Oct 15 04:15:45 PM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584979444 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_reset_error.2584979444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.3569915489 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 1254376899 ps |
| CPU time | 56.83 seconds |
| Started | Oct 15 04:10:47 PM UTC 24 |
| Finished | Oct 15 04:11:46 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569915489 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.3569915489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/67.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.2606758944 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 809599424 ps |
| CPU time | 65.17 seconds |
| Started | Oct 15 04:11:41 PM UTC 24 |
| Finished | Oct 15 04:12:48 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606758944 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device.2606758944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/68.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.2205683142 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 55934589421 ps |
| CPU time | 762.45 seconds |
| Started | Oct 15 04:11:39 PM UTC 24 |
| Finished | Oct 15 04:24:31 PM UTC 24 |
| Peak memory | 594668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205683142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_dev ice_slow_rsp.2205683142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.65544947 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 186302730 ps |
| CPU time | 13.98 seconds |
| Started | Oct 15 04:11:45 PM UTC 24 |
| Finished | Oct 15 04:12:00 PM UTC 24 |
| Peak memory | 591820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65544947 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_addr.65544947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.4265895650 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 66911865 ps |
| CPU time | 8.68 seconds |
| Started | Oct 15 04:11:43 PM UTC 24 |
| Finished | Oct 15 04:11:53 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265895650 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.4265895650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/68.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.4145345305 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 2147264722 ps |
| CPU time | 83.84 seconds |
| Started | Oct 15 04:11:17 PM UTC 24 |
| Finished | Oct 15 04:12:43 PM UTC 24 |
| Peak memory | 594064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145345305 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.4145345305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/68.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.2315174742 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 63425161141 ps |
| CPU time | 588.67 seconds |
| Started | Oct 15 04:11:28 PM UTC 24 |
| Finished | Oct 15 04:21:24 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315174742 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.2315174742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/68.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.2745332630 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 27631985842 ps |
| CPU time | 453.55 seconds |
| Started | Oct 15 04:11:37 PM UTC 24 |
| Finished | Oct 15 04:19:16 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745332630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.2745332630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/68.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.1273088050 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 429816089 ps |
| CPU time | 37.67 seconds |
| Started | Oct 15 04:11:21 PM UTC 24 |
| Finished | Oct 15 04:12:00 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273088050 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_delays.1273088050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/68.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.739169399 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 100476091 ps |
| CPU time | 14.04 seconds |
| Started | Oct 15 04:11:41 PM UTC 24 |
| Finished | Oct 15 04:11:57 PM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739169399 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.739169399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/68.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.1699921508 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 46857106 ps |
| CPU time | 8.56 seconds |
| Started | Oct 15 04:11:09 PM UTC 24 |
| Finished | Oct 15 04:11:18 PM UTC 24 |
| Peak memory | 591876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699921508 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.1699921508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/68.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.780441008 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 6654091667 ps |
| CPU time | 107.24 seconds |
| Started | Oct 15 04:11:13 PM UTC 24 |
| Finished | Oct 15 04:13:02 PM UTC 24 |
| Peak memory | 591892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780441008 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.780441008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/68.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.633953721 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 4896039164 ps |
| CPU time | 95.98 seconds |
| Started | Oct 15 04:11:15 PM UTC 24 |
| Finished | Oct 15 04:12:53 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633953721 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.633953721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.1535835420 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 43063942 ps |
| CPU time | 6.44 seconds |
| Started | Oct 15 04:11:11 PM UTC 24 |
| Finished | Oct 15 04:11:18 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535835420 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delays.1535835420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/68.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.1163639859 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 2132975089 ps |
| CPU time | 201.76 seconds |
| Started | Oct 15 04:11:51 PM UTC 24 |
| Finished | Oct 15 04:15:16 PM UTC 24 |
| Peak memory | 593876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163639859 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.1163639859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/68.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.3201418657 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 6476141203 ps |
| CPU time | 240.99 seconds |
| Started | Oct 15 04:11:51 PM UTC 24 |
| Finished | Oct 15 04:15:56 PM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201418657 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.3201418657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/68.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.1878816964 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 4878428932 ps |
| CPU time | 411.18 seconds |
| Started | Oct 15 04:11:51 PM UTC 24 |
| Finished | Oct 15 04:18:48 PM UTC 24 |
| Peak memory | 593988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878816964 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_rand_reset.1878816964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.594863041 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 73063743 ps |
| CPU time | 86.95 seconds |
| Started | Oct 15 04:12:01 PM UTC 24 |
| Finished | Oct 15 04:13:30 PM UTC 24 |
| Peak memory | 593956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594863041 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_reset_error.594863041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.3642439662 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 112137752 ps |
| CPU time | 10.98 seconds |
| Started | Oct 15 04:11:44 PM UTC 24 |
| Finished | Oct 15 04:11:56 PM UTC 24 |
| Peak memory | 591812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642439662 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.3642439662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/68.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.934873965 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 1108652541 ps |
| CPU time | 79.69 seconds |
| Started | Oct 15 04:12:37 PM UTC 24 |
| Finished | Oct 15 04:13:59 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934873965 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device.934873965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/69.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.804639186 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 12802387224 ps |
| CPU time | 209.72 seconds |
| Started | Oct 15 04:12:40 PM UTC 24 |
| Finished | Oct 15 04:16:13 PM UTC 24 |
| Peak memory | 593736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804639186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_devi ce_slow_rsp.804639186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.4183532708 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 1320671843 ps |
| CPU time | 50.68 seconds |
| Started | Oct 15 04:12:57 PM UTC 24 |
| Finished | Oct 15 04:13:50 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183532708 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_addr.4183532708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.2201425422 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 1648525926 ps |
| CPU time | 71.99 seconds |
| Started | Oct 15 04:12:40 PM UTC 24 |
| Finished | Oct 15 04:13:54 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201425422 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.2201425422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/69.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.666630183 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 307590560 ps |
| CPU time | 14.89 seconds |
| Started | Oct 15 04:12:20 PM UTC 24 |
| Finished | Oct 15 04:12:37 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666630183 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.666630183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/69.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.2004800250 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 57761884772 ps |
| CPU time | 549.29 seconds |
| Started | Oct 15 04:12:26 PM UTC 24 |
| Finished | Oct 15 04:21:41 PM UTC 24 |
| Peak memory | 593864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004800250 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.2004800250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/69.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.3013180871 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 11157404131 ps |
| CPU time | 201.87 seconds |
| Started | Oct 15 04:12:26 PM UTC 24 |
| Finished | Oct 15 04:15:51 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013180871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.3013180871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/69.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.2488898733 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 28913876 ps |
| CPU time | 8.61 seconds |
| Started | Oct 15 04:12:23 PM UTC 24 |
| Finished | Oct 15 04:12:33 PM UTC 24 |
| Peak memory | 591780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488898733 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_delays.2488898733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/69.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.1466141117 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 424964205 ps |
| CPU time | 32.18 seconds |
| Started | Oct 15 04:12:38 PM UTC 24 |
| Finished | Oct 15 04:13:11 PM UTC 24 |
| Peak memory | 593860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466141117 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.1466141117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/69.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.3572175124 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 40784014 ps |
| CPU time | 7.94 seconds |
| Started | Oct 15 04:12:03 PM UTC 24 |
| Finished | Oct 15 04:12:12 PM UTC 24 |
| Peak memory | 591612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572175124 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.3572175124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/69.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.4198937282 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 7933204906 ps |
| CPU time | 89.85 seconds |
| Started | Oct 15 04:12:10 PM UTC 24 |
| Finished | Oct 15 04:13:42 PM UTC 24 |
| Peak memory | 591828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198937282 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.4198937282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/69.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.1143688193 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 4760453725 ps |
| CPU time | 72.01 seconds |
| Started | Oct 15 04:12:16 PM UTC 24 |
| Finished | Oct 15 04:13:30 PM UTC 24 |
| Peak memory | 591820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143688193 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.1143688193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.3695676218 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 36784076 ps |
| CPU time | 7.16 seconds |
| Started | Oct 15 04:12:04 PM UTC 24 |
| Finished | Oct 15 04:12:12 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695676218 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delays.3695676218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/69.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.4012693106 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 1601478696 ps |
| CPU time | 144.51 seconds |
| Started | Oct 15 04:13:04 PM UTC 24 |
| Finished | Oct 15 04:15:31 PM UTC 24 |
| Peak memory | 593732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012693106 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.4012693106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/69.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.988830882 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 5021117424 ps |
| CPU time | 154.05 seconds |
| Started | Oct 15 04:13:07 PM UTC 24 |
| Finished | Oct 15 04:15:43 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988830882 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.988830882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/69.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.3324757988 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 710682044 ps |
| CPU time | 349.65 seconds |
| Started | Oct 15 04:13:02 PM UTC 24 |
| Finished | Oct 15 04:18:57 PM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324757988 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_rand_reset.3324757988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.269664942 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 4845484855 ps |
| CPU time | 353.99 seconds |
| Started | Oct 15 04:13:07 PM UTC 24 |
| Finished | Oct 15 04:19:06 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269664942 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_reset_error.269664942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.4100840522 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 45523084 ps |
| CPU time | 8.26 seconds |
| Started | Oct 15 04:12:48 PM UTC 24 |
| Finished | Oct 15 04:12:57 PM UTC 24 |
| Peak memory | 591696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100840522 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.4100840522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/69.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.2388989641 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 10301633496 ps |
| CPU time | 723.41 seconds |
| Started | Oct 15 02:53:17 PM UTC 24 |
| Finished | Oct 15 03:05:29 PM UTC 24 |
| Peak memory | 668488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2388989641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 7.chip_csr_mem_rw_with_rand_reset.2388989641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.1742979805 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 28547300389 ps |
| CPU time | 3847.01 seconds |
| Started | Oct 15 02:51:10 PM UTC 24 |
| Finished | Oct 15 03:56:02 PM UTC 24 |
| Peak memory | 608932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1742979805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.chip_same_csr_outstanding.1742979805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.1937076362 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 3407250338 ps |
| CPU time | 277.86 seconds |
| Started | Oct 15 02:51:12 PM UTC 24 |
| Finished | Oct 15 02:55:54 PM UTC 24 |
| Peak memory | 613196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937076362 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.1937076362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.2885696022 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 1350708636 ps |
| CPU time | 73.59 seconds |
| Started | Oct 15 02:51:59 PM UTC 24 |
| Finished | Oct 15 02:53:15 PM UTC 24 |
| Peak memory | 593688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885696022 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.2885696022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.4100001412 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 13293452028 ps |
| CPU time | 186.93 seconds |
| Started | Oct 15 02:52:31 PM UTC 24 |
| Finished | Oct 15 02:55:41 PM UTC 24 |
| Peak memory | 594116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100001412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_devi ce_slow_rsp.4100001412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.2573291980 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 849895774 ps |
| CPU time | 44.19 seconds |
| Started | Oct 15 02:52:56 PM UTC 24 |
| Finished | Oct 15 02:53:41 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573291980 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.2573291980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.3251678141 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 1338957189 ps |
| CPU time | 59.74 seconds |
| Started | Oct 15 02:52:46 PM UTC 24 |
| Finished | Oct 15 02:53:47 PM UTC 24 |
| Peak memory | 593956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251678141 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3251678141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.1288307359 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 359825636 ps |
| CPU time | 46.72 seconds |
| Started | Oct 15 02:51:40 PM UTC 24 |
| Finished | Oct 15 02:52:29 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288307359 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.1288307359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.2930019038 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 35148045840 ps |
| CPU time | 424.61 seconds |
| Started | Oct 15 02:51:57 PM UTC 24 |
| Finished | Oct 15 02:59:07 PM UTC 24 |
| Peak memory | 593876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930019038 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2930019038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.3528373549 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 6549996303 ps |
| CPU time | 115.02 seconds |
| Started | Oct 15 02:51:57 PM UTC 24 |
| Finished | Oct 15 02:53:54 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528373549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3528373549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.1129101773 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 338972190 ps |
| CPU time | 37.9 seconds |
| Started | Oct 15 02:51:53 PM UTC 24 |
| Finished | Oct 15 02:52:32 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129101773 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.1129101773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.580419738 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 146664274 ps |
| CPU time | 11.6 seconds |
| Started | Oct 15 02:52:31 PM UTC 24 |
| Finished | Oct 15 02:52:43 PM UTC 24 |
| Peak memory | 591992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580419738 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.580419738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.3067345424 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 230406685 ps |
| CPU time | 13.94 seconds |
| Started | Oct 15 02:51:15 PM UTC 24 |
| Finished | Oct 15 02:51:30 PM UTC 24 |
| Peak memory | 591844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067345424 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3067345424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.2878629858 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 7238731969 ps |
| CPU time | 97.29 seconds |
| Started | Oct 15 02:51:19 PM UTC 24 |
| Finished | Oct 15 02:52:58 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878629858 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2878629858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.3618811182 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 5043134400 ps |
| CPU time | 83.33 seconds |
| Started | Oct 15 02:51:30 PM UTC 24 |
| Finished | Oct 15 02:52:56 PM UTC 24 |
| Peak memory | 591696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618811182 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3618811182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.1537360078 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 41800074 ps |
| CPU time | 6.17 seconds |
| Started | Oct 15 02:51:20 PM UTC 24 |
| Finished | Oct 15 02:51:27 PM UTC 24 |
| Peak memory | 591868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537360078 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.1537360078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.2938946638 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 548409906 ps |
| CPU time | 53.94 seconds |
| Started | Oct 15 02:52:57 PM UTC 24 |
| Finished | Oct 15 02:53:52 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938946638 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2938946638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.66550688 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 1547146945 ps |
| CPU time | 147.05 seconds |
| Started | Oct 15 02:53:01 PM UTC 24 |
| Finished | Oct 15 02:55:30 PM UTC 24 |
| Peak memory | 593860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66550688 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.66550688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.2177510879 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 431976044 ps |
| CPU time | 273.84 seconds |
| Started | Oct 15 02:53:07 PM UTC 24 |
| Finished | Oct 15 02:57:45 PM UTC 24 |
| Peak memory | 593736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177510879 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.2177510879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.3114340449 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 42192420 ps |
| CPU time | 11.21 seconds |
| Started | Oct 15 02:52:46 PM UTC 24 |
| Finished | Oct 15 02:52:59 PM UTC 24 |
| Peak memory | 591764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114340449 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3114340449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.4172886822 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 1862387851 ps |
| CPU time | 95.72 seconds |
| Started | Oct 15 04:13:54 PM UTC 24 |
| Finished | Oct 15 04:15:32 PM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172886822 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device.4172886822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/70.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.491156232 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 46845252619 ps |
| CPU time | 754.23 seconds |
| Started | Oct 15 04:13:56 PM UTC 24 |
| Finished | Oct 15 04:26:40 PM UTC 24 |
| Peak memory | 596892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491156232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_devi ce_slow_rsp.491156232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.584815363 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 231684188 ps |
| CPU time | 30.98 seconds |
| Started | Oct 15 04:14:12 PM UTC 24 |
| Finished | Oct 15 04:14:45 PM UTC 24 |
| Peak memory | 593848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584815363 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_addr.584815363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.1893860856 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 125340159 ps |
| CPU time | 10.41 seconds |
| Started | Oct 15 04:14:13 PM UTC 24 |
| Finished | Oct 15 04:14:25 PM UTC 24 |
| Peak memory | 591772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893860856 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.1893860856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/70.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.2738563181 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 2566892060 ps |
| CPU time | 91.15 seconds |
| Started | Oct 15 04:13:27 PM UTC 24 |
| Finished | Oct 15 04:15:01 PM UTC 24 |
| Peak memory | 593884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738563181 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.2738563181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/70.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.3397573283 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 53236554205 ps |
| CPU time | 564.3 seconds |
| Started | Oct 15 04:13:52 PM UTC 24 |
| Finished | Oct 15 04:23:24 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397573283 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.3397573283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/70.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.115111137 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 17801332681 ps |
| CPU time | 259.07 seconds |
| Started | Oct 15 04:13:56 PM UTC 24 |
| Finished | Oct 15 04:18:19 PM UTC 24 |
| Peak memory | 593748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115111137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.115111137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/70.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.1602921267 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 93768033 ps |
| CPU time | 15.39 seconds |
| Started | Oct 15 04:13:38 PM UTC 24 |
| Finished | Oct 15 04:13:55 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602921267 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_delays.1602921267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/70.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.2184273395 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 140303726 ps |
| CPU time | 18.13 seconds |
| Started | Oct 15 04:14:06 PM UTC 24 |
| Finished | Oct 15 04:14:25 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184273395 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.2184273395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/70.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.1393048534 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 36865040 ps |
| CPU time | 8.31 seconds |
| Started | Oct 15 04:13:15 PM UTC 24 |
| Finished | Oct 15 04:13:24 PM UTC 24 |
| Peak memory | 591736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393048534 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.1393048534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/70.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.4128419469 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 8406831151 ps |
| CPU time | 92.11 seconds |
| Started | Oct 15 04:13:23 PM UTC 24 |
| Finished | Oct 15 04:14:57 PM UTC 24 |
| Peak memory | 592132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128419469 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.4128419469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/70.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.2569539495 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 4930827965 ps |
| CPU time | 72.3 seconds |
| Started | Oct 15 04:13:22 PM UTC 24 |
| Finished | Oct 15 04:14:36 PM UTC 24 |
| Peak memory | 591692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569539495 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.2569539495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.501439337 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 51920039 ps |
| CPU time | 9.32 seconds |
| Started | Oct 15 04:13:19 PM UTC 24 |
| Finished | Oct 15 04:13:29 PM UTC 24 |
| Peak memory | 591624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501439337 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delays.501439337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/70.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.2074063317 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 2771785045 ps |
| CPU time | 205.64 seconds |
| Started | Oct 15 04:14:15 PM UTC 24 |
| Finished | Oct 15 04:17:44 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074063317 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.2074063317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/70.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.3970845235 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 4656293704 ps |
| CPU time | 322.65 seconds |
| Started | Oct 15 04:14:22 PM UTC 24 |
| Finished | Oct 15 04:19:49 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970845235 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.3970845235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/70.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.38200942 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 167803702 ps |
| CPU time | 40.25 seconds |
| Started | Oct 15 04:14:20 PM UTC 24 |
| Finished | Oct 15 04:15:02 PM UTC 24 |
| Peak memory | 593860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38200942 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_rand_reset.38200942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.683694122 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 4123874269 ps |
| CPU time | 159.54 seconds |
| Started | Oct 15 04:14:27 PM UTC 24 |
| Finished | Oct 15 04:17:09 PM UTC 24 |
| Peak memory | 593992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683694122 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_reset_error.683694122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.1850940003 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 221483264 ps |
| CPU time | 33.74 seconds |
| Started | Oct 15 04:14:13 PM UTC 24 |
| Finished | Oct 15 04:14:48 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850940003 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.1850940003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/70.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.1562885864 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 305436076 ps |
| CPU time | 28.7 seconds |
| Started | Oct 15 04:15:13 PM UTC 24 |
| Finished | Oct 15 04:15:43 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562885864 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device.1562885864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/71.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.2182000787 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 75965839161 ps |
| CPU time | 1120.79 seconds |
| Started | Oct 15 04:15:10 PM UTC 24 |
| Finished | Oct 15 04:34:04 PM UTC 24 |
| Peak memory | 596768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182000787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_dev ice_slow_rsp.2182000787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.712923738 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 220338439 ps |
| CPU time | 12.47 seconds |
| Started | Oct 15 04:15:23 PM UTC 24 |
| Finished | Oct 15 04:15:37 PM UTC 24 |
| Peak memory | 594016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712923738 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_addr.712923738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.2093360608 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 267659746 ps |
| CPU time | 26.57 seconds |
| Started | Oct 15 04:15:20 PM UTC 24 |
| Finished | Oct 15 04:15:48 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093360608 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.2093360608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/71.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.4259483492 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 1741777584 ps |
| CPU time | 59.3 seconds |
| Started | Oct 15 04:15:02 PM UTC 24 |
| Finished | Oct 15 04:16:03 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259483492 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.4259483492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/71.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.1023887363 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 21670042089 ps |
| CPU time | 288.19 seconds |
| Started | Oct 15 04:15:10 PM UTC 24 |
| Finished | Oct 15 04:20:02 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023887363 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.1023887363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/71.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.1073816878 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 18088455714 ps |
| CPU time | 257.44 seconds |
| Started | Oct 15 04:15:09 PM UTC 24 |
| Finished | Oct 15 04:19:31 PM UTC 24 |
| Peak memory | 593808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073816878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.1073816878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/71.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.1088813063 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 245381216 ps |
| CPU time | 21.69 seconds |
| Started | Oct 15 04:15:05 PM UTC 24 |
| Finished | Oct 15 04:15:28 PM UTC 24 |
| Peak memory | 593884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088813063 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_delays.1088813063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/71.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.1592853800 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 229271432 ps |
| CPU time | 19.6 seconds |
| Started | Oct 15 04:15:20 PM UTC 24 |
| Finished | Oct 15 04:15:41 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592853800 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.1592853800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/71.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.2284990909 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 184583015 ps |
| CPU time | 11.26 seconds |
| Started | Oct 15 04:14:41 PM UTC 24 |
| Finished | Oct 15 04:14:54 PM UTC 24 |
| Peak memory | 591740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284990909 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.2284990909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/71.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.2573521758 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 9691992698 ps |
| CPU time | 89.78 seconds |
| Started | Oct 15 04:14:52 PM UTC 24 |
| Finished | Oct 15 04:16:24 PM UTC 24 |
| Peak memory | 591940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573521758 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.2573521758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/71.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.2210155707 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 5620922983 ps |
| CPU time | 78.76 seconds |
| Started | Oct 15 04:14:58 PM UTC 24 |
| Finished | Oct 15 04:16:19 PM UTC 24 |
| Peak memory | 591684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210155707 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.2210155707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.395292291 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 46831045 ps |
| CPU time | 6.38 seconds |
| Started | Oct 15 04:14:51 PM UTC 24 |
| Finished | Oct 15 04:14:59 PM UTC 24 |
| Peak memory | 591772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395292291 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delays.395292291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/71.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.1751102594 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 3197966255 ps |
| CPU time | 256.54 seconds |
| Started | Oct 15 04:15:27 PM UTC 24 |
| Finished | Oct 15 04:19:47 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751102594 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.1751102594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/71.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.267979572 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 2090097147 ps |
| CPU time | 155.24 seconds |
| Started | Oct 15 04:15:42 PM UTC 24 |
| Finished | Oct 15 04:18:20 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267979572 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.267979572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/71.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.3686193223 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 1218989717 ps |
| CPU time | 370.53 seconds |
| Started | Oct 15 04:15:27 PM UTC 24 |
| Finished | Oct 15 04:21:43 PM UTC 24 |
| Peak memory | 593976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686193223 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_rand_reset.3686193223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.3826336272 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 1780309811 ps |
| CPU time | 340.55 seconds |
| Started | Oct 15 04:15:43 PM UTC 24 |
| Finished | Oct 15 04:21:29 PM UTC 24 |
| Peak memory | 593732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826336272 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_reset_error.3826336272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.1092506266 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 57444565 ps |
| CPU time | 12.79 seconds |
| Started | Oct 15 04:15:22 PM UTC 24 |
| Finished | Oct 15 04:15:36 PM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092506266 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.1092506266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/71.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.3064903500 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 2836253515 ps |
| CPU time | 119.4 seconds |
| Started | Oct 15 04:16:08 PM UTC 24 |
| Finished | Oct 15 04:18:10 PM UTC 24 |
| Peak memory | 593752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064903500 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device.3064903500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/72.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.14485881 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 33282227750 ps |
| CPU time | 509.13 seconds |
| Started | Oct 15 04:16:10 PM UTC 24 |
| Finished | Oct 15 04:24:46 PM UTC 24 |
| Peak memory | 593880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14485881 -assert n opostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_devic e_slow_rsp.14485881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.3392484965 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 214588116 ps |
| CPU time | 14.11 seconds |
| Started | Oct 15 04:16:17 PM UTC 24 |
| Finished | Oct 15 04:16:32 PM UTC 24 |
| Peak memory | 594004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392484965 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_addr.3392484965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.1255978224 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 1165888392 ps |
| CPU time | 41.43 seconds |
| Started | Oct 15 04:16:08 PM UTC 24 |
| Finished | Oct 15 04:16:51 PM UTC 24 |
| Peak memory | 593824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255978224 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.1255978224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/72.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.3726950367 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 608803964 ps |
| CPU time | 29.21 seconds |
| Started | Oct 15 04:15:59 PM UTC 24 |
| Finished | Oct 15 04:16:29 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726950367 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.3726950367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/72.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.819532042 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 45992934285 ps |
| CPU time | 441.94 seconds |
| Started | Oct 15 04:15:59 PM UTC 24 |
| Finished | Oct 15 04:23:27 PM UTC 24 |
| Peak memory | 593956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819532042 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.819532042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/72.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.2086609409 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 35543073739 ps |
| CPU time | 487.23 seconds |
| Started | Oct 15 04:16:03 PM UTC 24 |
| Finished | Oct 15 04:24:16 PM UTC 24 |
| Peak memory | 594092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086609409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.2086609409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/72.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.2098853899 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 616751691 ps |
| CPU time | 45.83 seconds |
| Started | Oct 15 04:15:59 PM UTC 24 |
| Finished | Oct 15 04:16:47 PM UTC 24 |
| Peak memory | 593912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098853899 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_delays.2098853899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/72.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.2749455522 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 535771146 ps |
| CPU time | 21.7 seconds |
| Started | Oct 15 04:16:05 PM UTC 24 |
| Finished | Oct 15 04:16:28 PM UTC 24 |
| Peak memory | 593668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749455522 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.2749455522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/72.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.2127333865 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 38161787 ps |
| CPU time | 8.48 seconds |
| Started | Oct 15 04:15:49 PM UTC 24 |
| Finished | Oct 15 04:15:59 PM UTC 24 |
| Peak memory | 591740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127333865 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.2127333865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/72.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.1749228557 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 8638603309 ps |
| CPU time | 119.38 seconds |
| Started | Oct 15 04:15:54 PM UTC 24 |
| Finished | Oct 15 04:17:55 PM UTC 24 |
| Peak memory | 591816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749228557 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.1749228557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/72.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.2003748817 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 6078044013 ps |
| CPU time | 96.54 seconds |
| Started | Oct 15 04:15:58 PM UTC 24 |
| Finished | Oct 15 04:17:37 PM UTC 24 |
| Peak memory | 591944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003748817 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.2003748817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.1712798349 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 55972255 ps |
| CPU time | 8.85 seconds |
| Started | Oct 15 04:15:52 PM UTC 24 |
| Finished | Oct 15 04:16:02 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712798349 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delays.1712798349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/72.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.2210306381 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 6710168525 ps |
| CPU time | 241.19 seconds |
| Started | Oct 15 04:16:22 PM UTC 24 |
| Finished | Oct 15 04:20:27 PM UTC 24 |
| Peak memory | 594036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210306381 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.2210306381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/72.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.2572823052 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 3468015204 ps |
| CPU time | 123.09 seconds |
| Started | Oct 15 04:16:30 PM UTC 24 |
| Finished | Oct 15 04:18:35 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572823052 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.2572823052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/72.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.305379334 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 142738996 ps |
| CPU time | 56.84 seconds |
| Started | Oct 15 04:16:26 PM UTC 24 |
| Finished | Oct 15 04:17:25 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305379334 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_rand_reset.305379334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.960305611 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 10108455500 ps |
| CPU time | 923.29 seconds |
| Started | Oct 15 04:16:31 PM UTC 24 |
| Finished | Oct 15 04:32:06 PM UTC 24 |
| Peak memory | 601004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960305611 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_reset_error.960305611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.3788234752 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 149753132 ps |
| CPU time | 25.26 seconds |
| Started | Oct 15 04:16:10 PM UTC 24 |
| Finished | Oct 15 04:16:36 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788234752 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.3788234752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/72.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.1536899415 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 1096465802 ps |
| CPU time | 99.93 seconds |
| Started | Oct 15 04:17:01 PM UTC 24 |
| Finished | Oct 15 04:18:43 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536899415 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device.1536899415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/73.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.2266753076 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 67987181803 ps |
| CPU time | 1071.86 seconds |
| Started | Oct 15 04:17:04 PM UTC 24 |
| Finished | Oct 15 04:35:09 PM UTC 24 |
| Peak memory | 596776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266753076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_dev ice_slow_rsp.2266753076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.2174234242 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 168079817 ps |
| CPU time | 13.69 seconds |
| Started | Oct 15 04:17:20 PM UTC 24 |
| Finished | Oct 15 04:17:35 PM UTC 24 |
| Peak memory | 591816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174234242 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_addr.2174234242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.2059305602 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 524766234 ps |
| CPU time | 40.94 seconds |
| Started | Oct 15 04:17:11 PM UTC 24 |
| Finished | Oct 15 04:17:54 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059305602 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.2059305602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/73.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.3800100217 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 469211989 ps |
| CPU time | 41.58 seconds |
| Started | Oct 15 04:16:54 PM UTC 24 |
| Finished | Oct 15 04:17:37 PM UTC 24 |
| Peak memory | 594064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800100217 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.3800100217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/73.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.3265617237 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 36593387529 ps |
| CPU time | 362.25 seconds |
| Started | Oct 15 04:16:59 PM UTC 24 |
| Finished | Oct 15 04:23:07 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265617237 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.3265617237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/73.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.2216459165 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 21078731397 ps |
| CPU time | 319.99 seconds |
| Started | Oct 15 04:17:00 PM UTC 24 |
| Finished | Oct 15 04:22:24 PM UTC 24 |
| Peak memory | 593956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216459165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.2216459165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/73.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.2952156933 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 573657022 ps |
| CPU time | 56.62 seconds |
| Started | Oct 15 04:16:55 PM UTC 24 |
| Finished | Oct 15 04:17:54 PM UTC 24 |
| Peak memory | 594016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952156933 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_delays.2952156933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/73.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.2803824145 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 542367040 ps |
| CPU time | 52.29 seconds |
| Started | Oct 15 04:17:13 PM UTC 24 |
| Finished | Oct 15 04:18:07 PM UTC 24 |
| Peak memory | 593816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803824145 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.2803824145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/73.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.718390955 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 43372098 ps |
| CPU time | 8.48 seconds |
| Started | Oct 15 04:16:39 PM UTC 24 |
| Finished | Oct 15 04:16:49 PM UTC 24 |
| Peak memory | 591612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718390955 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.718390955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/73.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.1368878632 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 7386548797 ps |
| CPU time | 88.69 seconds |
| Started | Oct 15 04:16:46 PM UTC 24 |
| Finished | Oct 15 04:18:16 PM UTC 24 |
| Peak memory | 592012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368878632 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.1368878632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/73.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.859832599 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 3192234822 ps |
| CPU time | 73.22 seconds |
| Started | Oct 15 04:16:50 PM UTC 24 |
| Finished | Oct 15 04:18:05 PM UTC 24 |
| Peak memory | 592100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859832599 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.859832599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.1056075247 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 37360661 ps |
| CPU time | 7.81 seconds |
| Started | Oct 15 04:16:44 PM UTC 24 |
| Finished | Oct 15 04:16:53 PM UTC 24 |
| Peak memory | 591756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056075247 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delays.1056075247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/73.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.2375711676 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 4934455303 ps |
| CPU time | 167.84 seconds |
| Started | Oct 15 04:17:31 PM UTC 24 |
| Finished | Oct 15 04:20:22 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375711676 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.2375711676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/73.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.3685241921 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 14651999466 ps |
| CPU time | 531.07 seconds |
| Started | Oct 15 04:17:40 PM UTC 24 |
| Finished | Oct 15 04:26:38 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685241921 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.3685241921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/73.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.2692363817 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 249662293 ps |
| CPU time | 90.53 seconds |
| Started | Oct 15 04:17:36 PM UTC 24 |
| Finished | Oct 15 04:19:08 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692363817 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_rand_reset.2692363817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.299580203 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 2702000809 ps |
| CPU time | 164.61 seconds |
| Started | Oct 15 04:17:52 PM UTC 24 |
| Finished | Oct 15 04:20:39 PM UTC 24 |
| Peak memory | 593992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299580203 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_reset_error.299580203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.642440820 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 97114517 ps |
| CPU time | 18.5 seconds |
| Started | Oct 15 04:17:17 PM UTC 24 |
| Finished | Oct 15 04:17:36 PM UTC 24 |
| Peak memory | 593676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642440820 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.642440820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/73.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.4188963512 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 591658879 ps |
| CPU time | 56.44 seconds |
| Started | Oct 15 04:18:33 PM UTC 24 |
| Finished | Oct 15 04:19:31 PM UTC 24 |
| Peak memory | 593692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188963512 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device.4188963512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/74.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.1750487538 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 30285299467 ps |
| CPU time | 430.29 seconds |
| Started | Oct 15 04:18:30 PM UTC 24 |
| Finished | Oct 15 04:25:46 PM UTC 24 |
| Peak memory | 593916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750487538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_dev ice_slow_rsp.1750487538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.2671315811 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 1192764962 ps |
| CPU time | 52.49 seconds |
| Started | Oct 15 04:18:42 PM UTC 24 |
| Finished | Oct 15 04:19:36 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671315811 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_addr.2671315811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.722963442 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 2099272417 ps |
| CPU time | 64.01 seconds |
| Started | Oct 15 04:18:35 PM UTC 24 |
| Finished | Oct 15 04:19:41 PM UTC 24 |
| Peak memory | 593864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722963442 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.722963442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/74.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.2359185451 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 1567764011 ps |
| CPU time | 66.89 seconds |
| Started | Oct 15 04:18:09 PM UTC 24 |
| Finished | Oct 15 04:19:18 PM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359185451 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.2359185451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/74.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.309648410 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 28662037835 ps |
| CPU time | 268.52 seconds |
| Started | Oct 15 04:18:20 PM UTC 24 |
| Finished | Oct 15 04:22:52 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309648410 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.309648410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/74.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.2141568062 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 29089424280 ps |
| CPU time | 400.5 seconds |
| Started | Oct 15 04:18:18 PM UTC 24 |
| Finished | Oct 15 04:25:04 PM UTC 24 |
| Peak memory | 593888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141568062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.2141568062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/74.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.3173850788 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 611389545 ps |
| CPU time | 52.21 seconds |
| Started | Oct 15 04:18:20 PM UTC 24 |
| Finished | Oct 15 04:19:14 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173850788 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_delays.3173850788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/74.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.936780456 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 2073609647 ps |
| CPU time | 68.47 seconds |
| Started | Oct 15 04:18:36 PM UTC 24 |
| Finished | Oct 15 04:19:46 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936780456 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.936780456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/74.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.3683682146 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 119623816 ps |
| CPU time | 10.13 seconds |
| Started | Oct 15 04:18:01 PM UTC 24 |
| Finished | Oct 15 04:18:12 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683682146 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.3683682146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/74.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.2580114145 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 9592763310 ps |
| CPU time | 123.86 seconds |
| Started | Oct 15 04:18:03 PM UTC 24 |
| Finished | Oct 15 04:20:09 PM UTC 24 |
| Peak memory | 592108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580114145 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.2580114145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/74.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.3361069406 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 7053089240 ps |
| CPU time | 104.39 seconds |
| Started | Oct 15 04:18:02 PM UTC 24 |
| Finished | Oct 15 04:19:48 PM UTC 24 |
| Peak memory | 591952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361069406 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.3361069406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.1487819893 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 37008996 ps |
| CPU time | 6.87 seconds |
| Started | Oct 15 04:18:02 PM UTC 24 |
| Finished | Oct 15 04:18:10 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487819893 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delays.1487819893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/74.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.28292469 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 19516056829 ps |
| CPU time | 658.58 seconds |
| Started | Oct 15 04:18:39 PM UTC 24 |
| Finished | Oct 15 04:29:46 PM UTC 24 |
| Peak memory | 594040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28292469 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.28292469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/74.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.1057217509 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 3041938185 ps |
| CPU time | 254.51 seconds |
| Started | Oct 15 04:18:45 PM UTC 24 |
| Finished | Oct 15 04:23:03 PM UTC 24 |
| Peak memory | 594024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057217509 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.1057217509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/74.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.2243859129 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 98486249 ps |
| CPU time | 35.3 seconds |
| Started | Oct 15 04:18:43 PM UTC 24 |
| Finished | Oct 15 04:19:20 PM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243859129 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_rand_reset.2243859129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3085642703 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 42743300 ps |
| CPU time | 33.86 seconds |
| Started | Oct 15 04:18:55 PM UTC 24 |
| Finished | Oct 15 04:19:30 PM UTC 24 |
| Peak memory | 593724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085642703 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_reset_error.3085642703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.2808049277 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 481357733 ps |
| CPU time | 20.97 seconds |
| Started | Oct 15 04:18:37 PM UTC 24 |
| Finished | Oct 15 04:18:59 PM UTC 24 |
| Peak memory | 593884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808049277 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.2808049277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/74.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.3920501410 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 2397875725 ps |
| CPU time | 102.76 seconds |
| Started | Oct 15 04:19:32 PM UTC 24 |
| Finished | Oct 15 04:21:17 PM UTC 24 |
| Peak memory | 594000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920501410 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device.3920501410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/75.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.1475930692 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 17813676051 ps |
| CPU time | 280.95 seconds |
| Started | Oct 15 04:19:34 PM UTC 24 |
| Finished | Oct 15 04:24:19 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475930692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_dev ice_slow_rsp.1475930692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.3491680011 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 318704476 ps |
| CPU time | 40.31 seconds |
| Started | Oct 15 04:19:42 PM UTC 24 |
| Finished | Oct 15 04:20:24 PM UTC 24 |
| Peak memory | 593756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491680011 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_addr.3491680011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.2798792167 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 1202714597 ps |
| CPU time | 48.22 seconds |
| Started | Oct 15 04:19:41 PM UTC 24 |
| Finished | Oct 15 04:20:31 PM UTC 24 |
| Peak memory | 594060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798792167 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.2798792167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/75.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.3629032760 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 2554596668 ps |
| CPU time | 101.02 seconds |
| Started | Oct 15 04:19:14 PM UTC 24 |
| Finished | Oct 15 04:20:57 PM UTC 24 |
| Peak memory | 594012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629032760 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.3629032760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/75.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.3681238905 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 48263078457 ps |
| CPU time | 462.77 seconds |
| Started | Oct 15 04:19:25 PM UTC 24 |
| Finished | Oct 15 04:27:13 PM UTC 24 |
| Peak memory | 593884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681238905 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.3681238905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/75.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.729707061 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 23651747344 ps |
| CPU time | 309.59 seconds |
| Started | Oct 15 04:19:27 PM UTC 24 |
| Finished | Oct 15 04:24:41 PM UTC 24 |
| Peak memory | 594108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729707061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.729707061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/75.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.93454456 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 145032813 ps |
| CPU time | 16.99 seconds |
| Started | Oct 15 04:19:16 PM UTC 24 |
| Finished | Oct 15 04:19:34 PM UTC 24 |
| Peak memory | 593908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93454456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_delays.93454456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/75.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.4202767619 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 2404086015 ps |
| CPU time | 82.12 seconds |
| Started | Oct 15 04:19:35 PM UTC 24 |
| Finished | Oct 15 04:20:59 PM UTC 24 |
| Peak memory | 593992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202767619 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.4202767619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/75.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.1308690989 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 189281304 ps |
| CPU time | 11.71 seconds |
| Started | Oct 15 04:18:56 PM UTC 24 |
| Finished | Oct 15 04:19:08 PM UTC 24 |
| Peak memory | 591740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308690989 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.1308690989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/75.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.2233368962 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 7173827306 ps |
| CPU time | 82.12 seconds |
| Started | Oct 15 04:19:06 PM UTC 24 |
| Finished | Oct 15 04:20:30 PM UTC 24 |
| Peak memory | 591816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233368962 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.2233368962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/75.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.2942378331 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 6026593085 ps |
| CPU time | 81.19 seconds |
| Started | Oct 15 04:19:07 PM UTC 24 |
| Finished | Oct 15 04:20:30 PM UTC 24 |
| Peak memory | 591944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942378331 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.2942378331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.333961061 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 49234188 ps |
| CPU time | 8.48 seconds |
| Started | Oct 15 04:19:03 PM UTC 24 |
| Finished | Oct 15 04:19:13 PM UTC 24 |
| Peak memory | 591772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333961061 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delays.333961061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/75.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.381304336 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 842412395 ps |
| CPU time | 74.08 seconds |
| Started | Oct 15 04:19:43 PM UTC 24 |
| Finished | Oct 15 04:20:59 PM UTC 24 |
| Peak memory | 593884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381304336 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.381304336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/75.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.1269971746 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 17920909196 ps |
| CPU time | 513.56 seconds |
| Started | Oct 15 04:19:52 PM UTC 24 |
| Finished | Oct 15 04:28:32 PM UTC 24 |
| Peak memory | 594036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269971746 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.1269971746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/75.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.914445119 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 7847596 ps |
| CPU time | 15.15 seconds |
| Started | Oct 15 04:19:44 PM UTC 24 |
| Finished | Oct 15 04:20:01 PM UTC 24 |
| Peak memory | 591972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914445119 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_rand_reset.914445119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.2967058652 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 364719792 ps |
| CPU time | 49 seconds |
| Started | Oct 15 04:19:54 PM UTC 24 |
| Finished | Oct 15 04:20:44 PM UTC 24 |
| Peak memory | 593836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967058652 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_reset_error.2967058652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.203527676 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 1305049917 ps |
| CPU time | 54.35 seconds |
| Started | Oct 15 04:19:39 PM UTC 24 |
| Finished | Oct 15 04:20:34 PM UTC 24 |
| Peak memory | 593816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203527676 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.203527676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/75.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.531896703 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 95337659 ps |
| CPU time | 10.51 seconds |
| Started | Oct 15 04:20:17 PM UTC 24 |
| Finished | Oct 15 04:20:28 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531896703 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device.531896703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/76.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.8468680 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 56304998297 ps |
| CPU time | 981.82 seconds |
| Started | Oct 15 04:20:14 PM UTC 24 |
| Finished | Oct 15 04:36:49 PM UTC 24 |
| Peak memory | 594884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8468680 -assert no postproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device _slow_rsp.8468680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2474260022 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 239015277 ps |
| CPU time | 34.42 seconds |
| Started | Oct 15 04:20:33 PM UTC 24 |
| Finished | Oct 15 04:21:09 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474260022 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_addr.2474260022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.3793633969 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 780421353 ps |
| CPU time | 36.37 seconds |
| Started | Oct 15 04:20:27 PM UTC 24 |
| Finished | Oct 15 04:21:04 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793633969 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.3793633969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/76.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.244341276 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 323188384 ps |
| CPU time | 30.83 seconds |
| Started | Oct 15 04:20:05 PM UTC 24 |
| Finished | Oct 15 04:20:37 PM UTC 24 |
| Peak memory | 593752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244341276 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.244341276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/76.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.1959551434 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 43182858130 ps |
| CPU time | 395.07 seconds |
| Started | Oct 15 04:20:11 PM UTC 24 |
| Finished | Oct 15 04:26:51 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959551434 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.1959551434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/76.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.182712926 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 15778103496 ps |
| CPU time | 227.51 seconds |
| Started | Oct 15 04:20:13 PM UTC 24 |
| Finished | Oct 15 04:24:03 PM UTC 24 |
| Peak memory | 593952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182712926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.182712926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/76.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.778476571 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 423753556 ps |
| CPU time | 47.38 seconds |
| Started | Oct 15 04:20:08 PM UTC 24 |
| Finished | Oct 15 04:20:57 PM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778476571 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_delays.778476571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/76.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.518120693 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 385789450 ps |
| CPU time | 35.46 seconds |
| Started | Oct 15 04:20:19 PM UTC 24 |
| Finished | Oct 15 04:20:57 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518120693 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.518120693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/76.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.2497711523 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 240173793 ps |
| CPU time | 13.3 seconds |
| Started | Oct 15 04:19:54 PM UTC 24 |
| Finished | Oct 15 04:20:08 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497711523 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.2497711523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/76.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.748973876 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 6293433412 ps |
| CPU time | 77.96 seconds |
| Started | Oct 15 04:19:59 PM UTC 24 |
| Finished | Oct 15 04:21:19 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748973876 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.748973876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/76.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.3485489365 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 5481698826 ps |
| CPU time | 71.47 seconds |
| Started | Oct 15 04:20:07 PM UTC 24 |
| Finished | Oct 15 04:21:20 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485489365 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.3485489365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.3461794210 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 51491017 ps |
| CPU time | 6.8 seconds |
| Started | Oct 15 04:20:01 PM UTC 24 |
| Finished | Oct 15 04:20:09 PM UTC 24 |
| Peak memory | 591740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461794210 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays.3461794210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/76.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.1685403218 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 6502028169 ps |
| CPU time | 221.02 seconds |
| Started | Oct 15 04:20:32 PM UTC 24 |
| Finished | Oct 15 04:24:16 PM UTC 24 |
| Peak memory | 594040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685403218 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.1685403218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/76.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.3843225307 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 3925607498 ps |
| CPU time | 107.83 seconds |
| Started | Oct 15 04:20:47 PM UTC 24 |
| Finished | Oct 15 04:22:36 PM UTC 24 |
| Peak memory | 594000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843225307 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.3843225307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/76.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.1533986788 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 7265758209 ps |
| CPU time | 288.76 seconds |
| Started | Oct 15 04:20:35 PM UTC 24 |
| Finished | Oct 15 04:25:28 PM UTC 24 |
| Peak memory | 593976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533986788 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_rand_reset.1533986788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.2476827251 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 5257670016 ps |
| CPU time | 561.17 seconds |
| Started | Oct 15 04:20:47 PM UTC 24 |
| Finished | Oct 15 04:30:15 PM UTC 24 |
| Peak memory | 597892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476827251 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_reset_error.2476827251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.4010707119 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 118686932 ps |
| CPU time | 15.14 seconds |
| Started | Oct 15 04:20:25 PM UTC 24 |
| Finished | Oct 15 04:20:41 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010707119 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.4010707119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/76.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.1751979377 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 2334198067 ps |
| CPU time | 97.91 seconds |
| Started | Oct 15 04:21:00 PM UTC 24 |
| Finished | Oct 15 04:22:40 PM UTC 24 |
| Peak memory | 593756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751979377 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device.1751979377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/77.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.1711678171 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 22104142907 ps |
| CPU time | 330.44 seconds |
| Started | Oct 15 04:20:58 PM UTC 24 |
| Finished | Oct 15 04:26:34 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711678171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_dev ice_slow_rsp.1711678171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.3600530100 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 819171283 ps |
| CPU time | 41.66 seconds |
| Started | Oct 15 04:21:22 PM UTC 24 |
| Finished | Oct 15 04:22:05 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600530100 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_addr.3600530100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.2821484586 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 1439036492 ps |
| CPU time | 55.89 seconds |
| Started | Oct 15 04:21:10 PM UTC 24 |
| Finished | Oct 15 04:22:07 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821484586 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.2821484586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/77.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.561764136 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 1471356679 ps |
| CPU time | 47.07 seconds |
| Started | Oct 15 04:20:51 PM UTC 24 |
| Finished | Oct 15 04:21:40 PM UTC 24 |
| Peak memory | 594076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561764136 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.561764136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/77.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.592752 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 16601646263 ps |
| CPU time | 155.48 seconds |
| Started | Oct 15 04:20:59 PM UTC 24 |
| Finished | Oct 15 04:23:36 PM UTC 24 |
| Peak memory | 593816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.592752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/77.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.28136561 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 14386909988 ps |
| CPU time | 230.42 seconds |
| Started | Oct 15 04:20:56 PM UTC 24 |
| Finished | Oct 15 04:24:50 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28136561 -assert n opostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.28136561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/77.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.1698682415 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 220208219 ps |
| CPU time | 21.72 seconds |
| Started | Oct 15 04:20:53 PM UTC 24 |
| Finished | Oct 15 04:21:16 PM UTC 24 |
| Peak memory | 594056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698682415 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_delays.1698682415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/77.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.720439552 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 1960648955 ps |
| CPU time | 58.63 seconds |
| Started | Oct 15 04:21:04 PM UTC 24 |
| Finished | Oct 15 04:22:05 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720439552 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.720439552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/77.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.3222563939 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 208828648 ps |
| CPU time | 11.86 seconds |
| Started | Oct 15 04:20:49 PM UTC 24 |
| Finished | Oct 15 04:21:03 PM UTC 24 |
| Peak memory | 591612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222563939 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.3222563939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/77.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.1409738876 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 8906259061 ps |
| CPU time | 99.34 seconds |
| Started | Oct 15 04:20:49 PM UTC 24 |
| Finished | Oct 15 04:22:30 PM UTC 24 |
| Peak memory | 591836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409738876 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.1409738876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/77.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.2477761708 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 3615061878 ps |
| CPU time | 52.36 seconds |
| Started | Oct 15 04:20:57 PM UTC 24 |
| Finished | Oct 15 04:21:51 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477761708 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.2477761708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.1520687406 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 48461974 ps |
| CPU time | 7.66 seconds |
| Started | Oct 15 04:20:52 PM UTC 24 |
| Finished | Oct 15 04:21:00 PM UTC 24 |
| Peak memory | 591612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520687406 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delays.1520687406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/77.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.4056636379 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 13870825557 ps |
| CPU time | 492.47 seconds |
| Started | Oct 15 04:21:17 PM UTC 24 |
| Finished | Oct 15 04:29:37 PM UTC 24 |
| Peak memory | 594028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056636379 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.4056636379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/77.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.2639755824 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 2207607998 ps |
| CPU time | 194.01 seconds |
| Started | Oct 15 04:21:21 PM UTC 24 |
| Finished | Oct 15 04:24:38 PM UTC 24 |
| Peak memory | 594056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639755824 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.2639755824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/77.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2732606433 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 3450059697 ps |
| CPU time | 530.52 seconds |
| Started | Oct 15 04:21:21 PM UTC 24 |
| Finished | Oct 15 04:30:19 PM UTC 24 |
| Peak memory | 594032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732606433 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_rand_reset.2732606433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.817383887 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 2766720318 ps |
| CPU time | 125.37 seconds |
| Started | Oct 15 04:21:27 PM UTC 24 |
| Finished | Oct 15 04:23:34 PM UTC 24 |
| Peak memory | 594052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817383887 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_reset_error.817383887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.811731675 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 199849601 ps |
| CPU time | 24.82 seconds |
| Started | Oct 15 04:21:13 PM UTC 24 |
| Finished | Oct 15 04:21:39 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811731675 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.811731675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/77.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.4067615475 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 974865090 ps |
| CPU time | 72.72 seconds |
| Started | Oct 15 04:21:46 PM UTC 24 |
| Finished | Oct 15 04:23:00 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067615475 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device.4067615475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/78.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.337916575 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 56818597182 ps |
| CPU time | 906.11 seconds |
| Started | Oct 15 04:21:49 PM UTC 24 |
| Finished | Oct 15 04:37:06 PM UTC 24 |
| Peak memory | 594524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337916575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_devi ce_slow_rsp.337916575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.2741226082 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 1114108142 ps |
| CPU time | 56.17 seconds |
| Started | Oct 15 04:21:57 PM UTC 24 |
| Finished | Oct 15 04:22:56 PM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741226082 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_addr.2741226082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.496584045 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 2511327378 ps |
| CPU time | 86.65 seconds |
| Started | Oct 15 04:21:53 PM UTC 24 |
| Finished | Oct 15 04:23:22 PM UTC 24 |
| Peak memory | 593892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496584045 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.496584045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/78.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.701055435 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 1043604206 ps |
| CPU time | 49.39 seconds |
| Started | Oct 15 04:21:41 PM UTC 24 |
| Finished | Oct 15 04:22:32 PM UTC 24 |
| Peak memory | 593760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701055435 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.701055435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/78.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_large_delays.522337856 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 56975076477 ps |
| CPU time | 585.05 seconds |
| Started | Oct 15 04:21:45 PM UTC 24 |
| Finished | Oct 15 04:31:37 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522337856 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.522337856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/78.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.2379790686 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 12755665178 ps |
| CPU time | 183.41 seconds |
| Started | Oct 15 04:21:40 PM UTC 24 |
| Finished | Oct 15 04:24:47 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379790686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.2379790686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/78.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.2689255179 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 265072236 ps |
| CPU time | 25.96 seconds |
| Started | Oct 15 04:21:39 PM UTC 24 |
| Finished | Oct 15 04:22:06 PM UTC 24 |
| Peak memory | 594088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689255179 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_delays.2689255179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/78.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.2894813649 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 479517795 ps |
| CPU time | 47 seconds |
| Started | Oct 15 04:21:47 PM UTC 24 |
| Finished | Oct 15 04:22:35 PM UTC 24 |
| Peak memory | 593824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894813649 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.2894813649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/78.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.3185583110 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 44603465 ps |
| CPU time | 8.81 seconds |
| Started | Oct 15 04:21:23 PM UTC 24 |
| Finished | Oct 15 04:21:33 PM UTC 24 |
| Peak memory | 592000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185583110 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.3185583110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/78.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.1976672553 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 9512179509 ps |
| CPU time | 95.29 seconds |
| Started | Oct 15 04:21:28 PM UTC 24 |
| Finished | Oct 15 04:23:05 PM UTC 24 |
| Peak memory | 592128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976672553 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.1976672553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/78.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.4134250844 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 3393028764 ps |
| CPU time | 77.73 seconds |
| Started | Oct 15 04:21:33 PM UTC 24 |
| Finished | Oct 15 04:22:53 PM UTC 24 |
| Peak memory | 591944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134250844 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.4134250844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.1342392633 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 56467045 ps |
| CPU time | 8.4 seconds |
| Started | Oct 15 04:21:26 PM UTC 24 |
| Finished | Oct 15 04:21:35 PM UTC 24 |
| Peak memory | 591860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342392633 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delays.1342392633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/78.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.2508637393 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 3914122361 ps |
| CPU time | 312.34 seconds |
| Started | Oct 15 04:22:01 PM UTC 24 |
| Finished | Oct 15 04:27:19 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508637393 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.2508637393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/78.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.2777841750 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 12709711523 ps |
| CPU time | 464.55 seconds |
| Started | Oct 15 04:22:04 PM UTC 24 |
| Finished | Oct 15 04:29:55 PM UTC 24 |
| Peak memory | 593976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777841750 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.2777841750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/78.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.2235211204 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 4051860139 ps |
| CPU time | 340.47 seconds |
| Started | Oct 15 04:22:07 PM UTC 24 |
| Finished | Oct 15 04:27:52 PM UTC 24 |
| Peak memory | 594156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235211204 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_rand_reset.2235211204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1070765292 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 29195891544 ps |
| CPU time | 1194.87 seconds |
| Started | Oct 15 04:22:04 PM UTC 24 |
| Finished | Oct 15 04:42:14 PM UTC 24 |
| Peak memory | 596968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070765292 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_reset_error.1070765292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.1555004077 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 1455491522 ps |
| CPU time | 55.49 seconds |
| Started | Oct 15 04:21:58 PM UTC 24 |
| Finished | Oct 15 04:22:56 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555004077 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.1555004077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/78.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.3571197394 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 109782769 ps |
| CPU time | 13.35 seconds |
| Started | Oct 15 04:22:59 PM UTC 24 |
| Finished | Oct 15 04:23:14 PM UTC 24 |
| Peak memory | 591828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571197394 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device.3571197394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/79.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.2545159087 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 40014092097 ps |
| CPU time | 665.83 seconds |
| Started | Oct 15 04:23:00 PM UTC 24 |
| Finished | Oct 15 04:34:14 PM UTC 24 |
| Peak memory | 593888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545159087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_dev ice_slow_rsp.2545159087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.1988631979 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 1383123433 ps |
| CPU time | 64.98 seconds |
| Started | Oct 15 04:23:04 PM UTC 24 |
| Finished | Oct 15 04:24:11 PM UTC 24 |
| Peak memory | 593756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988631979 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_addr.1988631979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.1285890785 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 425134510 ps |
| CPU time | 31.41 seconds |
| Started | Oct 15 04:23:04 PM UTC 24 |
| Finished | Oct 15 04:23:37 PM UTC 24 |
| Peak memory | 594012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285890785 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.1285890785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/79.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.3792007864 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 1620749333 ps |
| CPU time | 64.8 seconds |
| Started | Oct 15 04:22:34 PM UTC 24 |
| Finished | Oct 15 04:23:41 PM UTC 24 |
| Peak memory | 593676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792007864 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.3792007864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/79.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_large_delays.1894898743 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 45576508822 ps |
| CPU time | 436.72 seconds |
| Started | Oct 15 04:22:57 PM UTC 24 |
| Finished | Oct 15 04:30:20 PM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894898743 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.1894898743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/79.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.857630400 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 30261970060 ps |
| CPU time | 430.71 seconds |
| Started | Oct 15 04:23:00 PM UTC 24 |
| Finished | Oct 15 04:30:16 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857630400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.857630400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/79.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.884786581 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 625764722 ps |
| CPU time | 50.78 seconds |
| Started | Oct 15 04:22:51 PM UTC 24 |
| Finished | Oct 15 04:23:43 PM UTC 24 |
| Peak memory | 594020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884786581 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_delays.884786581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/79.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.245086077 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 245024764 ps |
| CPU time | 14.6 seconds |
| Started | Oct 15 04:23:04 PM UTC 24 |
| Finished | Oct 15 04:23:20 PM UTC 24 |
| Peak memory | 591636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245086077 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.245086077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/79.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.2505002729 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 204457676 ps |
| CPU time | 12.64 seconds |
| Started | Oct 15 04:22:18 PM UTC 24 |
| Finished | Oct 15 04:22:32 PM UTC 24 |
| Peak memory | 591616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505002729 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.2505002729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/79.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.3856426082 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 9098940371 ps |
| CPU time | 97.31 seconds |
| Started | Oct 15 04:22:33 PM UTC 24 |
| Finished | Oct 15 04:24:12 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856426082 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.3856426082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/79.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.766162415 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 5546759090 ps |
| CPU time | 123.85 seconds |
| Started | Oct 15 04:22:34 PM UTC 24 |
| Finished | Oct 15 04:24:41 PM UTC 24 |
| Peak memory | 591904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766162415 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.766162415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.4188859093 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 42539986 ps |
| CPU time | 7.44 seconds |
| Started | Oct 15 04:22:33 PM UTC 24 |
| Finished | Oct 15 04:22:41 PM UTC 24 |
| Peak memory | 591752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188859093 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delays.4188859093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/79.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.2905394549 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 2217833008 ps |
| CPU time | 167.47 seconds |
| Started | Oct 15 04:23:19 PM UTC 24 |
| Finished | Oct 15 04:26:09 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905394549 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.2905394549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/79.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.245484950 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 10947826229 ps |
| CPU time | 372.99 seconds |
| Started | Oct 15 04:23:16 PM UTC 24 |
| Finished | Oct 15 04:29:35 PM UTC 24 |
| Peak memory | 593776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245484950 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.245484950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/79.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1689050183 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 6950240915 ps |
| CPU time | 353.99 seconds |
| Started | Oct 15 04:23:15 PM UTC 24 |
| Finished | Oct 15 04:29:14 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689050183 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_rand_reset.1689050183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.2343385660 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 212372683 ps |
| CPU time | 42.44 seconds |
| Started | Oct 15 04:23:22 PM UTC 24 |
| Finished | Oct 15 04:24:06 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343385660 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_reset_error.2343385660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.3472354834 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 150036936 ps |
| CPU time | 19.5 seconds |
| Started | Oct 15 04:23:03 PM UTC 24 |
| Finished | Oct 15 04:23:23 PM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472354834 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.3472354834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/79.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.3626625654 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 7914802139 ps |
| CPU time | 754.16 seconds |
| Started | Oct 15 02:55:31 PM UTC 24 |
| Finished | Oct 15 03:08:15 PM UTC 24 |
| Peak memory | 668236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3626625654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 8.chip_csr_mem_rw_with_rand_reset.3626625654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.1620476636 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 6774397160 ps |
| CPU time | 667.65 seconds |
| Started | Oct 15 02:55:07 PM UTC 24 |
| Finished | Oct 15 03:06:23 PM UTC 24 |
| Peak memory | 616980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620476636 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.1620476636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.3122734164 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 15766096662 ps |
| CPU time | 1719.05 seconds |
| Started | Oct 15 02:53:18 PM UTC 24 |
| Finished | Oct 15 03:22:18 PM UTC 24 |
| Peak memory | 608788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3122734164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.chip_same_csr_outstanding.3122734164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.4018498604 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 3649922296 ps |
| CPU time | 317.24 seconds |
| Started | Oct 15 02:53:20 PM UTC 24 |
| Finished | Oct 15 02:58:42 PM UTC 24 |
| Peak memory | 619196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018498604 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.4018498604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.2611725273 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 492222308 ps |
| CPU time | 58.44 seconds |
| Started | Oct 15 02:54:04 PM UTC 24 |
| Finished | Oct 15 02:55:04 PM UTC 24 |
| Peak memory | 593692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611725273 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.2611725273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.1377558922 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 48418982807 ps |
| CPU time | 665.36 seconds |
| Started | Oct 15 02:54:07 PM UTC 24 |
| Finished | Oct 15 03:05:21 PM UTC 24 |
| Peak memory | 593980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377558922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_devi ce_slow_rsp.1377558922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.4197564459 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 1004694411 ps |
| CPU time | 56.51 seconds |
| Started | Oct 15 02:54:19 PM UTC 24 |
| Finished | Oct 15 02:55:18 PM UTC 24 |
| Peak memory | 594064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197564459 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.4197564459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.2967372571 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 1437422761 ps |
| CPU time | 52.16 seconds |
| Started | Oct 15 02:54:18 PM UTC 24 |
| Finished | Oct 15 02:55:12 PM UTC 24 |
| Peak memory | 593676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967372571 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2967372571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.3891887478 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 567882076 ps |
| CPU time | 59.67 seconds |
| Started | Oct 15 02:53:39 PM UTC 24 |
| Finished | Oct 15 02:54:40 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891887478 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.3891887478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.3499242187 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 41315462114 ps |
| CPU time | 454.26 seconds |
| Started | Oct 15 02:53:58 PM UTC 24 |
| Finished | Oct 15 03:01:39 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499242187 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3499242187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.2644045949 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 20235878205 ps |
| CPU time | 302.22 seconds |
| Started | Oct 15 02:54:00 PM UTC 24 |
| Finished | Oct 15 02:59:07 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644045949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2644045949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.3094265000 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 551506827 ps |
| CPU time | 54.23 seconds |
| Started | Oct 15 02:53:41 PM UTC 24 |
| Finished | Oct 15 02:54:37 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094265000 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.3094265000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.226557794 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1671687162 ps |
| CPU time | 67.65 seconds |
| Started | Oct 15 02:54:11 PM UTC 24 |
| Finished | Oct 15 02:55:20 PM UTC 24 |
| Peak memory | 593900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226557794 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.226557794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.3057327210 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 248982232 ps |
| CPU time | 15.83 seconds |
| Started | Oct 15 02:53:20 PM UTC 24 |
| Finished | Oct 15 02:53:37 PM UTC 24 |
| Peak memory | 592032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057327210 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3057327210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.3254289188 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 9864266779 ps |
| CPU time | 98.73 seconds |
| Started | Oct 15 02:53:28 PM UTC 24 |
| Finished | Oct 15 02:55:09 PM UTC 24 |
| Peak memory | 592132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254289188 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3254289188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.950802350 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 5539278780 ps |
| CPU time | 90.08 seconds |
| Started | Oct 15 02:53:37 PM UTC 24 |
| Finished | Oct 15 02:55:09 PM UTC 24 |
| Peak memory | 591832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950802350 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.950802350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3036698005 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 48714512 ps |
| CPU time | 8.84 seconds |
| Started | Oct 15 02:53:23 PM UTC 24 |
| Finished | Oct 15 02:53:33 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036698005 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3036698005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.1328526189 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 3255177273 ps |
| CPU time | 135.74 seconds |
| Started | Oct 15 02:54:42 PM UTC 24 |
| Finished | Oct 15 02:57:00 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328526189 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1328526189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.1616455567 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 283952069 ps |
| CPU time | 23.48 seconds |
| Started | Oct 15 02:55:01 PM UTC 24 |
| Finished | Oct 15 02:55:26 PM UTC 24 |
| Peak memory | 593812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616455567 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1616455567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.511212417 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 1086415886 ps |
| CPU time | 101.05 seconds |
| Started | Oct 15 02:54:55 PM UTC 24 |
| Finished | Oct 15 02:56:38 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511212417 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.511212417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.507208135 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 268574612 ps |
| CPU time | 45.58 seconds |
| Started | Oct 15 02:55:04 PM UTC 24 |
| Finished | Oct 15 02:55:51 PM UTC 24 |
| Peak memory | 594040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507208135 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.507208135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.2115073424 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 37182865 ps |
| CPU time | 10.77 seconds |
| Started | Oct 15 02:54:19 PM UTC 24 |
| Finished | Oct 15 02:54:31 PM UTC 24 |
| Peak memory | 591904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115073424 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2115073424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.1785520922 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 214921153 ps |
| CPU time | 21.63 seconds |
| Started | Oct 15 04:23:47 PM UTC 24 |
| Finished | Oct 15 04:24:10 PM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785520922 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device.1785520922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/80.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.2029155348 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 51177858763 ps |
| CPU time | 776.87 seconds |
| Started | Oct 15 04:23:46 PM UTC 24 |
| Finished | Oct 15 04:36:53 PM UTC 24 |
| Peak memory | 593888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029155348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_dev ice_slow_rsp.2029155348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.3653484954 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 106152976 ps |
| CPU time | 18.7 seconds |
| Started | Oct 15 04:24:01 PM UTC 24 |
| Finished | Oct 15 04:24:21 PM UTC 24 |
| Peak memory | 593864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653484954 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_addr.3653484954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.1668799437 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 1521866779 ps |
| CPU time | 40.23 seconds |
| Started | Oct 15 04:23:57 PM UTC 24 |
| Finished | Oct 15 04:24:39 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668799437 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.1668799437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/80.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.2492828020 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 2117987335 ps |
| CPU time | 69.43 seconds |
| Started | Oct 15 04:23:37 PM UTC 24 |
| Finished | Oct 15 04:24:49 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492828020 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.2492828020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/80.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_large_delays.1213674524 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 19716562384 ps |
| CPU time | 282.23 seconds |
| Started | Oct 15 04:23:45 PM UTC 24 |
| Finished | Oct 15 04:28:32 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213674524 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.1213674524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/80.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.523684897 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 11060906784 ps |
| CPU time | 166.24 seconds |
| Started | Oct 15 04:23:48 PM UTC 24 |
| Finished | Oct 15 04:26:37 PM UTC 24 |
| Peak memory | 594100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523684897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.523684897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/80.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.2213406414 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 579812050 ps |
| CPU time | 52.63 seconds |
| Started | Oct 15 04:23:45 PM UTC 24 |
| Finished | Oct 15 04:24:39 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213406414 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_delays.2213406414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/80.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.1563010455 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 165205274 ps |
| CPU time | 17.55 seconds |
| Started | Oct 15 04:23:49 PM UTC 24 |
| Finished | Oct 15 04:24:07 PM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563010455 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.1563010455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/80.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.3043838411 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 252960751 ps |
| CPU time | 13.42 seconds |
| Started | Oct 15 04:23:26 PM UTC 24 |
| Finished | Oct 15 04:23:41 PM UTC 24 |
| Peak memory | 591612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043838411 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.3043838411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/80.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.1655571439 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 7461065534 ps |
| CPU time | 74.09 seconds |
| Started | Oct 15 04:23:28 PM UTC 24 |
| Finished | Oct 15 04:24:44 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655571439 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.1655571439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/80.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.1611956523 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 4414408873 ps |
| CPU time | 69.87 seconds |
| Started | Oct 15 04:23:32 PM UTC 24 |
| Finished | Oct 15 04:24:44 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611956523 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.1611956523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.1024587618 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 47310610 ps |
| CPU time | 9.22 seconds |
| Started | Oct 15 04:23:28 PM UTC 24 |
| Finished | Oct 15 04:23:39 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024587618 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delays.1024587618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/80.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.3026410401 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 3410254511 ps |
| CPU time | 291.87 seconds |
| Started | Oct 15 04:24:02 PM UTC 24 |
| Finished | Oct 15 04:28:58 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026410401 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.3026410401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/80.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.2327757433 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 17734616547 ps |
| CPU time | 670.27 seconds |
| Started | Oct 15 04:24:09 PM UTC 24 |
| Finished | Oct 15 04:35:28 PM UTC 24 |
| Peak memory | 594028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327757433 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.2327757433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/80.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.3472719770 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 89382487 ps |
| CPU time | 17.33 seconds |
| Started | Oct 15 04:24:03 PM UTC 24 |
| Finished | Oct 15 04:24:21 PM UTC 24 |
| Peak memory | 591884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472719770 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_rand_reset.3472719770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.3095358406 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 223858157 ps |
| CPU time | 75.49 seconds |
| Started | Oct 15 04:24:04 PM UTC 24 |
| Finished | Oct 15 04:25:21 PM UTC 24 |
| Peak memory | 593724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095358406 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_reset_error.3095358406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.2735190524 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 51178952 ps |
| CPU time | 11.76 seconds |
| Started | Oct 15 04:23:56 PM UTC 24 |
| Finished | Oct 15 04:24:09 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735190524 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.2735190524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/80.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.1940677236 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 1872543074 ps |
| CPU time | 67.87 seconds |
| Started | Oct 15 04:24:43 PM UTC 24 |
| Finished | Oct 15 04:25:53 PM UTC 24 |
| Peak memory | 593692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940677236 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device.1940677236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/81.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.1134665694 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 71943413485 ps |
| CPU time | 1007.89 seconds |
| Started | Oct 15 04:24:43 PM UTC 24 |
| Finished | Oct 15 04:41:43 PM UTC 24 |
| Peak memory | 594440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134665694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_dev ice_slow_rsp.1134665694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.359838649 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 168613708 ps |
| CPU time | 22.22 seconds |
| Started | Oct 15 04:25:05 PM UTC 24 |
| Finished | Oct 15 04:25:28 PM UTC 24 |
| Peak memory | 593904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359838649 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_addr.359838649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.2873522016 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 1881915632 ps |
| CPU time | 55.19 seconds |
| Started | Oct 15 04:24:48 PM UTC 24 |
| Finished | Oct 15 04:25:44 PM UTC 24 |
| Peak memory | 593952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873522016 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.2873522016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/81.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.129061644 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 117715003 ps |
| CPU time | 16.99 seconds |
| Started | Oct 15 04:24:38 PM UTC 24 |
| Finished | Oct 15 04:24:56 PM UTC 24 |
| Peak memory | 593888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129061644 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.129061644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/81.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_large_delays.3231381789 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 35497431489 ps |
| CPU time | 352.22 seconds |
| Started | Oct 15 04:24:39 PM UTC 24 |
| Finished | Oct 15 04:30:36 PM UTC 24 |
| Peak memory | 593944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231381789 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.3231381789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/81.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_slow_rsp.3091407140 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 12508130614 ps |
| CPU time | 192.58 seconds |
| Started | Oct 15 04:24:41 PM UTC 24 |
| Finished | Oct 15 04:27:57 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091407140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.3091407140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/81.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.2077006506 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 99031712 ps |
| CPU time | 15.25 seconds |
| Started | Oct 15 04:24:37 PM UTC 24 |
| Finished | Oct 15 04:24:53 PM UTC 24 |
| Peak memory | 593824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077006506 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_delays.2077006506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/81.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.2554451854 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 365777671 ps |
| CPU time | 23.9 seconds |
| Started | Oct 15 04:24:46 PM UTC 24 |
| Finished | Oct 15 04:25:11 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554451854 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.2554451854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/81.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.475174941 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 192008552 ps |
| CPU time | 11.32 seconds |
| Started | Oct 15 04:24:29 PM UTC 24 |
| Finished | Oct 15 04:24:41 PM UTC 24 |
| Peak memory | 591612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475174941 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.475174941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/81.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.1168446622 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 6336388481 ps |
| CPU time | 62.74 seconds |
| Started | Oct 15 04:24:34 PM UTC 24 |
| Finished | Oct 15 04:25:38 PM UTC 24 |
| Peak memory | 591836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168446622 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.1168446622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/81.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.1038636750 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 4979690850 ps |
| CPU time | 67.03 seconds |
| Started | Oct 15 04:24:36 PM UTC 24 |
| Finished | Oct 15 04:25:44 PM UTC 24 |
| Peak memory | 591824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038636750 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.1038636750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.755693838 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 50957327 ps |
| CPU time | 9.5 seconds |
| Started | Oct 15 04:24:33 PM UTC 24 |
| Finished | Oct 15 04:24:44 PM UTC 24 |
| Peak memory | 591780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755693838 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delays.755693838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/81.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.3763002684 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 2650692371 ps |
| CPU time | 104.44 seconds |
| Started | Oct 15 04:25:02 PM UTC 24 |
| Finished | Oct 15 04:26:48 PM UTC 24 |
| Peak memory | 593876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763002684 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.3763002684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/81.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.736916031 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 3760953613 ps |
| CPU time | 267.32 seconds |
| Started | Oct 15 04:25:02 PM UTC 24 |
| Finished | Oct 15 04:29:33 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736916031 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.736916031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/81.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.572726336 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 286900308 ps |
| CPU time | 87.73 seconds |
| Started | Oct 15 04:25:00 PM UTC 24 |
| Finished | Oct 15 04:26:30 PM UTC 24 |
| Peak memory | 593724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572726336 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_rand_reset.572726336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.988896829 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 5368257627 ps |
| CPU time | 239.42 seconds |
| Started | Oct 15 04:25:03 PM UTC 24 |
| Finished | Oct 15 04:29:06 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988896829 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_reset_error.988896829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.3357695586 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 95816567 ps |
| CPU time | 9.31 seconds |
| Started | Oct 15 04:24:55 PM UTC 24 |
| Finished | Oct 15 04:25:05 PM UTC 24 |
| Peak memory | 591760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357695586 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.3357695586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/81.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.3945134813 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 638928727 ps |
| CPU time | 52.99 seconds |
| Started | Oct 15 04:25:20 PM UTC 24 |
| Finished | Oct 15 04:26:14 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945134813 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device.3945134813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/82.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.3368657880 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 62388244012 ps |
| CPU time | 920.71 seconds |
| Started | Oct 15 04:25:20 PM UTC 24 |
| Finished | Oct 15 04:40:52 PM UTC 24 |
| Peak memory | 593740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368657880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_dev ice_slow_rsp.3368657880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.1682359301 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 749855630 ps |
| CPU time | 30.99 seconds |
| Started | Oct 15 04:25:39 PM UTC 24 |
| Finished | Oct 15 04:26:11 PM UTC 24 |
| Peak memory | 593992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682359301 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_addr.1682359301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.2973292662 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 62379797 ps |
| CPU time | 11.36 seconds |
| Started | Oct 15 04:25:29 PM UTC 24 |
| Finished | Oct 15 04:25:42 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973292662 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.2973292662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/82.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.1681803066 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 486814048 ps |
| CPU time | 43.18 seconds |
| Started | Oct 15 04:25:12 PM UTC 24 |
| Finished | Oct 15 04:25:57 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681803066 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.1681803066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/82.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_large_delays.466844911 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 4430151940 ps |
| CPU time | 53.19 seconds |
| Started | Oct 15 04:25:12 PM UTC 24 |
| Finished | Oct 15 04:26:07 PM UTC 24 |
| Peak memory | 591696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466844911 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.466844911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/82.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_slow_rsp.3927226173 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 33260810383 ps |
| CPU time | 658.22 seconds |
| Started | Oct 15 04:25:13 PM UTC 24 |
| Finished | Oct 15 04:36:20 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927226173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.3927226173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/82.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.2812973756 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 154360059 ps |
| CPU time | 21.12 seconds |
| Started | Oct 15 04:25:10 PM UTC 24 |
| Finished | Oct 15 04:25:33 PM UTC 24 |
| Peak memory | 593812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812973756 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_delays.2812973756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/82.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.567808543 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 358821533 ps |
| CPU time | 31.91 seconds |
| Started | Oct 15 04:25:28 PM UTC 24 |
| Finished | Oct 15 04:26:02 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567808543 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.567808543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/82.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.285945502 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 59975842 ps |
| CPU time | 10.46 seconds |
| Started | Oct 15 04:25:04 PM UTC 24 |
| Finished | Oct 15 04:25:16 PM UTC 24 |
| Peak memory | 591792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285945502 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.285945502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/82.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.1300467683 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 8497801946 ps |
| CPU time | 87.3 seconds |
| Started | Oct 15 04:25:07 PM UTC 24 |
| Finished | Oct 15 04:26:36 PM UTC 24 |
| Peak memory | 591884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300467683 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.1300467683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/82.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.1208133527 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 3856513192 ps |
| CPU time | 53.81 seconds |
| Started | Oct 15 04:25:08 PM UTC 24 |
| Finished | Oct 15 04:26:03 PM UTC 24 |
| Peak memory | 591812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208133527 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.1208133527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.225451639 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 51440434 ps |
| CPU time | 9.82 seconds |
| Started | Oct 15 04:25:07 PM UTC 24 |
| Finished | Oct 15 04:25:18 PM UTC 24 |
| Peak memory | 591996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225451639 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delays.225451639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/82.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.1320618498 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 1275477522 ps |
| CPU time | 91.9 seconds |
| Started | Oct 15 04:25:39 PM UTC 24 |
| Finished | Oct 15 04:27:12 PM UTC 24 |
| Peak memory | 593736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320618498 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.1320618498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/82.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.325809650 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 17888371449 ps |
| CPU time | 560.14 seconds |
| Started | Oct 15 04:25:53 PM UTC 24 |
| Finished | Oct 15 04:35:20 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325809650 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.325809650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/82.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.3146738020 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 619686275 ps |
| CPU time | 219.44 seconds |
| Started | Oct 15 04:25:48 PM UTC 24 |
| Finished | Oct 15 04:29:31 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146738020 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_rand_reset.3146738020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.803882852 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 518092431 ps |
| CPU time | 154.55 seconds |
| Started | Oct 15 04:25:52 PM UTC 24 |
| Finished | Oct 15 04:28:29 PM UTC 24 |
| Peak memory | 593956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803882852 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_reset_error.803882852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.3411435525 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 1452241239 ps |
| CPU time | 61.42 seconds |
| Started | Oct 15 04:25:32 PM UTC 24 |
| Finished | Oct 15 04:26:35 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411435525 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.3411435525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/82.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.3959162088 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 2601164017 ps |
| CPU time | 104.13 seconds |
| Started | Oct 15 04:26:24 PM UTC 24 |
| Finished | Oct 15 04:28:10 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959162088 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device.3959162088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/83.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.2663437715 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 26260151969 ps |
| CPU time | 359.66 seconds |
| Started | Oct 15 04:26:23 PM UTC 24 |
| Finished | Oct 15 04:32:28 PM UTC 24 |
| Peak memory | 593812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663437715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_dev ice_slow_rsp.2663437715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.3872335063 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 1385078879 ps |
| CPU time | 54.34 seconds |
| Started | Oct 15 04:26:37 PM UTC 24 |
| Finished | Oct 15 04:27:33 PM UTC 24 |
| Peak memory | 593768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872335063 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_addr.3872335063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.1510924779 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 279162651 ps |
| CPU time | 24.72 seconds |
| Started | Oct 15 04:26:32 PM UTC 24 |
| Finished | Oct 15 04:26:58 PM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510924779 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.1510924779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/83.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.1470249929 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 2284148991 ps |
| CPU time | 83.4 seconds |
| Started | Oct 15 04:26:09 PM UTC 24 |
| Finished | Oct 15 04:27:35 PM UTC 24 |
| Peak memory | 593888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470249929 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.1470249929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/83.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_large_delays.4264809664 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 5136319712 ps |
| CPU time | 72.34 seconds |
| Started | Oct 15 04:26:10 PM UTC 24 |
| Finished | Oct 15 04:27:24 PM UTC 24 |
| Peak memory | 591700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264809664 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.4264809664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/83.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_slow_rsp.3884358596 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 20265838036 ps |
| CPU time | 303.99 seconds |
| Started | Oct 15 04:26:18 PM UTC 24 |
| Finished | Oct 15 04:31:26 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884358596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.3884358596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/83.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.2512554906 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 440804065 ps |
| CPU time | 37.84 seconds |
| Started | Oct 15 04:26:11 PM UTC 24 |
| Finished | Oct 15 04:26:50 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512554906 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_delays.2512554906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/83.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.1528605955 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 219990884 ps |
| CPU time | 26.84 seconds |
| Started | Oct 15 04:26:28 PM UTC 24 |
| Finished | Oct 15 04:26:56 PM UTC 24 |
| Peak memory | 594060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528605955 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.1528605955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/83.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.2443007870 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 259812852 ps |
| CPU time | 14.38 seconds |
| Started | Oct 15 04:25:58 PM UTC 24 |
| Finished | Oct 15 04:26:14 PM UTC 24 |
| Peak memory | 592044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443007870 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.2443007870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/83.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.3189884597 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 8160465788 ps |
| CPU time | 75.16 seconds |
| Started | Oct 15 04:26:04 PM UTC 24 |
| Finished | Oct 15 04:27:21 PM UTC 24 |
| Peak memory | 591880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189884597 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.3189884597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/83.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.2557925817 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 5474961112 ps |
| CPU time | 92.97 seconds |
| Started | Oct 15 04:26:08 PM UTC 24 |
| Finished | Oct 15 04:27:43 PM UTC 24 |
| Peak memory | 591816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557925817 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.2557925817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.1022495786 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 45491158 ps |
| CPU time | 7.28 seconds |
| Started | Oct 15 04:25:57 PM UTC 24 |
| Finished | Oct 15 04:26:05 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022495786 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delays.1022495786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/83.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.397519858 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 11681369331 ps |
| CPU time | 364.92 seconds |
| Started | Oct 15 04:26:35 PM UTC 24 |
| Finished | Oct 15 04:32:45 PM UTC 24 |
| Peak memory | 594056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397519858 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.397519858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/83.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.4165935922 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 1913261360 ps |
| CPU time | 140.36 seconds |
| Started | Oct 15 04:26:42 PM UTC 24 |
| Finished | Oct 15 04:29:05 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165935922 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.4165935922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/83.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3487969345 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 4464497786 ps |
| CPU time | 230.37 seconds |
| Started | Oct 15 04:26:41 PM UTC 24 |
| Finished | Oct 15 04:30:35 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487969345 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_rand_reset.3487969345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3551073275 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 8931946544 ps |
| CPU time | 552.61 seconds |
| Started | Oct 15 04:26:56 PM UTC 24 |
| Finished | Oct 15 04:36:16 PM UTC 24 |
| Peak memory | 593984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551073275 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_reset_error.3551073275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.2017236213 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 308151575 ps |
| CPU time | 20.59 seconds |
| Started | Oct 15 04:26:35 PM UTC 24 |
| Finished | Oct 15 04:26:57 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017236213 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.2017236213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/83.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.1047976768 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 105597914 ps |
| CPU time | 11.28 seconds |
| Started | Oct 15 04:27:17 PM UTC 24 |
| Finished | Oct 15 04:27:29 PM UTC 24 |
| Peak memory | 591772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047976768 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device.1047976768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/84.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2280098796 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 4239765605 ps |
| CPU time | 93.03 seconds |
| Started | Oct 15 04:27:20 PM UTC 24 |
| Finished | Oct 15 04:28:55 PM UTC 24 |
| Peak memory | 591940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280098796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_dev ice_slow_rsp.2280098796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.2799881293 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 544697605 ps |
| CPU time | 20.58 seconds |
| Started | Oct 15 04:27:39 PM UTC 24 |
| Finished | Oct 15 04:28:01 PM UTC 24 |
| Peak memory | 593880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799881293 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_addr.2799881293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.3993177732 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 390539176 ps |
| CPU time | 30.04 seconds |
| Started | Oct 15 04:27:25 PM UTC 24 |
| Finished | Oct 15 04:27:56 PM UTC 24 |
| Peak memory | 593824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993177732 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.3993177732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/84.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.2140163192 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 374468474 ps |
| CPU time | 38.14 seconds |
| Started | Oct 15 04:27:06 PM UTC 24 |
| Finished | Oct 15 04:27:46 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140163192 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.2140163192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/84.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_large_delays.1234694940 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 21700872370 ps |
| CPU time | 228.65 seconds |
| Started | Oct 15 04:27:14 PM UTC 24 |
| Finished | Oct 15 04:31:06 PM UTC 24 |
| Peak memory | 594092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234694940 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.1234694940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/84.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_slow_rsp.2069302936 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 5945732486 ps |
| CPU time | 85.22 seconds |
| Started | Oct 15 04:27:15 PM UTC 24 |
| Finished | Oct 15 04:28:42 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069302936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.2069302936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/84.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.1040874733 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 540643891 ps |
| CPU time | 58.77 seconds |
| Started | Oct 15 04:27:06 PM UTC 24 |
| Finished | Oct 15 04:28:07 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040874733 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_delays.1040874733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/84.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.599270697 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 142635643 ps |
| CPU time | 13.04 seconds |
| Started | Oct 15 04:27:22 PM UTC 24 |
| Finished | Oct 15 04:27:36 PM UTC 24 |
| Peak memory | 594024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599270697 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.599270697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/84.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.653838185 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 48452418 ps |
| CPU time | 9.16 seconds |
| Started | Oct 15 04:26:59 PM UTC 24 |
| Finished | Oct 15 04:27:09 PM UTC 24 |
| Peak memory | 591820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653838185 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.653838185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/84.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.568917816 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 9089136179 ps |
| CPU time | 90.04 seconds |
| Started | Oct 15 04:27:02 PM UTC 24 |
| Finished | Oct 15 04:28:34 PM UTC 24 |
| Peak memory | 591940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568917816 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.568917816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/84.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.1807413784 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 4362122192 ps |
| CPU time | 66.47 seconds |
| Started | Oct 15 04:27:00 PM UTC 24 |
| Finished | Oct 15 04:28:08 PM UTC 24 |
| Peak memory | 591952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807413784 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.1807413784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.3264233429 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 37312844 ps |
| CPU time | 8.24 seconds |
| Started | Oct 15 04:27:03 PM UTC 24 |
| Finished | Oct 15 04:27:12 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264233429 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delays.3264233429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/84.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.2563207439 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 5545596 ps |
| CPU time | 5.62 seconds |
| Started | Oct 15 04:27:38 PM UTC 24 |
| Finished | Oct 15 04:27:45 PM UTC 24 |
| Peak memory | 581292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563207439 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.2563207439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/84.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.3161251672 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 15635103703 ps |
| CPU time | 564.09 seconds |
| Started | Oct 15 04:27:44 PM UTC 24 |
| Finished | Oct 15 04:37:16 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161251672 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.3161251672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/84.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.2740255839 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 11347398853 ps |
| CPU time | 464.52 seconds |
| Started | Oct 15 04:27:37 PM UTC 24 |
| Finished | Oct 15 04:35:28 PM UTC 24 |
| Peak memory | 594028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740255839 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_rand_reset.2740255839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.787812560 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 35732070 ps |
| CPU time | 17.88 seconds |
| Started | Oct 15 04:27:48 PM UTC 24 |
| Finished | Oct 15 04:28:07 PM UTC 24 |
| Peak memory | 593844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787812560 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_reset_error.787812560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.4188974644 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 700855097 ps |
| CPU time | 44.55 seconds |
| Started | Oct 15 04:27:34 PM UTC 24 |
| Finished | Oct 15 04:28:20 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188974644 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.4188974644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/84.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.937236787 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 1096828157 ps |
| CPU time | 60.16 seconds |
| Started | Oct 15 04:28:15 PM UTC 24 |
| Finished | Oct 15 04:29:17 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937236787 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device.937236787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/85.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.1488668709 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 62823432007 ps |
| CPU time | 942.17 seconds |
| Started | Oct 15 04:28:21 PM UTC 24 |
| Finished | Oct 15 04:44:15 PM UTC 24 |
| Peak memory | 596972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488668709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_dev ice_slow_rsp.1488668709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.3582331065 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 212788000 ps |
| CPU time | 32.44 seconds |
| Started | Oct 15 04:28:26 PM UTC 24 |
| Finished | Oct 15 04:29:00 PM UTC 24 |
| Peak memory | 593752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582331065 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_addr.3582331065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.473570071 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 428710580 ps |
| CPU time | 20.77 seconds |
| Started | Oct 15 04:28:23 PM UTC 24 |
| Finished | Oct 15 04:28:46 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473570071 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.473570071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/85.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.363339193 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 282481427 ps |
| CPU time | 17.28 seconds |
| Started | Oct 15 04:28:01 PM UTC 24 |
| Finished | Oct 15 04:28:20 PM UTC 24 |
| Peak memory | 594056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363339193 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.363339193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/85.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_large_delays.1667500512 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 14714425138 ps |
| CPU time | 155.01 seconds |
| Started | Oct 15 04:28:11 PM UTC 24 |
| Finished | Oct 15 04:30:49 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667500512 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.1667500512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/85.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_slow_rsp.1883042663 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 3890575763 ps |
| CPU time | 57.61 seconds |
| Started | Oct 15 04:28:09 PM UTC 24 |
| Finished | Oct 15 04:29:09 PM UTC 24 |
| Peak memory | 591912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883042663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.1883042663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/85.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.731296975 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 368504027 ps |
| CPU time | 45.95 seconds |
| Started | Oct 15 04:28:09 PM UTC 24 |
| Finished | Oct 15 04:28:57 PM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731296975 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_delays.731296975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/85.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.3518906607 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 226742916 ps |
| CPU time | 18.1 seconds |
| Started | Oct 15 04:28:19 PM UTC 24 |
| Finished | Oct 15 04:28:39 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518906607 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.3518906607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/85.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.4170677279 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 49543417 ps |
| CPU time | 8.88 seconds |
| Started | Oct 15 04:27:45 PM UTC 24 |
| Finished | Oct 15 04:27:55 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170677279 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.4170677279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/85.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.1504889949 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 5104609825 ps |
| CPU time | 54.52 seconds |
| Started | Oct 15 04:27:58 PM UTC 24 |
| Finished | Oct 15 04:28:54 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504889949 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.1504889949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/85.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.2798172946 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 5558912661 ps |
| CPU time | 85.45 seconds |
| Started | Oct 15 04:27:59 PM UTC 24 |
| Finished | Oct 15 04:29:26 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798172946 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.2798172946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.4178705317 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 51103890 ps |
| CPU time | 8.09 seconds |
| Started | Oct 15 04:27:52 PM UTC 24 |
| Finished | Oct 15 04:28:01 PM UTC 24 |
| Peak memory | 591752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178705317 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delays.4178705317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/85.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.3848629962 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 9781301140 ps |
| CPU time | 308.32 seconds |
| Started | Oct 15 04:28:33 PM UTC 24 |
| Finished | Oct 15 04:33:46 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848629962 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.3848629962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/85.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.3078057053 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 3681577388 ps |
| CPU time | 239.66 seconds |
| Started | Oct 15 04:28:36 PM UTC 24 |
| Finished | Oct 15 04:32:39 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078057053 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.3078057053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/85.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.4081169004 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 354451821 ps |
| CPU time | 153.01 seconds |
| Started | Oct 15 04:28:31 PM UTC 24 |
| Finished | Oct 15 04:31:07 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081169004 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_rand_reset.4081169004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.3568818721 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 8340455118 ps |
| CPU time | 334.56 seconds |
| Started | Oct 15 04:28:32 PM UTC 24 |
| Finished | Oct 15 04:34:11 PM UTC 24 |
| Peak memory | 594120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568818721 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_reset_error.3568818721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.298663271 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 278997430 ps |
| CPU time | 43.92 seconds |
| Started | Oct 15 04:28:26 PM UTC 24 |
| Finished | Oct 15 04:29:12 PM UTC 24 |
| Peak memory | 593952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298663271 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.298663271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/85.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.562138386 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 1723794438 ps |
| CPU time | 89.95 seconds |
| Started | Oct 15 04:29:10 PM UTC 24 |
| Finished | Oct 15 04:30:42 PM UTC 24 |
| Peak memory | 593688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562138386 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device.562138386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/86.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.1337434092 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 8337906679 ps |
| CPU time | 131.22 seconds |
| Started | Oct 15 04:29:15 PM UTC 24 |
| Finished | Oct 15 04:31:28 PM UTC 24 |
| Peak memory | 593736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337434092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_dev ice_slow_rsp.1337434092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.284217495 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 855021068 ps |
| CPU time | 44.63 seconds |
| Started | Oct 15 04:29:23 PM UTC 24 |
| Finished | Oct 15 04:30:09 PM UTC 24 |
| Peak memory | 593804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284217495 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_addr.284217495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.996931719 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 1442993345 ps |
| CPU time | 57.11 seconds |
| Started | Oct 15 04:29:19 PM UTC 24 |
| Finished | Oct 15 04:30:18 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996931719 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.996931719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/86.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.278790992 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 911749983 ps |
| CPU time | 41 seconds |
| Started | Oct 15 04:29:00 PM UTC 24 |
| Finished | Oct 15 04:29:42 PM UTC 24 |
| Peak memory | 593860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278790992 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.278790992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/86.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_large_delays.4136040791 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 23612405308 ps |
| CPU time | 230.02 seconds |
| Started | Oct 15 04:29:04 PM UTC 24 |
| Finished | Oct 15 04:32:57 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136040791 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.4136040791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/86.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_slow_rsp.2256932626 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 30154561041 ps |
| CPU time | 390.77 seconds |
| Started | Oct 15 04:29:09 PM UTC 24 |
| Finished | Oct 15 04:35:45 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256932626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.2256932626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/86.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.1048426802 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 71105390 ps |
| CPU time | 12.16 seconds |
| Started | Oct 15 04:29:01 PM UTC 24 |
| Finished | Oct 15 04:29:14 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048426802 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_delays.1048426802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/86.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.1707650628 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 170548242 ps |
| CPU time | 14.81 seconds |
| Started | Oct 15 04:29:20 PM UTC 24 |
| Finished | Oct 15 04:29:36 PM UTC 24 |
| Peak memory | 593952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707650628 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.1707650628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/86.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.3135531766 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 53264299 ps |
| CPU time | 6.34 seconds |
| Started | Oct 15 04:28:42 PM UTC 24 |
| Finished | Oct 15 04:28:49 PM UTC 24 |
| Peak memory | 591612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135531766 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.3135531766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/86.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.2981534399 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 6372739738 ps |
| CPU time | 63.83 seconds |
| Started | Oct 15 04:28:55 PM UTC 24 |
| Finished | Oct 15 04:30:01 PM UTC 24 |
| Peak memory | 591824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981534399 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.2981534399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/86.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.1069701547 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 4664547292 ps |
| CPU time | 68.58 seconds |
| Started | Oct 15 04:28:56 PM UTC 24 |
| Finished | Oct 15 04:30:06 PM UTC 24 |
| Peak memory | 591816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069701547 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.1069701547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.191909602 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 53342634 ps |
| CPU time | 8.06 seconds |
| Started | Oct 15 04:28:46 PM UTC 24 |
| Finished | Oct 15 04:28:55 PM UTC 24 |
| Peak memory | 591788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191909602 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delays.191909602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/86.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.2875342920 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 17812300928 ps |
| CPU time | 566.9 seconds |
| Started | Oct 15 04:29:23 PM UTC 24 |
| Finished | Oct 15 04:38:57 PM UTC 24 |
| Peak memory | 593992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875342920 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.2875342920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/86.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.2146302000 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 12453546735 ps |
| CPU time | 375.18 seconds |
| Started | Oct 15 04:29:33 PM UTC 24 |
| Finished | Oct 15 04:35:53 PM UTC 24 |
| Peak memory | 594016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146302000 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.2146302000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/86.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.3816032728 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 4118038614 ps |
| CPU time | 347.62 seconds |
| Started | Oct 15 04:29:25 PM UTC 24 |
| Finished | Oct 15 04:35:18 PM UTC 24 |
| Peak memory | 594092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816032728 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_rand_reset.3816032728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.83187769 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 7191905124 ps |
| CPU time | 321.65 seconds |
| Started | Oct 15 04:29:31 PM UTC 24 |
| Finished | Oct 15 04:34:57 PM UTC 24 |
| Peak memory | 593784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83187769 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_reset_error.83187769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.2008294874 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 1190966914 ps |
| CPU time | 53.42 seconds |
| Started | Oct 15 04:29:18 PM UTC 24 |
| Finished | Oct 15 04:30:13 PM UTC 24 |
| Peak memory | 593756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008294874 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.2008294874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/86.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.2975242377 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 1408326102 ps |
| CPU time | 61.15 seconds |
| Started | Oct 15 04:29:58 PM UTC 24 |
| Finished | Oct 15 04:31:01 PM UTC 24 |
| Peak memory | 593692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975242377 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device.2975242377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/87.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2477033075 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 27660748409 ps |
| CPU time | 387.21 seconds |
| Started | Oct 15 04:30:04 PM UTC 24 |
| Finished | Oct 15 04:36:36 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477033075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_dev ice_slow_rsp.2477033075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.1299471870 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 127774307 ps |
| CPU time | 19.13 seconds |
| Started | Oct 15 04:30:15 PM UTC 24 |
| Finished | Oct 15 04:30:35 PM UTC 24 |
| Peak memory | 593676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299471870 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_addr.1299471870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.205536875 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 926636536 ps |
| CPU time | 34.23 seconds |
| Started | Oct 15 04:30:09 PM UTC 24 |
| Finished | Oct 15 04:30:44 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205536875 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.205536875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/87.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.2417288975 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 92169914 ps |
| CPU time | 13.45 seconds |
| Started | Oct 15 04:29:42 PM UTC 24 |
| Finished | Oct 15 04:29:56 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417288975 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.2417288975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/87.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_large_delays.1568111152 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 8954549241 ps |
| CPU time | 106.39 seconds |
| Started | Oct 15 04:29:55 PM UTC 24 |
| Finished | Oct 15 04:31:44 PM UTC 24 |
| Peak memory | 591732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568111152 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.1568111152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/87.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_slow_rsp.1829494548 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 28821767751 ps |
| CPU time | 380.09 seconds |
| Started | Oct 15 04:29:55 PM UTC 24 |
| Finished | Oct 15 04:36:20 PM UTC 24 |
| Peak memory | 594152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829494548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.1829494548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/87.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.2424671096 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 399746331 ps |
| CPU time | 42.42 seconds |
| Started | Oct 15 04:29:51 PM UTC 24 |
| Finished | Oct 15 04:30:35 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424671096 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_delays.2424671096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/87.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.583333844 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 439596766 ps |
| CPU time | 44.43 seconds |
| Started | Oct 15 04:30:00 PM UTC 24 |
| Finished | Oct 15 04:30:46 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583333844 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.583333844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/87.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.4159665272 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 237751756 ps |
| CPU time | 13.88 seconds |
| Started | Oct 15 04:29:33 PM UTC 24 |
| Finished | Oct 15 04:29:48 PM UTC 24 |
| Peak memory | 591836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159665272 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.4159665272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/87.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.835157919 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 6965138591 ps |
| CPU time | 66.49 seconds |
| Started | Oct 15 04:29:42 PM UTC 24 |
| Finished | Oct 15 04:30:50 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835157919 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.835157919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/87.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.1204929801 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 4357800472 ps |
| CPU time | 93.38 seconds |
| Started | Oct 15 04:29:37 PM UTC 24 |
| Finished | Oct 15 04:31:13 PM UTC 24 |
| Peak memory | 591816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204929801 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.1204929801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.565709220 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 41169444 ps |
| CPU time | 8.65 seconds |
| Started | Oct 15 04:29:39 PM UTC 24 |
| Finished | Oct 15 04:29:48 PM UTC 24 |
| Peak memory | 591616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565709220 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delays.565709220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/87.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all.3628276742 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 7587572739 ps |
| CPU time | 328.15 seconds |
| Started | Oct 15 04:30:12 PM UTC 24 |
| Finished | Oct 15 04:35:45 PM UTC 24 |
| Peak memory | 594160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628276742 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.3628276742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/87.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_error.1762461148 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 15635322158 ps |
| CPU time | 529.48 seconds |
| Started | Oct 15 04:30:23 PM UTC 24 |
| Finished | Oct 15 04:39:19 PM UTC 24 |
| Peak memory | 594156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762461148 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.1762461148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/87.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.2889426105 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 2832339830 ps |
| CPU time | 289.41 seconds |
| Started | Oct 15 04:30:23 PM UTC 24 |
| Finished | Oct 15 04:35:16 PM UTC 24 |
| Peak memory | 594156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889426105 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_rand_reset.2889426105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.2201762993 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 9563443 ps |
| CPU time | 44.09 seconds |
| Started | Oct 15 04:30:26 PM UTC 24 |
| Finished | Oct 15 04:31:11 PM UTC 24 |
| Peak memory | 593896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201762993 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_reset_error.2201762993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.183082238 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 296310535 ps |
| CPU time | 31.33 seconds |
| Started | Oct 15 04:30:13 PM UTC 24 |
| Finished | Oct 15 04:30:46 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183082238 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.183082238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/87.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.1209354483 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 3042032142 ps |
| CPU time | 139.48 seconds |
| Started | Oct 15 04:30:55 PM UTC 24 |
| Finished | Oct 15 04:33:17 PM UTC 24 |
| Peak memory | 593756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209354483 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device.1209354483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/88.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.843625141 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 16721290359 ps |
| CPU time | 369.65 seconds |
| Started | Oct 15 04:31:02 PM UTC 24 |
| Finished | Oct 15 04:37:18 PM UTC 24 |
| Peak memory | 594196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843625141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_devi ce_slow_rsp.843625141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.1183984332 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 366855191 ps |
| CPU time | 21.22 seconds |
| Started | Oct 15 04:31:07 PM UTC 24 |
| Finished | Oct 15 04:31:30 PM UTC 24 |
| Peak memory | 593672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183984332 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_addr.1183984332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.647608062 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 218901930 ps |
| CPU time | 25.48 seconds |
| Started | Oct 15 04:31:01 PM UTC 24 |
| Finished | Oct 15 04:31:28 PM UTC 24 |
| Peak memory | 593812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647608062 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.647608062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/88.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.707052641 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 511384558 ps |
| CPU time | 42.38 seconds |
| Started | Oct 15 04:30:40 PM UTC 24 |
| Finished | Oct 15 04:31:23 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707052641 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.707052641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/88.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_large_delays.209543727 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 54095703201 ps |
| CPU time | 612.18 seconds |
| Started | Oct 15 04:30:42 PM UTC 24 |
| Finished | Oct 15 04:41:01 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209543727 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.209543727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/88.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_slow_rsp.94212348 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 30559078594 ps |
| CPU time | 470.64 seconds |
| Started | Oct 15 04:30:44 PM UTC 24 |
| Finished | Oct 15 04:38:40 PM UTC 24 |
| Peak memory | 593980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94212348 -assert n opostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.94212348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/88.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.4149622590 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 71927655 ps |
| CPU time | 12.83 seconds |
| Started | Oct 15 04:30:43 PM UTC 24 |
| Finished | Oct 15 04:30:57 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149622590 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_delays.4149622590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/88.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.2405358094 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 1563027484 ps |
| CPU time | 46.03 seconds |
| Started | Oct 15 04:31:00 PM UTC 24 |
| Finished | Oct 15 04:31:48 PM UTC 24 |
| Peak memory | 593852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405358094 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.2405358094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/88.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.2888793772 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 188928849 ps |
| CPU time | 13.06 seconds |
| Started | Oct 15 04:30:28 PM UTC 24 |
| Finished | Oct 15 04:30:42 PM UTC 24 |
| Peak memory | 591860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888793772 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.2888793772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/88.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.3812677359 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 11298406124 ps |
| CPU time | 121.54 seconds |
| Started | Oct 15 04:30:37 PM UTC 24 |
| Finished | Oct 15 04:32:41 PM UTC 24 |
| Peak memory | 591880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812677359 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.3812677359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/88.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.93290809 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 5014827276 ps |
| CPU time | 76.38 seconds |
| Started | Oct 15 04:30:36 PM UTC 24 |
| Finished | Oct 15 04:31:54 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93290809 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.93290809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.2377304808 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 43977160 ps |
| CPU time | 7.71 seconds |
| Started | Oct 15 04:30:31 PM UTC 24 |
| Finished | Oct 15 04:30:40 PM UTC 24 |
| Peak memory | 591952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377304808 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delays.2377304808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/88.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all.3386419538 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 1965682261 ps |
| CPU time | 138.18 seconds |
| Started | Oct 15 04:31:07 PM UTC 24 |
| Finished | Oct 15 04:33:27 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386419538 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.3386419538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/88.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_error.3443749815 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 13581765436 ps |
| CPU time | 464.17 seconds |
| Started | Oct 15 04:31:11 PM UTC 24 |
| Finished | Oct 15 04:39:02 PM UTC 24 |
| Peak memory | 594216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443749815 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.3443749815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/88.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.3039172188 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 10802180883 ps |
| CPU time | 554.11 seconds |
| Started | Oct 15 04:31:07 PM UTC 24 |
| Finished | Oct 15 04:40:28 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039172188 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_rand_reset.3039172188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.4131289902 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 316532266 ps |
| CPU time | 111.49 seconds |
| Started | Oct 15 04:31:09 PM UTC 24 |
| Finished | Oct 15 04:33:02 PM UTC 24 |
| Peak memory | 593944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131289902 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_reset_error.4131289902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.3347794892 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 386360877 ps |
| CPU time | 19.75 seconds |
| Started | Oct 15 04:31:02 PM UTC 24 |
| Finished | Oct 15 04:31:23 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347794892 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.3347794892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/88.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.2671585402 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 1333497496 ps |
| CPU time | 63.38 seconds |
| Started | Oct 15 04:31:48 PM UTC 24 |
| Finished | Oct 15 04:32:53 PM UTC 24 |
| Peak memory | 593832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671585402 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device.2671585402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/89.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.4208387231 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 2516805312 ps |
| CPU time | 37.97 seconds |
| Started | Oct 15 04:31:50 PM UTC 24 |
| Finished | Oct 15 04:32:30 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208387231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_dev ice_slow_rsp.4208387231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.3654607102 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 1449875192 ps |
| CPU time | 65.78 seconds |
| Started | Oct 15 04:31:52 PM UTC 24 |
| Finished | Oct 15 04:33:00 PM UTC 24 |
| Peak memory | 593816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654607102 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_addr.3654607102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.1220868596 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 1430409812 ps |
| CPU time | 51.89 seconds |
| Started | Oct 15 04:31:48 PM UTC 24 |
| Finished | Oct 15 04:32:41 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220868596 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.1220868596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/89.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.3655842124 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 166384732 ps |
| CPU time | 20.3 seconds |
| Started | Oct 15 04:31:30 PM UTC 24 |
| Finished | Oct 15 04:31:51 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655842124 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.3655842124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/89.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_large_delays.3048620118 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 12122032563 ps |
| CPU time | 124.4 seconds |
| Started | Oct 15 04:31:37 PM UTC 24 |
| Finished | Oct 15 04:33:44 PM UTC 24 |
| Peak memory | 593916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048620118 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.3048620118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/89.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_slow_rsp.1329307796 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 4103833293 ps |
| CPU time | 75.73 seconds |
| Started | Oct 15 04:31:37 PM UTC 24 |
| Finished | Oct 15 04:32:55 PM UTC 24 |
| Peak memory | 591888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329307796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.1329307796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/89.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.3483813530 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 159883672 ps |
| CPU time | 16.34 seconds |
| Started | Oct 15 04:31:30 PM UTC 24 |
| Finished | Oct 15 04:31:47 PM UTC 24 |
| Peak memory | 593956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483813530 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_delays.3483813530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/89.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.432300080 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 2625611606 ps |
| CPU time | 77.95 seconds |
| Started | Oct 15 04:31:47 PM UTC 24 |
| Finished | Oct 15 04:33:07 PM UTC 24 |
| Peak memory | 593992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432300080 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.432300080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/89.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.3898576625 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 51466006 ps |
| CPU time | 8.77 seconds |
| Started | Oct 15 04:31:14 PM UTC 24 |
| Finished | Oct 15 04:31:24 PM UTC 24 |
| Peak memory | 591612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898576625 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.3898576625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/89.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.1534855539 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 6111080071 ps |
| CPU time | 67.11 seconds |
| Started | Oct 15 04:31:22 PM UTC 24 |
| Finished | Oct 15 04:32:31 PM UTC 24 |
| Peak memory | 591816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534855539 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.1534855539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/89.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.3347275561 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 5228131472 ps |
| CPU time | 67.38 seconds |
| Started | Oct 15 04:31:22 PM UTC 24 |
| Finished | Oct 15 04:32:31 PM UTC 24 |
| Peak memory | 591880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347275561 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.3347275561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.2179805749 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 50108313 ps |
| CPU time | 9.76 seconds |
| Started | Oct 15 04:31:13 PM UTC 24 |
| Finished | Oct 15 04:31:24 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179805749 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delays.2179805749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/89.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all.4013802968 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 2096968251 ps |
| CPU time | 55.73 seconds |
| Started | Oct 15 04:31:52 PM UTC 24 |
| Finished | Oct 15 04:32:49 PM UTC 24 |
| Peak memory | 593824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013802968 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.4013802968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/89.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_error.1323900030 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 8189065746 ps |
| CPU time | 314.86 seconds |
| Started | Oct 15 04:31:59 PM UTC 24 |
| Finished | Oct 15 04:37:18 PM UTC 24 |
| Peak memory | 593988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323900030 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.1323900030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/89.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.1980827839 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 1942797523 ps |
| CPU time | 387.41 seconds |
| Started | Oct 15 04:31:55 PM UTC 24 |
| Finished | Oct 15 04:38:27 PM UTC 24 |
| Peak memory | 593952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980827839 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_rand_reset.1980827839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.3810175141 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 2812597877 ps |
| CPU time | 118.47 seconds |
| Started | Oct 15 04:32:07 PM UTC 24 |
| Finished | Oct 15 04:34:08 PM UTC 24 |
| Peak memory | 594016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810175141 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_reset_error.3810175141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.3175239658 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 311987715 ps |
| CPU time | 44.94 seconds |
| Started | Oct 15 04:31:51 PM UTC 24 |
| Finished | Oct 15 04:32:38 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175239658 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.3175239658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/89.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.258587331 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 10277610234 ps |
| CPU time | 950.04 seconds |
| Started | Oct 15 02:57:05 PM UTC 24 |
| Finished | Oct 15 03:13:07 PM UTC 24 |
| Peak memory | 655948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=258587331 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.258587331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.1853703966 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 5525452350 ps |
| CPU time | 549.57 seconds |
| Started | Oct 15 02:57:03 PM UTC 24 |
| Finished | Oct 15 03:06:20 PM UTC 24 |
| Peak memory | 617308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853703966 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.1853703966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.3276006255 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 28545340330 ps |
| CPU time | 3947.33 seconds |
| Started | Oct 15 02:55:34 PM UTC 24 |
| Finished | Oct 15 04:02:06 PM UTC 24 |
| Peak memory | 611968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3276006255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.chip_same_csr_outstanding.3276006255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.4256123751 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 3176263055 ps |
| CPU time | 214.62 seconds |
| Started | Oct 15 02:55:35 PM UTC 24 |
| Finished | Oct 15 02:59:13 PM UTC 24 |
| Peak memory | 619016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256123751 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.4256123751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.678612027 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 1539563283 ps |
| CPU time | 83.67 seconds |
| Started | Oct 15 02:55:57 PM UTC 24 |
| Finished | Oct 15 02:57:22 PM UTC 24 |
| Peak memory | 593880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678612027 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.678612027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.3147125662 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 182224513 ps |
| CPU time | 27.42 seconds |
| Started | Oct 15 02:56:20 PM UTC 24 |
| Finished | Oct 15 02:56:49 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147125662 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.3147125662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.2024203278 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 368013714 ps |
| CPU time | 20.51 seconds |
| Started | Oct 15 02:56:14 PM UTC 24 |
| Finished | Oct 15 02:56:36 PM UTC 24 |
| Peak memory | 593816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024203278 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2024203278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.3128699833 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 550527927 ps |
| CPU time | 61.17 seconds |
| Started | Oct 15 02:55:50 PM UTC 24 |
| Finished | Oct 15 02:56:53 PM UTC 24 |
| Peak memory | 594116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128699833 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.3128699833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.963881628 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 55196299051 ps |
| CPU time | 501.05 seconds |
| Started | Oct 15 02:55:53 PM UTC 24 |
| Finished | Oct 15 03:04:20 PM UTC 24 |
| Peak memory | 593648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963881628 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.963881628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.2497309563 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 10357715404 ps |
| CPU time | 145.7 seconds |
| Started | Oct 15 02:55:53 PM UTC 24 |
| Finished | Oct 15 02:58:21 PM UTC 24 |
| Peak memory | 593480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497309563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2497309563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.1402410063 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 360497448 ps |
| CPU time | 42.28 seconds |
| Started | Oct 15 02:55:50 PM UTC 24 |
| Finished | Oct 15 02:56:34 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402410063 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1402410063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.1352820179 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 1191436601 ps |
| CPU time | 50.2 seconds |
| Started | Oct 15 02:56:10 PM UTC 24 |
| Finished | Oct 15 02:57:02 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352820179 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1352820179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.3507652072 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 52516299 ps |
| CPU time | 8.38 seconds |
| Started | Oct 15 02:55:38 PM UTC 24 |
| Finished | Oct 15 02:55:48 PM UTC 24 |
| Peak memory | 591608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507652072 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3507652072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.1311867947 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 7601357924 ps |
| CPU time | 72.92 seconds |
| Started | Oct 15 02:55:40 PM UTC 24 |
| Finished | Oct 15 02:56:55 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311867947 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1311867947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.1669315670 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 6255210246 ps |
| CPU time | 120.94 seconds |
| Started | Oct 15 02:55:43 PM UTC 24 |
| Finished | Oct 15 02:57:46 PM UTC 24 |
| Peak memory | 591696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669315670 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1669315670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.146413362 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 48868642 ps |
| CPU time | 9.04 seconds |
| Started | Oct 15 02:55:44 PM UTC 24 |
| Finished | Oct 15 02:55:54 PM UTC 24 |
| Peak memory | 591832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146413362 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.146413362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.384859027 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 2338260096 ps |
| CPU time | 192.77 seconds |
| Started | Oct 15 02:56:22 PM UTC 24 |
| Finished | Oct 15 02:59:37 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384859027 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.384859027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.2603029005 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 1976667031 ps |
| CPU time | 66.07 seconds |
| Started | Oct 15 02:56:47 PM UTC 24 |
| Finished | Oct 15 02:57:54 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603029005 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2603029005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.3317126324 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 175192636 ps |
| CPU time | 71.63 seconds |
| Started | Oct 15 02:57:00 PM UTC 24 |
| Finished | Oct 15 02:58:14 PM UTC 24 |
| Peak memory | 594100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317126324 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.3317126324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.2068601349 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 476703472 ps |
| CPU time | 29.26 seconds |
| Started | Oct 15 02:56:17 PM UTC 24 |
| Finished | Oct 15 02:56:47 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068601349 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2068601349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.1488063679 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 3449689399 ps |
| CPU time | 132.52 seconds |
| Started | Oct 15 04:32:53 PM UTC 24 |
| Finished | Oct 15 04:35:08 PM UTC 24 |
| Peak memory | 593756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488063679 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device.1488063679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/90.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.2470807236 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 5392144739 ps |
| CPU time | 110.42 seconds |
| Started | Oct 15 04:32:58 PM UTC 24 |
| Finished | Oct 15 04:34:50 PM UTC 24 |
| Peak memory | 593884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470807236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_dev ice_slow_rsp.2470807236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.1190872714 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 1119621947 ps |
| CPU time | 44.56 seconds |
| Started | Oct 15 04:33:06 PM UTC 24 |
| Finished | Oct 15 04:33:53 PM UTC 24 |
| Peak memory | 593668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190872714 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_addr.1190872714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.3902928291 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 255444037 ps |
| CPU time | 25.49 seconds |
| Started | Oct 15 04:33:04 PM UTC 24 |
| Finished | Oct 15 04:33:31 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902928291 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.3902928291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/90.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.3644913784 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 892317089 ps |
| CPU time | 46.38 seconds |
| Started | Oct 15 04:32:31 PM UTC 24 |
| Finished | Oct 15 04:33:19 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644913784 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.3644913784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/90.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_large_delays.659857692 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 22583035293 ps |
| CPU time | 216.83 seconds |
| Started | Oct 15 04:32:46 PM UTC 24 |
| Finished | Oct 15 04:36:26 PM UTC 24 |
| Peak memory | 593960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659857692 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.659857692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/90.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_slow_rsp.2282550694 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 22243174533 ps |
| CPU time | 292.58 seconds |
| Started | Oct 15 04:32:49 PM UTC 24 |
| Finished | Oct 15 04:37:46 PM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282550694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.2282550694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/90.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.4031240508 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 292162561 ps |
| CPU time | 33.85 seconds |
| Started | Oct 15 04:32:47 PM UTC 24 |
| Finished | Oct 15 04:33:22 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031240508 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_delays.4031240508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/90.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.759917486 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 512150102 ps |
| CPU time | 53.66 seconds |
| Started | Oct 15 04:32:56 PM UTC 24 |
| Finished | Oct 15 04:33:51 PM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759917486 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.759917486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/90.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.1549705476 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 221956761 ps |
| CPU time | 11.3 seconds |
| Started | Oct 15 04:32:11 PM UTC 24 |
| Finished | Oct 15 04:32:24 PM UTC 24 |
| Peak memory | 592000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549705476 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.1549705476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/90.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.1392975685 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 9106099338 ps |
| CPU time | 90.01 seconds |
| Started | Oct 15 04:32:19 PM UTC 24 |
| Finished | Oct 15 04:33:51 PM UTC 24 |
| Peak memory | 591816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392975685 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.1392975685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/90.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.438260935 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 5618923428 ps |
| CPU time | 93.18 seconds |
| Started | Oct 15 04:32:21 PM UTC 24 |
| Finished | Oct 15 04:33:56 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438260935 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.438260935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.1092588173 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 40093507 ps |
| CPU time | 9.01 seconds |
| Started | Oct 15 04:32:11 PM UTC 24 |
| Finished | Oct 15 04:32:21 PM UTC 24 |
| Peak memory | 591868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092588173 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delays.1092588173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/90.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all.3746004379 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 868846813 ps |
| CPU time | 62.39 seconds |
| Started | Oct 15 04:33:05 PM UTC 24 |
| Finished | Oct 15 04:34:09 PM UTC 24 |
| Peak memory | 593668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746004379 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.3746004379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/90.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_error.3776841201 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 21254228694 ps |
| CPU time | 709.83 seconds |
| Started | Oct 15 04:33:13 PM UTC 24 |
| Finished | Oct 15 04:45:12 PM UTC 24 |
| Peak memory | 594568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776841201 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.3776841201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/90.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.4058619038 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 1296835863 ps |
| CPU time | 244.76 seconds |
| Started | Oct 15 04:33:09 PM UTC 24 |
| Finished | Oct 15 04:37:18 PM UTC 24 |
| Peak memory | 593732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058619038 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_rand_reset.4058619038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.1584221144 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 2941697627 ps |
| CPU time | 370.72 seconds |
| Started | Oct 15 04:33:17 PM UTC 24 |
| Finished | Oct 15 04:39:33 PM UTC 24 |
| Peak memory | 594140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584221144 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_reset_error.1584221144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.1191208896 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 23406828 ps |
| CPU time | 5.34 seconds |
| Started | Oct 15 04:33:05 PM UTC 24 |
| Finished | Oct 15 04:33:11 PM UTC 24 |
| Peak memory | 591632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191208896 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.1191208896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/90.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.3849799205 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 498067555 ps |
| CPU time | 36.12 seconds |
| Started | Oct 15 04:33:47 PM UTC 24 |
| Finished | Oct 15 04:34:25 PM UTC 24 |
| Peak memory | 593692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849799205 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device.3849799205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/91.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.1775371249 |
| Short name | T2908 |
| Test name | |
| Test status | |
| Simulation time | 56471695903 ps |
| CPU time | 803.14 seconds |
| Started | Oct 15 04:33:55 PM UTC 24 |
| Finished | Oct 15 04:47:28 PM UTC 24 |
| Peak memory | 596668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775371249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_dev ice_slow_rsp.1775371249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.3395243486 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 149623824 ps |
| CPU time | 18.78 seconds |
| Started | Oct 15 04:34:09 PM UTC 24 |
| Finished | Oct 15 04:34:28 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395243486 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_addr.3395243486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.3877657430 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 351524464 ps |
| CPU time | 28.56 seconds |
| Started | Oct 15 04:33:59 PM UTC 24 |
| Finished | Oct 15 04:34:29 PM UTC 24 |
| Peak memory | 593688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877657430 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.3877657430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/91.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.1443412716 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 381307585 ps |
| CPU time | 43.91 seconds |
| Started | Oct 15 04:33:34 PM UTC 24 |
| Finished | Oct 15 04:34:19 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443412716 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.1443412716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/91.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_large_delays.3682875496 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 20645541757 ps |
| CPU time | 273.6 seconds |
| Started | Oct 15 04:33:40 PM UTC 24 |
| Finished | Oct 15 04:38:18 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682875496 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.3682875496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/91.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_slow_rsp.2052700770 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 16604102971 ps |
| CPU time | 217.48 seconds |
| Started | Oct 15 04:33:43 PM UTC 24 |
| Finished | Oct 15 04:37:23 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052700770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.2052700770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/91.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.3588673769 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 208312417 ps |
| CPU time | 23.6 seconds |
| Started | Oct 15 04:33:36 PM UTC 24 |
| Finished | Oct 15 04:34:01 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588673769 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_delays.3588673769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/91.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.1405047699 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 2120690528 ps |
| CPU time | 57.9 seconds |
| Started | Oct 15 04:33:53 PM UTC 24 |
| Finished | Oct 15 04:34:52 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405047699 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.1405047699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/91.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.434729310 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 41955296 ps |
| CPU time | 8.87 seconds |
| Started | Oct 15 04:33:17 PM UTC 24 |
| Finished | Oct 15 04:33:27 PM UTC 24 |
| Peak memory | 591860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434729310 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.434729310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/91.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.1832989615 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 9124826704 ps |
| CPU time | 95.91 seconds |
| Started | Oct 15 04:33:22 PM UTC 24 |
| Finished | Oct 15 04:35:00 PM UTC 24 |
| Peak memory | 591832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832989615 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.1832989615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/91.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.1669034640 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 6246350660 ps |
| CPU time | 106.75 seconds |
| Started | Oct 15 04:33:27 PM UTC 24 |
| Finished | Oct 15 04:35:16 PM UTC 24 |
| Peak memory | 592024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669034640 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.1669034640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.2935669916 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 45317377 ps |
| CPU time | 9.18 seconds |
| Started | Oct 15 04:33:20 PM UTC 24 |
| Finished | Oct 15 04:33:30 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935669916 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delays.2935669916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/91.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all.1434478701 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 8278349163 ps |
| CPU time | 267.23 seconds |
| Started | Oct 15 04:34:08 PM UTC 24 |
| Finished | Oct 15 04:38:39 PM UTC 24 |
| Peak memory | 594036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434478701 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.1434478701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/91.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_error.239335493 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 1030981453 ps |
| CPU time | 95.9 seconds |
| Started | Oct 15 04:34:15 PM UTC 24 |
| Finished | Oct 15 04:35:53 PM UTC 24 |
| Peak memory | 593864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239335493 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.239335493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/91.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.3346869995 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 1460255905 ps |
| CPU time | 324.62 seconds |
| Started | Oct 15 04:34:14 PM UTC 24 |
| Finished | Oct 15 04:39:43 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346869995 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_rand_reset.3346869995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.424970072 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 9071857155 ps |
| CPU time | 411.98 seconds |
| Started | Oct 15 04:34:16 PM UTC 24 |
| Finished | Oct 15 04:41:13 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424970072 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_reset_error.424970072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.2282458709 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 305078625 ps |
| CPU time | 22.38 seconds |
| Started | Oct 15 04:33:56 PM UTC 24 |
| Finished | Oct 15 04:34:20 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282458709 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.2282458709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/91.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device.1195354814 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 2252611175 ps |
| CPU time | 131.56 seconds |
| Started | Oct 15 04:34:42 PM UTC 24 |
| Finished | Oct 15 04:36:56 PM UTC 24 |
| Peak memory | 593828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195354814 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device.1195354814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/92.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.2395980444 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 39408494864 ps |
| CPU time | 548.92 seconds |
| Started | Oct 15 04:34:49 PM UTC 24 |
| Finished | Oct 15 04:44:05 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395980444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_dev ice_slow_rsp.2395980444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.482507878 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 147466825 ps |
| CPU time | 23.34 seconds |
| Started | Oct 15 04:35:03 PM UTC 24 |
| Finished | Oct 15 04:35:27 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482507878 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_addr.482507878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.3967024326 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 526479463 ps |
| CPU time | 37.99 seconds |
| Started | Oct 15 04:34:56 PM UTC 24 |
| Finished | Oct 15 04:35:35 PM UTC 24 |
| Peak memory | 593676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967024326 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.3967024326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/92.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.1600733937 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 1971373720 ps |
| CPU time | 65.94 seconds |
| Started | Oct 15 04:34:32 PM UTC 24 |
| Finished | Oct 15 04:35:39 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600733937 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.1600733937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/92.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_large_delays.2595239006 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 28732531431 ps |
| CPU time | 281.09 seconds |
| Started | Oct 15 04:34:34 PM UTC 24 |
| Finished | Oct 15 04:39:19 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595239006 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.2595239006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/92.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_slow_rsp.272350831 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 20648882487 ps |
| CPU time | 276.56 seconds |
| Started | Oct 15 04:34:44 PM UTC 24 |
| Finished | Oct 15 04:39:24 PM UTC 24 |
| Peak memory | 593972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272350831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.272350831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/92.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.29264359 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 462579308 ps |
| CPU time | 53.31 seconds |
| Started | Oct 15 04:34:33 PM UTC 24 |
| Finished | Oct 15 04:35:28 PM UTC 24 |
| Peak memory | 593668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29264359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_delays.29264359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/92.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.3702791826 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 308734406 ps |
| CPU time | 15.9 seconds |
| Started | Oct 15 04:34:52 PM UTC 24 |
| Finished | Oct 15 04:35:09 PM UTC 24 |
| Peak memory | 594064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702791826 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.3702791826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/92.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.3418724223 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 220392319 ps |
| CPU time | 13.32 seconds |
| Started | Oct 15 04:34:22 PM UTC 24 |
| Finished | Oct 15 04:34:36 PM UTC 24 |
| Peak memory | 591956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418724223 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.3418724223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/92.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_large_delays.1722012774 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 8195085803 ps |
| CPU time | 70.99 seconds |
| Started | Oct 15 04:34:23 PM UTC 24 |
| Finished | Oct 15 04:35:36 PM UTC 24 |
| Peak memory | 592012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722012774 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.1722012774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/92.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.825815210 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 5394938006 ps |
| CPU time | 83.85 seconds |
| Started | Oct 15 04:34:31 PM UTC 24 |
| Finished | Oct 15 04:35:57 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825815210 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.825815210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.1012099114 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 44426782 ps |
| CPU time | 8.59 seconds |
| Started | Oct 15 04:34:25 PM UTC 24 |
| Finished | Oct 15 04:34:35 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012099114 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delays.1012099114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/92.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all.152757398 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 1349281123 ps |
| CPU time | 130.51 seconds |
| Started | Oct 15 04:35:17 PM UTC 24 |
| Finished | Oct 15 04:37:30 PM UTC 24 |
| Peak memory | 593732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152757398 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.152757398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/92.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_error.1811586553 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 8526987912 ps |
| CPU time | 276.97 seconds |
| Started | Oct 15 04:35:24 PM UTC 24 |
| Finished | Oct 15 04:40:05 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811586553 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.1811586553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/92.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.2154595938 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 998859989 ps |
| CPU time | 105.72 seconds |
| Started | Oct 15 04:35:19 PM UTC 24 |
| Finished | Oct 15 04:37:07 PM UTC 24 |
| Peak memory | 593732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154595938 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_rand_reset.2154595938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.914493828 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 2814427288 ps |
| CPU time | 124.32 seconds |
| Started | Oct 15 04:35:26 PM UTC 24 |
| Finished | Oct 15 04:37:33 PM UTC 24 |
| Peak memory | 593976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914493828 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_reset_error.914493828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_unmapped_addr.3692429694 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 57126408 ps |
| CPU time | 14.12 seconds |
| Started | Oct 15 04:35:01 PM UTC 24 |
| Finished | Oct 15 04:35:17 PM UTC 24 |
| Peak memory | 593816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692429694 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.3692429694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/92.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device.3342480638 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 393594175 ps |
| CPU time | 38.79 seconds |
| Started | Oct 15 04:35:54 PM UTC 24 |
| Finished | Oct 15 04:36:35 PM UTC 24 |
| Peak memory | 594052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342480638 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device.3342480638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/93.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.1732695960 |
| Short name | T2910 |
| Test name | |
| Test status | |
| Simulation time | 57623327182 ps |
| CPU time | 791.5 seconds |
| Started | Oct 15 04:35:53 PM UTC 24 |
| Finished | Oct 15 04:49:14 PM UTC 24 |
| Peak memory | 596852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732695960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_dev ice_slow_rsp.1732695960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.427220818 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 517921615 ps |
| CPU time | 21.7 seconds |
| Started | Oct 15 04:35:59 PM UTC 24 |
| Finished | Oct 15 04:36:22 PM UTC 24 |
| Peak memory | 594096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427220818 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_addr.427220818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_random.136290633 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 2111539529 ps |
| CPU time | 74.91 seconds |
| Started | Oct 15 04:35:53 PM UTC 24 |
| Finished | Oct 15 04:37:09 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136290633 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.136290633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/93.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random.953551035 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 509961355 ps |
| CPU time | 43.81 seconds |
| Started | Oct 15 04:35:41 PM UTC 24 |
| Finished | Oct 15 04:36:26 PM UTC 24 |
| Peak memory | 593856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953551035 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.953551035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/93.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_large_delays.574014251 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 52833277215 ps |
| CPU time | 545.2 seconds |
| Started | Oct 15 04:35:45 PM UTC 24 |
| Finished | Oct 15 04:44:58 PM UTC 24 |
| Peak memory | 593996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574014251 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.574014251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/93.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_slow_rsp.320523890 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 28574747304 ps |
| CPU time | 474.07 seconds |
| Started | Oct 15 04:35:48 PM UTC 24 |
| Finished | Oct 15 04:43:49 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320523890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.320523890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/93.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_zero_delays.2569338787 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 120844019 ps |
| CPU time | 16.5 seconds |
| Started | Oct 15 04:35:43 PM UTC 24 |
| Finished | Oct 15 04:36:01 PM UTC 24 |
| Peak memory | 594020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569338787 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_delays.2569338787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/93.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_same_source.4120909336 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 297718017 ps |
| CPU time | 15.9 seconds |
| Started | Oct 15 04:35:54 PM UTC 24 |
| Finished | Oct 15 04:36:11 PM UTC 24 |
| Peak memory | 594016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120909336 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.4120909336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/93.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.1360023441 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 230017072 ps |
| CPU time | 12.48 seconds |
| Started | Oct 15 04:35:37 PM UTC 24 |
| Finished | Oct 15 04:35:50 PM UTC 24 |
| Peak memory | 591740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360023441 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.1360023441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/93.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_large_delays.196479115 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 8498824878 ps |
| CPU time | 78.34 seconds |
| Started | Oct 15 04:35:37 PM UTC 24 |
| Finished | Oct 15 04:36:57 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196479115 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.196479115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/93.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.3841753292 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 4946032425 ps |
| CPU time | 77.92 seconds |
| Started | Oct 15 04:35:43 PM UTC 24 |
| Finished | Oct 15 04:37:03 PM UTC 24 |
| Peak memory | 591684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841753292 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.3841753292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.3533173401 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 39238475 ps |
| CPU time | 7.28 seconds |
| Started | Oct 15 04:35:35 PM UTC 24 |
| Finished | Oct 15 04:35:43 PM UTC 24 |
| Peak memory | 591872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533173401 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delays.3533173401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/93.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all.2741861668 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 6916466972 ps |
| CPU time | 287.74 seconds |
| Started | Oct 15 04:36:06 PM UTC 24 |
| Finished | Oct 15 04:40:58 PM UTC 24 |
| Peak memory | 593940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741861668 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.2741861668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/93.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_error.1735653928 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 6478237012 ps |
| CPU time | 213.16 seconds |
| Started | Oct 15 04:36:11 PM UTC 24 |
| Finished | Oct 15 04:39:47 PM UTC 24 |
| Peak memory | 593984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735653928 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.1735653928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/93.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.2937805399 |
| Short name | T2914 |
| Test name | |
| Test status | |
| Simulation time | 23612709628 ps |
| CPU time | 981.01 seconds |
| Started | Oct 15 04:36:07 PM UTC 24 |
| Finished | Oct 15 04:52:40 PM UTC 24 |
| Peak memory | 597072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937805399 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_rand_reset.2937805399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.598233225 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 103847955 ps |
| CPU time | 24.97 seconds |
| Started | Oct 15 04:36:07 PM UTC 24 |
| Finished | Oct 15 04:36:33 PM UTC 24 |
| Peak memory | 591648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598233225 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_reset_error.598233225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_unmapped_addr.2484386738 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 325215520 ps |
| CPU time | 46.74 seconds |
| Started | Oct 15 04:36:00 PM UTC 24 |
| Finished | Oct 15 04:36:48 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484386738 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.2484386738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/93.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device.707297842 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 329552721 ps |
| CPU time | 29.89 seconds |
| Started | Oct 15 04:36:47 PM UTC 24 |
| Finished | Oct 15 04:37:19 PM UTC 24 |
| Peak memory | 593692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707297842 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device.707297842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/94.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.4171367834 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 36431874831 ps |
| CPU time | 513.38 seconds |
| Started | Oct 15 04:36:48 PM UTC 24 |
| Finished | Oct 15 04:45:28 PM UTC 24 |
| Peak memory | 593924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171367834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_dev ice_slow_rsp.4171367834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.3385211990 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 675193955 ps |
| CPU time | 30.58 seconds |
| Started | Oct 15 04:36:53 PM UTC 24 |
| Finished | Oct 15 04:37:25 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385211990 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_addr.3385211990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_random.616050974 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 1813694998 ps |
| CPU time | 78.02 seconds |
| Started | Oct 15 04:36:54 PM UTC 24 |
| Finished | Oct 15 04:38:14 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616050974 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.616050974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/94.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random.3073068829 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 399596326 ps |
| CPU time | 21.91 seconds |
| Started | Oct 15 04:36:28 PM UTC 24 |
| Finished | Oct 15 04:36:51 PM UTC 24 |
| Peak memory | 594020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073068829 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.3073068829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/94.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_large_delays.1809499263 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 51869831929 ps |
| CPU time | 500.68 seconds |
| Started | Oct 15 04:36:41 PM UTC 24 |
| Finished | Oct 15 04:45:08 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809499263 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.1809499263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/94.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_slow_rsp.1483130651 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 3471138684 ps |
| CPU time | 65.63 seconds |
| Started | Oct 15 04:36:45 PM UTC 24 |
| Finished | Oct 15 04:37:52 PM UTC 24 |
| Peak memory | 591876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483130651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.1483130651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/94.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_zero_delays.841764538 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 186851618 ps |
| CPU time | 21.77 seconds |
| Started | Oct 15 04:36:35 PM UTC 24 |
| Finished | Oct 15 04:36:58 PM UTC 24 |
| Peak memory | 593812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841764538 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_delays.841764538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/94.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_same_source.195153257 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 408722424 ps |
| CPU time | 14.82 seconds |
| Started | Oct 15 04:36:46 PM UTC 24 |
| Finished | Oct 15 04:37:02 PM UTC 24 |
| Peak memory | 594132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195153257 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.195153257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/94.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke.3746286895 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 41155945 ps |
| CPU time | 6.11 seconds |
| Started | Oct 15 04:36:18 PM UTC 24 |
| Finished | Oct 15 04:36:25 PM UTC 24 |
| Peak memory | 591788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746286895 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.3746286895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/94.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_large_delays.1060195355 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 9268198407 ps |
| CPU time | 137.16 seconds |
| Started | Oct 15 04:36:20 PM UTC 24 |
| Finished | Oct 15 04:38:41 PM UTC 24 |
| Peak memory | 592052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060195355 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.1060195355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/94.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.2808086276 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 5245348786 ps |
| CPU time | 77.3 seconds |
| Started | Oct 15 04:36:24 PM UTC 24 |
| Finished | Oct 15 04:37:44 PM UTC 24 |
| Peak memory | 591916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808086276 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.2808086276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_zero_delays.2252773099 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 51671474 ps |
| CPU time | 9.73 seconds |
| Started | Oct 15 04:36:18 PM UTC 24 |
| Finished | Oct 15 04:36:29 PM UTC 24 |
| Peak memory | 591796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252773099 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delays.2252773099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/94.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all.3233274222 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 362422221 ps |
| CPU time | 44.9 seconds |
| Started | Oct 15 04:36:58 PM UTC 24 |
| Finished | Oct 15 04:37:44 PM UTC 24 |
| Peak memory | 593892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233274222 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.3233274222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/94.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_error.1649190467 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 14393152702 ps |
| CPU time | 465.99 seconds |
| Started | Oct 15 04:37:02 PM UTC 24 |
| Finished | Oct 15 04:44:55 PM UTC 24 |
| Peak memory | 593780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649190467 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.1649190467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/94.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.3226083775 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 8705808749 ps |
| CPU time | 457.88 seconds |
| Started | Oct 15 04:36:59 PM UTC 24 |
| Finished | Oct 15 04:44:44 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226083775 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_rand_reset.3226083775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.1673201723 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 3858435545 ps |
| CPU time | 229 seconds |
| Started | Oct 15 04:37:15 PM UTC 24 |
| Finished | Oct 15 04:41:08 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673201723 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_reset_error.1673201723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_unmapped_addr.1417908403 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 286353119 ps |
| CPU time | 36.55 seconds |
| Started | Oct 15 04:36:50 PM UTC 24 |
| Finished | Oct 15 04:37:28 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417908403 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.1417908403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/94.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device.3854134413 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 506939271 ps |
| CPU time | 39.24 seconds |
| Started | Oct 15 04:37:28 PM UTC 24 |
| Finished | Oct 15 04:38:09 PM UTC 24 |
| Peak memory | 593692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854134413 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device.3854134413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/95.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.4289319273 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 2901765619 ps |
| CPU time | 49.02 seconds |
| Started | Oct 15 04:37:31 PM UTC 24 |
| Finished | Oct 15 04:38:22 PM UTC 24 |
| Peak memory | 591696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289319273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_dev ice_slow_rsp.4289319273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.3723688762 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 150378352 ps |
| CPU time | 19.68 seconds |
| Started | Oct 15 04:37:43 PM UTC 24 |
| Finished | Oct 15 04:38:04 PM UTC 24 |
| Peak memory | 593676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723688762 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_addr.3723688762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_random.2391065978 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 1416449271 ps |
| CPU time | 42.01 seconds |
| Started | Oct 15 04:37:40 PM UTC 24 |
| Finished | Oct 15 04:38:23 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391065978 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.2391065978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/95.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random.3123915250 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 604046544 ps |
| CPU time | 56.97 seconds |
| Started | Oct 15 04:37:24 PM UTC 24 |
| Finished | Oct 15 04:38:22 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123915250 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.3123915250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/95.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_large_delays.1595891900 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 25542766016 ps |
| CPU time | 249.1 seconds |
| Started | Oct 15 04:37:29 PM UTC 24 |
| Finished | Oct 15 04:41:42 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595891900 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.1595891900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/95.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_slow_rsp.86647962 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 6090000537 ps |
| CPU time | 102.16 seconds |
| Started | Oct 15 04:37:28 PM UTC 24 |
| Finished | Oct 15 04:39:12 PM UTC 24 |
| Peak memory | 593948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86647962 -assert n opostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.86647962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/95.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_zero_delays.3900050334 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 585416020 ps |
| CPU time | 63.19 seconds |
| Started | Oct 15 04:37:24 PM UTC 24 |
| Finished | Oct 15 04:38:30 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900050334 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_delays.3900050334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/95.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_same_source.2647432893 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 411150321 ps |
| CPU time | 33.98 seconds |
| Started | Oct 15 04:37:35 PM UTC 24 |
| Finished | Oct 15 04:38:11 PM UTC 24 |
| Peak memory | 594120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647432893 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.2647432893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/95.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke.1308377929 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 189508579 ps |
| CPU time | 8.96 seconds |
| Started | Oct 15 04:37:09 PM UTC 24 |
| Finished | Oct 15 04:37:19 PM UTC 24 |
| Peak memory | 591676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308377929 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.1308377929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/95.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_large_delays.815680988 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 7720214892 ps |
| CPU time | 73.13 seconds |
| Started | Oct 15 04:37:18 PM UTC 24 |
| Finished | Oct 15 04:38:33 PM UTC 24 |
| Peak memory | 592068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815680988 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.815680988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/95.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.774432786 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 5333804193 ps |
| CPU time | 73.64 seconds |
| Started | Oct 15 04:37:22 PM UTC 24 |
| Finished | Oct 15 04:38:37 PM UTC 24 |
| Peak memory | 591884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774432786 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.774432786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_zero_delays.2091989049 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 49458101 ps |
| CPU time | 8.97 seconds |
| Started | Oct 15 04:37:15 PM UTC 24 |
| Finished | Oct 15 04:37:25 PM UTC 24 |
| Peak memory | 591700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091989049 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delays.2091989049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/95.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all.3820332812 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 3326069850 ps |
| CPU time | 340.61 seconds |
| Started | Oct 15 04:37:44 PM UTC 24 |
| Finished | Oct 15 04:43:30 PM UTC 24 |
| Peak memory | 594052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820332812 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.3820332812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/95.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_error.4045296694 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 11001217697 ps |
| CPU time | 377.01 seconds |
| Started | Oct 15 04:37:44 PM UTC 24 |
| Finished | Oct 15 04:44:07 PM UTC 24 |
| Peak memory | 593800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045296694 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.4045296694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/95.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.2910637877 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 90559554 ps |
| CPU time | 44.78 seconds |
| Started | Oct 15 04:37:43 PM UTC 24 |
| Finished | Oct 15 04:38:30 PM UTC 24 |
| Peak memory | 593964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910637877 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_rand_reset.2910637877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.1621377534 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 5177272953 ps |
| CPU time | 488.32 seconds |
| Started | Oct 15 04:37:49 PM UTC 24 |
| Finished | Oct 15 04:46:04 PM UTC 24 |
| Peak memory | 594020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621377534 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_reset_error.1621377534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_unmapped_addr.994118061 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 858232571 ps |
| CPU time | 41.62 seconds |
| Started | Oct 15 04:37:41 PM UTC 24 |
| Finished | Oct 15 04:38:25 PM UTC 24 |
| Peak memory | 593672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994118061 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.994118061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/95.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device.4033280634 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 316426359 ps |
| CPU time | 30.5 seconds |
| Started | Oct 15 04:38:18 PM UTC 24 |
| Finished | Oct 15 04:38:50 PM UTC 24 |
| Peak memory | 593692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033280634 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device.4033280634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/96.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.1956889714 |
| Short name | T2916 |
| Test name | |
| Test status | |
| Simulation time | 70420379374 ps |
| CPU time | 953.31 seconds |
| Started | Oct 15 04:38:24 PM UTC 24 |
| Finished | Oct 15 04:54:29 PM UTC 24 |
| Peak memory | 596776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956889714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_dev ice_slow_rsp.1956889714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.2439609138 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 906011515 ps |
| CPU time | 35.15 seconds |
| Started | Oct 15 04:38:35 PM UTC 24 |
| Finished | Oct 15 04:39:12 PM UTC 24 |
| Peak memory | 593676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439609138 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_addr.2439609138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_random.2222602952 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 2331765175 ps |
| CPU time | 63.78 seconds |
| Started | Oct 15 04:38:31 PM UTC 24 |
| Finished | Oct 15 04:39:37 PM UTC 24 |
| Peak memory | 593932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222602952 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.2222602952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/96.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random.2796863732 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 236195562 ps |
| CPU time | 16.27 seconds |
| Started | Oct 15 04:37:59 PM UTC 24 |
| Finished | Oct 15 04:38:16 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796863732 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.2796863732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/96.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_large_delays.538411226 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 3276188937 ps |
| CPU time | 32.87 seconds |
| Started | Oct 15 04:38:12 PM UTC 24 |
| Finished | Oct 15 04:38:46 PM UTC 24 |
| Peak memory | 591768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538411226 -ass ert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.538411226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/96.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_slow_rsp.34208357 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 1975101220 ps |
| CPU time | 38.64 seconds |
| Started | Oct 15 04:38:10 PM UTC 24 |
| Finished | Oct 15 04:38:50 PM UTC 24 |
| Peak memory | 591860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34208357 -assert n opostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.34208357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/96.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_zero_delays.991303538 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 198161250 ps |
| CPU time | 18.5 seconds |
| Started | Oct 15 04:38:10 PM UTC 24 |
| Finished | Oct 15 04:38:30 PM UTC 24 |
| Peak memory | 593808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991303538 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_delays.991303538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/96.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_same_source.3909368455 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 1971089487 ps |
| CPU time | 55.15 seconds |
| Started | Oct 15 04:38:27 PM UTC 24 |
| Finished | Oct 15 04:39:24 PM UTC 24 |
| Peak memory | 593936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909368455 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.3909368455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/96.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke.4035568680 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 45876621 ps |
| CPU time | 7.18 seconds |
| Started | Oct 15 04:37:48 PM UTC 24 |
| Finished | Oct 15 04:37:57 PM UTC 24 |
| Peak memory | 591968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035568680 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.4035568680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/96.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_large_delays.1529686134 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 6499243589 ps |
| CPU time | 69.87 seconds |
| Started | Oct 15 04:37:53 PM UTC 24 |
| Finished | Oct 15 04:39:05 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529686134 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.1529686134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/96.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.400768431 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 4898226689 ps |
| CPU time | 74.47 seconds |
| Started | Oct 15 04:37:57 PM UTC 24 |
| Finished | Oct 15 04:39:13 PM UTC 24 |
| Peak memory | 591844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400768431 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.400768431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_zero_delays.612532246 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 50946195 ps |
| CPU time | 9.5 seconds |
| Started | Oct 15 04:37:49 PM UTC 24 |
| Finished | Oct 15 04:38:00 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612532246 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delays.612532246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/96.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all.4218132989 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 3185753883 ps |
| CPU time | 99.79 seconds |
| Started | Oct 15 04:38:41 PM UTC 24 |
| Finished | Oct 15 04:40:23 PM UTC 24 |
| Peak memory | 593736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218132989 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.4218132989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/96.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_error.3786399673 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 12932418376 ps |
| CPU time | 393.38 seconds |
| Started | Oct 15 04:38:42 PM UTC 24 |
| Finished | Oct 15 04:45:21 PM UTC 24 |
| Peak memory | 594040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786399673 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.3786399673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/96.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.2772570561 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 903917727 ps |
| CPU time | 344.23 seconds |
| Started | Oct 15 04:38:43 PM UTC 24 |
| Finished | Oct 15 04:44:33 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772570561 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_rand_reset.2772570561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.638626205 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 9180534806 ps |
| CPU time | 419.49 seconds |
| Started | Oct 15 04:38:48 PM UTC 24 |
| Finished | Oct 15 04:45:54 PM UTC 24 |
| Peak memory | 593796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638626205 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_reset_error.638626205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_unmapped_addr.1657239671 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 68350156 ps |
| CPU time | 9.61 seconds |
| Started | Oct 15 04:38:32 PM UTC 24 |
| Finished | Oct 15 04:38:43 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657239671 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.1657239671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/96.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device.2450763922 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 3005585713 ps |
| CPU time | 114.64 seconds |
| Started | Oct 15 04:39:03 PM UTC 24 |
| Finished | Oct 15 04:41:00 PM UTC 24 |
| Peak memory | 593756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450763922 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device.2450763922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/97.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.1198828531 |
| Short name | T2912 |
| Test name | |
| Test status | |
| Simulation time | 49185969779 ps |
| CPU time | 687.07 seconds |
| Started | Oct 15 04:39:03 PM UTC 24 |
| Finished | Oct 15 04:50:39 PM UTC 24 |
| Peak memory | 593916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198828531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_dev ice_slow_rsp.1198828531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.2643485817 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 62554868 ps |
| CPU time | 12.52 seconds |
| Started | Oct 15 04:39:11 PM UTC 24 |
| Finished | Oct 15 04:39:25 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643485817 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_addr.2643485817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_random.509757066 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 2433981494 ps |
| CPU time | 86.75 seconds |
| Started | Oct 15 04:39:06 PM UTC 24 |
| Finished | Oct 15 04:40:35 PM UTC 24 |
| Peak memory | 593820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509757066 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.509757066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/97.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random.3563233356 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 1798229588 ps |
| CPU time | 62 seconds |
| Started | Oct 15 04:38:53 PM UTC 24 |
| Finished | Oct 15 04:39:57 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563233356 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.3563233356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/97.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_large_delays.1961013786 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 38469185312 ps |
| CPU time | 356.58 seconds |
| Started | Oct 15 04:38:58 PM UTC 24 |
| Finished | Oct 15 04:45:00 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961013786 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.1961013786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/97.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_slow_rsp.434615091 |
| Short name | T2906 |
| Test name | |
| Test status | |
| Simulation time | 31382387244 ps |
| CPU time | 456.7 seconds |
| Started | Oct 15 04:38:57 PM UTC 24 |
| Finished | Oct 15 04:46:40 PM UTC 24 |
| Peak memory | 593812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434615091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.434615091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/97.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_zero_delays.338774997 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 195588127 ps |
| CPU time | 17.38 seconds |
| Started | Oct 15 04:38:56 PM UTC 24 |
| Finished | Oct 15 04:39:14 PM UTC 24 |
| Peak memory | 593872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338774997 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_delays.338774997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/97.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_same_source.1528863006 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 178209988 ps |
| CPU time | 14.2 seconds |
| Started | Oct 15 04:39:05 PM UTC 24 |
| Finished | Oct 15 04:39:20 PM UTC 24 |
| Peak memory | 593908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528863006 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.1528863006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/97.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke.1963312966 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 161970682 ps |
| CPU time | 11.32 seconds |
| Started | Oct 15 04:38:47 PM UTC 24 |
| Finished | Oct 15 04:38:59 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963312966 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.1963312966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/97.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_large_delays.973325460 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 7821674689 ps |
| CPU time | 72.1 seconds |
| Started | Oct 15 04:38:49 PM UTC 24 |
| Finished | Oct 15 04:40:03 PM UTC 24 |
| Peak memory | 591688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973325460 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.973325460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/97.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.1711627143 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 4554877821 ps |
| CPU time | 68.82 seconds |
| Started | Oct 15 04:38:53 PM UTC 24 |
| Finished | Oct 15 04:40:03 PM UTC 24 |
| Peak memory | 591888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711627143 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.1711627143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_zero_delays.999671957 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 49177755 ps |
| CPU time | 9.84 seconds |
| Started | Oct 15 04:38:49 PM UTC 24 |
| Finished | Oct 15 04:39:00 PM UTC 24 |
| Peak memory | 591856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999671957 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delays.999671957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/97.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all.4115370284 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 4032819173 ps |
| CPU time | 339.98 seconds |
| Started | Oct 15 04:39:16 PM UTC 24 |
| Finished | Oct 15 04:45:01 PM UTC 24 |
| Peak memory | 594032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115370284 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.4115370284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/97.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_error.2007311627 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 441195927 ps |
| CPU time | 17.79 seconds |
| Started | Oct 15 04:39:23 PM UTC 24 |
| Finished | Oct 15 04:39:43 PM UTC 24 |
| Peak memory | 594028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007311627 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.2007311627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/97.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.2877684158 |
| Short name | T2911 |
| Test name | |
| Test status | |
| Simulation time | 9758673112 ps |
| CPU time | 594.64 seconds |
| Started | Oct 15 04:39:14 PM UTC 24 |
| Finished | Oct 15 04:49:16 PM UTC 24 |
| Peak memory | 593792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877684158 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_rand_reset.2877684158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.4009036478 |
| Short name | T2917 |
| Test name | |
| Test status | |
| Simulation time | 12183998013 ps |
| CPU time | 1025.54 seconds |
| Started | Oct 15 04:39:23 PM UTC 24 |
| Finished | Oct 15 04:56:42 PM UTC 24 |
| Peak memory | 596712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009036478 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_reset_error.4009036478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_unmapped_addr.614022401 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 167865966 ps |
| CPU time | 18.64 seconds |
| Started | Oct 15 04:39:06 PM UTC 24 |
| Finished | Oct 15 04:39:26 PM UTC 24 |
| Peak memory | 593816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614022401 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.614022401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/97.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device.2658754389 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 1085959259 ps |
| CPU time | 46.27 seconds |
| Started | Oct 15 04:39:46 PM UTC 24 |
| Finished | Oct 15 04:40:33 PM UTC 24 |
| Peak memory | 593928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658754389 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device.2658754389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/98.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.2969754988 |
| Short name | T2915 |
| Test name | |
| Test status | |
| Simulation time | 64455053276 ps |
| CPU time | 853.91 seconds |
| Started | Oct 15 04:39:42 PM UTC 24 |
| Finished | Oct 15 04:54:06 PM UTC 24 |
| Peak memory | 593740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969754988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_dev ice_slow_rsp.2969754988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.1847251396 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 150105895 ps |
| CPU time | 10.16 seconds |
| Started | Oct 15 04:39:48 PM UTC 24 |
| Finished | Oct 15 04:39:59 PM UTC 24 |
| Peak memory | 591764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847251396 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_addr.1847251396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_random.1427030446 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 188511914 ps |
| CPU time | 11.25 seconds |
| Started | Oct 15 04:39:46 PM UTC 24 |
| Finished | Oct 15 04:39:59 PM UTC 24 |
| Peak memory | 591628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427030446 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.1427030446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/98.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random.1168255831 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 1335785495 ps |
| CPU time | 43.82 seconds |
| Started | Oct 15 04:39:34 PM UTC 24 |
| Finished | Oct 15 04:40:20 PM UTC 24 |
| Peak memory | 594040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168255831 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.1168255831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/98.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_large_delays.1032869850 |
| Short name | T2909 |
| Test name | |
| Test status | |
| Simulation time | 60326100795 ps |
| CPU time | 526.73 seconds |
| Started | Oct 15 04:39:36 PM UTC 24 |
| Finished | Oct 15 04:48:29 PM UTC 24 |
| Peak memory | 593980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032869850 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.1032869850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/98.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_slow_rsp.1192085169 |
| Short name | T2907 |
| Test name | |
| Test status | |
| Simulation time | 27343883733 ps |
| CPU time | 421.6 seconds |
| Started | Oct 15 04:39:44 PM UTC 24 |
| Finished | Oct 15 04:46:51 PM UTC 24 |
| Peak memory | 593744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192085169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.1192085169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/98.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_zero_delays.3033739367 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 277619931 ps |
| CPU time | 24.35 seconds |
| Started | Oct 15 04:39:35 PM UTC 24 |
| Finished | Oct 15 04:40:01 PM UTC 24 |
| Peak memory | 593684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033739367 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_delays.3033739367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/98.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_same_source.543968655 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 2290865322 ps |
| CPU time | 61.31 seconds |
| Started | Oct 15 04:39:45 PM UTC 24 |
| Finished | Oct 15 04:40:47 PM UTC 24 |
| Peak memory | 593968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543968655 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.543968655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/98.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke.1420919950 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 228973731 ps |
| CPU time | 8.36 seconds |
| Started | Oct 15 04:39:26 PM UTC 24 |
| Finished | Oct 15 04:39:35 PM UTC 24 |
| Peak memory | 591740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420919950 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.1420919950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/98.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_large_delays.2979810489 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 9236757260 ps |
| CPU time | 86.86 seconds |
| Started | Oct 15 04:39:26 PM UTC 24 |
| Finished | Oct 15 04:40:55 PM UTC 24 |
| Peak memory | 591940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979810489 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.2979810489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/98.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.1061164437 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 4293390175 ps |
| CPU time | 89.26 seconds |
| Started | Oct 15 04:39:36 PM UTC 24 |
| Finished | Oct 15 04:41:08 PM UTC 24 |
| Peak memory | 592052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061164437 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.1061164437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_zero_delays.3564204291 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 41057711 ps |
| CPU time | 5.42 seconds |
| Started | Oct 15 04:39:24 PM UTC 24 |
| Finished | Oct 15 04:39:31 PM UTC 24 |
| Peak memory | 591620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564204291 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delays.3564204291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/98.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all.1935187873 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 3504137695 ps |
| CPU time | 271.39 seconds |
| Started | Oct 15 04:39:57 PM UTC 24 |
| Finished | Oct 15 04:44:33 PM UTC 24 |
| Peak memory | 594040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935187873 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.1935187873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/98.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_error.217407474 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 1589596256 ps |
| CPU time | 134.26 seconds |
| Started | Oct 15 04:40:01 PM UTC 24 |
| Finished | Oct 15 04:42:18 PM UTC 24 |
| Peak memory | 593732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217407474 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.217407474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/98.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.3399232675 |
| Short name | T2913 |
| Test name | |
| Test status | |
| Simulation time | 16635677302 ps |
| CPU time | 734.62 seconds |
| Started | Oct 15 04:39:57 PM UTC 24 |
| Finished | Oct 15 04:52:20 PM UTC 24 |
| Peak memory | 593988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399232675 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_rand_reset.3399232675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.513541189 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 2638439560 ps |
| CPU time | 251.69 seconds |
| Started | Oct 15 04:40:02 PM UTC 24 |
| Finished | Oct 15 04:44:18 PM UTC 24 |
| Peak memory | 594016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513541189 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_reset_error.513541189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_unmapped_addr.1406577124 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 848864497 ps |
| CPU time | 42.2 seconds |
| Started | Oct 15 04:39:48 PM UTC 24 |
| Finished | Oct 15 04:40:31 PM UTC 24 |
| Peak memory | 593944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406577124 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.1406577124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/98.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device.290412416 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 1609017446 ps |
| CPU time | 82.68 seconds |
| Started | Oct 15 04:40:26 PM UTC 24 |
| Finished | Oct 15 04:41:50 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290412416 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device.290412416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/99.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.41591209 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 9671912320 ps |
| CPU time | 158.92 seconds |
| Started | Oct 15 04:40:29 PM UTC 24 |
| Finished | Oct 15 04:43:11 PM UTC 24 |
| Peak memory | 591704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41591209 -assert n opostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_devic e_slow_rsp.41591209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.2459524647 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 188938319 ps |
| CPU time | 9.94 seconds |
| Started | Oct 15 04:40:49 PM UTC 24 |
| Finished | Oct 15 04:41:00 PM UTC 24 |
| Peak memory | 591756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459524647 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_addr.2459524647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_random.3300513469 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 117906490 ps |
| CPU time | 7.47 seconds |
| Started | Oct 15 04:40:43 PM UTC 24 |
| Finished | Oct 15 04:40:51 PM UTC 24 |
| Peak memory | 591880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300513469 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.3300513469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/99.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random.2778678288 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 193872184 ps |
| CPU time | 19.13 seconds |
| Started | Oct 15 04:40:22 PM UTC 24 |
| Finished | Oct 15 04:40:42 PM UTC 24 |
| Peak memory | 593808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778678288 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.2778678288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/99.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_large_delays.3513672925 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 18360677304 ps |
| CPU time | 191.35 seconds |
| Started | Oct 15 04:40:24 PM UTC 24 |
| Finished | Oct 15 04:43:39 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513672925 -as sert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.3513672925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/99.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_slow_rsp.3115426622 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 8859877879 ps |
| CPU time | 142.12 seconds |
| Started | Oct 15 04:40:27 PM UTC 24 |
| Finished | Oct 15 04:42:52 PM UTC 24 |
| Peak memory | 593736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +xbar_mode=1 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115426622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.3115426622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/99.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_zero_delays.1492713376 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 314822681 ps |
| CPU time | 35.01 seconds |
| Started | Oct 15 04:40:23 PM UTC 24 |
| Finished | Oct 15 04:40:59 PM UTC 24 |
| Peak memory | 593868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492713376 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_delays.1492713376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/99.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_same_source.4607664 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 591082064 ps |
| CPU time | 47.9 seconds |
| Started | Oct 15 04:40:44 PM UTC 24 |
| Finished | Oct 15 04:41:33 PM UTC 24 |
| Peak memory | 593680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4607664 -assert nopostproc +UVM_TESTNAME=x bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.4607664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/99.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke.2346691828 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 293757909 ps |
| CPU time | 14.86 seconds |
| Started | Oct 15 04:40:10 PM UTC 24 |
| Finished | Oct 15 04:40:26 PM UTC 24 |
| Peak memory | 591748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346691828 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.2346691828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/99.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_large_delays.1924784373 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 7695589424 ps |
| CPU time | 88.26 seconds |
| Started | Oct 15 04:40:10 PM UTC 24 |
| Finished | Oct 15 04:41:40 PM UTC 24 |
| Peak memory | 591940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924784373 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.1924784373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/99.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.2126300405 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 4268183994 ps |
| CPU time | 68.61 seconds |
| Started | Oct 15 04:40:21 PM UTC 24 |
| Finished | Oct 15 04:41:32 PM UTC 24 |
| Peak memory | 591696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126300405 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.2126300405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_zero_delays.2949578441 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 48196286 ps |
| CPU time | 9.17 seconds |
| Started | Oct 15 04:40:07 PM UTC 24 |
| Finished | Oct 15 04:40:17 PM UTC 24 |
| Peak memory | 591756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949578441 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delays.2949578441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/99.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all.930854181 |
| Short name | T2905 |
| Test name | |
| Test status | |
| Simulation time | 9976479703 ps |
| CPU time | 322.7 seconds |
| Started | Oct 15 04:40:54 PM UTC 24 |
| Finished | Oct 15 04:46:22 PM UTC 24 |
| Peak memory | 594056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930854181 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.930854181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/99.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_error.1264610070 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 2139767017 ps |
| CPU time | 78.37 seconds |
| Started | Oct 15 04:41:01 PM UTC 24 |
| Finished | Oct 15 04:42:22 PM UTC 24 |
| Peak memory | 594032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264610070 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.1264610070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/99.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.3820012782 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 5013995430 ps |
| CPU time | 249.67 seconds |
| Started | Oct 15 04:41:00 PM UTC 24 |
| Finished | Oct 15 04:45:14 PM UTC 24 |
| Peak memory | 594028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820012782 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_rand_reset.3820012782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.1325729729 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 380007275 ps |
| CPU time | 82.33 seconds |
| Started | Oct 15 04:40:58 PM UTC 24 |
| Finished | Oct 15 04:42:23 PM UTC 24 |
| Peak memory | 593724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325729729 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_reset_error.1325729729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_unmapped_addr.1672933644 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 1349188336 ps |
| CPU time | 45.19 seconds |
| Started | Oct 15 04:40:47 PM UTC 24 |
| Finished | Oct 15 04:41:33 PM UTC 24 |
| Peak memory | 593920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672933644 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.1672933644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/99.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.1166427854 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 13211874108 ps |
| CPU time | 1452.03 seconds |
| Started | Oct 15 05:29:18 PM UTC 24 |
| Finished | Oct 15 05:53:49 PM UTC 24 |
| Peak memory | 625044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166427854 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.1166427854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_jtag_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.3433966101 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 2875866412 ps |
| CPU time | 235.32 seconds |
| Started | Oct 15 04:46:48 PM UTC 24 |
| Finished | Oct 15 04:50:47 PM UTC 24 |
| Peak memory | 625416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim _dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433966101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.3433966101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sival_flash_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.4232648279 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2956675452 ps |
| CPU time | 246.63 seconds |
| Started | Oct 15 05:03:27 PM UTC 24 |
| Finished | Oct 15 05:07:37 PM UTC 24 |
| Peak memory | 627284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_i mages=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232648279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.4232648279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.2314652391 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 2410329658 ps |
| CPU time | 318.98 seconds |
| Started | Oct 15 05:03:52 PM UTC 24 |
| Finished | Oct 15 05:09:16 PM UTC 24 |
| Peak memory | 627280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314652391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.2314652391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1442436695 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 2981873581 ps |
| CPU time | 257.33 seconds |
| Started | Oct 15 05:39:19 PM UTC 24 |
| Finished | Oct 15 05:43:40 PM UTC 24 |
| Peak memory | 625236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442436695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.1442436695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_entropy.1776412205 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 2926761626 ps |
| CPU time | 242.12 seconds |
| Started | Oct 15 05:08:24 PM UTC 24 |
| Finished | Oct 15 05:12:30 PM UTC 24 |
| Peak memory | 627460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776412205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_aes_entropy.1776412205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_idle.573736494 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2186233594 ps |
| CPU time | 222.36 seconds |
| Started | Oct 15 05:03:53 PM UTC 24 |
| Finished | Oct 15 05:07:38 PM UTC 24 |
| Peak memory | 627512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=573736494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.573736494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.4136536742 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 3279073633 ps |
| CPU time | 329.68 seconds |
| Started | Oct 15 05:05:28 PM UTC 24 |
| Finished | Oct 15 05:11:03 PM UTC 24 |
| Peak memory | 627468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136536742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_aes_masking_off.4136536742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_masking_off/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_smoketest.794240503 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 3323876686 ps |
| CPU time | 325.04 seconds |
| Started | Oct 15 06:36:29 PM UTC 24 |
| Finished | Oct 15 06:41:59 PM UTC 24 |
| Peak memory | 625240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=794240503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ae s_smoketest.794240503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.2339129580 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 2937342493 ps |
| CPU time | 348.15 seconds |
| Started | Oct 15 05:08:01 PM UTC 24 |
| Finished | Oct 15 05:13:54 PM UTC 24 |
| Peak memory | 627656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339129580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.2339129580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.2200574052 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 4950277622 ps |
| CPU time | 505.8 seconds |
| Started | Oct 15 05:06:23 PM UTC 24 |
| Finished | Oct 15 05:14:56 PM UTC 24 |
| Peak memory | 639772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200574052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_ earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.2200574052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.817817549 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 8578617416 ps |
| CPU time | 2026.44 seconds |
| Started | Oct 15 05:06:56 PM UTC 24 |
| Finished | Oct 15 05:41:09 PM UTC 24 |
| Peak memory | 627540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817817549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_ear lgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.817817549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1196311860 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 7620120576 ps |
| CPU time | 1495.83 seconds |
| Started | Oct 15 05:07:23 PM UTC 24 |
| Finished | Oct 15 05:32:38 PM UTC 24 |
| Peak memory | 627292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196311860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_toggle.1196311860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.1539998401 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 7539178948 ps |
| CPU time | 1369.91 seconds |
| Started | Oct 15 05:06:29 PM UTC 24 |
| Finished | Oct 15 05:29:37 PM UTC 24 |
| Peak memory | 627708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539998401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.1539998401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.622474638 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 2836566360 ps |
| CPU time | 254.59 seconds |
| Started | Oct 15 05:06:26 PM UTC 24 |
| Finished | Oct 15 05:10:45 PM UTC 24 |
| Peak memory | 627540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622474638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.622474638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.2795622286 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 4011187144 ps |
| CPU time | 440.65 seconds |
| Started | Oct 15 05:01:40 PM UTC 24 |
| Finished | Oct 15 05:09:07 PM UTC 24 |
| Peak memory | 627284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795622286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.2795622286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1686117515 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 7944743520 ps |
| CPU time | 451.3 seconds |
| Started | Oct 15 05:02:44 PM UTC 24 |
| Finished | Oct 15 05:10:22 PM UTC 24 |
| Peak memory | 627364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686117515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1686117515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_smoketest.3656102238 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 3137604710 ps |
| CPU time | 378.37 seconds |
| Started | Oct 15 06:38:34 PM UTC 24 |
| Finished | Oct 15 06:44:59 PM UTC 24 |
| Peak memory | 625456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656102238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_aon_timer_smoketest.3656102238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2773628133 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 9936734400 ps |
| CPU time | 814.11 seconds |
| Started | Oct 15 05:03:29 PM UTC 24 |
| Finished | Oct 15 05:17:14 PM UTC 24 |
| Peak memory | 627516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773628133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.2773628133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2297810579 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 5737345712 ps |
| CPU time | 595.09 seconds |
| Started | Oct 15 05:03:18 PM UTC 24 |
| Finished | Oct 15 05:13:21 PM UTC 24 |
| Peak memory | 627476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297810579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.2297810579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.1645723409 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 6794124180 ps |
| CPU time | 726.71 seconds |
| Started | Oct 15 05:30:40 PM UTC 24 |
| Finished | Oct 15 05:42:56 PM UTC 24 |
| Peak memory | 633908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_ clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h w/dv/tools/sim.tcl +ntb_random_seed=1645723409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.1645723409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3253375702 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 12366887173 ps |
| CPU time | 988.2 seconds |
| Started | Oct 15 05:23:32 PM UTC 24 |
| Finished | Oct 15 05:40:14 PM UTC 24 |
| Peak memory | 641712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_de vice=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253375702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.3253375702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2156919526 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 3703161080 ps |
| CPU time | 669.88 seconds |
| Started | Oct 15 05:25:36 PM UTC 24 |
| Finished | Oct 15 05:36:55 PM UTC 24 |
| Peak memory | 629672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156919526 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_rma.2156919526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1426065192 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 4648119148 ps |
| CPU time | 705.27 seconds |
| Started | Oct 15 05:23:32 PM UTC 24 |
| Finished | Oct 15 05:35:27 PM UTC 24 |
| Peak memory | 629576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142 6065192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_exter nal_clk_src_for_sw_fast_test_unlocked0.1426065192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3644773013 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 5294515612 ps |
| CPU time | 668.13 seconds |
| Started | Oct 15 05:25:17 PM UTC 24 |
| Finished | Oct 15 05:36:34 PM UTC 24 |
| Peak memory | 629280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644773013 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_dev.3644773013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3585556009 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 4534774788 ps |
| CPU time | 569.18 seconds |
| Started | Oct 15 05:27:05 PM UTC 24 |
| Finished | Oct 15 05:36:42 PM UTC 24 |
| Peak memory | 629516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585556009 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_rma.3585556009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2065651808 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 4394758440 ps |
| CPU time | 607.72 seconds |
| Started | Oct 15 05:23:57 PM UTC 24 |
| Finished | Oct 15 05:34:13 PM UTC 24 |
| Peak memory | 629288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206 5651808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_exter nal_clk_src_for_sw_slow_test_unlocked0.2065651808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.3027766761 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 2443120333 ps |
| CPU time | 197.33 seconds |
| Started | Oct 15 05:28:51 PM UTC 24 |
| Finished | Oct 15 05:32:12 PM UTC 24 |
| Peak memory | 625304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3027766761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_clkmgr_jitter.3027766761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3338238028 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 3678653070 ps |
| CPU time | 463.55 seconds |
| Started | Oct 15 05:28:39 PM UTC 24 |
| Finished | Oct 15 05:36:29 PM UTC 24 |
| Peak memory | 625240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=3338238028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_clkmgr_jitter_frequency.3338238028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3461295327 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 2737730809 ps |
| CPU time | 192.31 seconds |
| Started | Oct 15 05:39:12 PM UTC 24 |
| Finished | Oct 15 05:42:28 PM UTC 24 |
| Peak memory | 627460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkm gr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3461295327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.3461295327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2038828042 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 4475461520 ps |
| CPU time | 517.76 seconds |
| Started | Oct 15 05:21:41 PM UTC 24 |
| Finished | Oct 15 05:30:26 PM UTC 24 |
| Peak memory | 627544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2038828042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.2038828042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2108006308 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 4935202176 ps |
| CPU time | 556.19 seconds |
| Started | Oct 15 05:21:55 PM UTC 24 |
| Finished | Oct 15 05:31:19 PM UTC 24 |
| Peak memory | 625244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2108006308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_clkmgr_off_hmac_trans.2108006308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.596753036 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 4777146308 ps |
| CPU time | 374.11 seconds |
| Started | Oct 15 05:22:26 PM UTC 24 |
| Finished | Oct 15 05:28:45 PM UTC 24 |
| Peak memory | 627288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=596753036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.596753036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.930812106 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 5635896808 ps |
| CPU time | 395.89 seconds |
| Started | Oct 15 05:23:05 PM UTC 24 |
| Finished | Oct 15 05:29:46 PM UTC 24 |
| Peak memory | 627280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=930812106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.930812106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_peri.2695540574 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 8378905500 ps |
| CPU time | 1126.99 seconds |
| Started | Oct 15 05:21:53 PM UTC 24 |
| Finished | Oct 15 05:40:55 PM UTC 24 |
| Peak memory | 627464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_i mages=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695540574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.2695540574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.232252135 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 4101756904 ps |
| CPU time | 583.97 seconds |
| Started | Oct 15 05:27:05 PM UTC 24 |
| Finished | Oct 15 05:36:58 PM UTC 24 |
| Peak memory | 627508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232252135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.232252135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1788408641 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 4763769752 ps |
| CPU time | 719.2 seconds |
| Started | Oct 15 05:29:17 PM UTC 24 |
| Finished | Oct 15 05:41:25 PM UTC 24 |
| Peak memory | 627296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788408641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.1788408641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_smoketest.3773522273 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 2457630182 ps |
| CPU time | 379.21 seconds |
| Started | Oct 15 06:39:11 PM UTC 24 |
| Finished | Oct 15 06:45:36 PM UTC 24 |
| Peak memory | 625236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3773522273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_clkmgr_smoketest.3773522273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.4270925600 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 34728297249 ps |
| CPU time | 6793 seconds |
| Started | Oct 15 05:39:09 PM UTC 24 |
| Finished | Oct 15 07:33:44 PM UTC 24 |
| Peak memory | 630140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accele rate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270925600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_b ase_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.4270925600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.637576484 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 2629207848 ps |
| CPU time | 332.49 seconds |
| Started | Oct 15 05:12:09 PM UTC 24 |
| Finished | Oct 15 05:17:47 PM UTC 24 |
| Peak memory | 625404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=637576484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.637576484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_smoketest.3374669730 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 2414893390 ps |
| CPU time | 278.95 seconds |
| Started | Oct 15 06:39:30 PM UTC 24 |
| Finished | Oct 15 06:44:14 PM UTC 24 |
| Peak memory | 625244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3374669730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _csrng_smoketest.3374669730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.4127454605 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 7220454180 ps |
| CPU time | 1304.02 seconds |
| Started | Oct 15 05:12:18 PM UTC 24 |
| Finished | Oct 15 05:34:19 PM UTC 24 |
| Peak memory | 627412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127454605 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.4127454605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.192223172 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 6083165162 ps |
| CPU time | 973.39 seconds |
| Started | Oct 15 05:12:12 PM UTC 24 |
| Finished | Oct 15 05:28:39 PM UTC 24 |
| Peak memory | 627660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192223172 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.192223172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.1408994825 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 3235388000 ps |
| CPU time | 530.75 seconds |
| Started | Oct 15 05:10:03 PM UTC 24 |
| Finished | Oct 15 05:19:01 PM UTC 24 |
| Peak memory | 633420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_a ssert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=1408994825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_edn_kat.1408994825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_kat/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_sw_mode.328241160 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 9108401208 ps |
| CPU time | 1901.16 seconds |
| Started | Oct 15 05:10:03 PM UTC 24 |
| Finished | Oct 15 05:42:07 PM UTC 24 |
| Peak memory | 627496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=328241160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_edn_sw_mode.328241160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2458196057 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 2425616624 ps |
| CPU time | 259.05 seconds |
| Started | Oct 15 05:12:13 PM UTC 24 |
| Finished | Oct 15 05:16:36 PM UTC 24 |
| Peak memory | 625496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458196057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.2458196057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.4109839280 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 3280555816 ps |
| CPU time | 285.37 seconds |
| Started | Oct 15 05:08:24 PM UTC 24 |
| Finished | Oct 15 05:13:14 PM UTC 24 |
| Peak memory | 627280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109839280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.4109839280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_smoketest.1496392932 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 3002794492 ps |
| CPU time | 433.75 seconds |
| Started | Oct 15 06:39:44 PM UTC 24 |
| Finished | Oct 15 06:47:04 PM UTC 24 |
| Peak memory | 625384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_de vice=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496392932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.1496392932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.426655095 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 2731478894 ps |
| CPU time | 216.63 seconds |
| Started | Oct 15 04:50:12 PM UTC 24 |
| Finished | Oct 15 04:53:52 PM UTC 24 |
| Peak memory | 625236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=426655095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_example_flash.426655095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.2601875770 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 2611051604 ps |
| CPU time | 264.85 seconds |
| Started | Oct 15 04:49:55 PM UTC 24 |
| Finished | Oct 15 04:54:24 PM UTC 24 |
| Peak memory | 625476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2601875770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ex ample_manufacturer.2601875770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_manufacturer/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.2029738548 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3108814940 ps |
| CPU time | 112.08 seconds |
| Started | Oct 15 04:46:06 PM UTC 24 |
| Finished | Oct 15 04:48:00 PM UTC 24 |
| Peak memory | 627536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:t est_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2029738548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_example_rom.2029738548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_crash_alert.991137440 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 5817540848 ps |
| CPU time | 638.89 seconds |
| Started | Oct 15 05:39:06 PM UTC 24 |
| Finished | Oct 15 05:49:54 PM UTC 24 |
| Peak memory | 627520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check= 1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991137440 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.991137440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access.3001119312 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 5371731744 ps |
| CPU time | 928.41 seconds |
| Started | Oct 15 04:49:12 PM UTC 24 |
| Finished | Oct 15 05:04:52 PM UTC 24 |
| Peak memory | 625384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3001119312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _flash_ctrl_access.3001119312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1681416132 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 6096151495 ps |
| CPU time | 959.71 seconds |
| Started | Oct 15 04:49:27 PM UTC 24 |
| Finished | Oct 15 05:05:39 PM UTC 24 |
| Peak memory | 627532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=1681416132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_flash_ctrl_access_jitter_en.1681416132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4017474883 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 7524880881 ps |
| CPU time | 1044.02 seconds |
| Started | Oct 15 05:38:56 PM UTC 24 |
| Finished | Oct 15 05:56:33 PM UTC 24 |
| Peak memory | 627536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017474883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4017474883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.16248891 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 5364175264 ps |
| CPU time | 988.05 seconds |
| Started | Oct 15 04:49:11 PM UTC 24 |
| Finished | Oct 15 05:05:52 PM UTC 24 |
| Peak memory | 625236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=16248891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.16248891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_mem_protection.767899457 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 5608426008 ps |
| CPU time | 963.68 seconds |
| Started | Oct 15 05:42:16 PM UTC 24 |
| Finished | Oct 15 05:58:32 PM UTC 24 |
| Peak memory | 625492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=767899457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 0.chip_sw_flash_ctrl_mem_protection.767899457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2010124741 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 4115374262 ps |
| CPU time | 634.04 seconds |
| Started | Oct 15 04:50:00 PM UTC 24 |
| Finished | Oct 15 05:00:43 PM UTC 24 |
| Peak memory | 625668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010124741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.2010124741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3996841600 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 5367349223 ps |
| CPU time | 539.29 seconds |
| Started | Oct 15 05:39:11 PM UTC 24 |
| Finished | Oct 15 05:48:19 PM UTC 24 |
| Peak memory | 625496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996841600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3996841600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.577714759 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 3838548982 ps |
| CPU time | 315.66 seconds |
| Started | Oct 15 05:39:06 PM UTC 24 |
| Finished | Oct 15 05:44:27 PM UTC 24 |
| Peak memory | 627480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_image s=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577714759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.577714759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_scrambling_smoketest.2152303161 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 3265365912 ps |
| CPU time | 173.2 seconds |
| Started | Oct 15 05:43:25 PM UTC 24 |
| Finished | Oct 15 05:46:22 PM UTC 24 |
| Peak memory | 627520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_ima ges=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoketest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152303161 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.2152303161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio_smoketest.2732951675 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2980886902 ps |
| CPU time | 379.85 seconds |
| Started | Oct 15 06:40:16 PM UTC 24 |
| Finished | Oct 15 06:46:41 PM UTC 24 |
| Peak memory | 625388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2732951675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_sw_gpio_smoketest.2732951675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc.3466353228 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 3154116316 ps |
| CPU time | 303.13 seconds |
| Started | Oct 15 05:12:21 PM UTC 24 |
| Finished | Oct 15 05:17:29 PM UTC 24 |
| Peak memory | 625480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3466353228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_h mac_enc.3466353228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.3700488676 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 3108698193 ps |
| CPU time | 313.77 seconds |
| Started | Oct 15 05:12:52 PM UTC 24 |
| Finished | Oct 15 05:18:11 PM UTC 24 |
| Peak memory | 625236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3700488676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_hmac_enc_jitter_en.3700488676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.181486474 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 2652987819 ps |
| CPU time | 213.18 seconds |
| Started | Oct 15 05:39:17 PM UTC 24 |
| Finished | Oct 15 05:42:54 PM UTC 24 |
| Peak memory | 625308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181486474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.181486474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.2906905494 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 8537957944 ps |
| CPU time | 1952.7 seconds |
| Started | Oct 15 05:13:22 PM UTC 24 |
| Finished | Oct 15 05:46:20 PM UTC 24 |
| Peak memory | 625500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2906905494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_multistream.2906905494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_multistream/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.4065744281 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 2888362976 ps |
| CPU time | 385.61 seconds |
| Started | Oct 15 05:13:07 PM UTC 24 |
| Finished | Oct 15 05:19:38 PM UTC 24 |
| Peak memory | 625492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4065744281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_h mac_oneshot.4065744281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_smoketest.3642643037 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 3382969160 ps |
| CPU time | 391.16 seconds |
| Started | Oct 15 06:40:16 PM UTC 24 |
| Finished | Oct 15 06:46:53 PM UTC 24 |
| Peak memory | 625388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3642643037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ hmac_smoketest.3642643037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.3767922381 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3629290130 ps |
| CPU time | 421.29 seconds |
| Started | Oct 15 04:50:19 PM UTC 24 |
| Finished | Oct 15 04:57:27 PM UTC 24 |
| Peak memory | 627600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3767922381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.3767922381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.4204769168 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 5474332440 ps |
| CPU time | 703.38 seconds |
| Started | Oct 15 04:49:43 PM UTC 24 |
| Finished | Oct 15 05:01:36 PM UTC 24 |
| Peak memory | 625544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=4204769168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_i2c_host_tx_rx.4204769168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3733582772 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 5403801152 ps |
| CPU time | 751.91 seconds |
| Started | Oct 15 04:47:58 PM UTC 24 |
| Finished | Oct 15 05:00:40 PM UTC 24 |
| Peak memory | 625556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3733582772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.3733582772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.643631366 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 2518875568 ps |
| CPU time | 184.77 seconds |
| Started | Oct 15 05:17:25 PM UTC 24 |
| Finished | Oct 15 05:20:33 PM UTC 24 |
| Peak memory | 625236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=643631366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_kmac_app_rom.643631366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_entropy.319121747 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 2711714456 ps |
| CPU time | 285.79 seconds |
| Started | Oct 15 04:50:33 PM UTC 24 |
| Finished | Oct 15 04:55:23 PM UTC 24 |
| Peak memory | 625460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=319121747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_kmac_entropy.319121747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_idle.2133387598 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 2902441032 ps |
| CPU time | 315.4 seconds |
| Started | Oct 15 05:17:28 PM UTC 24 |
| Finished | Oct 15 05:22:48 PM UTC 24 |
| Peak memory | 625464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2133387598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ kmac_idle.2133387598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.1725656954 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 2513143956 ps |
| CPU time | 278.1 seconds |
| Started | Oct 15 05:15:32 PM UTC 24 |
| Finished | Oct 15 05:20:15 PM UTC 24 |
| Peak memory | 625564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1725656954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_sw_kmac_mode_cshake.1725656954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.1259307939 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 2742869802 ps |
| CPU time | 323.64 seconds |
| Started | Oct 15 05:15:45 PM UTC 24 |
| Finished | Oct 15 05:21:13 PM UTC 24 |
| Peak memory | 625444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259307939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_kmac_mode_kmac.1259307939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3065691461 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 3331091238 ps |
| CPU time | 302.85 seconds |
| Started | Oct 15 05:15:48 PM UTC 24 |
| Finished | Oct 15 05:20:56 PM UTC 24 |
| Peak memory | 625552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_km ac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3065691461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.3065691461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1647528951 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 2946675211 ps |
| CPU time | 281.66 seconds |
| Started | Oct 15 05:39:19 PM UTC 24 |
| Finished | Oct 15 05:44:06 PM UTC 24 |
| Peak memory | 627616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647528951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1647528951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_smoketest.2658162282 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 3351740092 ps |
| CPU time | 335.77 seconds |
| Started | Oct 15 06:41:06 PM UTC 24 |
| Finished | Oct 15 06:46:47 PM UTC 24 |
| Peak memory | 625244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2658162282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ kmac_smoketest.2658162282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.40157969 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3265125400 ps |
| CPU time | 313.57 seconds |
| Started | Oct 15 04:50:28 PM UTC 24 |
| Finished | Oct 15 04:55:46 PM UTC 24 |
| Peak memory | 625468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=40157969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_lc_ctrl_otp_hw_cfg0.40157969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2098265580 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3352201350 ps |
| CPU time | 153.56 seconds |
| Started | Oct 15 04:56:11 PM UTC 24 |
| Finished | Oct 15 04:58:47 PM UTC 24 |
| Peak memory | 639444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098265580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.2098265580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.600579376 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3299113880 ps |
| CPU time | 133.68 seconds |
| Started | Oct 15 04:54:13 PM UTC 24 |
| Finished | Oct 15 04:56:29 PM UTC 24 |
| Peak memory | 638984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600579376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.600579376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3486612599 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 4071989809 ps |
| CPU time | 214.37 seconds |
| Started | Oct 15 04:57:04 PM UTC 24 |
| Finished | Oct 15 05:00:42 PM UTC 24 |
| Peak memory | 639268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTes tLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486612599 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.3486612599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.1252547209 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 9154304255 ps |
| CPU time | 580.88 seconds |
| Started | Oct 15 04:53:20 PM UTC 24 |
| Finished | Oct 15 05:03:10 PM UTC 24 |
| Peak memory | 641692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1252547209 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_lc_ctrl_transition.1252547209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3048138390 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 2253248056 ps |
| CPU time | 108.36 seconds |
| Started | Oct 15 04:56:43 PM UTC 24 |
| Finished | Oct 15 04:58:34 PM UTC 24 |
| Peak memory | 635140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048138390 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.3048138390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.411560593 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 46892846170 ps |
| CPU time | 6160.4 seconds |
| Started | Oct 15 04:56:30 PM UTC 24 |
| Finished | Oct 15 06:40:25 PM UTC 24 |
| Peak memory | 644600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411560593 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prod.411560593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_rma.3200818440 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 44863429944 ps |
| CPU time | 6557.44 seconds |
| Started | Oct 15 04:56:40 PM UTC 24 |
| Finished | Oct 15 06:47:16 PM UTC 24 |
| Peak memory | 644492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +fl ash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200818440 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_rma.3200818440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.663828766 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 34260066834 ps |
| CPU time | 2237.13 seconds |
| Started | Oct 15 04:56:56 PM UTC 24 |
| Finished | Oct 15 05:34:41 PM UTC 24 |
| Peak memory | 641944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnl ock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663828766 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testunlocks.663828766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.478322313 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 17083071992 ps |
| CPU time | 4203.83 seconds |
| Started | Oct 15 05:02:47 PM UTC 24 |
| Finished | Oct 15 06:13:41 PM UTC 24 |
| Peak memory | 630420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478322313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.478322313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1212430955 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 18851499869 ps |
| CPU time | 4365.23 seconds |
| Started | Oct 15 05:03:21 PM UTC 24 |
| Finished | Oct 15 06:17:00 PM UTC 24 |
| Peak memory | 629940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212430955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1212430955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.2383695574 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 4035868560 ps |
| CPU time | 469.81 seconds |
| Started | Oct 15 05:02:48 PM UTC 24 |
| Finished | Oct 15 05:10:44 PM UTC 24 |
| Peak memory | 625440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383695574 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.2383695574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.726127900 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 5579997776 ps |
| CPU time | 868.84 seconds |
| Started | Oct 15 05:02:46 PM UTC 24 |
| Finished | Oct 15 05:17:26 PM UTC 24 |
| Peak memory | 627480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726127900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.726127900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_randomness/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_smoketest.1151439256 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 6718626046 ps |
| CPU time | 1176.76 seconds |
| Started | Oct 15 06:42:57 PM UTC 24 |
| Finished | Oct 15 07:02:50 PM UTC 24 |
| Peak memory | 625556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=1151439256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ otbn_smoketest.1151439256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_dai_lock.3558578620 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 27242642344 ps |
| CPU time | 5360.83 seconds |
| Started | Oct 15 04:52:18 PM UTC 24 |
| Finished | Oct 15 06:22:41 PM UTC 24 |
| Peak memory | 630004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_i mages=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558578620 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.3558578620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_descrambling.539807620 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 4180439176 ps |
| CPU time | 554.95 seconds |
| Started | Oct 15 04:53:18 PM UTC 24 |
| Finished | Oct 15 05:02:40 PM UTC 24 |
| Peak memory | 627792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_ima ges=otp_ctrl_descrambling_test:1:new_rules,otp_ctrl_descrambling_otp_image:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539807620 -assert nopostproc +UVM_TESTNAME=chip_base_test + UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_descrambling.539807620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_descrambling/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2112849321 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 3284851785 ps |
| CPU time | 326.38 seconds |
| Started | Oct 15 04:52:35 PM UTC 24 |
| Finished | Oct 15 04:58:06 PM UTC 24 |
| Peak memory | 625240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_ error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2112849321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.2112849321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.742264891 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 7369901580 ps |
| CPU time | 988.54 seconds |
| Started | Oct 15 04:50:40 PM UTC 24 |
| Finished | Oct 15 05:07:21 PM UTC 24 |
| Peak memory | 627648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742264891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.742264891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1698960211 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 7072280000 ps |
| CPU time | 1146.66 seconds |
| Started | Oct 15 04:50:40 PM UTC 24 |
| Finished | Oct 15 05:10:01 PM UTC 24 |
| Peak memory | 627800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_buil d_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698960211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.1698960211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2755999434 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 7248545546 ps |
| CPU time | 993.15 seconds |
| Started | Oct 15 04:50:01 PM UTC 24 |
| Finished | Oct 15 05:06:46 PM UTC 24 |
| Peak memory | 627472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755999434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.2755999434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2837045409 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 4809734100 ps |
| CPU time | 581.59 seconds |
| Started | Oct 15 04:49:28 PM UTC 24 |
| Finished | Oct 15 04:59:18 PM UTC 24 |
| Peak memory | 627664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837045409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_ asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2837045409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_smoketest.3517791199 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 2833208064 ps |
| CPU time | 231.2 seconds |
| Started | Oct 15 06:43:02 PM UTC 24 |
| Finished | Oct 15 06:46:57 PM UTC 24 |
| Peak memory | 625716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3517791199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_otp_ctrl_smoketest.3517791199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.1817815894 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3312385020 ps |
| CPU time | 173.96 seconds |
| Started | Oct 15 04:45:45 PM UTC 24 |
| Finished | Oct 15 04:48:42 PM UTC 24 |
| Peak memory | 627512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_im ages=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817815894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.1817815894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pattgen_ios/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.3754374924 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 2730132140 ps |
| CPU time | 276.45 seconds |
| Started | Oct 15 05:21:34 PM UTC 24 |
| Finished | Oct 15 05:26:14 PM UTC 24 |
| Peak memory | 625744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3754374924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_plic_sw_irq.3754374924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.1897855628 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 4662129736 ps |
| CPU time | 329.26 seconds |
| Started | Oct 15 05:41:46 PM UTC 24 |
| Finished | Oct 15 05:47:21 PM UTC 24 |
| Peak memory | 625244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1897855628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.1897855628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3470420283 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 11570541184 ps |
| CPU time | 1593.11 seconds |
| Started | Oct 15 04:57:32 PM UTC 24 |
| Finished | Oct 15 05:24:25 PM UTC 24 |
| Peak memory | 627576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470420283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep _all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.3470420283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1656471808 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 23096119530 ps |
| CPU time | 2414.48 seconds |
| Started | Oct 15 05:20:29 PM UTC 24 |
| Finished | Oct 15 06:01:14 PM UTC 24 |
| Peak memory | 627288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656471808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_re set_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.1656471808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1801969908 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 14489690146 ps |
| CPU time | 1606.34 seconds |
| Started | Oct 15 04:57:31 PM UTC 24 |
| Finished | Oct 15 05:24:37 PM UTC 24 |
| Peak memory | 629596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801969908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1801969908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1426745932 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 23371822240 ps |
| CPU time | 2205.35 seconds |
| Started | Oct 15 05:31:46 PM UTC 24 |
| Finished | Oct 15 06:08:58 PM UTC 24 |
| Peak memory | 628492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426745932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr _deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1426745932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.4161589807 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 9132167500 ps |
| CPU time | 704.77 seconds |
| Started | Oct 15 05:01:05 PM UTC 24 |
| Finished | Oct 15 05:12:59 PM UTC 24 |
| Peak memory | 627360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_res et_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=4161589807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.4161589807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.60847606 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 3886225640 ps |
| CPU time | 351.55 seconds |
| Started | Oct 15 04:57:07 PM UTC 24 |
| Finished | Oct 15 05:03:04 PM UTC 24 |
| Peak memory | 633640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60847606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_ power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.60847606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.506091264 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 11408583027 ps |
| CPU time | 1457.05 seconds |
| Started | Oct 15 04:58:07 PM UTC 24 |
| Finished | Oct 15 05:22:42 PM UTC 24 |
| Peak memory | 629400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_r eset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=506091264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.506091264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.833959629 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 6591166284 ps |
| CPU time | 646.55 seconds |
| Started | Oct 15 05:02:58 PM UTC 24 |
| Finished | Oct 15 05:13:53 PM UTC 24 |
| Peak memory | 627552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_r eset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=833959629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.833959629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2814320727 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 20656886855 ps |
| CPU time | 2748.05 seconds |
| Started | Oct 15 04:57:35 PM UTC 24 |
| Finished | Oct 15 05:43:57 PM UTC 24 |
| Peak memory | 631940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814320727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2814320727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3915999831 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 2672617780 ps |
| CPU time | 210.11 seconds |
| Started | Oct 15 05:02:34 PM UTC 24 |
| Finished | Oct 15 05:06:08 PM UTC 24 |
| Peak memory | 625464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3915999831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_pwrmgr_sleep_disabled.3915999831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.218283336 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 6204343980 ps |
| CPU time | 391.74 seconds |
| Started | Oct 15 05:32:50 PM UTC 24 |
| Finished | Oct 15 05:39:28 PM UTC 24 |
| Peak memory | 627468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218283336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.218283336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_smoketest.2859634255 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 6217548916 ps |
| CPU time | 566.43 seconds |
| Started | Oct 15 06:43:02 PM UTC 24 |
| Finished | Oct 15 06:52:36 PM UTC 24 |
| Peak memory | 627520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_ima ges=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859634255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.2859634255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2706881592 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 8358065316 ps |
| CPU time | 899.28 seconds |
| Started | Oct 15 04:57:32 PM UTC 24 |
| Finished | Oct 15 05:12:43 PM UTC 24 |
| Peak memory | 627288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2706881592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.2706881592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3670835819 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 5707703636 ps |
| CPU time | 358.01 seconds |
| Started | Oct 15 06:43:26 PM UTC 24 |
| Finished | Oct 15 06:49:29 PM UTC 24 |
| Peak memory | 625568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3670835819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_pwrmgr_usbdev_smoketest.3670835819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.309051585 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 5332277244 ps |
| CPU time | 676.18 seconds |
| Started | Oct 15 05:03:19 PM UTC 24 |
| Finished | Oct 15 05:14:45 PM UTC 24 |
| Peak memory | 627516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309051585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.309051585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.543249055 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 5772906032 ps |
| CPU time | 694.9 seconds |
| Started | Oct 15 04:49:24 PM UTC 24 |
| Finished | Oct 15 05:01:08 PM UTC 24 |
| Peak memory | 669616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543249055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_ cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.543249055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_smoketest.2163289169 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 3342053136 ps |
| CPU time | 238.84 seconds |
| Started | Oct 15 06:46:16 PM UTC 24 |
| Finished | Oct 15 06:50:18 PM UTC 24 |
| Peak memory | 625552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2163289169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_rstmgr_smoketest.2163289169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.667529340 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 4503222250 ps |
| CPU time | 289.8 seconds |
| Started | Oct 15 04:57:28 PM UTC 24 |
| Finished | Oct 15 05:02:22 PM UTC 24 |
| Peak memory | 627280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=667529340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_rstmgr_sw_req.667529340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.2038678383 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 2656278200 ps |
| CPU time | 169.43 seconds |
| Started | Oct 15 04:57:24 PM UTC 24 |
| Finished | Oct 15 05:00:17 PM UTC 24 |
| Peak memory | 625716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2038678383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_rstmgr_sw_rst.2038678383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.353172831 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 3013532057 ps |
| CPU time | 239.66 seconds |
| Started | Oct 15 05:36:07 PM UTC 24 |
| Finished | Oct 15 05:40:10 PM UTC 24 |
| Peak memory | 627484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_inval idate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=353172831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.353172831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.625501318 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 5559455592 ps |
| CPU time | 1011.45 seconds |
| Started | Oct 15 05:03:30 PM UTC 24 |
| Finished | Oct 15 05:20:34 PM UTC 24 |
| Peak memory | 627756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_b uild_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625501318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.625501318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.657161052 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 7188770672 ps |
| CPU time | 466.99 seconds |
| Started | Oct 15 05:33:42 PM UTC 24 |
| Finished | Oct 15 05:41:35 PM UTC 24 |
| Peak memory | 637444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_acc ess_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=657161052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wake up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.657161052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.645357205 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 4853932584 ps |
| CPU time | 343.73 seconds |
| Started | Oct 15 05:33:40 PM UTC 24 |
| Finished | Oct 15 05:39:29 PM UTC 24 |
| Peak memory | 639708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm _reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645357205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_res et_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.645357205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_plic_smoketest.104473051 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 2509356688 ps |
| CPU time | 266.85 seconds |
| Started | Oct 15 06:44:54 PM UTC 24 |
| Finished | Oct 15 06:49:25 PM UTC 24 |
| Peak memory | 625496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=104473051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_rv_plic_smoketest.104473051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.2155169617 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 3001483830 ps |
| CPU time | 247.55 seconds |
| Started | Oct 15 05:01:03 PM UTC 24 |
| Finished | Oct 15 05:05:15 PM UTC 24 |
| Peak memory | 625468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2155169617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_rv_timer_irq.2155169617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_smoketest.3177564116 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 3098725050 ps |
| CPU time | 190.24 seconds |
| Started | Oct 15 06:45:39 PM UTC 24 |
| Finished | Oct 15 06:48:53 PM UTC 24 |
| Peak memory | 625296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3177564116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_rv_timer_smoketest.3177564116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.443781774 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 3363308331 ps |
| CPU time | 230.71 seconds |
| Started | Oct 15 05:19:24 PM UTC 24 |
| Finished | Oct 15 05:23:19 PM UTC 24 |
| Peak memory | 627484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443781774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_st atus_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.443781774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.1184795453 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3322200792 ps |
| CPU time | 321.94 seconds |
| Started | Oct 15 04:50:15 PM UTC 24 |
| Finished | Oct 15 04:55:42 PM UTC 24 |
| Peak memory | 625452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1184795453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_sleep_pin_retention.1184795453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.3770146012 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 7930580984 ps |
| CPU time | 1218.24 seconds |
| Started | Oct 15 04:50:40 PM UTC 24 |
| Finished | Oct 15 05:11:13 PM UTC 24 |
| Peak memory | 627480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3770146012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_sleep_pwm_pulses.3770146012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1034493759 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 8993925124 ps |
| CPU time | 812.31 seconds |
| Started | Oct 15 05:19:03 PM UTC 24 |
| Finished | Oct 15 05:32:46 PM UTC 24 |
| Peak memory | 627384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034493759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_sram_ret_contents _no_scramble.1034493759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.330373764 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 7663505400 ps |
| CPU time | 804.33 seconds |
| Started | Oct 15 05:19:23 PM UTC 24 |
| Finished | Oct 15 05:32:58 PM UTC 24 |
| Peak memory | 627468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330373764 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_sram_ret_contents_scramble.330373764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.3492576068 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 7472048345 ps |
| CPU time | 663.69 seconds |
| Started | Oct 15 04:50:31 PM UTC 24 |
| Finished | Oct 15 05:01:44 PM UTC 24 |
| Peak memory | 641832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492576068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_spi_device_pass_through.3492576068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.1749966007 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5184988174 ps |
| CPU time | 534.81 seconds |
| Started | Oct 15 04:49:12 PM UTC 24 |
| Finished | Oct 15 04:58:15 PM UTC 24 |
| Peak memory | 642144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749966007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.1749966007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.1200294726 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3178264585 ps |
| CPU time | 307.44 seconds |
| Started | Oct 15 04:49:25 PM UTC 24 |
| Finished | Oct 15 04:54:37 PM UTC 24 |
| Peak memory | 637716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1200294726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_spi_device_tpm.1200294726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.91774519 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 4181426670 ps |
| CPU time | 624.56 seconds |
| Started | Oct 15 05:19:03 PM UTC 24 |
| Finished | Oct 15 05:29:37 PM UTC 24 |
| Peak memory | 627396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91774519 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access.91774519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1682677438 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 5313682008 ps |
| CPU time | 480.58 seconds |
| Started | Oct 15 05:39:20 PM UTC 24 |
| Finished | Oct 15 05:47:27 PM UTC 24 |
| Peak memory | 627484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_r eady_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682677438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1682677438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_smoketest.637946119 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 2841040862 ps |
| CPU time | 190.38 seconds |
| Started | Oct 15 06:48:14 PM UTC 24 |
| Finished | Oct 15 06:51:27 PM UTC 24 |
| Peak memory | 625492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637946119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_sram_ctrl_smoketest.637946119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2131796516 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 20674718909 ps |
| CPU time | 3560.66 seconds |
| Started | Oct 15 05:02:47 PM UTC 24 |
| Finished | Oct 15 06:02:51 PM UTC 24 |
| Peak memory | 630092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2131796516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.2131796516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1754197305 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 4322767458 ps |
| CPU time | 609.44 seconds |
| Started | Oct 15 05:01:50 PM UTC 24 |
| Finished | Oct 15 05:12:09 PM UTC 24 |
| Peak memory | 632084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1754197305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_sysrst_ctrl_in_irq.1754197305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.175942067 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 3259115027 ps |
| CPU time | 394.3 seconds |
| Started | Oct 15 05:02:22 PM UTC 24 |
| Finished | Oct 15 05:09:03 PM UTC 24 |
| Peak memory | 629828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=175942067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_sysrst_ctrl_inputs.175942067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.396301591 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 6768325860 ps |
| CPU time | 519.75 seconds |
| Started | Oct 15 05:01:31 PM UTC 24 |
| Finished | Oct 15 05:10:18 PM UTC 24 |
| Peak memory | 627596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=396301591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.396301591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_rand_baudrate.1714784439 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 4068097530 ps |
| CPU time | 567.87 seconds |
| Started | Oct 15 04:50:03 PM UTC 24 |
| Finished | Oct 15 04:59:39 PM UTC 24 |
| Peak memory | 642112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714784439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.1714784439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_smoketest.106476708 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 3121169940 ps |
| CPU time | 243.35 seconds |
| Started | Oct 15 06:48:11 PM UTC 24 |
| Finished | Oct 15 06:52:18 PM UTC 24 |
| Peak memory | 625428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=106476708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_uart_smoketest.106476708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3975974497 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 4140999276 ps |
| CPU time | 372.98 seconds |
| Started | Oct 15 04:49:09 PM UTC 24 |
| Finished | Oct 15 04:55:28 PM UTC 24 |
| Peak memory | 637540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975974497 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3975974497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.4102528765 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 82064048260 ps |
| CPU time | 19146.6 seconds |
| Started | Oct 15 04:47:51 PM UTC 24 |
| Finished | Oct 15 10:10:50 PM UTC 24 |
| Peak memory | 658820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout _ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102528765 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.4102528765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.3350953627 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 3881074280 ps |
| CPU time | 559.88 seconds |
| Started | Oct 15 04:49:47 PM UTC 24 |
| Finished | Oct 15 04:59:15 PM UTC 24 |
| Peak memory | 637620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350953627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.3350953627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.1444851963 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 2831636041 ps |
| CPU time | 282.83 seconds |
| Started | Oct 15 05:36:21 PM UTC 24 |
| Finished | Oct 15 05:41:08 PM UTC 24 |
| Peak memory | 625496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw _images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444851963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.1444851963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.475969809 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11356010250 ps |
| CPU time | 2726.35 seconds |
| Started | Oct 15 04:45:53 PM UTC 24 |
| Finished | Oct 15 05:31:53 PM UTC 24 |
| Peak memory | 629816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_ 000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475969809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.475969809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.2223086405 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 31767567192 ps |
| CPU time | 8424.82 seconds |
| Started | Oct 15 04:47:29 PM UTC 24 |
| Finished | Oct 15 07:09:33 PM UTC 24 |
| Peak memory | 627772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000 _000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223086405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlg rey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.2223086405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.3152223753 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3157931944 ps |
| CPU time | 271.67 seconds |
| Started | Oct 15 04:47:02 PM UTC 24 |
| Finished | Oct 15 04:51:38 PM UTC 24 |
| Peak memory | 627292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152223753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.3152223753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.548115970 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3528737778 ps |
| CPU time | 530.71 seconds |
| Started | Oct 15 04:50:27 PM UTC 24 |
| Finished | Oct 15 04:59:25 PM UTC 24 |
| Peak memory | 627464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548115970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.548115970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_stream.2733026354 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 18424956862 ps |
| CPU time | 4334.49 seconds |
| Started | Oct 15 04:48:44 PM UTC 24 |
| Finished | Oct 15 06:01:50 PM UTC 24 |
| Peak memory | 627764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_ 000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733026354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_ear lgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.2733026354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_stream/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_vbus.3193763243 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2383363448 ps |
| CPU time | 239.91 seconds |
| Started | Oct 15 04:49:20 PM UTC 24 |
| Finished | Oct 15 04:53:24 PM UTC 24 |
| Peak memory | 625668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193763243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.3193763243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.2790203955 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2455209677 ps |
| CPU time | 164.44 seconds |
| Started | Oct 15 05:33:41 PM UTC 24 |
| Finished | Oct 15 05:36:28 PM UTC 24 |
| Peak memory | 641556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790203955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.2790203955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.1585014482 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2484208871 ps |
| CPU time | 170.22 seconds |
| Started | Oct 15 05:35:07 PM UTC 24 |
| Finished | Oct 15 05:38:01 PM UTC 24 |
| Peak memory | 642020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585014482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.1585014482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.2575882697 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 6596108711 ps |
| CPU time | 630.81 seconds |
| Started | Oct 15 05:34:50 PM UTC 24 |
| Finished | Oct 15 05:45:30 PM UTC 24 |
| Peak memory | 642336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575882697 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.2575882697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.2802063581 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 14871151280 ps |
| CPU time | 4318.92 seconds |
| Started | Oct 15 05:54:36 PM UTC 24 |
| Finished | Oct 15 07:07:28 PM UTC 24 |
| Peak memory | 627484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802063581 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.2802063581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.2024220725 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 15582296904 ps |
| CPU time | 4540.28 seconds |
| Started | Oct 15 05:57:21 PM UTC 24 |
| Finished | Oct 15 07:13:57 PM UTC 24 |
| Peak memory | 625616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024220725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.2024220725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.2962746148 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 15780812995 ps |
| CPU time | 4541.68 seconds |
| Started | Oct 15 05:59:37 PM UTC 24 |
| Finished | Oct 15 07:16:13 PM UTC 24 |
| Peak memory | 627936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296274 6148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_in it_prod_end.2962746148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.3210657975 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 15140089252 ps |
| CPU time | 4311.57 seconds |
| Started | Oct 15 05:59:38 PM UTC 24 |
| Finished | Oct 15 07:12:23 PM UTC 24 |
| Peak memory | 625572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210657975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.3210657975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1125088878 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 12063431080 ps |
| CPU time | 2890.74 seconds |
| Started | Oct 15 05:53:14 PM UTC 24 |
| Finished | Oct 15 06:42:00 PM UTC 24 |
| Peak memory | 627484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1125088878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e 2e_asm_init_test_unlocked0.1125088878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.4001103958 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 24956974456 ps |
| CPU time | 7561.75 seconds |
| Started | Oct 15 05:46:52 PM UTC 24 |
| Finished | Oct 15 07:54:26 PM UTC 24 |
| Peak memory | 628000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001103958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.4001103958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.538916749 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 25078023560 ps |
| CPU time | 7515.71 seconds |
| Started | Oct 15 05:47:51 PM UTC 24 |
| Finished | Oct 15 07:54:34 PM UTC 24 |
| Peak memory | 628096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538916749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.538916749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1248756600 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 23979279848 ps |
| CPU time | 7666.52 seconds |
| Started | Oct 15 05:47:58 PM UTC 24 |
| Finished | Oct 15 07:57:15 PM UTC 24 |
| Peak memory | 628092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248756600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1248756600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2154688911 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 18932826674 ps |
| CPU time | 6069.42 seconds |
| Started | Oct 15 05:47:38 PM UTC 24 |
| Finished | Oct 15 07:29:59 PM UTC 24 |
| Peak memory | 628040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154688911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2154688911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3271048901 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 15519448940 ps |
| CPU time | 4619.1 seconds |
| Started | Oct 15 05:47:54 PM UTC 24 |
| Finished | Oct 15 07:05:48 PM UTC 24 |
| Peak memory | 626360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271048901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3271048901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2659214503 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 15011129288 ps |
| CPU time | 4408.52 seconds |
| Started | Oct 15 05:46:54 PM UTC 24 |
| Finished | Oct 15 07:01:17 PM UTC 24 |
| Peak memory | 628136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659214503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2659214503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2379310441 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 15954345870 ps |
| CPU time | 4228.6 seconds |
| Started | Oct 15 05:48:39 PM UTC 24 |
| Finished | Oct 15 07:00:00 PM UTC 24 |
| Peak memory | 625588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379310441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2379310441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2920395935 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 15470141386 ps |
| CPU time | 4006.61 seconds |
| Started | Oct 15 05:47:19 PM UTC 24 |
| Finished | Oct 15 06:54:52 PM UTC 24 |
| Peak memory | 625580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920395935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2920395935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2157344846 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 11407324000 ps |
| CPU time | 3091.02 seconds |
| Started | Oct 15 05:47:21 PM UTC 24 |
| Finished | Oct 15 06:39:28 PM UTC 24 |
| Peak memory | 627972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157344846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2157344846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1248777593 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 15570669490 ps |
| CPU time | 4443.24 seconds |
| Started | Oct 15 05:44:57 PM UTC 24 |
| Finished | Oct 15 06:59:52 PM UTC 24 |
| Peak memory | 628152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248777593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1248777593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.4237048860 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 16319704286 ps |
| CPU time | 4755.62 seconds |
| Started | Oct 15 05:46:50 PM UTC 24 |
| Finished | Oct 15 07:07:03 PM UTC 24 |
| Peak memory | 627984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237048860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.4237048860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3952319693 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 15019776936 ps |
| CPU time | 4299.33 seconds |
| Started | Oct 15 05:45:27 PM UTC 24 |
| Finished | Oct 15 06:57:59 PM UTC 24 |
| Peak memory | 627900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952319693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3952319693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.128781064 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 15272758808 ps |
| CPU time | 4475.92 seconds |
| Started | Oct 15 05:45:26 PM UTC 24 |
| Finished | Oct 15 07:00:56 PM UTC 24 |
| Peak memory | 627900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128781064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.128781064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2069393780 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 11332164072 ps |
| CPU time | 3095.69 seconds |
| Started | Oct 15 05:46:17 PM UTC 24 |
| Finished | Oct 15 06:38:30 PM UTC 24 |
| Peak memory | 625832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069393780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2069393780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_rma.493477440 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 12049694631 ps |
| CPU time | 2115.22 seconds |
| Started | Oct 15 06:03:28 PM UTC 24 |
| Finished | Oct 15 06:39:10 PM UTC 24 |
| Peak memory | 641912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_devic e=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493477440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag _debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.493477440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2741813149 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 11378167570 ps |
| CPU time | 2133.18 seconds |
| Started | Oct 15 06:01:51 PM UTC 24 |
| Finished | Oct 15 06:37:54 PM UTC 24 |
| Peak memory | 642168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_devic e=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741813149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.2741813149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.183658595 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 39964082814 ps |
| CPU time | 3814.56 seconds |
| Started | Oct 15 06:09:55 PM UTC 24 |
| Finished | Oct 15 07:14:15 PM UTC 24 |
| Peak memory | 641484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_imag e=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183658595 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.183658595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.866506882 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 31095246901 ps |
| CPU time | 3865.57 seconds |
| Started | Oct 15 06:10:02 PM UTC 24 |
| Finished | Oct 15 07:15:13 PM UTC 24 |
| Peak memory | 641476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_imag e=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866506882 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.866506882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2932921333 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 32022754614 ps |
| CPU time | 3641.19 seconds |
| Started | Oct 15 06:09:56 PM UTC 24 |
| Finished | Oct 15 07:11:21 PM UTC 24 |
| Peak memory | 641452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_imag e=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932921333 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_test_unlocked0.2932921333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2892819014 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 15399645624 ps |
| CPU time | 4798.32 seconds |
| Started | Oct 15 06:19:20 PM UTC 24 |
| Finished | Oct 15 07:40:19 PM UTC 24 |
| Peak memory | 629940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892819014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2892819014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2546947477 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 14802953520 ps |
| CPU time | 4680.06 seconds |
| Started | Oct 15 06:14:30 PM UTC 24 |
| Finished | Oct 15 07:33:26 PM UTC 24 |
| Peak memory | 628368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546947477 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.2546947477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1576732235 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 14976453150 ps |
| CPU time | 4582.79 seconds |
| Started | Oct 15 06:17:48 PM UTC 24 |
| Finished | Oct 15 07:35:05 PM UTC 24 |
| Peak memory | 626236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576732235 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_no_meas.1576732235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_self_hash.2662292477 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 26212992072 ps |
| CPU time | 7747.14 seconds |
| Started | Oct 15 06:32:18 PM UTC 24 |
| Finished | Oct 15 08:42:57 PM UTC 24 |
| Peak memory | 628024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_rules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662292477 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.2662292477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_exception_c.2131860323 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 15498965160 ps |
| CPU time | 3806.74 seconds |
| Started | Oct 15 05:44:20 PM UTC 24 |
| Finished | Oct 15 06:48:32 PM UTC 24 |
| Peak memory | 630236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131860323 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_exception_c.2131860323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.1841179764 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 25508050280 ps |
| CPU time | 4383.98 seconds |
| Started | Oct 15 05:44:12 PM UTC 24 |
| Finished | Oct 15 06:58:10 PM UTC 24 |
| Peak memory | 630120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_flash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841179764 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.1841179764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2861181763 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 23957567690 ps |
| CPU time | 7162.8 seconds |
| Started | Oct 15 05:49:09 PM UTC 24 |
| Finished | Oct 15 07:49:56 PM UTC 24 |
| Peak memory | 630052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_fla sh_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861181763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2861181763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.122113420 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 23591799265 ps |
| CPU time | 7281.04 seconds |
| Started | Oct 15 05:49:34 PM UTC 24 |
| Finished | Oct 15 07:52:24 PM UTC 24 |
| Peak memory | 630060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_fl ash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122113420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_prod.122113420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.515267203 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 23419076408 ps |
| CPU time | 7508.61 seconds |
| Started | Oct 15 05:50:02 PM UTC 24 |
| Finished | Oct 15 07:56:39 PM UTC 24 |
| Peak memory | 630232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_fl ash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515267203 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.515267203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.39463344 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 23235316356 ps |
| CPU time | 7206.81 seconds |
| Started | Oct 15 05:49:53 PM UTC 24 |
| Finished | Oct 15 07:51:27 PM UTC 24 |
| Peak memory | 630236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_fl ash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39463344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_rma.39463344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2344240784 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 17980508482 ps |
| CPU time | 5907.64 seconds |
| Started | Oct 15 05:49:20 PM UTC 24 |
| Finished | Oct 15 07:29:01 PM UTC 24 |
| Peak memory | 630280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_fl ash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344240784 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2344240784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2695348354 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 14820326536 ps |
| CPU time | 4204.68 seconds |
| Started | Oct 15 05:48:40 PM UTC 24 |
| Finished | Oct 15 06:59:36 PM UTC 24 |
| Peak memory | 627616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2695348354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2695348354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1604338995 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 15193126200 ps |
| CPU time | 3896.57 seconds |
| Started | Oct 15 05:49:09 PM UTC 24 |
| Finished | Oct 15 06:54:51 PM UTC 24 |
| Peak memory | 627624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mas k_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1604338995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1604338995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3286313668 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 14375874295 ps |
| CPU time | 4180.84 seconds |
| Started | Oct 15 05:49:05 PM UTC 24 |
| Finished | Oct 15 06:59:35 PM UTC 24 |
| Peak memory | 627796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4 ,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3286313668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3286313668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2907957468 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 14533738132 ps |
| CPU time | 3702.35 seconds |
| Started | Oct 15 05:49:27 PM UTC 24 |
| Finished | Oct 15 06:51:53 PM UTC 24 |
| Peak memory | 627680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2907957468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2907957468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1121896896 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 11504992130 ps |
| CPU time | 3205.46 seconds |
| Started | Oct 15 05:48:45 PM UTC 24 |
| Finished | Oct 15 06:42:48 PM UTC 24 |
| Peak memory | 629780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_ test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1121896896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1121896896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3636666171 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 14666305108 ps |
| CPU time | 3901.88 seconds |
| Started | Oct 15 05:50:09 PM UTC 24 |
| Finished | Oct 15 06:55:58 PM UTC 24 |
| Peak memory | 627636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3636666171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3636666171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3354209102 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 14964500824 ps |
| CPU time | 3714.11 seconds |
| Started | Oct 15 05:50:38 PM UTC 24 |
| Finished | Oct 15 06:53:16 PM UTC 24 |
| Peak memory | 625492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4 ,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3354209102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3354209102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.4261278902 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 14481562102 ps |
| CPU time | 3727.01 seconds |
| Started | Oct 15 05:51:23 PM UTC 24 |
| Finished | Oct 15 06:54:14 PM UTC 24 |
| Peak memory | 629836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4261278902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.4261278902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2123007188 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 11004628280 ps |
| CPU time | 2903.37 seconds |
| Started | Oct 15 05:49:54 PM UTC 24 |
| Finished | Oct 15 06:38:50 PM UTC 24 |
| Peak memory | 627756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unloc ked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123007188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2123007188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_smoke.2235010474 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 14986439976 ps |
| CPU time | 4253.04 seconds |
| Started | Oct 15 05:44:51 PM UTC 24 |
| Finished | Oct 15 06:56:37 PM UTC 24 |
| Peak memory | 628068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235010474 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.2235010474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.1015901220 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 18050680928 ps |
| CPU time | 5189.48 seconds |
| Started | Oct 15 06:12:40 PM UTC 24 |
| Finished | Oct 15 07:40:14 PM UTC 24 |
| Peak memory | 630196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015901220 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.1015901220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_keymgr_functest.2463147686 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 4678010976 ps |
| CPU time | 508.17 seconds |
| Started | Oct 15 06:33:42 PM UTC 24 |
| Finished | Oct 15 06:42:17 PM UTC 24 |
| Peak memory | 627552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463147686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 0.rom_keymgr_functest.2463147686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_keymgr_functest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_raw_unlock.1995165270 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 4597318883 ps |
| CPU time | 272.43 seconds |
| Started | Oct 15 06:26:52 PM UTC 24 |
| Finished | Oct 15 06:31:28 PM UTC 24 |
| Peak memory | 639156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images =empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995165270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.1995165270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.1163955819 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 2462756020 ps |
| CPU time | 165.26 seconds |
| Started | Oct 15 06:23:22 PM UTC 24 |
| Finished | Oct 15 06:26:10 PM UTC 24 |
| Peak memory | 637012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRa w +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot _flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1163955819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.1163955819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.rom_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.4106479552 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 13307126808 ps |
| CPU time | 1367.53 seconds |
| Started | Oct 15 07:51:51 PM UTC 24 |
| Finished | Oct 15 08:14:56 PM UTC 24 |
| Peak memory | 625040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106479552 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.4106479552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_jtag_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.3075586898 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 4014055756 ps |
| CPU time | 513.79 seconds |
| Started | Oct 15 07:54:52 PM UTC 24 |
| Finished | Oct 15 08:03:33 PM UTC 24 |
| Peak memory | 639956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075586898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_ reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.3075586898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sival_flash_info_access.4013876461 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 3374558060 ps |
| CPU time | 311.97 seconds |
| Started | Oct 15 06:48:54 PM UTC 24 |
| Finished | Oct 15 06:54:10 PM UTC 24 |
| Peak memory | 627540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim _dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013876461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.4013876461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sival_flash_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1874433193 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 19717789272 ps |
| CPU time | 549.19 seconds |
| Started | Oct 15 07:21:52 PM UTC 24 |
| Finished | Oct 15 07:31:09 PM UTC 24 |
| Peak memory | 639660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874433193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/c hip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1874433193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.87036012 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 2590757368 ps |
| CPU time | 356.83 seconds |
| Started | Oct 15 07:23:16 PM UTC 24 |
| Finished | Oct 15 07:29:18 PM UTC 24 |
| Peak memory | 625748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_i mages=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=87036012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_aes_enc.87036012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.2023377473 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 3046270285 ps |
| CPU time | 292.41 seconds |
| Started | Oct 15 07:23:56 PM UTC 24 |
| Finished | Oct 15 07:28:53 PM UTC 24 |
| Peak memory | 625480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023377473 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.2023377473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2567552566 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 2722058237 ps |
| CPU time | 277.24 seconds |
| Started | Oct 15 08:00:40 PM UTC 24 |
| Finished | Oct 15 08:05:22 PM UTC 24 |
| Peak memory | 625752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567552566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.2567552566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.1246623211 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 2818535302 ps |
| CPU time | 293.4 seconds |
| Started | Oct 15 07:30:55 PM UTC 24 |
| Finished | Oct 15 07:35:53 PM UTC 24 |
| Peak memory | 627460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246623211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_aes_entropy.1246623211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.392434420 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 2521614290 ps |
| CPU time | 237.61 seconds |
| Started | Oct 15 07:23:55 PM UTC 24 |
| Finished | Oct 15 07:27:57 PM UTC 24 |
| Peak memory | 625376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=392434420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.392434420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.667797039 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 3391308989 ps |
| CPU time | 280.57 seconds |
| Started | Oct 15 07:23:55 PM UTC 24 |
| Finished | Oct 15 07:28:40 PM UTC 24 |
| Peak memory | 627412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667797039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_aes_masking_off.667797039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_masking_off/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.2411539835 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 2942588016 ps |
| CPU time | 282.81 seconds |
| Started | Oct 15 08:07:30 PM UTC 24 |
| Finished | Oct 15 08:12:17 PM UTC 24 |
| Peak memory | 625412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2411539835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_a es_smoketest.2411539835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.3013331859 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 3219402290 ps |
| CPU time | 295.03 seconds |
| Started | Oct 15 07:28:37 PM UTC 24 |
| Finished | Oct 15 07:33:36 PM UTC 24 |
| Peak memory | 625328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013331859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.3013331859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.460118853 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 5383564234 ps |
| CPU time | 444.36 seconds |
| Started | Oct 15 07:25:59 PM UTC 24 |
| Finished | Oct 15 07:33:29 PM UTC 24 |
| Peak memory | 640028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460118853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_e arlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.460118853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1588396657 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 4702542644 ps |
| CPU time | 895.01 seconds |
| Started | Oct 15 07:28:04 PM UTC 24 |
| Finished | Oct 15 07:43:11 PM UTC 24 |
| Peak memory | 627684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588396657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_ea rlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.1588396657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1698765867 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 7347645754 ps |
| CPU time | 1375.23 seconds |
| Started | Oct 15 07:28:01 PM UTC 24 |
| Finished | Oct 15 07:51:13 PM UTC 24 |
| Peak memory | 627680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698765867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_toggle.1698765867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.896733675 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 9521865422 ps |
| CPU time | 995.43 seconds |
| Started | Oct 15 07:27:57 PM UTC 24 |
| Finished | Oct 15 07:44:46 PM UTC 24 |
| Peak memory | 627312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896733675 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handl er_lpg_sleep_mode_pings.896733675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.2971668796 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 7406496220 ps |
| CPU time | 1455.05 seconds |
| Started | Oct 15 07:28:03 PM UTC 24 |
| Finished | Oct 15 07:52:36 PM UTC 24 |
| Peak memory | 627488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971668796 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.2971668796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.3357502669 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 2881384038 ps |
| CPU time | 333.31 seconds |
| Started | Oct 15 07:28:04 PM UTC 24 |
| Finished | Oct 15 07:33:42 PM UTC 24 |
| Peak memory | 627420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357502669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.3357502669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.74744370 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 2380301240 ps |
| CPU time | 284.86 seconds |
| Started | Oct 15 07:24:55 PM UTC 24 |
| Finished | Oct 15 07:29:44 PM UTC 24 |
| Peak memory | 625440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand om_seed=74744370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_ test.74744370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.1164414537 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 4302591164 ps |
| CPU time | 489.91 seconds |
| Started | Oct 15 07:18:06 PM UTC 24 |
| Finished | Oct 15 07:26:23 PM UTC 24 |
| Peak memory | 627620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164414537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.1164414537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1993098325 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 6533690164 ps |
| CPU time | 497.64 seconds |
| Started | Oct 15 07:18:21 PM UTC 24 |
| Finished | Oct 15 07:26:45 PM UTC 24 |
| Peak memory | 627288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993098325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1993098325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.27961122 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 3265367980 ps |
| CPU time | 370.97 seconds |
| Started | Oct 15 08:07:55 PM UTC 24 |
| Finished | Oct 15 08:14:12 PM UTC 24 |
| Peak memory | 625680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27961122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_aon_timer_smoketest.27961122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3017299290 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 9631913412 ps |
| CPU time | 853.82 seconds |
| Started | Oct 15 07:18:18 PM UTC 24 |
| Finished | Oct 15 07:32:43 PM UTC 24 |
| Peak memory | 627456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017299290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.3017299290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2294844880 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 5222709208 ps |
| CPU time | 522.65 seconds |
| Started | Oct 15 07:19:53 PM UTC 24 |
| Finished | Oct 15 07:28:43 PM UTC 24 |
| Peak memory | 627612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294844880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.2294844880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.2945904110 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 7192494904 ps |
| CPU time | 1070.86 seconds |
| Started | Oct 15 07:52:22 PM UTC 24 |
| Finished | Oct 15 08:10:27 PM UTC 24 |
| Peak memory | 633520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_ clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h w/dv/tools/sim.tcl +ntb_random_seed=2945904110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.2945904110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1351412272 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 7137383242 ps |
| CPU time | 487.34 seconds |
| Started | Oct 15 07:46:28 PM UTC 24 |
| Finished | Oct 15 07:54:42 PM UTC 24 |
| Peak memory | 641708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_de vice=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351412272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.1351412272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.810043195 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 4689981336 ps |
| CPU time | 684.28 seconds |
| Started | Oct 15 07:48:57 PM UTC 24 |
| Finished | Oct 15 08:00:31 PM UTC 24 |
| Peak memory | 631316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810043195 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src _for_sw_fast_dev.810043195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2455504568 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 3749799000 ps |
| CPU time | 715.46 seconds |
| Started | Oct 15 07:50:36 PM UTC 24 |
| Finished | Oct 15 08:02:41 PM UTC 24 |
| Peak memory | 629532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455504568 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_rma.2455504568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2722127724 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 4195319164 ps |
| CPU time | 576.81 seconds |
| Started | Oct 15 07:47:35 PM UTC 24 |
| Finished | Oct 15 07:57:20 PM UTC 24 |
| Peak memory | 629536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272 2127724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_exter nal_clk_src_for_sw_fast_test_unlocked0.2722127724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3591388108 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 5169054680 ps |
| CPU time | 606.13 seconds |
| Started | Oct 15 07:50:10 PM UTC 24 |
| Finished | Oct 15 08:00:25 PM UTC 24 |
| Peak memory | 629520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591388108 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_dev.3591388108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.108729721 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 4870217762 ps |
| CPU time | 553.66 seconds |
| Started | Oct 15 07:51:19 PM UTC 24 |
| Finished | Oct 15 08:00:40 PM UTC 24 |
| Peak memory | 631716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108729721 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src _for_sw_slow_rma.108729721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3572021861 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 4772694504 ps |
| CPU time | 527.87 seconds |
| Started | Oct 15 07:47:55 PM UTC 24 |
| Finished | Oct 15 07:56:50 PM UTC 24 |
| Peak memory | 629296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357 2021861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_exter nal_clk_src_for_sw_slow_test_unlocked0.3572021861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.2997534520 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 3423603920 ps |
| CPU time | 280.18 seconds |
| Started | Oct 15 07:51:48 PM UTC 24 |
| Finished | Oct 15 07:56:33 PM UTC 24 |
| Peak memory | 625384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2997534520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_clkmgr_jitter.2997534520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.57060055 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 3978984144 ps |
| CPU time | 429.75 seconds |
| Started | Oct 15 07:51:51 PM UTC 24 |
| Finished | Oct 15 07:59:07 PM UTC 24 |
| Peak memory | 627428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=57060055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_clkmgr_jitter_frequency.57060055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.897296710 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 2363038433 ps |
| CPU time | 233.43 seconds |
| Started | Oct 15 07:58:07 PM UTC 24 |
| Finished | Oct 15 08:02:04 PM UTC 24 |
| Peak memory | 625236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkm gr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=897296710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.897296710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3882033806 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 4346226744 ps |
| CPU time | 397.65 seconds |
| Started | Oct 15 07:44:21 PM UTC 24 |
| Finished | Oct 15 07:51:04 PM UTC 24 |
| Peak memory | 627368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3882033806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.3882033806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2027641912 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 4298165000 ps |
| CPU time | 371.78 seconds |
| Started | Oct 15 07:44:21 PM UTC 24 |
| Finished | Oct 15 07:50:38 PM UTC 24 |
| Peak memory | 627508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2027641912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_clkmgr_off_hmac_trans.2027641912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2180364126 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 4403654812 ps |
| CPU time | 427.1 seconds |
| Started | Oct 15 07:44:25 PM UTC 24 |
| Finished | Oct 15 07:51:38 PM UTC 24 |
| Peak memory | 625240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2180364126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_clkmgr_off_kmac_trans.2180364126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.596338418 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 3848161630 ps |
| CPU time | 507.45 seconds |
| Started | Oct 15 07:45:26 PM UTC 24 |
| Finished | Oct 15 07:54:00 PM UTC 24 |
| Peak memory | 625480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=596338418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.596338418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.2733811031 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 8297509492 ps |
| CPU time | 879.32 seconds |
| Started | Oct 15 07:44:22 PM UTC 24 |
| Finished | Oct 15 07:59:13 PM UTC 24 |
| Peak memory | 627820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_i mages=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733811031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.2733811031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.1221412707 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 3413542500 ps |
| CPU time | 511.46 seconds |
| Started | Oct 15 07:51:46 PM UTC 24 |
| Finished | Oct 15 08:00:24 PM UTC 24 |
| Peak memory | 627440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221412707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.1221412707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.103923807 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 4796512134 ps |
| CPU time | 667.61 seconds |
| Started | Oct 15 07:51:52 PM UTC 24 |
| Finished | Oct 15 08:03:09 PM UTC 24 |
| Peak memory | 627516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103923807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.103923807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.3491945899 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 2715352200 ps |
| CPU time | 231.27 seconds |
| Started | Oct 15 08:07:56 PM UTC 24 |
| Finished | Oct 15 08:11:52 PM UTC 24 |
| Peak memory | 627280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3491945899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_clkmgr_smoketest.3491945899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.1183200842 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 23201980656 ps |
| CPU time | 6600.17 seconds |
| Started | Oct 15 07:30:55 PM UTC 24 |
| Finished | Oct 15 09:22:15 PM UTC 24 |
| Peak memory | 629948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1183200842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_csrng_edn_concurrency.1183200842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3921238665 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 30039378415 ps |
| CPU time | 6320.09 seconds |
| Started | Oct 15 08:02:11 PM UTC 24 |
| Finished | Oct 15 09:48:47 PM UTC 24 |
| Peak memory | 630424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accele rate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921238665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_b ase_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.3921238665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3477656562 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 4424439510 ps |
| CPU time | 563.46 seconds |
| Started | Oct 15 07:31:18 PM UTC 24 |
| Finished | Oct 15 07:40:49 PM UTC 24 |
| Peak memory | 627292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477656562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src _fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.3477656562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.3088421420 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 2597235840 ps |
| CPU time | 247.56 seconds |
| Started | Oct 15 07:30:57 PM UTC 24 |
| Finished | Oct 15 07:35:08 PM UTC 24 |
| Peak memory | 627776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088421420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_csrng_kat_test.3088421420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3700096942 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 5407891200 ps |
| CPU time | 657.05 seconds |
| Started | Oct 15 07:30:49 PM UTC 24 |
| Finished | Oct 15 07:41:55 PM UTC 24 |
| Peak memory | 627572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_ otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700096942 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_lc_hw_debug_en_test.3700096942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.3991840568 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 2609681064 ps |
| CPU time | 177.96 seconds |
| Started | Oct 15 08:08:04 PM UTC 24 |
| Finished | Oct 15 08:11:05 PM UTC 24 |
| Peak memory | 625344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3991840568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _csrng_smoketest.3991840568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.1304696618 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 6071864734 ps |
| CPU time | 730.34 seconds |
| Started | Oct 15 06:50:25 PM UTC 24 |
| Finished | Oct 15 07:02:45 PM UTC 24 |
| Peak memory | 627556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304696618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.1304696618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.3964610258 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 7599391864 ps |
| CPU time | 1714.23 seconds |
| Started | Oct 15 07:30:56 PM UTC 24 |
| Finished | Oct 15 07:59:52 PM UTC 24 |
| Peak memory | 625372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_ device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964610258 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_auto_mode.3964610258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.3150593864 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 2776192296 ps |
| CPU time | 490.96 seconds |
| Started | Oct 15 07:30:10 PM UTC 24 |
| Finished | Oct 15 07:38:27 PM UTC 24 |
| Peak memory | 625584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_ device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150593864 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_boot_mode.3150593864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.534658821 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 7021661840 ps |
| CPU time | 1018.27 seconds |
| Started | Oct 15 07:33:24 PM UTC 24 |
| Finished | Oct 15 07:50:35 PM UTC 24 |
| Peak memory | 627412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534658821 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.534658821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.533499528 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 6160085112 ps |
| CPU time | 955.92 seconds |
| Started | Oct 15 07:35:22 PM UTC 24 |
| Finished | Oct 15 07:51:31 PM UTC 24 |
| Peak memory | 627404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533499528 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.533499528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.3331971110 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 3768639936 ps |
| CPU time | 664.94 seconds |
| Started | Oct 15 07:30:52 PM UTC 24 |
| Finished | Oct 15 07:42:06 PM UTC 24 |
| Peak memory | 633916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_a ssert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=3331971110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_edn_kat.3331971110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_kat/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.2758994308 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 7093084616 ps |
| CPU time | 1400.1 seconds |
| Started | Oct 15 07:30:59 PM UTC 24 |
| Finished | Oct 15 07:54:37 PM UTC 24 |
| Peak memory | 627512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2758994308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_edn_sw_mode.2758994308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2240715917 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 2514380024 ps |
| CPU time | 269.45 seconds |
| Started | Oct 15 07:31:49 PM UTC 24 |
| Finished | Oct 15 07:36:23 PM UTC 24 |
| Peak memory | 625240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240715917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.2240715917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.2141899285 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 7804289280 ps |
| CPU time | 1801.52 seconds |
| Started | Oct 15 07:32:58 PM UTC 24 |
| Finished | Oct 15 08:03:22 PM UTC 24 |
| Peak memory | 625364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_ srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141899285 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.2141899285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.1892885397 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 2539020556 ps |
| CPU time | 243.69 seconds |
| Started | Oct 15 07:29:59 PM UTC 24 |
| Finished | Oct 15 07:34:06 PM UTC 24 |
| Peak memory | 627432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892885397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.1892885397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.2929707814 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 2760109608 ps |
| CPU time | 310.14 seconds |
| Started | Oct 15 08:08:24 PM UTC 24 |
| Finished | Oct 15 08:13:39 PM UTC 24 |
| Peak memory | 625468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_de vice=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929707814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.2929707814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_concurrency.2669402184 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 2642576660 ps |
| CPU time | 252.53 seconds |
| Started | Oct 15 06:48:15 PM UTC 24 |
| Finished | Oct 15 06:52:31 PM UTC 24 |
| Peak memory | 625240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2669402184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_concurrency.2669402184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_flash.1613716515 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 2796625896 ps |
| CPU time | 256.63 seconds |
| Started | Oct 15 06:48:08 PM UTC 24 |
| Finished | Oct 15 06:52:29 PM UTC 24 |
| Peak memory | 625740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1613716515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_example_flash.1613716515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_manufacturer.590819662 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 3304130760 ps |
| CPU time | 210.19 seconds |
| Started | Oct 15 06:48:14 PM UTC 24 |
| Finished | Oct 15 06:51:47 PM UTC 24 |
| Peak memory | 625236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=590819662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exa mple_manufacturer.590819662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_manufacturer/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_rom.760866969 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 2291027564 ps |
| CPU time | 119.18 seconds |
| Started | Oct 15 06:47:41 PM UTC 24 |
| Finished | Oct 15 06:49:43 PM UTC 24 |
| Peak memory | 627208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:t est_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=760866969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_sw_example_rom.760866969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.2759773471 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 4702587846 ps |
| CPU time | 507.84 seconds |
| Started | Oct 15 07:58:07 PM UTC 24 |
| Finished | Oct 15 08:06:42 PM UTC 24 |
| Peak memory | 627432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check= 1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759773471 -assert nopostproc +UVM_TESTNAME=chip_base_test + UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.2759773471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.2149458552 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 5069851860 ps |
| CPU time | 928 seconds |
| Started | Oct 15 07:00:44 PM UTC 24 |
| Finished | Oct 15 07:16:24 PM UTC 24 |
| Peak memory | 625316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2149458552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _flash_ctrl_access.2149458552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1425335204 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 6428230620 ps |
| CPU time | 1095.28 seconds |
| Started | Oct 15 07:00:44 PM UTC 24 |
| Finished | Oct 15 07:19:14 PM UTC 24 |
| Peak memory | 627276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=1425335204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_flash_ctrl_access_jitter_en.1425335204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1796750578 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 7537966003 ps |
| CPU time | 1131.24 seconds |
| Started | Oct 15 08:00:07 PM UTC 24 |
| Finished | Oct 15 08:19:12 PM UTC 24 |
| Peak memory | 625492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796750578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1796750578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3089096011 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 5338662987 ps |
| CPU time | 1102.23 seconds |
| Started | Oct 15 07:02:05 PM UTC 24 |
| Finished | Oct 15 07:20:42 PM UTC 24 |
| Peak memory | 625404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=3089096011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_flash_ctrl_clock_freqs.3089096011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2287453083 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 3633840504 ps |
| CPU time | 341.24 seconds |
| Started | Oct 15 07:00:44 PM UTC 24 |
| Finished | Oct 15 07:06:30 PM UTC 24 |
| Peak memory | 627432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2287453083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_flash_ctrl_idle_low_power.2287453083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3062267894 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 4928592450 ps |
| CPU time | 645.07 seconds |
| Started | Oct 15 06:59:33 PM UTC 24 |
| Finished | Oct 15 07:10:27 PM UTC 24 |
| Peak memory | 627484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062267894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ct rl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.3062267894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2604134595 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 5349029406 ps |
| CPU time | 971.02 seconds |
| Started | Oct 15 08:02:58 PM UTC 24 |
| Finished | Oct 15 08:19:21 PM UTC 24 |
| Peak memory | 625592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2604134595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_flash_ctrl_mem_protection.2604134595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.3804154198 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 3985547736 ps |
| CPU time | 635.91 seconds |
| Started | Oct 15 06:58:52 PM UTC 24 |
| Finished | Oct 15 07:09:37 PM UTC 24 |
| Peak memory | 627288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804154198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.3804154198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3972632111 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 3877828921 ps |
| CPU time | 619.86 seconds |
| Started | Oct 15 06:59:33 PM UTC 24 |
| Finished | Oct 15 07:10:01 PM UTC 24 |
| Peak memory | 625800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972632111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.3972632111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.355151303 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 3384372426 ps |
| CPU time | 343.21 seconds |
| Started | Oct 15 07:58:06 PM UTC 24 |
| Finished | Oct 15 08:03:54 PM UTC 24 |
| Peak memory | 627416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_image s=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355151303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.355151303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.908793971 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 17995814247 ps |
| CPU time | 1704.97 seconds |
| Started | Oct 15 07:00:38 PM UTC 24 |
| Finished | Oct 15 07:29:25 PM UTC 24 |
| Peak memory | 631540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908793971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.908793971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_init/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init_reduced_freq.2762699080 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 20346799269 ps |
| CPU time | 1744.23 seconds |
| Started | Oct 15 08:01:48 PM UTC 24 |
| Finished | Oct 15 08:31:14 PM UTC 24 |
| Peak memory | 627440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_buil d_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762699080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.2762699080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.37171339 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 3028127528 ps |
| CPU time | 194.9 seconds |
| Started | Oct 15 08:04:25 PM UTC 24 |
| Finished | Oct 15 08:07:43 PM UTC 24 |
| Peak memory | 625672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_ima ges=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoketest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37171339 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_ earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.37171339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.2632336758 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 2754579170 ps |
| CPU time | 247.17 seconds |
| Started | Oct 15 08:08:26 PM UTC 24 |
| Finished | Oct 15 08:12:37 PM UTC 24 |
| Peak memory | 625496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2632336758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_sw_gpio_smoketest.2632336758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.3003048047 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 2876044240 ps |
| CPU time | 233.46 seconds |
| Started | Oct 15 07:35:19 PM UTC 24 |
| Finished | Oct 15 07:39:16 PM UTC 24 |
| Peak memory | 627416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3003048047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_h mac_enc.3003048047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.3639972129 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 2520232342 ps |
| CPU time | 319.22 seconds |
| Started | Oct 15 07:35:24 PM UTC 24 |
| Finished | Oct 15 07:40:48 PM UTC 24 |
| Peak memory | 625504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3639972129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_hmac_enc_idle.3639972129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.4101249022 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 2801263363 ps |
| CPU time | 295.68 seconds |
| Started | Oct 15 07:35:13 PM UTC 24 |
| Finished | Oct 15 07:40:13 PM UTC 24 |
| Peak memory | 627424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4101249022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_hmac_enc_jitter_en.4101249022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3088273916 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 3588224098 ps |
| CPU time | 255.48 seconds |
| Started | Oct 15 08:01:54 PM UTC 24 |
| Finished | Oct 15 08:06:14 PM UTC 24 |
| Peak memory | 627288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088273916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.3088273916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.3761217175 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 8641432134 ps |
| CPU time | 1865.73 seconds |
| Started | Oct 15 07:35:22 PM UTC 24 |
| Finished | Oct 15 08:06:51 PM UTC 24 |
| Peak memory | 625500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3761217175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_multistream.3761217175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_multistream/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.1821349798 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 2645213472 ps |
| CPU time | 278.97 seconds |
| Started | Oct 15 07:35:12 PM UTC 24 |
| Finished | Oct 15 07:39:56 PM UTC 24 |
| Peak memory | 625360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1821349798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_h mac_oneshot.1821349798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.1861021809 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 3366341244 ps |
| CPU time | 395.17 seconds |
| Started | Oct 15 08:08:43 PM UTC 24 |
| Finished | Oct 15 08:15:24 PM UTC 24 |
| Peak memory | 625384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=1861021809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ hmac_smoketest.1861021809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.4150060294 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 5245856798 ps |
| CPU time | 770.1 seconds |
| Started | Oct 15 06:55:41 PM UTC 24 |
| Finished | Oct 15 07:08:42 PM UTC 24 |
| Peak memory | 625384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=4150060294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_i2c_host_tx_rx.4150060294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.509454477 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 4742745928 ps |
| CPU time | 770.8 seconds |
| Started | Oct 15 06:55:41 PM UTC 24 |
| Finished | Oct 15 07:08:42 PM UTC 24 |
| Peak memory | 625680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=509454477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.509454477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.205958092 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 4470359230 ps |
| CPU time | 703.32 seconds |
| Started | Oct 15 06:56:37 PM UTC 24 |
| Finished | Oct 15 07:08:30 PM UTC 24 |
| Peak memory | 625832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=205958092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.205958092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_inject_scramble_seed.1470058185 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 65873014680 ps |
| CPU time | 15838.4 seconds |
| Started | Oct 15 06:54:04 PM UTC 24 |
| Finished | Oct 15 11:21:14 PM UTC 24 |
| Peak memory | 644272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=1 50_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470058185 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.1470058185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_aes.1489719717 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 13246228500 ps |
| CPU time | 2497.28 seconds |
| Started | Oct 15 07:36:42 PM UTC 24 |
| Finished | Oct 15 08:18:49 PM UTC 24 |
| Peak memory | 627700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489719717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sidel oad_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.1489719717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.1387867118 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 9583146336 ps |
| CPU time | 1703.6 seconds |
| Started | Oct 15 07:36:02 PM UTC 24 |
| Finished | Oct 15 08:04:46 PM UTC 24 |
| Peak memory | 627580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387867118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_side load_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.1387867118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_otbn.3350366029 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 16226738840 ps |
| CPU time | 5122.26 seconds |
| Started | Oct 15 07:36:45 PM UTC 24 |
| Finished | Oct 15 09:03:09 PM UTC 24 |
| Peak memory | 629944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350366029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.3350366029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.3661071481 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 2585747088 ps |
| CPU time | 184 seconds |
| Started | Oct 15 07:39:08 PM UTC 24 |
| Finished | Oct 15 07:42:15 PM UTC 24 |
| Peak memory | 625488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=3661071481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_kmac_app_rom.3661071481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.409819450 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 3059532900 ps |
| CPU time | 236.98 seconds |
| Started | Oct 15 07:02:06 PM UTC 24 |
| Finished | Oct 15 07:06:07 PM UTC 24 |
| Peak memory | 625460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=409819450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_kmac_entropy.409819450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.2783112590 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 2083224564 ps |
| CPU time | 201.29 seconds |
| Started | Oct 15 07:40:07 PM UTC 24 |
| Finished | Oct 15 07:43:32 PM UTC 24 |
| Peak memory | 625176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2783112590 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ kmac_idle.2783112590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.2169077383 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 3113138780 ps |
| CPU time | 261.21 seconds |
| Started | Oct 15 07:37:04 PM UTC 24 |
| Finished | Oct 15 07:41:29 PM UTC 24 |
| Peak memory | 625648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2169077383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_sw_kmac_mode_cshake.2169077383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.1319869981 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 2809187860 ps |
| CPU time | 304.22 seconds |
| Started | Oct 15 07:38:10 PM UTC 24 |
| Finished | Oct 15 07:43:19 PM UTC 24 |
| Peak memory | 625240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319869981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_kmac_mode_kmac.1319869981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3929453942 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 3209944999 ps |
| CPU time | 264.48 seconds |
| Started | Oct 15 07:38:14 PM UTC 24 |
| Finished | Oct 15 07:42:42 PM UTC 24 |
| Peak memory | 627280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_km ac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3929453942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.3929453942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.374867793 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 3745782381 ps |
| CPU time | 281.9 seconds |
| Started | Oct 15 08:01:48 PM UTC 24 |
| Finished | Oct 15 08:06:35 PM UTC 24 |
| Peak memory | 627480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374867793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.374867793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.3470199955 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 3374184408 ps |
| CPU time | 344.23 seconds |
| Started | Oct 15 08:10:46 PM UTC 24 |
| Finished | Oct 15 08:16:36 PM UTC 24 |
| Peak memory | 625496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3470199955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ kmac_smoketest.3470199955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.4055675281 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 3499075008 ps |
| CPU time | 321.92 seconds |
| Started | Oct 15 07:04:44 PM UTC 24 |
| Finished | Oct 15 07:10:11 PM UTC 24 |
| Peak memory | 625372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=4055675281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.4055675281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.3608714856 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 4706927174 ps |
| CPU time | 584.97 seconds |
| Started | Oct 15 07:52:23 PM UTC 24 |
| Finished | Oct 15 08:02:16 PM UTC 24 |
| Peak memory | 627460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608714856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_l c_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.3608714856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.4210194157 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 3660444405 ps |
| CPU time | 243.95 seconds |
| Started | Oct 15 07:07:25 PM UTC 24 |
| Finished | Oct 15 07:11:32 PM UTC 24 |
| Peak memory | 639580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210194157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.4210194157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.3417937208 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 10855838504 ps |
| CPU time | 924.02 seconds |
| Started | Oct 15 07:07:17 PM UTC 24 |
| Finished | Oct 15 07:22:53 PM UTC 24 |
| Peak memory | 641920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3417937208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_lc_ctrl_transition.3417937208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.535747216 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 1962963170 ps |
| CPU time | 143.14 seconds |
| Started | Oct 15 07:07:25 PM UTC 24 |
| Finished | Oct 15 07:09:51 PM UTC 24 |
| Peak memory | 634892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535747216 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.535747216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3711762626 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 2696263630 ps |
| CPU time | 131.51 seconds |
| Started | Oct 15 07:07:51 PM UTC 24 |
| Finished | Oct 15 07:10:05 PM UTC 24 |
| Peak memory | 635288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSo urceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37117626 26 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc _ctrl_volatile_raw_unlock_ext_clk_48mhz.3711762626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_dev.1789134167 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 48180544716 ps |
| CPU time | 6664.27 seconds |
| Started | Oct 15 07:06:45 PM UTC 24 |
| Finished | Oct 15 08:59:11 PM UTC 24 |
| Peak memory | 644600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789134167 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_dev.1789134167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.3564526793 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 50949084505 ps |
| CPU time | 5955.99 seconds |
| Started | Oct 15 07:07:21 PM UTC 24 |
| Finished | Oct 15 08:47:48 PM UTC 24 |
| Peak memory | 644424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564526793 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prod.3564526793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.21761029 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 11265083688 ps |
| CPU time | 1103.56 seconds |
| Started | Oct 15 07:07:45 PM UTC 24 |
| Finished | Oct 15 07:26:22 PM UTC 24 |
| Peak memory | 641892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21761029 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.21761029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_rma.762279229 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 45994222664 ps |
| CPU time | 6539.83 seconds |
| Started | Oct 15 07:07:50 PM UTC 24 |
| Finished | Oct 15 08:58:11 PM UTC 24 |
| Peak memory | 644348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +fl ash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762279229 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_rma.762279229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1205112022 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 30058511112 ps |
| CPU time | 2235.27 seconds |
| Started | Oct 15 07:08:08 PM UTC 24 |
| Finished | Oct 15 07:45:50 PM UTC 24 |
| Peak memory | 641880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnl ock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205112022 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testunlocks.1205112022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.667466296 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 17079042360 ps |
| CPU time | 4340.3 seconds |
| Started | Oct 15 07:21:59 PM UTC 24 |
| Finished | Oct 15 08:35:13 PM UTC 24 |
| Peak memory | 629944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667466296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.667466296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2289955101 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 18591891567 ps |
| CPU time | 4370.56 seconds |
| Started | Oct 15 07:21:58 PM UTC 24 |
| Finished | Oct 15 08:35:44 PM UTC 24 |
| Peak memory | 627900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289955101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2289955101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3882667137 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 25305740031 ps |
| CPU time | 4799.62 seconds |
| Started | Oct 15 08:00:09 PM UTC 24 |
| Finished | Oct 15 09:21:07 PM UTC 24 |
| Peak memory | 629952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882667137 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3882667137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.985221636 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 3260185250 ps |
| CPU time | 472.08 seconds |
| Started | Oct 15 07:22:39 PM UTC 24 |
| Finished | Oct 15 07:30:37 PM UTC 24 |
| Peak memory | 627220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985221636 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.985221636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.4284035910 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 6282700724 ps |
| CPU time | 839.27 seconds |
| Started | Oct 15 07:21:53 PM UTC 24 |
| Finished | Oct 15 07:36:03 PM UTC 24 |
| Peak memory | 627644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284035910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.4284035910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_randomness/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_smoketest.2716945987 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 7411249888 ps |
| CPU time | 1363.68 seconds |
| Started | Oct 15 08:10:47 PM UTC 24 |
| Finished | Oct 15 08:33:48 PM UTC 24 |
| Peak memory | 625372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2716945987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ otbn_smoketest.2716945987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_descrambling.3411696720 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 4198783048 ps |
| CPU time | 496.48 seconds |
| Started | Oct 15 07:05:01 PM UTC 24 |
| Finished | Oct 15 07:13:25 PM UTC 24 |
| Peak memory | 625236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_ima ges=otp_ctrl_descrambling_test:1:new_rules,otp_ctrl_descrambling_otp_image:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411696720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlg rey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_descrambling.3411696720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_descrambling/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.34445844 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 3294671066 ps |
| CPU time | 344.9 seconds |
| Started | Oct 15 07:04:51 PM UTC 24 |
| Finished | Oct 15 07:10:41 PM UTC 24 |
| Peak memory | 627804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_ error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=34445844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.34445844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3920680297 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 9882723334 ps |
| CPU time | 1268.55 seconds |
| Started | Oct 15 07:04:43 PM UTC 24 |
| Finished | Oct 15 07:26:07 PM UTC 24 |
| Peak memory | 627488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920680297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.3920680297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2466777343 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 8094765220 ps |
| CPU time | 1083.23 seconds |
| Started | Oct 15 07:04:42 PM UTC 24 |
| Finished | Oct 15 07:22:59 PM UTC 24 |
| Peak memory | 627468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_buil d_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466777343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.2466777343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2480788030 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 7430836740 ps |
| CPU time | 1292.76 seconds |
| Started | Oct 15 07:04:49 PM UTC 24 |
| Finished | Oct 15 07:26:39 PM UTC 24 |
| Peak memory | 627420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480788030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.2480788030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2589888065 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 3959623192 ps |
| CPU time | 615.59 seconds |
| Started | Oct 15 07:04:47 PM UTC 24 |
| Finished | Oct 15 07:15:11 PM UTC 24 |
| Peak memory | 627548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589888065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_ asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2589888065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.2017785159 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 2642347130 ps |
| CPU time | 318.88 seconds |
| Started | Oct 15 08:11:29 PM UTC 24 |
| Finished | Oct 15 08:16:53 PM UTC 24 |
| Peak memory | 625736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2017785159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_otp_ctrl_smoketest.2017785159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pattgen_ios.1711853418 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 2090979648 ps |
| CPU time | 207.16 seconds |
| Started | Oct 15 06:52:09 PM UTC 24 |
| Finished | Oct 15 06:55:40 PM UTC 24 |
| Peak memory | 627468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_im ages=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711853418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.1711853418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pattgen_ios/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.3712520950 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 2602772200 ps |
| CPU time | 231.8 seconds |
| Started | Oct 15 07:43:21 PM UTC 24 |
| Finished | Oct 15 07:47:17 PM UTC 24 |
| Peak memory | 625464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3712520950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_plic_sw_irq.3712520950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.2688372615 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 4653954112 ps |
| CPU time | 666.83 seconds |
| Started | Oct 15 08:02:10 PM UTC 24 |
| Finished | Oct 15 08:13:26 PM UTC 24 |
| Peak memory | 627284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688372615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_power_idle_load.2688372615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_idle_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.3186423415 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 10800123988 ps |
| CPU time | 549.61 seconds |
| Started | Oct 15 08:01:56 PM UTC 24 |
| Finished | Oct 15 08:11:13 PM UTC 24 |
| Peak memory | 627544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3186423415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.3186423415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_sleep_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_virus.518762776 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 5977302320 ps |
| CPU time | 1405.03 seconds |
| Started | Oct 15 08:04:11 PM UTC 24 |
| Finished | Oct 15 08:27:54 PM UTC 24 |
| Peak memory | 642384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_tim eout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_ img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518762776 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_virus.518762776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.799557207 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 10975174727 ps |
| CPU time | 1645.72 seconds |
| Started | Oct 15 07:11:39 PM UTC 24 |
| Finished | Oct 15 07:39:26 PM UTC 24 |
| Peak memory | 629464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799557207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_ all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.799557207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3477353429 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 28176631300 ps |
| CPU time | 3118.86 seconds |
| Started | Oct 15 07:42:07 PM UTC 24 |
| Finished | Oct 15 08:34:44 PM UTC 24 |
| Peak memory | 629756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477353429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_re set_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.3477353429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2222460753 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 12662610343 ps |
| CPU time | 1178.77 seconds |
| Started | Oct 15 07:12:22 PM UTC 24 |
| Finished | Oct 15 07:32:16 PM UTC 24 |
| Peak memory | 629412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222460753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2222460753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.835084029 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 23124895888 ps |
| CPU time | 1412.06 seconds |
| Started | Oct 15 07:53:45 PM UTC 24 |
| Finished | Oct 15 08:17:35 PM UTC 24 |
| Peak memory | 627476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835084029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_ deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.835084029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.658505661 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 9486646208 ps |
| CPU time | 513.51 seconds |
| Started | Oct 15 07:12:18 PM UTC 24 |
| Finished | Oct 15 07:20:58 PM UTC 24 |
| Peak memory | 627780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_res et_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=658505661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.658505661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3352462363 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 7660116720 ps |
| CPU time | 495.27 seconds |
| Started | Oct 15 07:12:21 PM UTC 24 |
| Finished | Oct 15 07:20:43 PM UTC 24 |
| Peak memory | 635444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352462363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3352462363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2522412804 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 7156011856 ps |
| CPU time | 516.17 seconds |
| Started | Oct 15 07:12:11 PM UTC 24 |
| Finished | Oct 15 07:20:54 PM UTC 24 |
| Peak memory | 627552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2522412804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_pwrmgr_full_aon_reset.2522412804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3476079052 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 5106425507 ps |
| CPU time | 360.22 seconds |
| Started | Oct 15 07:11:01 PM UTC 24 |
| Finished | Oct 15 07:17:07 PM UTC 24 |
| Peak memory | 635728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476079052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_mai n_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.3476079052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.797881974 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 10770532018 ps |
| CPU time | 1254.19 seconds |
| Started | Oct 15 07:12:26 PM UTC 24 |
| Finished | Oct 15 07:33:35 PM UTC 24 |
| Peak memory | 629596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_r eset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=797881974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.797881974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.924896028 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 7124611632 ps |
| CPU time | 435.72 seconds |
| Started | Oct 15 07:53:16 PM UTC 24 |
| Finished | Oct 15 08:00:38 PM UTC 24 |
| Peak memory | 627292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_w ake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=924896028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.924896028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.969755717 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 6925001895 ps |
| CPU time | 604.29 seconds |
| Started | Oct 15 07:12:12 PM UTC 24 |
| Finished | Oct 15 07:22:25 PM UTC 24 |
| Peak memory | 627436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_r eset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=969755717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.969755717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.271713699 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 25966492389 ps |
| CPU time | 2240.26 seconds |
| Started | Oct 15 07:11:40 PM UTC 24 |
| Finished | Oct 15 07:49:29 PM UTC 24 |
| Peak memory | 627372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271713699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_ asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.271713699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3761864085 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 23591763070 ps |
| CPU time | 1663.45 seconds |
| Started | Oct 15 07:53:45 PM UTC 24 |
| Finished | Oct 15 08:21:49 PM UTC 24 |
| Peak memory | 627788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761864085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3761864085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1114549826 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 37125930616 ps |
| CPU time | 3463.58 seconds |
| Started | Oct 15 07:12:47 PM UTC 24 |
| Finished | Oct 15 08:11:14 PM UTC 24 |
| Peak memory | 631896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_00 0_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power_glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114549826 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1114549826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2711818683 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 5893661740 ps |
| CPU time | 531.83 seconds |
| Started | Oct 15 07:54:52 PM UTC 24 |
| Finished | Oct 15 08:03:51 PM UTC 24 |
| Peak memory | 627600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711818683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2711818683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1460938287 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 2662600344 ps |
| CPU time | 252.88 seconds |
| Started | Oct 15 07:13:04 PM UTC 24 |
| Finished | Oct 15 07:17:21 PM UTC 24 |
| Peak memory | 627780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1460938287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_pwrmgr_sleep_disabled.1460938287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.693000609 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 4863037960 ps |
| CPU time | 511.45 seconds |
| Started | Oct 15 07:41:43 PM UTC 24 |
| Finished | Oct 15 07:50:22 PM UTC 24 |
| Peak memory | 627524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_im ages=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693000609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.693000609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1114150303 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 6116981360 ps |
| CPU time | 359.89 seconds |
| Started | Oct 15 07:53:58 PM UTC 24 |
| Finished | Oct 15 08:00:03 PM UTC 24 |
| Peak memory | 627580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114150303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.1114150303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.1404720321 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 6879421488 ps |
| CPU time | 447.09 seconds |
| Started | Oct 15 08:11:26 PM UTC 24 |
| Finished | Oct 15 08:19:00 PM UTC 24 |
| Peak memory | 627428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_ima ges=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404720321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.1404720321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1003819789 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 8433636696 ps |
| CPU time | 1069.48 seconds |
| Started | Oct 15 07:11:28 PM UTC 24 |
| Finished | Oct 15 07:29:31 PM UTC 24 |
| Peak memory | 627296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1003819789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.1003819789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3757606250 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 5196510206 ps |
| CPU time | 719.26 seconds |
| Started | Oct 15 07:14:06 PM UTC 24 |
| Finished | Oct 15 07:26:15 PM UTC 24 |
| Peak memory | 627764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_w hen_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=3757606250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3757606250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3757255131 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 5735895332 ps |
| CPU time | 384.46 seconds |
| Started | Oct 15 08:11:39 PM UTC 24 |
| Finished | Oct 15 08:18:09 PM UTC 24 |
| Peak memory | 627444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3757255131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_pwrmgr_usbdev_smoketest.3757255131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.4182290136 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 3881144280 ps |
| CPU time | 411.28 seconds |
| Started | Oct 15 07:18:22 PM UTC 24 |
| Finished | Oct 15 07:25:19 PM UTC 24 |
| Peak memory | 627292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182290136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.4182290136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1011660027 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 8809567732 ps |
| CPU time | 473.81 seconds |
| Started | Oct 15 07:40:16 PM UTC 24 |
| Finished | Oct 15 07:48:16 PM UTC 24 |
| Peak memory | 627348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1011660027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.1011660027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.207255654 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 12572344814 ps |
| CPU time | 1791.34 seconds |
| Started | Oct 15 07:09:30 PM UTC 24 |
| Finished | Oct 15 07:39:44 PM UTC 24 |
| Peak memory | 627492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_buil d_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207255654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.207255654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.3373928325 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 6393509316 ps |
| CPU time | 618.5 seconds |
| Started | Oct 15 07:11:50 PM UTC 24 |
| Finished | Oct 15 07:22:16 PM UTC 24 |
| Peak memory | 627644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373928325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_sw_rstmgr_cpu_info.3373928325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1059104694 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 4685256032 ps |
| CPU time | 538.26 seconds |
| Started | Oct 15 06:49:35 PM UTC 24 |
| Finished | Oct 15 06:58:40 PM UTC 24 |
| Peak memory | 671912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059104694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr _cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.1059104694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.1761322176 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 2683978584 ps |
| CPU time | 269.8 seconds |
| Started | Oct 15 08:12:04 PM UTC 24 |
| Finished | Oct 15 08:16:38 PM UTC 24 |
| Peak memory | 625748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1761322176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_rstmgr_smoketest.1761322176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.4114708261 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 4555257720 ps |
| CPU time | 364.31 seconds |
| Started | Oct 15 07:09:30 PM UTC 24 |
| Finished | Oct 15 07:15:40 PM UTC 24 |
| Peak memory | 627440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=4114708261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_rstmgr_sw_req.4114708261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.3736940548 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 2698145662 ps |
| CPU time | 219.54 seconds |
| Started | Oct 15 07:09:34 PM UTC 24 |
| Finished | Oct 15 07:13:17 PM UTC 24 |
| Peak memory | 625488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3736940548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_rstmgr_sw_rst.3736940548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1677828760 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 2541571704 ps |
| CPU time | 353.27 seconds |
| Started | Oct 15 07:57:37 PM UTC 24 |
| Finished | Oct 15 08:03:36 PM UTC 24 |
| Peak memory | 627496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_im ages=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677828760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.1677828760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2281081810 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 3108651869 ps |
| CPU time | 284.7 seconds |
| Started | Oct 15 07:58:05 PM UTC 24 |
| Finished | Oct 15 08:02:54 PM UTC 24 |
| Peak memory | 625492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_inval idate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2281081810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.2281081810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1786334022 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 4392806536 ps |
| CPU time | 834.35 seconds |
| Started | Oct 15 07:23:17 PM UTC 24 |
| Finished | Oct 15 07:37:22 PM UTC 24 |
| Peak memory | 625312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786334022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.1786334022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.1792877466 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 5251241860 ps |
| CPU time | 983.79 seconds |
| Started | Oct 15 07:23:15 PM UTC 24 |
| Finished | Oct 15 07:39:52 PM UTC 24 |
| Peak memory | 627284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_b uild_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792877466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.1792877466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1191415073 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 4810957630 ps |
| CPU time | 558.99 seconds |
| Started | Oct 15 07:55:48 PM UTC 24 |
| Finished | Oct 15 08:05:14 PM UTC 24 |
| Peak memory | 641804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_han dler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191415073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_esc alation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.1191415073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.1287795861 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 7209746498 ps |
| CPU time | 519.88 seconds |
| Started | Oct 15 07:55:47 PM UTC 24 |
| Finished | Oct 15 08:04:34 PM UTC 24 |
| Peak memory | 637688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_acc ess_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287795861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wak eup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.1287795861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1412053827 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 4174938620 ps |
| CPU time | 424.42 seconds |
| Started | Oct 15 07:55:46 PM UTC 24 |
| Finished | Oct 15 08:02:56 PM UTC 24 |
| Peak memory | 640024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm _reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412053827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_re set_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asi c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1412053827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.1123257375 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 2970242236 ps |
| CPU time | 241.31 seconds |
| Started | Oct 15 08:12:04 PM UTC 24 |
| Finished | Oct 15 08:16:10 PM UTC 24 |
| Peak memory | 627544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=1123257375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_rv_plic_smoketest.1123257375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.1613063605 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 2413368222 ps |
| CPU time | 194.72 seconds |
| Started | Oct 15 07:14:06 PM UTC 24 |
| Finished | Oct 15 07:17:24 PM UTC 24 |
| Peak memory | 625736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1613063605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_rv_timer_irq.1613063605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.3258913538 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 3105336696 ps |
| CPU time | 244.3 seconds |
| Started | Oct 15 08:12:05 PM UTC 24 |
| Finished | Oct 15 08:16:13 PM UTC 24 |
| Peak memory | 625492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3258913538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_rv_timer_smoketest.3258913538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.2080133057 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 6558910290 ps |
| CPU time | 896.22 seconds |
| Started | Oct 15 07:41:47 PM UTC 24 |
| Finished | Oct 15 07:56:55 PM UTC 24 |
| Peak memory | 627548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080133057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.2080133057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.114670374 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 3203763034 ps |
| CPU time | 305.75 seconds |
| Started | Oct 15 07:41:46 PM UTC 24 |
| Finished | Oct 15 07:46:56 PM UTC 24 |
| Peak memory | 627740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114670374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_st atus_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.114670374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.1182738486 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 8894961440 ps |
| CPU time | 1159.63 seconds |
| Started | Oct 15 06:51:09 PM UTC 24 |
| Finished | Oct 15 07:10:44 PM UTC 24 |
| Peak memory | 627540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1182738486 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_sleep_pwm_pulses.1182738486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3907675690 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 8283638032 ps |
| CPU time | 752.47 seconds |
| Started | Oct 15 07:41:48 PM UTC 24 |
| Finished | Oct 15 07:54:30 PM UTC 24 |
| Peak memory | 627228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907675690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_sram_ret_contents _no_scramble.3907675690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3289199349 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 7748306990 ps |
| CPU time | 670.81 seconds |
| Started | Oct 15 07:41:41 PM UTC 24 |
| Finished | Oct 15 07:53:00 PM UTC 24 |
| Peak memory | 627364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289199349 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_sram_ret_contents_sc ramble.3289199349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.2666629280 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 7797278916 ps |
| CPU time | 840.68 seconds |
| Started | Oct 15 06:57:58 PM UTC 24 |
| Finished | Oct 15 07:12:10 PM UTC 24 |
| Peak memory | 642064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666629280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_spi_device_pass_through.2666629280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.2122556461 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 4536788951 ps |
| CPU time | 469.85 seconds |
| Started | Oct 15 06:58:24 PM UTC 24 |
| Finished | Oct 15 07:06:21 PM UTC 24 |
| Peak memory | 641836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122556461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.2122556461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.4159285579 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 3933231046 ps |
| CPU time | 342.08 seconds |
| Started | Oct 15 06:57:43 PM UTC 24 |
| Finished | Oct 15 07:03:30 PM UTC 24 |
| Peak memory | 637708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4159285579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_device_pinmux_sleep_retention.4159285579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_tpm.3989726753 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 2948503853 ps |
| CPU time | 365.47 seconds |
| Started | Oct 15 06:56:41 PM UTC 24 |
| Finished | Oct 15 07:02:51 PM UTC 24 |
| Peak memory | 637724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3989726753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_spi_device_tpm.3989726753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.45821946 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 2978929224 ps |
| CPU time | 342.99 seconds |
| Started | Oct 15 06:57:17 PM UTC 24 |
| Finished | Oct 15 07:03:05 PM UTC 24 |
| Peak memory | 625368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45821946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_spi_host_tx_rx.45821946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.687480618 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 9795938126 ps |
| CPU time | 803.71 seconds |
| Started | Oct 15 07:41:12 PM UTC 24 |
| Finished | Oct 15 07:54:46 PM UTC 24 |
| Peak memory | 627520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=687480618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.687480618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2989137688 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 5485580888 ps |
| CPU time | 761.1 seconds |
| Started | Oct 15 07:40:28 PM UTC 24 |
| Finished | Oct 15 07:53:20 PM UTC 24 |
| Peak memory | 627412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989137688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_ access.2989137688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2071431597 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 4072464371 ps |
| CPU time | 550.83 seconds |
| Started | Oct 15 07:41:12 PM UTC 24 |
| Finished | Oct 15 07:50:31 PM UTC 24 |
| Peak memory | 627624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_ch eck=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071431597 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ct rl_scrambled_access_jitter_en.2071431597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1025060055 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 5387396692 ps |
| CPU time | 452.72 seconds |
| Started | Oct 15 08:02:16 PM UTC 24 |
| Finished | Oct 15 08:09:55 PM UTC 24 |
| Peak memory | 627748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_r eady_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025060055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1025060055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.2972405902 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 2653113720 ps |
| CPU time | 233.89 seconds |
| Started | Oct 15 08:12:27 PM UTC 24 |
| Finished | Oct 15 08:16:24 PM UTC 24 |
| Peak memory | 625232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972405902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_sram_ctrl_smoketest.2972405902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1745929781 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 20004442772 ps |
| CPU time | 3233.29 seconds |
| Started | Oct 15 07:17:07 PM UTC 24 |
| Finished | Oct 15 08:11:40 PM UTC 24 |
| Peak memory | 627428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1745929781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.1745929781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2394557170 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 4473111333 ps |
| CPU time | 613.22 seconds |
| Started | Oct 15 07:16:03 PM UTC 24 |
| Finished | Oct 15 07:26:26 PM UTC 24 |
| Peak memory | 629948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2394557170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_sysrst_ctrl_in_irq.2394557170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2313284859 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 3253887641 ps |
| CPU time | 422.39 seconds |
| Started | Oct 15 07:14:55 PM UTC 24 |
| Finished | Oct 15 07:22:04 PM UTC 24 |
| Peak memory | 629848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2313284859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_sysrst_ctrl_inputs.2313284859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.601304583 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 3945438922 ps |
| CPU time | 420.57 seconds |
| Started | Oct 15 07:17:06 PM UTC 24 |
| Finished | Oct 15 07:24:13 PM UTC 24 |
| Peak memory | 625468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=601304583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_sysrst_ctrl_outputs.601304583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.862615812 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 23458428574 ps |
| CPU time | 1598.34 seconds |
| Started | Oct 15 07:16:20 PM UTC 24 |
| Finished | Oct 15 07:43:18 PM UTC 24 |
| Peak memory | 631904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_i mages=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862615812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.862615812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2758916261 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 5121786734 ps |
| CPU time | 410.64 seconds |
| Started | Oct 15 07:16:03 PM UTC 24 |
| Finished | Oct 15 07:23:00 PM UTC 24 |
| Peak memory | 627596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2758916261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2758916261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.4192235779 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 12538291270 ps |
| CPU time | 2575.62 seconds |
| Started | Oct 15 06:54:04 PM UTC 24 |
| Finished | Oct 15 07:37:32 PM UTC 24 |
| Peak memory | 641708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192235779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.4192235779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.189739072 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 2792509490 ps |
| CPU time | 242.87 seconds |
| Started | Oct 15 08:12:31 PM UTC 24 |
| Finished | Oct 15 08:16:38 PM UTC 24 |
| Peak memory | 625436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=189739072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_uart_smoketest.189739072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.2383306759 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 4172593350 ps |
| CPU time | 608.95 seconds |
| Started | Oct 15 06:52:40 PM UTC 24 |
| Finished | Oct 15 07:02:57 PM UTC 24 |
| Peak memory | 637788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383306759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.2383306759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2809927591 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 8364440532 ps |
| CPU time | 1612.9 seconds |
| Started | Oct 15 06:55:05 PM UTC 24 |
| Finished | Oct 15 07:22:18 PM UTC 24 |
| Peak memory | 637768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809927591 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_alt_clk_freq.2809927591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1572316313 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 80422914904 ps |
| CPU time | 16799.7 seconds |
| Started | Oct 15 06:53:58 PM UTC 24 |
| Finished | Oct 15 11:37:13 PM UTC 24 |
| Peak memory | 656816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout _ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572316313 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.1572316313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.2613145175 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 4716219056 ps |
| CPU time | 507.62 seconds |
| Started | Oct 15 06:52:40 PM UTC 24 |
| Finished | Oct 15 07:01:15 PM UTC 24 |
| Peak memory | 637532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613145175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.2613145175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.818377959 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 4606773426 ps |
| CPU time | 568.75 seconds |
| Started | Oct 15 06:53:59 PM UTC 24 |
| Finished | Oct 15 07:03:36 PM UTC 24 |
| Peak memory | 637800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818377959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.818377959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.934628392 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 4737631540 ps |
| CPU time | 695.22 seconds |
| Started | Oct 15 06:54:03 PM UTC 24 |
| Finished | Oct 15 07:05:47 PM UTC 24 |
| Peak memory | 637732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934628392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.934628392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.3264554698 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 3434508958 ps |
| CPU time | 220.85 seconds |
| Started | Oct 15 07:55:32 PM UTC 24 |
| Finished | Oct 15 07:59:16 PM UTC 24 |
| Peak memory | 641628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264554698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.3264554698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.3689432731 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 8664634170 ps |
| CPU time | 713.81 seconds |
| Started | Oct 15 07:55:59 PM UTC 24 |
| Finished | Oct 15 08:08:02 PM UTC 24 |
| Peak memory | 642080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689432731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.3689432731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.3245871870 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 3389176890 ps |
| CPU time | 268.25 seconds |
| Started | Oct 15 07:55:42 PM UTC 24 |
| Finished | Oct 15 08:00:14 PM UTC 24 |
| Peak memory | 642076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245871870 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.3245871870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_dev.1128343604 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 15524602677 ps |
| CPU time | 4150.51 seconds |
| Started | Oct 15 08:07:53 PM UTC 24 |
| Finished | Oct 15 09:17:53 PM UTC 24 |
| Peak memory | 630160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128343604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.1128343604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod.2055199326 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 16161223934 ps |
| CPU time | 4501.75 seconds |
| Started | Oct 15 08:08:05 PM UTC 24 |
| Finished | Oct 15 09:24:01 PM UTC 24 |
| Peak memory | 630176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055199326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.2055199326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod_end.2447408727 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 15665513264 ps |
| CPU time | 4568.75 seconds |
| Started | Oct 15 08:06:50 PM UTC 24 |
| Finished | Oct 15 09:23:56 PM UTC 24 |
| Peak memory | 629996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244740 8727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_in it_prod_end.2447408727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_rma.369540668 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 14871920056 ps |
| CPU time | 4534.52 seconds |
| Started | Oct 15 08:08:01 PM UTC 24 |
| Finished | Oct 15 09:24:31 PM UTC 24 |
| Peak memory | 630188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369540668 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.369540668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_test_unlocked0.27041677 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 11454954264 ps |
| CPU time | 3197.88 seconds |
| Started | Oct 15 08:07:47 PM UTC 24 |
| Finished | Oct 15 09:01:43 PM UTC 24 |
| Peak memory | 628480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=27041677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e _asm_init_test_unlocked0.27041677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3648390505 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 14897627942 ps |
| CPU time | 4307.43 seconds |
| Started | Oct 15 08:08:05 PM UTC 24 |
| Finished | Oct 15 09:20:45 PM UTC 24 |
| Peak memory | 627892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648390505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3648390505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1658037018 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 15164107876 ps |
| CPU time | 4290.74 seconds |
| Started | Oct 15 08:07:27 PM UTC 24 |
| Finished | Oct 15 09:19:49 PM UTC 24 |
| Peak memory | 628468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658037018 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.1658037018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3903774051 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 16105236516 ps |
| CPU time | 4297 seconds |
| Started | Oct 15 08:08:07 PM UTC 24 |
| Finished | Oct 15 09:20:38 PM UTC 24 |
| Peak memory | 627628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903774051 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_no_meas.3903774051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.3724466307 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 27644223412 ps |
| CPU time | 7762.23 seconds |
| Started | Oct 15 08:08:26 PM UTC 24 |
| Finished | Oct 15 10:19:24 PM UTC 24 |
| Peak memory | 628064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_rules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724466307 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.3724466307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_exception_c.3906639375 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 14688577319 ps |
| CPU time | 3918.94 seconds |
| Started | Oct 15 08:07:56 PM UTC 24 |
| Finished | Oct 15 09:14:02 PM UTC 24 |
| Peak memory | 630132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906639375 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_exception_c.3906639375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_output.3049723390 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 28559443500 ps |
| CPU time | 3749.97 seconds |
| Started | Oct 15 08:06:51 PM UTC 24 |
| Finished | Oct 15 09:10:05 PM UTC 24 |
| Peak memory | 629996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_flash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049723390 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.3049723390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_smoke.1744528226 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 15806753354 ps |
| CPU time | 4243.02 seconds |
| Started | Oct 15 08:05:14 PM UTC 24 |
| Finished | Oct 15 09:16:50 PM UTC 24 |
| Peak memory | 628036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744528226 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.1744528226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.rom_e2e_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_static_critical.3160851826 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 17663889938 ps |
| CPU time | 4907.81 seconds |
| Started | Oct 15 08:08:06 PM UTC 24 |
| Finished | Oct 15 09:30:54 PM UTC 24 |
| Peak memory | 630200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160851826 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.3160851826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.1513121105 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 4420065430 ps |
| CPU time | 587.55 seconds |
| Started | Oct 15 08:08:09 PM UTC 24 |
| Finished | Oct 15 08:18:04 PM UTC 24 |
| Peak memory | 627688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513121105 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 1.rom_keymgr_functest.1513121105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.rom_keymgr_functest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.404791742 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 6527853939 ps |
| CPU time | 284.96 seconds |
| Started | Oct 15 08:07:15 PM UTC 24 |
| Finished | Oct 15 08:12:05 PM UTC 24 |
| Peak memory | 637288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images =empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404791742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.404791742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.2225060695 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 2523339693 ps |
| CPU time | 156.67 seconds |
| Started | Oct 15 08:08:08 PM UTC 24 |
| Finished | Oct 15 08:10:48 PM UTC 24 |
| Peak memory | 637012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRa w +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot _flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2225060695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.2225060695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/1.rom_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.662945338 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 6058623200 ps |
| CPU time | 669.61 seconds |
| Started | Oct 15 10:13:12 PM UTC 24 |
| Finished | Oct 15 10:24:30 PM UTC 24 |
| Peak memory | 637988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662945338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.662945338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.1513640340 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 11210666113 ps |
| CPU time | 1096.81 seconds |
| Started | Oct 15 10:13:32 PM UTC 24 |
| Finished | Oct 15 10:32:04 PM UTC 24 |
| Peak memory | 641704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1513640340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 10.chip_sw_lc_ctrl_transition.1513640340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.3193090126 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 8732065240 ps |
| CPU time | 1563.76 seconds |
| Started | Oct 15 10:13:12 PM UTC 24 |
| Finished | Oct 15 10:39:36 PM UTC 24 |
| Peak memory | 641892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193090126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.3193090126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.2841289991 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 10183878993 ps |
| CPU time | 1044.26 seconds |
| Started | Oct 15 10:15:35 PM UTC 24 |
| Finished | Oct 15 10:33:14 PM UTC 24 |
| Peak memory | 642020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2841289991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 11.chip_sw_lc_ctrl_transition.2841289991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.59841402 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 4064587652 ps |
| CPU time | 561.25 seconds |
| Started | Oct 15 10:14:36 PM UTC 24 |
| Finished | Oct 15 10:24:05 PM UTC 24 |
| Peak memory | 641868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59841402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ua rt_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.59841402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2496514348 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 3434464456 ps |
| CPU time | 374.08 seconds |
| Started | Oct 15 10:18:13 PM UTC 24 |
| Finished | Oct 15 10:24:33 PM UTC 24 |
| Peak memory | 637876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496514348 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2496514348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.3727300257 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 5645285237 ps |
| CPU time | 406.9 seconds |
| Started | Oct 15 10:18:18 PM UTC 24 |
| Finished | Oct 15 10:25:11 PM UTC 24 |
| Peak memory | 641696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3727300257 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 12.chip_sw_lc_ctrl_transition.3727300257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.241259437 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 4286863356 ps |
| CPU time | 504.79 seconds |
| Started | Oct 15 10:17:34 PM UTC 24 |
| Finished | Oct 15 10:26:07 PM UTC 24 |
| Peak memory | 641828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241259437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.241259437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.990005011 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 12153899036 ps |
| CPU time | 1065.76 seconds |
| Started | Oct 15 10:20:24 PM UTC 24 |
| Finished | Oct 15 10:38:24 PM UTC 24 |
| Peak memory | 641956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=990005011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.chip_sw_lc_ctrl_transition.990005011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.1229689052 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 3387401728 ps |
| CPU time | 517.35 seconds |
| Started | Oct 15 10:18:42 PM UTC 24 |
| Finished | Oct 15 10:27:27 PM UTC 24 |
| Peak memory | 637796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229689052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.1229689052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.3508195654 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 5729419782 ps |
| CPU time | 475.47 seconds |
| Started | Oct 15 10:20:29 PM UTC 24 |
| Finished | Oct 15 10:28:32 PM UTC 24 |
| Peak memory | 641696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3508195654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 14.chip_sw_lc_ctrl_transition.3508195654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.2484842802 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 12933328672 ps |
| CPU time | 2657.69 seconds |
| Started | Oct 15 10:20:26 PM UTC 24 |
| Finished | Oct 15 11:05:16 PM UTC 24 |
| Peak memory | 641888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484842802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.2484842802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.1577237869 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 8265202430 ps |
| CPU time | 1500.06 seconds |
| Started | Oct 15 10:21:45 PM UTC 24 |
| Finished | Oct 15 10:47:04 PM UTC 24 |
| Peak memory | 641636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577237869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.1577237869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.568638360 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 3940581928 ps |
| CPU time | 523.98 seconds |
| Started | Oct 15 10:23:59 PM UTC 24 |
| Finished | Oct 15 10:32:51 PM UTC 24 |
| Peak memory | 637800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568638360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.568638360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.1671695160 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 4120638168 ps |
| CPU time | 609.49 seconds |
| Started | Oct 15 10:25:23 PM UTC 24 |
| Finished | Oct 15 10:35:41 PM UTC 24 |
| Peak memory | 641768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671695160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.1671695160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1989527254 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 4045619400 ps |
| CPU time | 386.28 seconds |
| Started | Oct 15 10:27:00 PM UTC 24 |
| Finished | Oct 15 10:33:32 PM UTC 24 |
| Peak memory | 673644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989527254 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1989527254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.2595303033 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 4195585880 ps |
| CPU time | 520.95 seconds |
| Started | Oct 15 10:26:03 PM UTC 24 |
| Finished | Oct 15 10:34:51 PM UTC 24 |
| Peak memory | 675932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595303033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.2595303033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.4155589068 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 13042370728 ps |
| CPU time | 2649.64 seconds |
| Started | Oct 15 10:26:04 PM UTC 24 |
| Finished | Oct 15 11:10:46 PM UTC 24 |
| Peak memory | 637760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155589068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.4155589068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.591363062 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 3182026744 ps |
| CPU time | 388.7 seconds |
| Started | Oct 15 10:28:12 PM UTC 24 |
| Finished | Oct 15 10:34:47 PM UTC 24 |
| Peak memory | 673656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591363062 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_alert_handler_lpg_s leep_mode_alerts.591363062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.4197381152 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 8686170586 ps |
| CPU time | 1317.85 seconds |
| Started | Oct 15 10:27:20 PM UTC 24 |
| Finished | Oct 15 10:49:35 PM UTC 24 |
| Peak memory | 641636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197381152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.4197381152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.1927605377 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 4037355099 ps |
| CPU time | 282.81 seconds |
| Started | Oct 15 09:24:28 PM UTC 24 |
| Finished | Oct 15 09:29:14 PM UTC 24 |
| Peak memory | 624784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192760 5377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_csr_rw.1927605377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_mem_access.2349170880 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 13324969756 ps |
| CPU time | 998.75 seconds |
| Started | Oct 15 09:24:36 PM UTC 24 |
| Finished | Oct 15 09:41:28 PM UTC 24 |
| Peak memory | 625036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349170880 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.2349170880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_jtag_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_rv_dm_ndm_reset_req.1965324213 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 5363032084 ps |
| CPU time | 516.25 seconds |
| Started | Oct 15 09:28:06 PM UTC 24 |
| Finished | Oct 15 09:36:49 PM UTC 24 |
| Peak memory | 639676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965324213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_ reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.1965324213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.3239326631 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 2737796768 ps |
| CPU time | 267.5 seconds |
| Started | Oct 15 08:14:20 PM UTC 24 |
| Finished | Oct 15 08:18:52 PM UTC 24 |
| Peak memory | 627756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim _dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239326631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.3239326631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sival_flash_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2374309467 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 19002559604 ps |
| CPU time | 623.81 seconds |
| Started | Oct 15 08:50:10 PM UTC 24 |
| Finished | Oct 15 09:00:43 PM UTC 24 |
| Peak memory | 637532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374309467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/c hip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2374309467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc.1334553023 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 3223697832 ps |
| CPU time | 238.16 seconds |
| Started | Oct 15 08:54:05 PM UTC 24 |
| Finished | Oct 15 08:58:07 PM UTC 24 |
| Peak memory | 625544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_i mages=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334553023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.1334553023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en.2543159552 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 2449053645 ps |
| CPU time | 268.3 seconds |
| Started | Oct 15 08:54:09 PM UTC 24 |
| Finished | Oct 15 08:58:42 PM UTC 24 |
| Peak memory | 627752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543159552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.2543159552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3535010652 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 3181204734 ps |
| CPU time | 237.47 seconds |
| Started | Oct 15 09:33:33 PM UTC 24 |
| Finished | Oct 15 09:37:34 PM UTC 24 |
| Peak memory | 627720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535010652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.3535010652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_entropy.910450109 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 2759801112 ps |
| CPU time | 319.53 seconds |
| Started | Oct 15 09:00:27 PM UTC 24 |
| Finished | Oct 15 09:05:52 PM UTC 24 |
| Peak memory | 627692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910450109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_aes_entropy.910450109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_idle.1138139091 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 2780589500 ps |
| CPU time | 348.45 seconds |
| Started | Oct 15 08:54:46 PM UTC 24 |
| Finished | Oct 15 09:00:40 PM UTC 24 |
| Peak memory | 627284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138139091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.1138139091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_masking_off.1800968401 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 3203655046 ps |
| CPU time | 384.01 seconds |
| Started | Oct 15 08:56:31 PM UTC 24 |
| Finished | Oct 15 09:03:01 PM UTC 24 |
| Peak memory | 625236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800968401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_aes_masking_off.1800968401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_masking_off/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_smoketest.2500997072 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 3255358376 ps |
| CPU time | 281.01 seconds |
| Started | Oct 15 09:39:59 PM UTC 24 |
| Finished | Oct 15 09:44:44 PM UTC 24 |
| Peak memory | 625636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2500997072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_a es_smoketest.2500997072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_entropy.2000044016 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3468338680 ps |
| CPU time | 350.83 seconds |
| Started | Oct 15 09:00:27 PM UTC 24 |
| Finished | Oct 15 09:06:24 PM UTC 24 |
| Peak memory | 627420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000044016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.2000044016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_escalation.3382316397 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 5429585020 ps |
| CPU time | 542.57 seconds |
| Started | Oct 15 08:57:36 PM UTC 24 |
| Finished | Oct 15 09:06:46 PM UTC 24 |
| Peak memory | 639516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382316397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_ earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.3382316397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3159055839 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 7265416300 ps |
| CPU time | 1499.79 seconds |
| Started | Oct 15 09:00:24 PM UTC 24 |
| Finished | Oct 15 09:25:44 PM UTC 24 |
| Peak memory | 627440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159055839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_ea rlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.3159055839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3961357005 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 7682310492 ps |
| CPU time | 1488.5 seconds |
| Started | Oct 15 09:00:22 PM UTC 24 |
| Finished | Oct 15 09:25:29 PM UTC 24 |
| Peak memory | 627432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961357005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_toggle.3961357005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.242435470 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 10356262956 ps |
| CPU time | 1000.39 seconds |
| Started | Oct 15 08:59:59 PM UTC 24 |
| Finished | Oct 15 09:16:52 PM UTC 24 |
| Peak memory | 627400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242435470 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handl er_lpg_sleep_mode_pings.242435470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_ok.3348929296 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 7619036280 ps |
| CPU time | 1457.09 seconds |
| Started | Oct 15 08:59:35 PM UTC 24 |
| Finished | Oct 15 09:24:11 PM UTC 24 |
| Peak memory | 627284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348929296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.3348929296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_timeout.697010080 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 3783807188 ps |
| CPU time | 422.18 seconds |
| Started | Oct 15 08:59:22 PM UTC 24 |
| Finished | Oct 15 09:06:30 PM UTC 24 |
| Peak memory | 627536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697010080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.697010080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1286656110 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 254456531208 ps |
| CPU time | 12238.5 seconds |
| Started | Oct 15 08:59:19 PM UTC 24 |
| Finished | Oct 16 12:25:25 AM UTC 24 |
| Peak memory | 630036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=s im_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286656110 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1286656110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_test.719085772 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 3042041772 ps |
| CPU time | 365.98 seconds |
| Started | Oct 15 08:57:23 PM UTC 24 |
| Finished | Oct 15 09:03:34 PM UTC 24 |
| Peak memory | 625468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand om_seed=719085772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert _test.719085772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.1096858357 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 5792603866 ps |
| CPU time | 580.63 seconds |
| Started | Oct 15 08:14:54 PM UTC 24 |
| Finished | Oct 15 08:24:42 PM UTC 24 |
| Peak memory | 639776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096858357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.1096858357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.548766947 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 3702496600 ps |
| CPU time | 337.96 seconds |
| Started | Oct 15 08:47:45 PM UTC 24 |
| Finished | Oct 15 08:53:28 PM UTC 24 |
| Peak memory | 625372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548766947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_aon_timer_irq.548766947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3525129185 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 8005860440 ps |
| CPU time | 639.83 seconds |
| Started | Oct 15 08:48:30 PM UTC 24 |
| Finished | Oct 15 08:59:18 PM UTC 24 |
| Peak memory | 627524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525129185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3525129185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_smoketest.661682894 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 2948182372 ps |
| CPU time | 306.78 seconds |
| Started | Oct 15 09:39:56 PM UTC 24 |
| Finished | Oct 15 09:45:07 PM UTC 24 |
| Peak memory | 625496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661682894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_aon_timer_smoketest.661682894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2678949716 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 6819496100 ps |
| CPU time | 722.17 seconds |
| Started | Oct 15 08:48:31 PM UTC 24 |
| Finished | Oct 15 09:00:43 PM UTC 24 |
| Peak memory | 627512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678949716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.2678949716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1492880976 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 5218532958 ps |
| CPU time | 533.45 seconds |
| Started | Oct 15 08:49:48 PM UTC 24 |
| Finished | Oct 15 08:58:48 PM UTC 24 |
| Peak memory | 627296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492880976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.1492880976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_outputs.1625357045 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 7162901024 ps |
| CPU time | 973.75 seconds |
| Started | Oct 15 09:25:13 PM UTC 24 |
| Finished | Oct 15 09:41:40 PM UTC 24 |
| Peak memory | 633704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_ clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h w/dv/tools/sim.tcl +ntb_random_seed=1625357045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.1625357045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_rst_inputs.602297410 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 25321085272 ps |
| CPU time | 4210.03 seconds |
| Started | Oct 15 09:35:11 PM UTC 24 |
| Finished | Oct 15 10:46:12 PM UTC 24 |
| Peak memory | 629964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_ images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602297410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.602297410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1142384897 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 5821705403 ps |
| CPU time | 548.89 seconds |
| Started | Oct 15 09:22:07 PM UTC 24 |
| Finished | Oct 15 09:31:24 PM UTC 24 |
| Peak memory | 642088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_de vice=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142384897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.1142384897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3266644917 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 3691840144 ps |
| CPU time | 616.72 seconds |
| Started | Oct 15 09:22:36 PM UTC 24 |
| Finished | Oct 15 09:33:01 PM UTC 24 |
| Peak memory | 629420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266644917 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_dev.3266644917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.111812432 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 3923045260 ps |
| CPU time | 556.37 seconds |
| Started | Oct 15 09:22:40 PM UTC 24 |
| Finished | Oct 15 09:32:04 PM UTC 24 |
| Peak memory | 629592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111812432 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src _for_sw_fast_rma.111812432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3151320041 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 3554177860 ps |
| CPU time | 546.86 seconds |
| Started | Oct 15 09:22:31 PM UTC 24 |
| Finished | Oct 15 09:31:46 PM UTC 24 |
| Peak memory | 629776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315 1320041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_exter nal_clk_src_for_sw_fast_test_unlocked0.3151320041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4144677554 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 4179703352 ps |
| CPU time | 551.96 seconds |
| Started | Oct 15 09:22:19 PM UTC 24 |
| Finished | Oct 15 09:31:39 PM UTC 24 |
| Peak memory | 629408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144677554 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_dev.4144677554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2535815288 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 4598024688 ps |
| CPU time | 585.58 seconds |
| Started | Oct 15 09:22:40 PM UTC 24 |
| Finished | Oct 15 09:32:33 PM UTC 24 |
| Peak memory | 629516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535815288 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_rma.2535815288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3138252700 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 5339148560 ps |
| CPU time | 554.29 seconds |
| Started | Oct 15 09:22:37 PM UTC 24 |
| Finished | Oct 15 09:31:59 PM UTC 24 |
| Peak memory | 629720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313 8252700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_exter nal_clk_src_for_sw_slow_test_unlocked0.3138252700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter.998437282 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 2796595605 ps |
| CPU time | 255.64 seconds |
| Started | Oct 15 09:24:14 PM UTC 24 |
| Finished | Oct 15 09:28:34 PM UTC 24 |
| Peak memory | 625492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=998437282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_clkmgr_jitter.998437282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2795902542 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 3848020632 ps |
| CPU time | 489.69 seconds |
| Started | Oct 15 09:23:18 PM UTC 24 |
| Finished | Oct 15 09:31:35 PM UTC 24 |
| Peak memory | 627288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=2795902542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_clkmgr_jitter_frequency.2795902542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.1149762103 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 3222113979 ps |
| CPU time | 168.86 seconds |
| Started | Oct 15 09:32:48 PM UTC 24 |
| Finished | Oct 15 09:35:40 PM UTC 24 |
| Peak memory | 627800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkm gr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1149762103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.1149762103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1814044314 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 4183115648 ps |
| CPU time | 431.97 seconds |
| Started | Oct 15 09:19:08 PM UTC 24 |
| Finished | Oct 15 09:26:26 PM UTC 24 |
| Peak memory | 627500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1814044314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.1814044314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3892064427 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 5375647994 ps |
| CPU time | 375.85 seconds |
| Started | Oct 15 09:19:07 PM UTC 24 |
| Finished | Oct 15 09:25:28 PM UTC 24 |
| Peak memory | 627668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3892064427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_clkmgr_off_hmac_trans.3892064427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.827045481 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 4427778272 ps |
| CPU time | 514.41 seconds |
| Started | Oct 15 09:20:30 PM UTC 24 |
| Finished | Oct 15 09:29:11 PM UTC 24 |
| Peak memory | 625500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=827045481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.827045481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3983885698 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 4914481656 ps |
| CPU time | 452.6 seconds |
| Started | Oct 15 09:22:17 PM UTC 24 |
| Finished | Oct 15 09:29:57 PM UTC 24 |
| Peak memory | 627516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3983885698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_clkmgr_off_otbn_trans.3983885698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_peri.2355394829 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 10671334626 ps |
| CPU time | 1088.19 seconds |
| Started | Oct 15 09:19:04 PM UTC 24 |
| Finished | Oct 15 09:37:26 PM UTC 24 |
| Peak memory | 627452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_i mages=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355394829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.2355394829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_reset_frequency.1090995423 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 3953100708 ps |
| CPU time | 494.18 seconds |
| Started | Oct 15 09:22:55 PM UTC 24 |
| Finished | Oct 15 09:31:16 PM UTC 24 |
| Peak memory | 627296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090995423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.1090995423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3713948030 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 4478525504 ps |
| CPU time | 596.17 seconds |
| Started | Oct 15 09:24:36 PM UTC 24 |
| Finished | Oct 15 09:34:40 PM UTC 24 |
| Peak memory | 627436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713948030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.3713948030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_smoketest.591592760 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 2699968360 ps |
| CPU time | 339.68 seconds |
| Started | Oct 15 09:40:27 PM UTC 24 |
| Finished | Oct 15 09:46:12 PM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=591592760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _clkmgr_smoketest.591592760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.1405776325 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 31665143288 ps |
| CPU time | 8473.07 seconds |
| Started | Oct 15 09:04:09 PM UTC 24 |
| Finished | Oct 15 11:27:02 PM UTC 24 |
| Peak memory | 630180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1405776325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 2.chip_sw_csrng_edn_concurrency.1405776325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3482463737 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 9173251127 ps |
| CPU time | 1639.18 seconds |
| Started | Oct 15 09:35:55 PM UTC 24 |
| Finished | Oct 15 10:03:35 PM UTC 24 |
| Peak memory | 627572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accele rate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482463737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_b ase_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.3482463737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1036937769 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 4298936620 ps |
| CPU time | 425.5 seconds |
| Started | Oct 15 09:04:11 PM UTC 24 |
| Finished | Oct 15 09:11:22 PM UTC 24 |
| Peak memory | 627424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036937769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src _fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.1036937769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_kat_test.583119950 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 2306305668 ps |
| CPU time | 223.18 seconds |
| Started | Oct 15 09:03:58 PM UTC 24 |
| Finished | Oct 15 09:07:45 PM UTC 24 |
| Peak memory | 627284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=583119950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.583119950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1517341959 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 6134007000 ps |
| CPU time | 700.26 seconds |
| Started | Oct 15 09:03:53 PM UTC 24 |
| Finished | Oct 15 09:15:43 PM UTC 24 |
| Peak memory | 627816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_ otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517341959 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_lc_hw_debug_en_test.1517341959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_smoketest.3567051528 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 2041166140 ps |
| CPU time | 218.39 seconds |
| Started | Oct 15 09:40:30 PM UTC 24 |
| Finished | Oct 15 09:44:12 PM UTC 24 |
| Peak memory | 625436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3567051528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _csrng_smoketest.3567051528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.104767758 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 4986374184 ps |
| CPU time | 726.64 seconds |
| Started | Oct 15 08:16:17 PM UTC 24 |
| Finished | Oct 15 08:28:34 PM UTC 24 |
| Peak memory | 627780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104767758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.104767758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_auto_mode.268039972 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 4413721864 ps |
| CPU time | 959.93 seconds |
| Started | Oct 15 09:01:44 PM UTC 24 |
| Finished | Oct 15 09:17:57 PM UTC 24 |
| Peak memory | 625436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_ device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268039972 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_auto_mode.268039972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_boot_mode.2598162597 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 2952486360 ps |
| CPU time | 499.67 seconds |
| Started | Oct 15 09:01:44 PM UTC 24 |
| Finished | Oct 15 09:10:11 PM UTC 24 |
| Peak memory | 625556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_ device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598162597 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_boot_mode.2598162597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs.1776418472 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 6873783876 ps |
| CPU time | 1221.07 seconds |
| Started | Oct 15 09:06:32 PM UTC 24 |
| Finished | Oct 15 09:27:09 PM UTC 24 |
| Peak memory | 627624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776418472 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.1776418472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1929913340 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 7255102125 ps |
| CPU time | 1091.38 seconds |
| Started | Oct 15 09:06:45 PM UTC 24 |
| Finished | Oct 15 09:25:11 PM UTC 24 |
| Peak memory | 627672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929913340 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.1929913340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_kat.3462120979 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 3154815360 ps |
| CPU time | 525.26 seconds |
| Started | Oct 15 09:01:44 PM UTC 24 |
| Finished | Oct 15 09:10:37 PM UTC 24 |
| Peak memory | 631540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_a ssert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=3462120979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_edn_kat.3462120979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_kat/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_sw_mode.4118054792 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 9481483140 ps |
| CPU time | 2013.63 seconds |
| Started | Oct 15 09:02:24 PM UTC 24 |
| Finished | Oct 15 09:36:23 PM UTC 24 |
| Peak memory | 627284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=4118054792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_edn_sw_mode.4118054792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1892876902 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 2457830184 ps |
| CPU time | 197.66 seconds |
| Started | Oct 15 09:04:15 PM UTC 24 |
| Finished | Oct 15 09:07:36 PM UTC 24 |
| Peak memory | 625476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892876902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.1892876902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.2898480671 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 7983317520 ps |
| CPU time | 1811.14 seconds |
| Started | Oct 15 09:04:54 PM UTC 24 |
| Finished | Oct 15 09:35:28 PM UTC 24 |
| Peak memory | 625856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_ srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898480671 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.2898480671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_kat_test.2435125418 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 2647350680 ps |
| CPU time | 210.11 seconds |
| Started | Oct 15 09:00:41 PM UTC 24 |
| Finished | Oct 15 09:04:14 PM UTC 24 |
| Peak memory | 625240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435125418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.2435125418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_smoketest.2220271027 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 3697818766 ps |
| CPU time | 578.29 seconds |
| Started | Oct 15 09:42:17 PM UTC 24 |
| Finished | Oct 15 09:52:04 PM UTC 24 |
| Peak memory | 627640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_de vice=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220271027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.2220271027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.574848705 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 2832072664 ps |
| CPU time | 252.34 seconds |
| Started | Oct 15 08:14:06 PM UTC 24 |
| Finished | Oct 15 08:18:22 PM UTC 24 |
| Peak memory | 627820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=574848705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_example_concurrency.574848705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_example_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.2920278134 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 2779571128 ps |
| CPU time | 215.43 seconds |
| Started | Oct 15 08:12:47 PM UTC 24 |
| Finished | Oct 15 08:16:26 PM UTC 24 |
| Peak memory | 625240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2920278134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_example_flash.2920278134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_example_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.2232652260 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 2055773236 ps |
| CPU time | 235.89 seconds |
| Started | Oct 15 08:13:16 PM UTC 24 |
| Finished | Oct 15 08:17:16 PM UTC 24 |
| Peak memory | 625400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2232652260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ex ample_manufacturer.2232652260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_example_manufacturer/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.453108895 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 3013430860 ps |
| CPU time | 157.22 seconds |
| Started | Oct 15 08:12:48 PM UTC 24 |
| Finished | Oct 15 08:15:28 PM UTC 24 |
| Peak memory | 626964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:t est_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=453108895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_sw_example_rom.453108895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_example_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1010203851 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 61542809060 ps |
| CPU time | 12347.1 seconds |
| Started | Oct 15 08:19:17 PM UTC 24 |
| Finished | Oct 15 11:47:26 PM UTC 24 |
| Peak memory | 644500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw _build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010203851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.1010203851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_crash_alert.459142630 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 4688061352 ps |
| CPU time | 433.56 seconds |
| Started | Oct 15 09:32:25 PM UTC 24 |
| Finished | Oct 15 09:39:44 PM UTC 24 |
| Peak memory | 627508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check= 1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459142630 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.459142630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access.2777416890 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 5384512112 ps |
| CPU time | 925.34 seconds |
| Started | Oct 15 08:27:00 PM UTC 24 |
| Finished | Oct 15 08:42:38 PM UTC 24 |
| Peak memory | 625248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2777416890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _flash_ctrl_access.2777416890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.268245474 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 5832568623 ps |
| CPU time | 1015.42 seconds |
| Started | Oct 15 08:27:55 PM UTC 24 |
| Finished | Oct 15 08:45:05 PM UTC 24 |
| Peak memory | 627276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=268245474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_flash_ctrl_access_jitter_en.268245474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.988814062 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 7654132027 ps |
| CPU time | 1139.42 seconds |
| Started | Oct 15 09:33:35 PM UTC 24 |
| Finished | Oct 15 09:52:50 PM UTC 24 |
| Peak memory | 627292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988814062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.988814062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1141728656 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 6291848657 ps |
| CPU time | 989.88 seconds |
| Started | Oct 15 08:29:46 PM UTC 24 |
| Finished | Oct 15 08:46:28 PM UTC 24 |
| Peak memory | 625484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=1141728656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_flash_ctrl_clock_freqs.1141728656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1520793238 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 3561298348 ps |
| CPU time | 381.43 seconds |
| Started | Oct 15 08:28:35 PM UTC 24 |
| Finished | Oct 15 08:35:02 PM UTC 24 |
| Peak memory | 627288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1520793238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_flash_ctrl_idle_low_power.1520793238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1745021381 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 5327222444 ps |
| CPU time | 458.05 seconds |
| Started | Oct 15 08:26:59 PM UTC 24 |
| Finished | Oct 15 08:34:44 PM UTC 24 |
| Peak memory | 627736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745021381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ct rl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.1745021381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2410507854 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 6162698570 ps |
| CPU time | 1197.35 seconds |
| Started | Oct 15 09:36:25 PM UTC 24 |
| Finished | Oct 15 09:56:38 PM UTC 24 |
| Peak memory | 625544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2410507854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_flash_ctrl_mem_protection.2410507854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops.3917617988 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 3702597650 ps |
| CPU time | 576.51 seconds |
| Started | Oct 15 08:25:40 PM UTC 24 |
| Finished | Oct 15 08:35:24 PM UTC 24 |
| Peak memory | 627284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917617988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.3917617988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2581442935 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 4345967805 ps |
| CPU time | 750.13 seconds |
| Started | Oct 15 08:26:08 PM UTC 24 |
| Finished | Oct 15 08:38:48 PM UTC 24 |
| Peak memory | 627544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581442935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.2581442935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1834298338 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 4604149299 ps |
| CPU time | 788.35 seconds |
| Started | Oct 15 09:33:35 PM UTC 24 |
| Finished | Oct 15 09:46:54 PM UTC 24 |
| Peak memory | 627396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834298338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1834298338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_write_clear.2334544197 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 3607070288 ps |
| CPU time | 275.4 seconds |
| Started | Oct 15 09:34:58 PM UTC 24 |
| Finished | Oct 15 09:39:38 PM UTC 24 |
| Peak memory | 625372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_image s=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334544197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.2334544197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init.2185495789 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 20598006752 ps |
| CPU time | 2287.29 seconds |
| Started | Oct 15 08:29:09 PM UTC 24 |
| Finished | Oct 15 09:07:46 PM UTC 24 |
| Peak memory | 629484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185495789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_flash_init.2185495789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_init/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.4020269557 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 22453655243 ps |
| CPU time | 1826.39 seconds |
| Started | Oct 15 09:35:00 PM UTC 24 |
| Finished | Oct 15 10:05:49 PM UTC 24 |
| Peak memory | 633692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_buil d_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020269557 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.4020269557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_scrambling_smoketest.4025495220 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 2436292912 ps |
| CPU time | 224.27 seconds |
| Started | Oct 15 09:38:26 PM UTC 24 |
| Finished | Oct 15 09:42:14 PM UTC 24 |
| Peak memory | 625392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_ima ges=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoketest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025495220 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.4025495220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio_smoketest.3946220750 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 2816232778 ps |
| CPU time | 353.63 seconds |
| Started | Oct 15 09:42:20 PM UTC 24 |
| Finished | Oct 15 09:48:19 PM UTC 24 |
| Peak memory | 625756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3946220750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_sw_gpio_smoketest.3946220750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc.2788975551 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 2420286928 ps |
| CPU time | 247.48 seconds |
| Started | Oct 15 09:06:48 PM UTC 24 |
| Finished | Oct 15 09:11:00 PM UTC 24 |
| Peak memory | 625488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2788975551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_h mac_enc.2788975551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_idle.45925146 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 3055969358 ps |
| CPU time | 238.35 seconds |
| Started | Oct 15 09:07:22 PM UTC 24 |
| Finished | Oct 15 09:11:25 PM UTC 24 |
| Peak memory | 625452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=45925146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_hmac_enc_idle.45925146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en.3792938360 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 2636103328 ps |
| CPU time | 247.41 seconds |
| Started | Oct 15 09:07:12 PM UTC 24 |
| Finished | Oct 15 09:11:23 PM UTC 24 |
| Peak memory | 625448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3792938360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_hmac_enc_jitter_en.3792938360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3394699948 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 2625199877 ps |
| CPU time | 190.63 seconds |
| Started | Oct 15 09:35:25 PM UTC 24 |
| Finished | Oct 15 09:38:39 PM UTC 24 |
| Peak memory | 625460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394699948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.3394699948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_multistream.2888486657 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 7181575768 ps |
| CPU time | 1644.82 seconds |
| Started | Oct 15 09:09:04 PM UTC 24 |
| Finished | Oct 15 09:36:50 PM UTC 24 |
| Peak memory | 625512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2888486657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_multistream.2888486657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_multistream/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_oneshot.1071028619 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 3111457240 ps |
| CPU time | 312.08 seconds |
| Started | Oct 15 09:07:26 PM UTC 24 |
| Finished | Oct 15 09:12:43 PM UTC 24 |
| Peak memory | 625496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1071028619 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_h mac_oneshot.1071028619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_smoketest.360450667 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 3371608960 ps |
| CPU time | 394.52 seconds |
| Started | Oct 15 09:43:24 PM UTC 24 |
| Finished | Oct 15 09:50:04 PM UTC 24 |
| Peak memory | 625728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=360450667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_h mac_smoketest.360450667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx.1181184083 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 4534263064 ps |
| CPU time | 852.68 seconds |
| Started | Oct 15 08:20:36 PM UTC 24 |
| Finished | Oct 15 08:35:00 PM UTC 24 |
| Peak memory | 627564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1181184083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_i2c_host_tx_rx.1181184083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.4186710271 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 5267832108 ps |
| CPU time | 807.21 seconds |
| Started | Oct 15 08:20:07 PM UTC 24 |
| Finished | Oct 15 08:33:45 PM UTC 24 |
| Peak memory | 625428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=4186710271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.4186710271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3075111012 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 5134494384 ps |
| CPU time | 792.07 seconds |
| Started | Oct 15 08:20:36 PM UTC 24 |
| Finished | Oct 15 08:33:59 PM UTC 24 |
| Peak memory | 625532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3075111012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.3075111012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.2832748041 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 66364218578 ps |
| CPU time | 13512.4 seconds |
| Started | Oct 15 08:19:39 PM UTC 24 |
| Finished | Oct 16 12:07:29 AM UTC 24 |
| Peak memory | 644528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=1 50_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832748041 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.2832748041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_aes.3606728524 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 10792577848 ps |
| CPU time | 2362.11 seconds |
| Started | Oct 15 09:10:58 PM UTC 24 |
| Finished | Oct 15 09:50:50 PM UTC 24 |
| Peak memory | 627700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606728524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sidel oad_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.3606728524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_kmac.936579708 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 10185259878 ps |
| CPU time | 1669.08 seconds |
| Started | Oct 15 09:09:09 PM UTC 24 |
| Finished | Oct 15 09:37:18 PM UTC 24 |
| Peak memory | 627516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936579708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sidel oad_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.936579708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.2908727821 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 16007685384 ps |
| CPU time | 4464.73 seconds |
| Started | Oct 15 09:10:59 PM UTC 24 |
| Finished | Oct 15 10:26:19 PM UTC 24 |
| Peak memory | 630028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908727821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.2908727821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_app_rom.3641143767 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 2540263270 ps |
| CPU time | 256.07 seconds |
| Started | Oct 15 09:12:44 PM UTC 24 |
| Finished | Oct 15 09:17:04 PM UTC 24 |
| Peak memory | 625244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=3641143767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_kmac_app_rom.3641143767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_entropy.3991144749 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 2387083472 ps |
| CPU time | 230.52 seconds |
| Started | Oct 15 08:29:43 PM UTC 24 |
| Finished | Oct 15 08:33:37 PM UTC 24 |
| Peak memory | 625416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=3991144749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_kmac_entropy.3991144749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_idle.415536528 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 2874099346 ps |
| CPU time | 258.51 seconds |
| Started | Oct 15 09:12:40 PM UTC 24 |
| Finished | Oct 15 09:17:03 PM UTC 24 |
| Peak memory | 625420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=415536528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_k mac_idle.415536528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_cshake.1243494175 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 2102586128 ps |
| CPU time | 205.49 seconds |
| Started | Oct 15 09:11:11 PM UTC 24 |
| Finished | Oct 15 09:14:40 PM UTC 24 |
| Peak memory | 625272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1243494175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_sw_kmac_mode_cshake.1243494175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac.3640757634 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 3078211456 ps |
| CPU time | 332.33 seconds |
| Started | Oct 15 09:11:39 PM UTC 24 |
| Finished | Oct 15 09:17:16 PM UTC 24 |
| Peak memory | 625244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640757634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_kmac_mode_kmac.3640757634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1724901543 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 2812375896 ps |
| CPU time | 330.18 seconds |
| Started | Oct 15 09:12:40 PM UTC 24 |
| Finished | Oct 15 09:18:15 PM UTC 24 |
| Peak memory | 627464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_km ac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1724901543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.1724901543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3692209618 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 3890206239 ps |
| CPU time | 348.36 seconds |
| Started | Oct 15 09:36:37 PM UTC 24 |
| Finished | Oct 15 09:42:31 PM UTC 24 |
| Peak memory | 625560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692209618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3692209618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_smoketest.3102411752 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 2578315500 ps |
| CPU time | 295.44 seconds |
| Started | Oct 15 09:43:25 PM UTC 24 |
| Finished | Oct 15 09:48:25 PM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3102411752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ kmac_smoketest.3102411752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.698810513 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 3426346576 ps |
| CPU time | 335.08 seconds |
| Started | Oct 15 08:29:47 PM UTC 24 |
| Finished | Oct 15 08:35:27 PM UTC 24 |
| Peak memory | 625240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=698810513 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_lc_ctrl_otp_hw_cfg0.698810513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_program_error.149268452 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 5426826600 ps |
| CPU time | 443.51 seconds |
| Started | Oct 15 09:25:49 PM UTC 24 |
| Finished | Oct 15 09:33:19 PM UTC 24 |
| Peak memory | 627444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149268452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc _ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asi c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.149268452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3190372291 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 3169554437 ps |
| CPU time | 325.92 seconds |
| Started | Oct 15 08:34:52 PM UTC 24 |
| Finished | Oct 15 08:40:23 PM UTC 24 |
| Peak memory | 639728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190372291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.3190372291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_transition.2835964273 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 6883003778 ps |
| CPU time | 614.15 seconds |
| Started | Oct 15 08:34:49 PM UTC 24 |
| Finished | Oct 15 08:45:11 PM UTC 24 |
| Peak memory | 642060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2835964273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_lc_ctrl_transition.2835964273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3210524471 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 2694037406 ps |
| CPU time | 114.63 seconds |
| Started | Oct 15 08:36:30 PM UTC 24 |
| Finished | Oct 15 08:38:27 PM UTC 24 |
| Peak memory | 635144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210524471 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.3210524471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2668242039 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 2272898507 ps |
| CPU time | 160.33 seconds |
| Started | Oct 15 08:36:52 PM UTC 24 |
| Finished | Oct 15 08:39:35 PM UTC 24 |
| Peak memory | 637384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSo urceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26682420 39 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc _ctrl_volatile_raw_unlock_ext_clk_48mhz.2668242039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.2796502384 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 46929011893 ps |
| CPU time | 7210.7 seconds |
| Started | Oct 15 08:34:51 PM UTC 24 |
| Finished | Oct 15 10:36:31 PM UTC 24 |
| Peak memory | 644600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796502384 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_dev.2796502384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.4213252659 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 50529705420 ps |
| CPU time | 5995.28 seconds |
| Started | Oct 15 08:35:02 PM UTC 24 |
| Finished | Oct 15 10:16:09 PM UTC 24 |
| Peak memory | 644600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213252659 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prod.4213252659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prodend.1394218685 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 9062372856 ps |
| CPU time | 1070.34 seconds |
| Started | Oct 15 08:35:06 PM UTC 24 |
| Finished | Oct 15 08:53:11 PM UTC 24 |
| Peak memory | 641756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394218685 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.1394218685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.3959292507 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 46070438860 ps |
| CPU time | 6720.93 seconds |
| Started | Oct 15 08:36:38 PM UTC 24 |
| Finished | Oct 15 10:30:00 PM UTC 24 |
| Peak memory | 644604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +fl ash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959292507 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_rma.3959292507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.4112899806 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 25671716068 ps |
| CPU time | 2604.68 seconds |
| Started | Oct 15 08:36:54 PM UTC 24 |
| Finished | Oct 15 09:20:50 PM UTC 24 |
| Peak memory | 641764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnl ock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112899806 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testunlocks.4112899806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3103306937 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 17012092716 ps |
| CPU time | 4196.09 seconds |
| Started | Oct 15 08:51:54 PM UTC 24 |
| Finished | Oct 15 10:02:44 PM UTC 24 |
| Peak memory | 629944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103306937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.3103306937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1090646124 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 18880427741 ps |
| CPU time | 4582.82 seconds |
| Started | Oct 15 08:53:37 PM UTC 24 |
| Finished | Oct 15 10:10:57 PM UTC 24 |
| Peak memory | 630076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090646124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1090646124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3203940945 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 24820278400 ps |
| CPU time | 4701.39 seconds |
| Started | Oct 15 09:35:24 PM UTC 24 |
| Finished | Oct 15 10:54:45 PM UTC 24 |
| Peak memory | 630108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203940945 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3203940945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_mem_scramble.2625949837 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 3673885472 ps |
| CPU time | 528.56 seconds |
| Started | Oct 15 08:53:49 PM UTC 24 |
| Finished | Oct 15 09:02:45 PM UTC 24 |
| Peak memory | 625420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625949837 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.2625949837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_randomness.3313057386 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 6088319632 ps |
| CPU time | 1025.51 seconds |
| Started | Oct 15 08:50:32 PM UTC 24 |
| Finished | Oct 15 09:07:51 PM UTC 24 |
| Peak memory | 627752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313057386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.3313057386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_randomness/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.2335503721 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 5250353462 ps |
| CPU time | 1016.24 seconds |
| Started | Oct 15 09:43:23 PM UTC 24 |
| Finished | Oct 15 10:00:32 PM UTC 24 |
| Peak memory | 625624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2335503721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ otbn_smoketest.2335503721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_descrambling.3354395872 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 3856151452 ps |
| CPU time | 481.82 seconds |
| Started | Oct 15 08:33:53 PM UTC 24 |
| Finished | Oct 15 08:42:01 PM UTC 24 |
| Peak memory | 627540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_ima ges=otp_ctrl_descrambling_test:1:new_rules,otp_ctrl_descrambling_otp_image:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354395872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlg rey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_descrambling.3354395872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_descrambling/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1394989935 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 3053179216 ps |
| CPU time | 228.18 seconds |
| Started | Oct 15 08:33:43 PM UTC 24 |
| Finished | Oct 15 08:37:35 PM UTC 24 |
| Peak memory | 627360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_ error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1394989935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.1394989935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2396276431 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 8941622532 ps |
| CPU time | 1018.02 seconds |
| Started | Oct 15 08:30:26 PM UTC 24 |
| Finished | Oct 15 08:47:38 PM UTC 24 |
| Peak memory | 627292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396276431 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.2396276431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.4135374450 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 7403602446 ps |
| CPU time | 1130.09 seconds |
| Started | Oct 15 08:30:25 PM UTC 24 |
| Finished | Oct 15 08:49:30 PM UTC 24 |
| Peak memory | 627376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_buil d_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135374450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.4135374450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2986258223 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 8276956014 ps |
| CPU time | 1233.32 seconds |
| Started | Oct 15 08:31:56 PM UTC 24 |
| Finished | Oct 15 08:52:45 PM UTC 24 |
| Peak memory | 627760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986258223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.2986258223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1725335134 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 4859595376 ps |
| CPU time | 665.58 seconds |
| Started | Oct 15 08:30:26 PM UTC 24 |
| Finished | Oct 15 08:41:41 PM UTC 24 |
| Peak memory | 627488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725335134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_ asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1725335134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_smoketest.2759492065 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 3402705898 ps |
| CPU time | 334.43 seconds |
| Started | Oct 15 09:43:23 PM UTC 24 |
| Finished | Oct 15 09:49:03 PM UTC 24 |
| Peak memory | 625596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2759492065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_otp_ctrl_smoketest.2759492065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.3222071457 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 2639020000 ps |
| CPU time | 248.52 seconds |
| Started | Oct 15 08:18:16 PM UTC 24 |
| Finished | Oct 15 08:22:29 PM UTC 24 |
| Peak memory | 627512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_im ages=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222071457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.3222071457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pattgen_ios/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_plic_sw_irq.964834255 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 2855375866 ps |
| CPU time | 259.47 seconds |
| Started | Oct 15 09:19:09 PM UTC 24 |
| Finished | Oct 15 09:23:32 PM UTC 24 |
| Peak memory | 627532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=964834255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _plic_sw_irq.964834255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_idle_load.3896393749 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 4423372482 ps |
| CPU time | 657.01 seconds |
| Started | Oct 15 09:36:10 PM UTC 24 |
| Finished | Oct 15 09:47:16 PM UTC 24 |
| Peak memory | 627720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896393749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_power_idle_load.3896393749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_idle_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_sleep_load.2256633699 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 11277817382 ps |
| CPU time | 475.16 seconds |
| Started | Oct 15 09:36:39 PM UTC 24 |
| Finished | Oct 15 09:44:40 PM UTC 24 |
| Peak memory | 627496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2256633699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.2256633699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_sleep_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_virus.438911153 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 5720533270 ps |
| CPU time | 1615.03 seconds |
| Started | Oct 15 09:37:08 PM UTC 24 |
| Finished | Oct 15 10:04:24 PM UTC 24 |
| Peak memory | 642228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_tim eout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_ img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438911153 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_virus.438911153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2751532065 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 9912191042 ps |
| CPU time | 1394.34 seconds |
| Started | Oct 15 08:39:26 PM UTC 24 |
| Finished | Oct 15 09:02:59 PM UTC 24 |
| Peak memory | 627760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751532065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep _all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.2751532065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1215475029 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 22800567829 ps |
| CPU time | 3189.71 seconds |
| Started | Oct 15 09:18:35 PM UTC 24 |
| Finished | Oct 15 10:12:25 PM UTC 24 |
| Peak memory | 627284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215475029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_re set_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.1215475029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1323510116 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 24249682254 ps |
| CPU time | 1090.25 seconds |
| Started | Oct 15 09:26:51 PM UTC 24 |
| Finished | Oct 15 09:45:14 PM UTC 24 |
| Peak memory | 627452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323510116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr _deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1323510116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1121617830 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 7383450264 ps |
| CPU time | 634.46 seconds |
| Started | Oct 15 08:41:43 PM UTC 24 |
| Finished | Oct 15 08:52:26 PM UTC 24 |
| Peak memory | 627296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_res et_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1121617830 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.1121617830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.500057067 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 7861740736 ps |
| CPU time | 430.48 seconds |
| Started | Oct 15 08:42:39 PM UTC 24 |
| Finished | Oct 15 08:49:56 PM UTC 24 |
| Peak memory | 633404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500057067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asi c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.500057067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3887743831 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 8567784733 ps |
| CPU time | 385.03 seconds |
| Started | Oct 15 08:37:00 PM UTC 24 |
| Finished | Oct 15 08:43:31 PM UTC 24 |
| Peak memory | 627356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3887743831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_pwrmgr_full_aon_reset.3887743831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2196802821 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 4128957308 ps |
| CPU time | 358.9 seconds |
| Started | Oct 15 09:27:04 PM UTC 24 |
| Finished | Oct 15 09:33:09 PM UTC 24 |
| Peak memory | 625368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=2196802821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_pwrmgr_lowpower_cancel.2196802821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.875985135 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 3823343792 ps |
| CPU time | 330.4 seconds |
| Started | Oct 15 08:38:15 PM UTC 24 |
| Finished | Oct 15 08:43:50 PM UTC 24 |
| Peak memory | 633460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875985135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main _power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.875985135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3758469720 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 9423433860 ps |
| CPU time | 1093.53 seconds |
| Started | Oct 15 08:41:05 PM UTC 24 |
| Finished | Oct 15 08:59:32 PM UTC 24 |
| Peak memory | 629668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_r eset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3758469720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3758469720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.548925751 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 7068396664 ps |
| CPU time | 335.45 seconds |
| Started | Oct 15 09:27:06 PM UTC 24 |
| Finished | Oct 15 09:32:47 PM UTC 24 |
| Peak memory | 627552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_w ake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=548925751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.548925751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2193206126 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 7077715606 ps |
| CPU time | 610.12 seconds |
| Started | Oct 15 08:42:20 PM UTC 24 |
| Finished | Oct 15 08:52:39 PM UTC 24 |
| Peak memory | 627680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_r eset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2193206126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.2193206126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2249372431 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 21982654519 ps |
| CPU time | 2806.97 seconds |
| Started | Oct 15 08:40:29 PM UTC 24 |
| Finished | Oct 15 09:27:51 PM UTC 24 |
| Peak memory | 627628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249372431 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2249372431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.187148891 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 21498766300 ps |
| CPU time | 1731.04 seconds |
| Started | Oct 15 09:26:54 PM UTC 24 |
| Finished | Oct 15 09:56:06 PM UTC 24 |
| Peak memory | 627468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187148891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.187148891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3201891970 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 5197769696 ps |
| CPU time | 385.86 seconds |
| Started | Oct 15 09:27:10 PM UTC 24 |
| Finished | Oct 15 09:33:41 PM UTC 24 |
| Peak memory | 627612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201891970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3201891970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3835380697 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 3001742416 ps |
| CPU time | 314.93 seconds |
| Started | Oct 15 08:43:36 PM UTC 24 |
| Finished | Oct 15 08:48:55 PM UTC 24 |
| Peak memory | 625496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3835380697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_pwrmgr_sleep_disabled.3835380697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2836522811 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 5166386880 ps |
| CPU time | 382.13 seconds |
| Started | Oct 15 09:18:58 PM UTC 24 |
| Finished | Oct 15 09:25:26 PM UTC 24 |
| Peak memory | 625484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_im ages=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836522811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2836522811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2329385182 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 5369585816 ps |
| CPU time | 378.29 seconds |
| Started | Oct 15 09:27:09 PM UTC 24 |
| Finished | Oct 15 09:33:33 PM UTC 24 |
| Peak memory | 627356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329385182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.2329385182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_smoketest.3467391004 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 5894210230 ps |
| CPU time | 473.1 seconds |
| Started | Oct 15 09:44:52 PM UTC 24 |
| Finished | Oct 15 09:52:53 PM UTC 24 |
| Peak memory | 627284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_ima ges=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467391004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.3467391004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2811670115 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 8995554646 ps |
| CPU time | 1125.64 seconds |
| Started | Oct 15 08:39:08 PM UTC 24 |
| Finished | Oct 15 08:58:08 PM UTC 24 |
| Peak memory | 627548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2811670115 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.2811670115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2578613357 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 5458970992 ps |
| CPU time | 418.06 seconds |
| Started | Oct 15 08:44:08 PM UTC 24 |
| Finished | Oct 15 08:51:12 PM UTC 24 |
| Peak memory | 625248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_w hen_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2578613357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2578613357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.181338636 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 5539268550 ps |
| CPU time | 363.26 seconds |
| Started | Oct 15 09:45:26 PM UTC 24 |
| Finished | Oct 15 09:51:35 PM UTC 24 |
| Peak memory | 625408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=181338636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2. chip_sw_pwrmgr_usbdev_smoketest.181338636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2346811313 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 4594253800 ps |
| CPU time | 587.15 seconds |
| Started | Oct 15 08:49:48 PM UTC 24 |
| Finished | Oct 15 08:59:43 PM UTC 24 |
| Peak memory | 627288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346811313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.2346811313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rom_ctrl_integrity_check.68048186 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 9128650826 ps |
| CPU time | 499.33 seconds |
| Started | Oct 15 09:12:43 PM UTC 24 |
| Finished | Oct 15 09:21:09 PM UTC 24 |
| Peak memory | 641924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=68048186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.68048186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.1878584718 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 12526121516 ps |
| CPU time | 2042.67 seconds |
| Started | Oct 15 08:36:59 PM UTC 24 |
| Finished | Oct 15 09:11:27 PM UTC 24 |
| Peak memory | 627288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_buil d_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878584718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.1878584718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_cpu_info.1913041150 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 4924210840 ps |
| CPU time | 596.49 seconds |
| Started | Oct 15 08:36:54 PM UTC 24 |
| Finished | Oct 15 08:46:59 PM UTC 24 |
| Peak memory | 625516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913041150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_sw_rstmgr_cpu_info.1913041150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.4286764901 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 4796080384 ps |
| CPU time | 628.83 seconds |
| Started | Oct 15 08:15:38 PM UTC 24 |
| Finished | Oct 15 08:26:16 PM UTC 24 |
| Peak memory | 671864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286764901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr _cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.4286764901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_smoketest.2438094290 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 3060020736 ps |
| CPU time | 357.04 seconds |
| Started | Oct 15 09:46:05 PM UTC 24 |
| Finished | Oct 15 09:52:08 PM UTC 24 |
| Peak memory | 625464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2438094290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_rstmgr_smoketest.2438094290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_req.2571016122 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 5060046130 ps |
| CPU time | 595.4 seconds |
| Started | Oct 15 08:36:49 PM UTC 24 |
| Finished | Oct 15 08:46:53 PM UTC 24 |
| Peak memory | 627552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2571016122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_rstmgr_sw_req.2571016122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_rst.3338372384 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 3131996710 ps |
| CPU time | 246.35 seconds |
| Started | Oct 15 08:36:52 PM UTC 24 |
| Finished | Oct 15 08:41:02 PM UTC 24 |
| Peak memory | 625384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3338372384 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_rstmgr_sw_rst.3338372384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1964068121 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 2917489908 ps |
| CPU time | 285.25 seconds |
| Started | Oct 15 09:29:58 PM UTC 24 |
| Finished | Oct 15 09:34:48 PM UTC 24 |
| Peak memory | 625492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_im ages=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964068121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.1964068121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3662622199 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 3276333732 ps |
| CPU time | 259.67 seconds |
| Started | Oct 15 09:31:35 PM UTC 24 |
| Finished | Oct 15 09:35:58 PM UTC 24 |
| Peak memory | 627284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_inval idate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3662622199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.3662622199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1835796023 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 4695966200 ps |
| CPU time | 817.75 seconds |
| Started | Oct 15 08:53:53 PM UTC 24 |
| Finished | Oct 15 09:07:42 PM UTC 24 |
| Peak memory | 625368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835796023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.1835796023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_rnd.2269531550 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 5779076006 ps |
| CPU time | 1044.86 seconds |
| Started | Oct 15 08:53:49 PM UTC 24 |
| Finished | Oct 15 09:11:28 PM UTC 24 |
| Peak memory | 627684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_b uild_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269531550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.2269531550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3295560691 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 5904152081 ps |
| CPU time | 524.94 seconds |
| Started | Oct 15 09:28:36 PM UTC 24 |
| Finished | Oct 15 09:37:29 PM UTC 24 |
| Peak memory | 641548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_han dler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295560691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_esc alation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.3295560691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2969315128 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 5932676080 ps |
| CPU time | 403.34 seconds |
| Started | Oct 15 09:28:07 PM UTC 24 |
| Finished | Oct 15 09:34:56 PM UTC 24 |
| Peak memory | 637708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_acc ess_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969315128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wak eup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.2969315128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3652343904 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 4474045700 ps |
| CPU time | 424.01 seconds |
| Started | Oct 15 09:28:03 PM UTC 24 |
| Finished | Oct 15 09:35:13 PM UTC 24 |
| Peak memory | 639664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm _reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652343904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_re set_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asi c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3652343904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_plic_smoketest.220322266 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 2527972632 ps |
| CPU time | 203.39 seconds |
| Started | Oct 15 09:45:57 PM UTC 24 |
| Finished | Oct 15 09:49:24 PM UTC 24 |
| Peak memory | 625316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=220322266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_rv_plic_smoketest.220322266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_irq.688242772 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 3012800898 ps |
| CPU time | 260.81 seconds |
| Started | Oct 15 08:44:31 PM UTC 24 |
| Finished | Oct 15 08:48:55 PM UTC 24 |
| Peak memory | 625736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=688242772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_rv_timer_irq.688242772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_smoketest.2156800187 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 3275528560 ps |
| CPU time | 294.03 seconds |
| Started | Oct 15 09:45:59 PM UTC 24 |
| Finished | Oct 15 09:50:58 PM UTC 24 |
| Peak memory | 627352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2156800187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_rv_timer_smoketest.2156800187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_status.1609635184 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 3111862676 ps |
| CPU time | 255.2 seconds |
| Started | Oct 15 09:16:22 PM UTC 24 |
| Finished | Oct 15 09:20:41 PM UTC 24 |
| Peak memory | 627492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609635184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_s tatus_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.1609635184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pwm_pulses.3436380171 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 9810738848 ps |
| CPU time | 1302.08 seconds |
| Started | Oct 15 08:19:32 PM UTC 24 |
| Finished | Oct 15 08:41:31 PM UTC 24 |
| Peak memory | 627792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3436380171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_sleep_pwm_pulses.3436380171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1329420398 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 6896103070 ps |
| CPU time | 739.14 seconds |
| Started | Oct 15 09:14:51 PM UTC 24 |
| Finished | Oct 15 09:27:20 PM UTC 24 |
| Peak memory | 627644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329420398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_sram_ret_contents _no_scramble.1329420398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3222503832 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 8190517066 ps |
| CPU time | 651.58 seconds |
| Started | Oct 15 09:14:51 PM UTC 24 |
| Finished | Oct 15 09:25:52 PM UTC 24 |
| Peak memory | 627228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222503832 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_sram_ret_contents_sc ramble.3222503832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through.1366520750 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 6683531962 ps |
| CPU time | 572.21 seconds |
| Started | Oct 15 08:23:11 PM UTC 24 |
| Finished | Oct 15 08:32:51 PM UTC 24 |
| Peak memory | 641840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366520750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_spi_device_pass_through.1366520750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through_collision.3850677184 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 4973515013 ps |
| CPU time | 570.89 seconds |
| Started | Oct 15 08:24:45 PM UTC 24 |
| Finished | Oct 15 08:34:23 PM UTC 24 |
| Peak memory | 642252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850677184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.3850677184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2747023931 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 3633043242 ps |
| CPU time | 278.68 seconds |
| Started | Oct 15 08:22:31 PM UTC 24 |
| Finished | Oct 15 08:27:14 PM UTC 24 |
| Peak memory | 637968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2747023931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.2747023931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.41744117 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3636416619 ps |
| CPU time | 520.57 seconds |
| Started | Oct 15 08:20:35 PM UTC 24 |
| Finished | Oct 15 08:29:23 PM UTC 24 |
| Peak memory | 637796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=41744117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.41744117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.748806370 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 2955544280 ps |
| CPU time | 284.48 seconds |
| Started | Oct 15 08:21:21 PM UTC 24 |
| Finished | Oct 15 08:26:09 PM UTC 24 |
| Peak memory | 627412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748806370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_spi_host_tx_rx.748806370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_execution_main.3653269279 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 7722783320 ps |
| CPU time | 497.59 seconds |
| Started | Oct 15 09:13:22 PM UTC 24 |
| Finished | Oct 15 09:21:47 PM UTC 24 |
| Peak memory | 627284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3653269279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.3653269279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1519025587 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 3705399568 ps |
| CPU time | 484.09 seconds |
| Started | Oct 15 09:12:38 PM UTC 24 |
| Finished | Oct 15 09:20:49 PM UTC 24 |
| Peak memory | 627480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519025587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_ access.1519025587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2572644946 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 5154406750 ps |
| CPU time | 568.31 seconds |
| Started | Oct 15 09:13:02 PM UTC 24 |
| Finished | Oct 15 09:22:38 PM UTC 24 |
| Peak memory | 627492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_ch eck=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572644946 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ct rl_scrambled_access_jitter_en.2572644946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3452109691 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 4155359848 ps |
| CPU time | 580.48 seconds |
| Started | Oct 15 09:34:58 PM UTC 24 |
| Finished | Oct 15 09:44:47 PM UTC 24 |
| Peak memory | 627556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_r eady_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452109691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3452109691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_smoketest.171922799 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 2741284056 ps |
| CPU time | 206.77 seconds |
| Started | Oct 15 09:46:01 PM UTC 24 |
| Finished | Oct 15 09:49:31 PM UTC 24 |
| Peak memory | 625472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171922799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_sram_ctrl_smoketest.171922799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2044727302 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 20599248792 ps |
| CPU time | 3856.51 seconds |
| Started | Oct 15 08:47:44 PM UTC 24 |
| Finished | Oct 15 09:52:50 PM UTC 24 |
| Peak memory | 627572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2044727302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.2044727302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1954144134 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 4393296992 ps |
| CPU time | 646.29 seconds |
| Started | Oct 15 08:45:59 PM UTC 24 |
| Finished | Oct 15 08:56:55 PM UTC 24 |
| Peak memory | 632008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1954144134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_sysrst_ctrl_in_irq.1954144134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3654006103 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 3501771640 ps |
| CPU time | 401.54 seconds |
| Started | Oct 15 08:45:58 PM UTC 24 |
| Finished | Oct 15 08:52:46 PM UTC 24 |
| Peak memory | 627776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3654006103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_sysrst_ctrl_inputs.3654006103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2017548614 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 3869286232 ps |
| CPU time | 404.85 seconds |
| Started | Oct 15 08:47:19 PM UTC 24 |
| Finished | Oct 15 08:54:10 PM UTC 24 |
| Peak memory | 625488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2017548614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_sysrst_ctrl_outputs.2017548614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_reset.2929743570 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 25478472688 ps |
| CPU time | 1808.12 seconds |
| Started | Oct 15 08:47:15 PM UTC 24 |
| Finished | Oct 15 09:17:46 PM UTC 24 |
| Peak memory | 631716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_i mages=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929743570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.2929743570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2785331598 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 6211228220 ps |
| CPU time | 572.55 seconds |
| Started | Oct 15 08:46:09 PM UTC 24 |
| Finished | Oct 15 08:55:50 PM UTC 24 |
| Peak memory | 627604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2785331598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2785331598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_rand_baudrate.67740227 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 3815670912 ps |
| CPU time | 495.38 seconds |
| Started | Oct 15 08:20:17 PM UTC 24 |
| Finished | Oct 15 08:28:40 PM UTC 24 |
| Peak memory | 641888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67740227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ua rt_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.67740227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_smoketest.1205114775 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 3444471420 ps |
| CPU time | 331.95 seconds |
| Started | Oct 15 09:46:06 PM UTC 24 |
| Finished | Oct 15 09:51:43 PM UTC 24 |
| Peak memory | 625384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=1205114775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_sw_uart_smoketest.1205114775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx.2875580090 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 4186926724 ps |
| CPU time | 560.55 seconds |
| Started | Oct 15 08:20:04 PM UTC 24 |
| Finished | Oct 15 08:29:32 PM UTC 24 |
| Peak memory | 638096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875580090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.2875580090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2591385794 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 7544043784 ps |
| CPU time | 1573.45 seconds |
| Started | Oct 15 08:20:03 PM UTC 24 |
| Finished | Oct 15 08:46:37 PM UTC 24 |
| Peak memory | 637532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591385794 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_alt_clk_freq.2591385794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2561815443 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 9195672256 ps |
| CPU time | 1152.3 seconds |
| Started | Oct 15 08:20:17 PM UTC 24 |
| Finished | Oct 15 08:39:45 PM UTC 24 |
| Peak memory | 637540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561815443 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2561815443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.640507084 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 81991421442 ps |
| CPU time | 14837.3 seconds |
| Started | Oct 15 08:19:37 PM UTC 24 |
| Finished | Oct 16 12:29:39 AM UTC 24 |
| Peak memory | 656576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout _ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640507084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.640507084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx1.1335708534 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 4447490232 ps |
| CPU time | 603.84 seconds |
| Started | Oct 15 08:19:19 PM UTC 24 |
| Finished | Oct 15 08:29:31 PM UTC 24 |
| Peak memory | 637692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335708534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.1335708534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx2.1194721220 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 4117197664 ps |
| CPU time | 587.98 seconds |
| Started | Oct 15 08:18:36 PM UTC 24 |
| Finished | Oct 15 08:28:32 PM UTC 24 |
| Peak memory | 637952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194721220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.1194721220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx3.1933525515 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 4457708700 ps |
| CPU time | 569.97 seconds |
| Started | Oct 15 08:19:00 PM UTC 24 |
| Finished | Oct 15 08:28:38 PM UTC 24 |
| Peak memory | 637776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933525515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.1933525515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_dev.4090896045 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 4087281529 ps |
| CPU time | 299.72 seconds |
| Started | Oct 15 09:28:32 PM UTC 24 |
| Finished | Oct 15 09:33:37 PM UTC 24 |
| Peak memory | 641624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090896045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.4090896045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_prod.2188592416 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 2414103127 ps |
| CPU time | 118.27 seconds |
| Started | Oct 15 09:29:54 PM UTC 24 |
| Finished | Oct 15 09:31:55 PM UTC 24 |
| Peak memory | 641308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188592416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.2188592416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.3977920965 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 5240797168 ps |
| CPU time | 453.21 seconds |
| Started | Oct 15 09:29:05 PM UTC 24 |
| Finished | Oct 15 09:36:45 PM UTC 24 |
| Peak memory | 644324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977920965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_tap_straps_rma.3977920965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_testunlock0.3215045775 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 4695321478 ps |
| CPU time | 426.09 seconds |
| Started | Oct 15 09:28:53 PM UTC 24 |
| Finished | Oct 15 09:36:05 PM UTC 24 |
| Peak memory | 642304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215045775 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.3215045775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.3005151917 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 15805258223 ps |
| CPU time | 4578.67 seconds |
| Started | Oct 15 09:38:45 PM UTC 24 |
| Finished | Oct 15 10:56:00 PM UTC 24 |
| Peak memory | 630172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005151917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.3005151917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.2709814600 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 16134085480 ps |
| CPU time | 4498.63 seconds |
| Started | Oct 15 09:40:04 PM UTC 24 |
| Finished | Oct 15 10:55:58 PM UTC 24 |
| Peak memory | 628116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709814600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.2709814600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.339706323 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 15763530882 ps |
| CPU time | 4327.17 seconds |
| Started | Oct 15 09:39:56 PM UTC 24 |
| Finished | Oct 15 10:52:56 PM UTC 24 |
| Peak memory | 628208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339706 323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_ini t_prod_end.339706323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.834106135 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 14893165636 ps |
| CPU time | 4166.91 seconds |
| Started | Oct 15 09:40:23 PM UTC 24 |
| Finished | Oct 15 10:50:41 PM UTC 24 |
| Peak memory | 625688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834106135 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.834106135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3341293253 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 11621205200 ps |
| CPU time | 3238.09 seconds |
| Started | Oct 15 09:38:27 PM UTC 24 |
| Finished | Oct 15 10:33:04 PM UTC 24 |
| Peak memory | 630220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3341293253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e 2e_asm_init_test_unlocked0.3341293253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1377784423 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 15924164006 ps |
| CPU time | 4219.45 seconds |
| Started | Oct 15 09:39:32 PM UTC 24 |
| Finished | Oct 15 10:50:43 PM UTC 24 |
| Peak memory | 627892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377784423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1377784423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1038757700 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 15251314462 ps |
| CPU time | 4345.4 seconds |
| Started | Oct 15 09:40:14 PM UTC 24 |
| Finished | Oct 15 10:53:34 PM UTC 24 |
| Peak memory | 627532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038757700 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.1038757700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.273477011 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 15041573560 ps |
| CPU time | 4524.75 seconds |
| Started | Oct 15 09:39:36 PM UTC 24 |
| Finished | Oct 15 10:55:58 PM UTC 24 |
| Peak memory | 630020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273477011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_no_meas.273477011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.3403141217 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 26761348288 ps |
| CPU time | 6633.91 seconds |
| Started | Oct 15 09:40:04 PM UTC 24 |
| Finished | Oct 15 11:31:55 PM UTC 24 |
| Peak memory | 630084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_rules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403141217 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.3403141217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.rom_e2e_self_hash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.2128110455 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 14089596274 ps |
| CPU time | 3964.05 seconds |
| Started | Oct 15 09:38:20 PM UTC 24 |
| Finished | Oct 15 10:45:13 PM UTC 24 |
| Peak memory | 627944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128110455 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_exception_c.2128110455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.888879399 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 22712839077 ps |
| CPU time | 3605.94 seconds |
| Started | Oct 15 09:38:22 PM UTC 24 |
| Finished | Oct 15 10:39:11 PM UTC 24 |
| Peak memory | 630412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_flash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888879399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.888879399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.rom_e2e_shutdown_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.1650984749 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 15252326368 ps |
| CPU time | 4365.63 seconds |
| Started | Oct 15 09:36:40 PM UTC 24 |
| Finished | Oct 15 10:50:21 PM UTC 24 |
| Peak memory | 629932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650984749 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.1650984749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.rom_e2e_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.2499127293 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 17408248304 ps |
| CPU time | 4634.49 seconds |
| Started | Oct 15 09:39:53 PM UTC 24 |
| Finished | Oct 15 10:58:06 PM UTC 24 |
| Peak memory | 627968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499127293 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.2499127293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.rom_e2e_static_critical/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_keymgr_functest.821237147 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 4356290550 ps |
| CPU time | 503.81 seconds |
| Started | Oct 15 09:39:35 PM UTC 24 |
| Finished | Oct 15 09:48:05 PM UTC 24 |
| Peak memory | 627544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821237147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.rom_keymgr_functest.821237147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.rom_keymgr_functest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_raw_unlock.2049170345 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 5894782827 ps |
| CPU time | 299.29 seconds |
| Started | Oct 15 09:39:25 PM UTC 24 |
| Finished | Oct 15 09:44:29 PM UTC 24 |
| Peak memory | 637344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images =empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049170345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.2049170345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.rom_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_volatile_raw_unlock.761765319 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 1913254293 ps |
| CPU time | 141.15 seconds |
| Started | Oct 15 09:40:01 PM UTC 24 |
| Finished | Oct 15 09:42:25 PM UTC 24 |
| Peak memory | 637280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRa w +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot _flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=761765319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.761765319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/2.rom_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3505655100 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 3718763672 ps |
| CPU time | 447.77 seconds |
| Started | Oct 15 10:30:43 PM UTC 24 |
| Finished | Oct 15 10:38:18 PM UTC 24 |
| Peak memory | 673648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505655100 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3505655100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.2197506262 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 4437632344 ps |
| CPU time | 589.43 seconds |
| Started | Oct 15 10:34:01 PM UTC 24 |
| Finished | Oct 15 10:43:59 PM UTC 24 |
| Peak memory | 675756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197506262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.2197506262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.1168899229 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 6485521230 ps |
| CPU time | 655.85 seconds |
| Started | Oct 15 10:34:17 PM UTC 24 |
| Finished | Oct 15 10:45:22 PM UTC 24 |
| Peak memory | 675912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168899229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.1168899229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.222370054 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 5215438732 ps |
| CPU time | 514.52 seconds |
| Started | Oct 15 10:35:02 PM UTC 24 |
| Finished | Oct 15 10:43:43 PM UTC 24 |
| Peak memory | 675688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222370054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.222370054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.4166187486 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 3275737946 ps |
| CPU time | 419.22 seconds |
| Started | Oct 15 09:50:56 PM UTC 24 |
| Finished | Oct 15 09:58:01 PM UTC 24 |
| Peak memory | 673784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166187486 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_alert_handler_lpg_s leep_mode_alerts.4166187486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_all_escalation_resets.2685949889 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 4153629464 ps |
| CPU time | 527.8 seconds |
| Started | Oct 15 09:46:55 PM UTC 24 |
| Finished | Oct 15 09:55:50 PM UTC 24 |
| Peak memory | 637868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685949889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.2685949889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3579404017 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 6966436760 ps |
| CPU time | 517.97 seconds |
| Started | Oct 15 09:50:56 PM UTC 24 |
| Finished | Oct 15 09:59:40 PM UTC 24 |
| Peak memory | 627816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579404017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3579404017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.2008238552 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 15277956620 ps |
| CPU time | 4160.18 seconds |
| Started | Oct 15 09:51:41 PM UTC 24 |
| Finished | Oct 15 11:01:53 PM UTC 24 |
| Peak memory | 630020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2008238552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 3.chip_sw_csrng_edn_concurrency.2008238552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.3895639081 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 4984185088 ps |
| CPU time | 738.41 seconds |
| Started | Oct 15 09:47:36 PM UTC 24 |
| Finished | Oct 15 10:00:05 PM UTC 24 |
| Peak memory | 627296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895639081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.3895639081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_lc_ctrl_transition.569140879 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 12466527904 ps |
| CPU time | 952.41 seconds |
| Started | Oct 15 09:50:15 PM UTC 24 |
| Finished | Oct 15 10:06:20 PM UTC 24 |
| Peak memory | 641696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=569140879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 3.chip_sw_lc_ctrl_transition.569140879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.3184614360 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 8116057624 ps |
| CPU time | 631.05 seconds |
| Started | Oct 15 09:51:42 PM UTC 24 |
| Finished | Oct 15 10:02:21 PM UTC 24 |
| Peak memory | 627292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184614360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.3184614360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.2400058332 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 4985638152 ps |
| CPU time | 659.39 seconds |
| Started | Oct 15 09:49:25 PM UTC 24 |
| Finished | Oct 15 10:00:34 PM UTC 24 |
| Peak memory | 637536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400058332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.2400058332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx.2299101165 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 3940336300 ps |
| CPU time | 718.16 seconds |
| Started | Oct 15 09:47:58 PM UTC 24 |
| Finished | Oct 15 10:00:07 PM UTC 24 |
| Peak memory | 637536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299101165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.2299101165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1021175339 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 8292658968 ps |
| CPU time | 1639.43 seconds |
| Started | Oct 15 09:49:41 PM UTC 24 |
| Finished | Oct 15 10:17:21 PM UTC 24 |
| Peak memory | 637540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021175339 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_alt_clk_freq.1021175339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4019211768 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 9071883218 ps |
| CPU time | 1084.42 seconds |
| Started | Oct 15 09:50:15 PM UTC 24 |
| Finished | Oct 15 10:08:33 PM UTC 24 |
| Peak memory | 637952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019211768 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4019211768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx1.1491452552 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 4742071006 ps |
| CPU time | 710.06 seconds |
| Started | Oct 15 09:49:08 PM UTC 24 |
| Finished | Oct 15 10:01:08 PM UTC 24 |
| Peak memory | 637768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491452552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.1491452552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx2.2327635400 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 4677781460 ps |
| CPU time | 662.7 seconds |
| Started | Oct 15 09:49:12 PM UTC 24 |
| Finished | Oct 15 10:00:25 PM UTC 24 |
| Peak memory | 637984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327635400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.2327635400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx3.350124592 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 4715695374 ps |
| CPU time | 512.82 seconds |
| Started | Oct 15 09:49:12 PM UTC 24 |
| Finished | Oct 15 09:57:52 PM UTC 24 |
| Peak memory | 641844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350124592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.350124592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.2879419343 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 10514264357 ps |
| CPU time | 1337.88 seconds |
| Started | Oct 15 09:52:08 PM UTC 24 |
| Finished | Oct 15 10:14:44 PM UTC 24 |
| Peak memory | 642156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879419343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.2879419343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_prod.2206000481 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 13948564667 ps |
| CPU time | 1452.54 seconds |
| Started | Oct 15 09:52:41 PM UTC 24 |
| Finished | Oct 15 10:17:12 PM UTC 24 |
| Peak memory | 642580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206000481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.2206000481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_rma.228436932 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 7121206561 ps |
| CPU time | 744.92 seconds |
| Started | Oct 15 09:52:41 PM UTC 24 |
| Finished | Oct 15 10:05:16 PM UTC 24 |
| Peak memory | 652480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228436932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 3.chip_tap_straps_rma.228436932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_testunlock0.3030275514 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 3031587769 ps |
| CPU time | 231.26 seconds |
| Started | Oct 15 09:52:16 PM UTC 24 |
| Finished | Oct 15 09:56:11 PM UTC 24 |
| Peak memory | 642084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030275514 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.3030275514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3545469798 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 4145415736 ps |
| CPU time | 382.35 seconds |
| Started | Oct 15 10:37:38 PM UTC 24 |
| Finished | Oct 15 10:44:06 PM UTC 24 |
| Peak memory | 673900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545469798 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3545469798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.1402484550 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 5151203308 ps |
| CPU time | 633.59 seconds |
| Started | Oct 15 10:35:41 PM UTC 24 |
| Finished | Oct 15 10:46:24 PM UTC 24 |
| Peak memory | 675680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402484550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.1402484550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1858436371 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3837732274 ps |
| CPU time | 356.69 seconds |
| Started | Oct 15 10:37:58 PM UTC 24 |
| Finished | Oct 15 10:44:00 PM UTC 24 |
| Peak memory | 671840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858436371 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1858436371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.102079367 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 5280920360 ps |
| CPU time | 460.57 seconds |
| Started | Oct 15 10:37:53 PM UTC 24 |
| Finished | Oct 15 10:45:40 PM UTC 24 |
| Peak memory | 675856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102079367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.102079367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.1698128603 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 6105770674 ps |
| CPU time | 633.7 seconds |
| Started | Oct 15 10:40:34 PM UTC 24 |
| Finished | Oct 15 10:51:17 PM UTC 24 |
| Peak memory | 675820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698128603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.1698128603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3178407757 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 4011025118 ps |
| CPU time | 360.67 seconds |
| Started | Oct 15 10:39:58 PM UTC 24 |
| Finished | Oct 15 10:46:04 PM UTC 24 |
| Peak memory | 673912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178407757 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3178407757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.3132211035 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 5395883488 ps |
| CPU time | 720.17 seconds |
| Started | Oct 15 10:40:03 PM UTC 24 |
| Finished | Oct 15 10:52:13 PM UTC 24 |
| Peak memory | 675748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132211035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.3132211035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.2365758647 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 6229419510 ps |
| CPU time | 635.12 seconds |
| Started | Oct 15 10:40:37 PM UTC 24 |
| Finished | Oct 15 10:51:20 PM UTC 24 |
| Peak memory | 675864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365758647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.2365758647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.2871328632 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 5160876940 ps |
| CPU time | 668.09 seconds |
| Started | Oct 15 10:40:36 PM UTC 24 |
| Finished | Oct 15 10:51:54 PM UTC 24 |
| Peak memory | 675904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871328632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.2871328632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2088096342 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 3125880768 ps |
| CPU time | 315.67 seconds |
| Started | Oct 15 10:01:24 PM UTC 24 |
| Finished | Oct 15 10:06:44 PM UTC 24 |
| Peak memory | 673864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088096342 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_alert_handler_lpg_s leep_mode_alerts.2088096342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.4076217586 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 4659896014 ps |
| CPU time | 525.7 seconds |
| Started | Oct 15 09:53:54 PM UTC 24 |
| Finished | Oct 15 10:02:47 PM UTC 24 |
| Peak memory | 675900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076217586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.4076217586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2402048690 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 6411575240 ps |
| CPU time | 435.19 seconds |
| Started | Oct 15 10:01:20 PM UTC 24 |
| Finished | Oct 15 10:08:42 PM UTC 24 |
| Peak memory | 627680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402048690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2402048690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.700340494 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 32579233536 ps |
| CPU time | 6955.76 seconds |
| Started | Oct 15 10:01:29 PM UTC 24 |
| Finished | Oct 15 11:58:42 PM UTC 24 |
| Peak memory | 630020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=700340494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 4.chip_sw_csrng_edn_concurrency.700340494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.604316447 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 5146830496 ps |
| CPU time | 792.48 seconds |
| Started | Oct 15 09:53:55 PM UTC 24 |
| Finished | Oct 15 10:07:18 PM UTC 24 |
| Peak memory | 627440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604316447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.604316447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.1785086261 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 6215837988 ps |
| CPU time | 449.87 seconds |
| Started | Oct 15 10:00:21 PM UTC 24 |
| Finished | Oct 15 10:07:57 PM UTC 24 |
| Peak memory | 642184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1785086261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 4.chip_sw_lc_ctrl_transition.1785086261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.1020244969 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 3884604240 ps |
| CPU time | 576.35 seconds |
| Started | Oct 15 09:57:19 PM UTC 24 |
| Finished | Oct 15 10:07:03 PM UTC 24 |
| Peak memory | 637756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020244969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.1020244969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.2605538637 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 4583735372 ps |
| CPU time | 744.83 seconds |
| Started | Oct 15 09:53:55 PM UTC 24 |
| Finished | Oct 15 10:06:30 PM UTC 24 |
| Peak memory | 637864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605538637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.2605538637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2131705069 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 4956826650 ps |
| CPU time | 766.46 seconds |
| Started | Oct 15 09:58:45 PM UTC 24 |
| Finished | Oct 15 10:11:43 PM UTC 24 |
| Peak memory | 637672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131705069 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_alt_clk_freq.2131705069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.544490305 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 4201287221 ps |
| CPU time | 506.65 seconds |
| Started | Oct 15 09:58:46 PM UTC 24 |
| Finished | Oct 15 10:07:20 PM UTC 24 |
| Peak memory | 637740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544490305 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.544490305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.301399381 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 4446459144 ps |
| CPU time | 664.44 seconds |
| Started | Oct 15 09:56:29 PM UTC 24 |
| Finished | Oct 15 10:07:43 PM UTC 24 |
| Peak memory | 638088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301399381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.301399381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.1696730152 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 3802623620 ps |
| CPU time | 571.21 seconds |
| Started | Oct 15 09:56:58 PM UTC 24 |
| Finished | Oct 15 10:06:37 PM UTC 24 |
| Peak memory | 637776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696730152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.1696730152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.409720072 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 4267555380 ps |
| CPU time | 617.83 seconds |
| Started | Oct 15 09:56:58 PM UTC 24 |
| Finished | Oct 15 10:07:25 PM UTC 24 |
| Peak memory | 637944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409720072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.409720072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.2083323245 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 4262182782 ps |
| CPU time | 344.52 seconds |
| Started | Oct 15 10:01:24 PM UTC 24 |
| Finished | Oct 15 10:07:13 PM UTC 24 |
| Peak memory | 642160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083323245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.2083323245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.2831816919 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 3557535631 ps |
| CPU time | 284.43 seconds |
| Started | Oct 15 10:02:54 PM UTC 24 |
| Finished | Oct 15 10:07:43 PM UTC 24 |
| Peak memory | 641628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831816919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.2831816919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_rma.2940042627 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 4919488319 ps |
| CPU time | 435.62 seconds |
| Started | Oct 15 10:01:42 PM UTC 24 |
| Finished | Oct 15 10:09:04 PM UTC 24 |
| Peak memory | 642260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940042627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 4.chip_tap_straps_rma.2940042627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_testunlock0.762142353 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 2892907850 ps |
| CPU time | 190.98 seconds |
| Started | Oct 15 10:01:41 PM UTC 24 |
| Finished | Oct 15 10:04:55 PM UTC 24 |
| Peak memory | 641624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762142353 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlg rey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.762142353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.2895579762 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 5344765838 ps |
| CPU time | 571.1 seconds |
| Started | Oct 15 10:41:53 PM UTC 24 |
| Finished | Oct 15 10:51:32 PM UTC 24 |
| Peak memory | 675940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895579762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.2895579762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.1365422884 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 5070140400 ps |
| CPU time | 670.49 seconds |
| Started | Oct 15 10:41:56 PM UTC 24 |
| Finished | Oct 15 10:53:16 PM UTC 24 |
| Peak memory | 675816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365422884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.1365422884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1873193292 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 4257153934 ps |
| CPU time | 399.27 seconds |
| Started | Oct 15 10:43:38 PM UTC 24 |
| Finished | Oct 15 10:50:23 PM UTC 24 |
| Peak memory | 673644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873193292 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1873193292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3560595476 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 3688791224 ps |
| CPU time | 403.91 seconds |
| Started | Oct 15 10:45:04 PM UTC 24 |
| Finished | Oct 15 10:51:54 PM UTC 24 |
| Peak memory | 673936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560595476 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3560595476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.3628277146 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 5220722328 ps |
| CPU time | 604.41 seconds |
| Started | Oct 15 10:44:59 PM UTC 24 |
| Finished | Oct 15 10:55:12 PM UTC 24 |
| Peak memory | 675840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628277146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.3628277146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3798836494 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 3868617320 ps |
| CPU time | 394.56 seconds |
| Started | Oct 15 10:46:33 PM UTC 24 |
| Finished | Oct 15 10:53:13 PM UTC 24 |
| Peak memory | 673812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798836494 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3798836494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1686735615 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 4242827712 ps |
| CPU time | 352.62 seconds |
| Started | Oct 15 10:47:35 PM UTC 24 |
| Finished | Oct 15 10:53:33 PM UTC 24 |
| Peak memory | 673952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686735615 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1686735615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.1792008158 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 4317825912 ps |
| CPU time | 504.78 seconds |
| Started | Oct 15 10:46:16 PM UTC 24 |
| Finished | Oct 15 10:54:48 PM UTC 24 |
| Peak memory | 675920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792008158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.1792008158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1349512080 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 4306073020 ps |
| CPU time | 349.04 seconds |
| Started | Oct 15 10:47:20 PM UTC 24 |
| Finished | Oct 15 10:53:14 PM UTC 24 |
| Peak memory | 673900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349512080 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1349512080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.4254099632 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 3596959580 ps |
| CPU time | 365 seconds |
| Started | Oct 15 10:48:08 PM UTC 24 |
| Finished | Oct 15 10:54:19 PM UTC 24 |
| Peak memory | 673644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254099632 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_alert_handler_lpg_ sleep_mode_alerts.4254099632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.632822454 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 5019825460 ps |
| CPU time | 453.17 seconds |
| Started | Oct 15 10:47:35 PM UTC 24 |
| Finished | Oct 15 10:55:15 PM UTC 24 |
| Peak memory | 675936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632822454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.632822454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1000616921 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 3986497304 ps |
| CPU time | 428.79 seconds |
| Started | Oct 15 10:05:36 PM UTC 24 |
| Finished | Oct 15 10:12:51 PM UTC 24 |
| Peak memory | 673644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000616921 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_alert_handler_lpg_s leep_mode_alerts.1000616921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.1080851244 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 19309028376 ps |
| CPU time | 4845.01 seconds |
| Started | Oct 15 10:05:55 PM UTC 24 |
| Finished | Oct 15 11:27:37 PM UTC 24 |
| Peak memory | 630204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1080851244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 5.chip_sw_csrng_edn_concurrency.1080851244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.1507905370 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 8068697466 ps |
| CPU time | 505.95 seconds |
| Started | Oct 15 10:05:06 PM UTC 24 |
| Finished | Oct 15 10:13:39 PM UTC 24 |
| Peak memory | 641672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1507905370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 5.chip_sw_lc_ctrl_transition.1507905370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.3617618758 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 4092328564 ps |
| CPU time | 473.55 seconds |
| Started | Oct 15 10:04:17 PM UTC 24 |
| Finished | Oct 15 10:12:17 PM UTC 24 |
| Peak memory | 641632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617618758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.3617618758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.1125165541 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 5415452712 ps |
| CPU time | 469.55 seconds |
| Started | Oct 15 10:48:24 PM UTC 24 |
| Finished | Oct 15 10:56:20 PM UTC 24 |
| Peak memory | 675692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125165541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.1125165541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.4287966346 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 3705499870 ps |
| CPU time | 419.7 seconds |
| Started | Oct 15 10:48:21 PM UTC 24 |
| Finished | Oct 15 10:55:26 PM UTC 24 |
| Peak memory | 673892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287966346 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_alert_handler_lpg_ sleep_mode_alerts.4287966346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.1013339507 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 5206489264 ps |
| CPU time | 646.54 seconds |
| Started | Oct 15 10:48:20 PM UTC 24 |
| Finished | Oct 15 10:59:15 PM UTC 24 |
| Peak memory | 675940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013339507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.1013339507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.4172476632 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4208301870 ps |
| CPU time | 381.15 seconds |
| Started | Oct 15 10:48:23 PM UTC 24 |
| Finished | Oct 15 10:54:49 PM UTC 24 |
| Peak memory | 673956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172476632 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_alert_handler_lpg_ sleep_mode_alerts.4172476632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.764266605 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 5834398440 ps |
| CPU time | 622.39 seconds |
| Started | Oct 15 10:48:23 PM UTC 24 |
| Finished | Oct 15 10:58:54 PM UTC 24 |
| Peak memory | 637940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764266605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.764266605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.330841002 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 3915419570 ps |
| CPU time | 423.6 seconds |
| Started | Oct 15 10:49:43 PM UTC 24 |
| Finished | Oct 15 10:56:52 PM UTC 24 |
| Peak memory | 673832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330841002 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_alert_handler_lpg_s leep_mode_alerts.330841002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.204979198 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 4872277640 ps |
| CPU time | 656.39 seconds |
| Started | Oct 15 10:49:38 PM UTC 24 |
| Finished | Oct 15 11:00:44 PM UTC 24 |
| Peak memory | 675956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204979198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.204979198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.3312993625 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 5241610432 ps |
| CPU time | 496.39 seconds |
| Started | Oct 15 10:49:43 PM UTC 24 |
| Finished | Oct 15 10:58:06 PM UTC 24 |
| Peak memory | 639992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312993625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.3312993625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1639522746 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 3887664696 ps |
| CPU time | 342.46 seconds |
| Started | Oct 15 10:50:38 PM UTC 24 |
| Finished | Oct 15 10:56:26 PM UTC 24 |
| Peak memory | 673784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639522746 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1639522746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.2360048889 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 5706825620 ps |
| CPU time | 563.97 seconds |
| Started | Oct 15 10:50:41 PM UTC 24 |
| Finished | Oct 15 11:00:12 PM UTC 24 |
| Peak memory | 676000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360048889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.2360048889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2362154924 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 4269291016 ps |
| CPU time | 327.06 seconds |
| Started | Oct 15 10:51:08 PM UTC 24 |
| Finished | Oct 15 10:56:40 PM UTC 24 |
| Peak memory | 674004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362154924 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2362154924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.1363299788 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 5919351560 ps |
| CPU time | 600.39 seconds |
| Started | Oct 15 10:50:42 PM UTC 24 |
| Finished | Oct 15 11:00:51 PM UTC 24 |
| Peak memory | 675776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363299788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.1363299788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1166310956 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 3574412596 ps |
| CPU time | 309.25 seconds |
| Started | Oct 15 10:51:52 PM UTC 24 |
| Finished | Oct 15 10:57:05 PM UTC 24 |
| Peak memory | 673920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166310956 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1166310956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_all_escalation_resets.621482425 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 5686248972 ps |
| CPU time | 597.65 seconds |
| Started | Oct 15 10:51:17 PM UTC 24 |
| Finished | Oct 15 11:01:24 PM UTC 24 |
| Peak memory | 675688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621482425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.621482425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1639480403 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 4034339352 ps |
| CPU time | 346.95 seconds |
| Started | Oct 15 10:53:51 PM UTC 24 |
| Finished | Oct 15 10:59:43 PM UTC 24 |
| Peak memory | 673784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639480403 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1639480403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.730763834 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 6179600150 ps |
| CPU time | 606.74 seconds |
| Started | Oct 15 10:52:55 PM UTC 24 |
| Finished | Oct 15 11:03:10 PM UTC 24 |
| Peak memory | 675940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730763834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.730763834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1630914142 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 4099794800 ps |
| CPU time | 286.31 seconds |
| Started | Oct 15 10:53:51 PM UTC 24 |
| Finished | Oct 15 10:58:42 PM UTC 24 |
| Peak memory | 673704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630914142 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1630914142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.3260543943 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 5500048090 ps |
| CPU time | 662.16 seconds |
| Started | Oct 15 10:53:06 PM UTC 24 |
| Finished | Oct 15 11:04:17 PM UTC 24 |
| Peak memory | 675848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260543943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.3260543943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.178018988 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 3684155570 ps |
| CPU time | 620.64 seconds |
| Started | Oct 15 10:08:54 PM UTC 24 |
| Finished | Oct 15 10:19:24 PM UTC 24 |
| Peak memory | 673656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178018988 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_alert_handler_lpg_sl eep_mode_alerts.178018988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.432023628 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 4796317180 ps |
| CPU time | 609.58 seconds |
| Started | Oct 15 10:06:33 PM UTC 24 |
| Finished | Oct 15 10:16:51 PM UTC 24 |
| Peak memory | 675840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432023628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.432023628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.615885212 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 18574289800 ps |
| CPU time | 4421.28 seconds |
| Started | Oct 15 10:08:58 PM UTC 24 |
| Finished | Oct 15 11:23:30 PM UTC 24 |
| Peak memory | 630096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=615885212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 6.chip_sw_csrng_edn_concurrency.615885212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.204182585 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 9930382011 ps |
| CPU time | 1029.22 seconds |
| Started | Oct 15 10:07:45 PM UTC 24 |
| Finished | Oct 15 10:25:08 PM UTC 24 |
| Peak memory | 641692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=204182585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.chip_sw_lc_ctrl_transition.204182585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.4202656165 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 8236494950 ps |
| CPU time | 1809.8 seconds |
| Started | Oct 15 10:07:43 PM UTC 24 |
| Finished | Oct 15 10:38:17 PM UTC 24 |
| Peak memory | 641712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202656165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.4202656165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3109344091 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 4487211396 ps |
| CPU time | 356.74 seconds |
| Started | Oct 15 10:56:59 PM UTC 24 |
| Finished | Oct 15 11:03:02 PM UTC 24 |
| Peak memory | 673712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109344091 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3109344091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.193684102 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 4228226850 ps |
| CPU time | 417.08 seconds |
| Started | Oct 15 10:55:35 PM UTC 24 |
| Finished | Oct 15 11:02:38 PM UTC 24 |
| Peak memory | 673992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193684102 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_alert_handler_lpg_s leep_mode_alerts.193684102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2915817259 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 3354000500 ps |
| CPU time | 253.39 seconds |
| Started | Oct 15 10:54:54 PM UTC 24 |
| Finished | Oct 15 10:59:11 PM UTC 24 |
| Peak memory | 673856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915817259 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2915817259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.4094483874 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 5064282400 ps |
| CPU time | 458.63 seconds |
| Started | Oct 15 10:54:20 PM UTC 24 |
| Finished | Oct 15 11:02:05 PM UTC 24 |
| Peak memory | 675940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094483874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.4094483874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2334220516 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 3582408500 ps |
| CPU time | 378.99 seconds |
| Started | Oct 15 10:55:34 PM UTC 24 |
| Finished | Oct 15 11:01:59 PM UTC 24 |
| Peak memory | 673864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334220516 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2334220516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.3227320768 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 6040692368 ps |
| CPU time | 503.9 seconds |
| Started | Oct 15 10:55:01 PM UTC 24 |
| Finished | Oct 15 11:03:32 PM UTC 24 |
| Peak memory | 675888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227320768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.3227320768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3596164703 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 4215851080 ps |
| CPU time | 332.85 seconds |
| Started | Oct 15 10:56:21 PM UTC 24 |
| Finished | Oct 15 11:01:58 PM UTC 24 |
| Peak memory | 673892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596164703 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3596164703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.2076576586 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 4144963360 ps |
| CPU time | 554.19 seconds |
| Started | Oct 15 10:56:12 PM UTC 24 |
| Finished | Oct 15 11:05:34 PM UTC 24 |
| Peak memory | 637724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076576586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.2076576586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.34010235 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 3845998616 ps |
| CPU time | 395.96 seconds |
| Started | Oct 15 10:56:55 PM UTC 24 |
| Finished | Oct 15 11:03:37 PM UTC 24 |
| Peak memory | 673944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34010235 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_alert_handler_lpg_sl eep_mode_alerts.34010235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.4191014423 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 5154152896 ps |
| CPU time | 571.15 seconds |
| Started | Oct 15 10:57:16 PM UTC 24 |
| Finished | Oct 15 11:06:55 PM UTC 24 |
| Peak memory | 675988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191014423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.4191014423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1370450456 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 4132895608 ps |
| CPU time | 432.21 seconds |
| Started | Oct 15 10:58:06 PM UTC 24 |
| Finished | Oct 15 11:05:24 PM UTC 24 |
| Peak memory | 673752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370450456 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1370450456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2185260884 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 3859265220 ps |
| CPU time | 451.76 seconds |
| Started | Oct 15 10:58:07 PM UTC 24 |
| Finished | Oct 15 11:05:46 PM UTC 24 |
| Peak memory | 673900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185260884 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2185260884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.3434289561 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 5073294822 ps |
| CPU time | 497.28 seconds |
| Started | Oct 15 10:58:13 PM UTC 24 |
| Finished | Oct 15 11:06:38 PM UTC 24 |
| Peak memory | 675696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434289561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.3434289561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.507381697 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 3840972632 ps |
| CPU time | 344.47 seconds |
| Started | Oct 15 10:08:58 PM UTC 24 |
| Finished | Oct 15 10:14:48 PM UTC 24 |
| Peak memory | 673916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507381697 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_alert_handler_lpg_sl eep_mode_alerts.507381697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.3201048998 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 6258504276 ps |
| CPU time | 752.67 seconds |
| Started | Oct 15 10:08:53 PM UTC 24 |
| Finished | Oct 15 10:21:37 PM UTC 24 |
| Peak memory | 675924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201048998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.3201048998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.1954416378 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 16435299948 ps |
| CPU time | 4192.42 seconds |
| Started | Oct 15 10:09:31 PM UTC 24 |
| Finished | Oct 15 11:20:14 PM UTC 24 |
| Peak memory | 630096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1954416378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 7.chip_sw_csrng_edn_concurrency.1954416378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.4060134710 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 10109993894 ps |
| CPU time | 1153.27 seconds |
| Started | Oct 15 10:09:33 PM UTC 24 |
| Finished | Oct 15 10:29:02 PM UTC 24 |
| Peak memory | 641692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=4060134710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 7.chip_sw_lc_ctrl_transition.4060134710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.3605399600 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 7628478112 ps |
| CPU time | 1557.38 seconds |
| Started | Oct 15 10:09:32 PM UTC 24 |
| Finished | Oct 15 10:35:49 PM UTC 24 |
| Peak memory | 637788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605399600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.3605399600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3853398469 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 4221065064 ps |
| CPU time | 364.23 seconds |
| Started | Oct 15 10:58:07 PM UTC 24 |
| Finished | Oct 15 11:04:17 PM UTC 24 |
| Peak memory | 673892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853398469 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3853398469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.3781342505 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 6345910278 ps |
| CPU time | 586.49 seconds |
| Started | Oct 15 10:58:06 PM UTC 24 |
| Finished | Oct 15 11:08:01 PM UTC 24 |
| Peak memory | 675820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781342505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.3781342505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.201392921 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 4008970406 ps |
| CPU time | 392.26 seconds |
| Started | Oct 15 10:58:13 PM UTC 24 |
| Finished | Oct 15 11:04:51 PM UTC 24 |
| Peak memory | 673808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201392921 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_alert_handler_lpg_s leep_mode_alerts.201392921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.1560764974 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 5102780264 ps |
| CPU time | 486.09 seconds |
| Started | Oct 15 10:58:18 PM UTC 24 |
| Finished | Oct 15 11:06:31 PM UTC 24 |
| Peak memory | 675868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560764974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.1560764974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1205419174 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3313833844 ps |
| CPU time | 445.1 seconds |
| Started | Oct 15 10:58:10 PM UTC 24 |
| Finished | Oct 15 11:05:42 PM UTC 24 |
| Peak memory | 673888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205419174 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1205419174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3290963762 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 4277552408 ps |
| CPU time | 432.75 seconds |
| Started | Oct 15 10:58:12 PM UTC 24 |
| Finished | Oct 15 11:05:31 PM UTC 24 |
| Peak memory | 673720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290963762 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3290963762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.3808528124 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 4829692234 ps |
| CPU time | 598.39 seconds |
| Started | Oct 15 10:58:18 PM UTC 24 |
| Finished | Oct 15 11:08:25 PM UTC 24 |
| Peak memory | 675900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808528124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.3808528124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2915323859 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 3968344436 ps |
| CPU time | 347.02 seconds |
| Started | Oct 15 10:58:09 PM UTC 24 |
| Finished | Oct 15 11:04:02 PM UTC 24 |
| Peak memory | 673720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915323859 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2915323859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.2101484267 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 4060025254 ps |
| CPU time | 515.64 seconds |
| Started | Oct 15 10:58:26 PM UTC 24 |
| Finished | Oct 15 11:07:09 PM UTC 24 |
| Peak memory | 675824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101484267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.2101484267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2915940205 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 3657751640 ps |
| CPU time | 348.13 seconds |
| Started | Oct 15 10:58:25 PM UTC 24 |
| Finished | Oct 15 11:04:19 PM UTC 24 |
| Peak memory | 673796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915940205 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2915940205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.919509276 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 4967954448 ps |
| CPU time | 518.83 seconds |
| Started | Oct 15 10:58:19 PM UTC 24 |
| Finished | Oct 15 11:07:05 PM UTC 24 |
| Peak memory | 675700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919509276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.919509276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2000777839 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 4426394024 ps |
| CPU time | 447.47 seconds |
| Started | Oct 15 10:58:26 PM UTC 24 |
| Finished | Oct 15 11:06:00 PM UTC 24 |
| Peak memory | 673992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000777839 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2000777839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.140877038 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 4833927552 ps |
| CPU time | 479.47 seconds |
| Started | Oct 15 10:58:24 PM UTC 24 |
| Finished | Oct 15 11:06:30 PM UTC 24 |
| Peak memory | 675920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140877038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.140877038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2326177242 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 3606616716 ps |
| CPU time | 359.46 seconds |
| Started | Oct 15 10:58:52 PM UTC 24 |
| Finished | Oct 15 11:04:57 PM UTC 24 |
| Peak memory | 673712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326177242 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2326177242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.2191705677 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 5364769240 ps |
| CPU time | 519.65 seconds |
| Started | Oct 15 10:58:51 PM UTC 24 |
| Finished | Oct 15 11:07:38 PM UTC 24 |
| Peak memory | 675940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191705677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.2191705677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3303234551 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 4502778332 ps |
| CPU time | 474.71 seconds |
| Started | Oct 15 10:59:35 PM UTC 24 |
| Finished | Oct 15 11:07:37 PM UTC 24 |
| Peak memory | 673664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303234551 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3303234551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.1454342361 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 5484508624 ps |
| CPU time | 484.03 seconds |
| Started | Oct 15 10:59:33 PM UTC 24 |
| Finished | Oct 15 11:07:44 PM UTC 24 |
| Peak memory | 676048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454342361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.1454342361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1987429364 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 3715356296 ps |
| CPU time | 334.94 seconds |
| Started | Oct 15 11:00:00 PM UTC 24 |
| Finished | Oct 15 11:06:06 PM UTC 24 |
| Peak memory | 673980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987429364 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1987429364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.3803035509 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 5667604032 ps |
| CPU time | 466.83 seconds |
| Started | Oct 15 11:00:00 PM UTC 24 |
| Finished | Oct 15 11:08:19 PM UTC 24 |
| Peak memory | 675932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803035509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.3803035509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3010181257 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 3955000142 ps |
| CPU time | 432.33 seconds |
| Started | Oct 15 10:10:06 PM UTC 24 |
| Finished | Oct 15 10:17:25 PM UTC 24 |
| Peak memory | 673724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010181257 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_alert_handler_lpg_s leep_mode_alerts.3010181257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.2483181346 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 5952746132 ps |
| CPU time | 804.22 seconds |
| Started | Oct 15 10:09:33 PM UTC 24 |
| Finished | Oct 15 10:23:08 PM UTC 24 |
| Peak memory | 675864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483181346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.2483181346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.4210697237 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 18695369260 ps |
| CPU time | 4557.17 seconds |
| Started | Oct 15 10:10:04 PM UTC 24 |
| Finished | Oct 15 11:26:54 PM UTC 24 |
| Peak memory | 630448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=4210697237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 8.chip_sw_csrng_edn_concurrency.4210697237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.443917744 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 9067523307 ps |
| CPU time | 977.27 seconds |
| Started | Oct 15 10:10:09 PM UTC 24 |
| Finished | Oct 15 10:26:39 PM UTC 24 |
| Peak memory | 641780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=443917744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 8.chip_sw_lc_ctrl_transition.443917744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.652145862 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 8455395400 ps |
| CPU time | 1552.96 seconds |
| Started | Oct 15 10:10:03 PM UTC 24 |
| Finished | Oct 15 10:36:16 PM UTC 24 |
| Peak memory | 641640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652145862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.652145862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2955508926 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 3908311164 ps |
| CPU time | 366.34 seconds |
| Started | Oct 15 11:00:26 PM UTC 24 |
| Finished | Oct 15 11:06:38 PM UTC 24 |
| Peak memory | 673888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955508926 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2955508926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.1817424469 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 6385128690 ps |
| CPU time | 593.68 seconds |
| Started | Oct 15 11:00:26 PM UTC 24 |
| Finished | Oct 15 11:10:28 PM UTC 24 |
| Peak memory | 675940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817424469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.1817424469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1635100326 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 3629084264 ps |
| CPU time | 364.33 seconds |
| Started | Oct 15 11:01:38 PM UTC 24 |
| Finished | Oct 15 11:07:48 PM UTC 24 |
| Peak memory | 673712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635100326 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1635100326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.170185992 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 4104400564 ps |
| CPU time | 374.37 seconds |
| Started | Oct 15 11:02:06 PM UTC 24 |
| Finished | Oct 15 11:08:26 PM UTC 24 |
| Peak memory | 673652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170185992 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_alert_handler_lpg_s leep_mode_alerts.170185992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.3422062687 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 5795231644 ps |
| CPU time | 555.36 seconds |
| Started | Oct 15 11:01:38 PM UTC 24 |
| Finished | Oct 15 11:11:01 PM UTC 24 |
| Peak memory | 675688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422062687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.3422062687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2973973761 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 4386455118 ps |
| CPU time | 324.72 seconds |
| Started | Oct 15 11:03:24 PM UTC 24 |
| Finished | Oct 15 11:08:54 PM UTC 24 |
| Peak memory | 673648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973973761 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2973973761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.3971373294 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 6785404268 ps |
| CPU time | 530.09 seconds |
| Started | Oct 15 11:03:16 PM UTC 24 |
| Finished | Oct 15 11:12:13 PM UTC 24 |
| Peak memory | 675692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971373294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.3971373294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.708284735 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 4200919128 ps |
| CPU time | 348.06 seconds |
| Started | Oct 15 11:03:26 PM UTC 24 |
| Finished | Oct 15 11:09:19 PM UTC 24 |
| Peak memory | 673860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708284735 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_alert_handler_lpg_s leep_mode_alerts.708284735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.3999264183 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 6397795392 ps |
| CPU time | 604.79 seconds |
| Started | Oct 15 11:03:20 PM UTC 24 |
| Finished | Oct 15 11:13:32 PM UTC 24 |
| Peak memory | 675684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999264183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.3999264183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.596570444 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 4358463416 ps |
| CPU time | 365.06 seconds |
| Started | Oct 15 11:05:07 PM UTC 24 |
| Finished | Oct 15 11:11:17 PM UTC 24 |
| Peak memory | 673888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596570444 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_alert_handler_lpg_s leep_mode_alerts.596570444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.1131146301 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 4654069828 ps |
| CPU time | 507.13 seconds |
| Started | Oct 15 11:03:25 PM UTC 24 |
| Finished | Oct 15 11:11:59 PM UTC 24 |
| Peak memory | 675952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131146301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.1131146301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.4253013779 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 4700165964 ps |
| CPU time | 434.63 seconds |
| Started | Oct 15 11:04:12 PM UTC 24 |
| Finished | Oct 15 11:11:33 PM UTC 24 |
| Peak memory | 675848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253013779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.4253013779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1725601181 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 3258770876 ps |
| CPU time | 272.36 seconds |
| Started | Oct 15 11:05:41 PM UTC 24 |
| Finished | Oct 15 11:10:17 PM UTC 24 |
| Peak memory | 673944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725601181 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1725601181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.309757363 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 6160301896 ps |
| CPU time | 544.36 seconds |
| Started | Oct 15 11:05:08 PM UTC 24 |
| Finished | Oct 15 11:14:19 PM UTC 24 |
| Peak memory | 675916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309757363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.309757363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_all_escalation_resets.2362854993 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 4042040312 ps |
| CPU time | 364.25 seconds |
| Started | Oct 15 11:06:52 PM UTC 24 |
| Finished | Oct 15 11:13:01 PM UTC 24 |
| Peak memory | 675744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362854993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.2362854993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3532515626 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 3686549224 ps |
| CPU time | 440.77 seconds |
| Started | Oct 15 10:11:44 PM UTC 24 |
| Finished | Oct 15 10:19:11 PM UTC 24 |
| Peak memory | 673708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532515626 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_alert_handler_lpg_s leep_mode_alerts.3532515626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.2662309608 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 5317612040 ps |
| CPU time | 518.1 seconds |
| Started | Oct 15 10:10:10 PM UTC 24 |
| Finished | Oct 15 10:18:55 PM UTC 24 |
| Peak memory | 675928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662309608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.2662309608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.2678056663 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 15936818632 ps |
| CPU time | 3885.36 seconds |
| Started | Oct 15 10:12:23 PM UTC 24 |
| Finished | Oct 15 11:17:55 PM UTC 24 |
| Peak memory | 627684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2678056663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 9.chip_sw_csrng_edn_concurrency.2678056663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.177306171 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 5023775669 ps |
| CPU time | 553.29 seconds |
| Started | Oct 15 10:11:43 PM UTC 24 |
| Finished | Oct 15 10:21:04 PM UTC 24 |
| Peak memory | 639644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=177306171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.chip_sw_lc_ctrl_transition.177306171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.1466236771 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 3426312680 ps |
| CPU time | 508.11 seconds |
| Started | Oct 15 10:10:10 PM UTC 24 |
| Finished | Oct 15 10:18:46 PM UTC 24 |
| Peak memory | 642112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466236771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.1466236771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.2735633508 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 6387062828 ps |
| CPU time | 405.95 seconds |
| Started | Oct 15 11:06:53 PM UTC 24 |
| Finished | Oct 15 11:13:44 PM UTC 24 |
| Peak memory | 675692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735633508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.2735633508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.4293475016 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 6147204310 ps |
| CPU time | 522.6 seconds |
| Started | Oct 15 11:06:52 PM UTC 24 |
| Finished | Oct 15 11:15:41 PM UTC 24 |
| Peak memory | 675688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293475016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.4293475016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.2527442964 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 4650068124 ps |
| CPU time | 394.24 seconds |
| Started | Oct 15 11:07:07 PM UTC 24 |
| Finished | Oct 15 11:13:47 PM UTC 24 |
| Peak memory | 675684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527442964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.2527442964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.2820231328 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 4853382550 ps |
| CPU time | 431.33 seconds |
| Started | Oct 15 11:07:02 PM UTC 24 |
| Finished | Oct 15 11:14:19 PM UTC 24 |
| Peak memory | 675752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820231328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.2820231328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.3524399032 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 4821827468 ps |
| CPU time | 508.45 seconds |
| Started | Oct 15 11:07:09 PM UTC 24 |
| Finished | Oct 15 11:15:43 PM UTC 24 |
| Peak memory | 675688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524399032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.3524399032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.400749384 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 5193504028 ps |
| CPU time | 495.22 seconds |
| Started | Oct 15 11:06:56 PM UTC 24 |
| Finished | Oct 15 11:15:17 PM UTC 24 |
| Peak memory | 675832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400749384 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.400749384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.3449181592 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 4721317160 ps |
| CPU time | 502.82 seconds |
| Started | Oct 15 11:07:08 PM UTC 24 |
| Finished | Oct 15 11:15:37 PM UTC 24 |
| Peak memory | 637948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449181592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.3449181592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.1456208283 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 5057304820 ps |
| CPU time | 464.34 seconds |
| Started | Oct 15 11:07:09 PM UTC 24 |
| Finished | Oct 15 11:14:59 PM UTC 24 |
| Peak memory | 676012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456208283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.1456208283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2795468401 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 4846435408 ps |
| CPU time | 262.86 seconds |
| Started | Oct 15 04:41:08 PM UTC 24 |
| Finished | Oct 15 04:45:35 PM UTC 24 |
| Peak memory | 657932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795468 401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 0.chip_ padctrl_attributes.2795468401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/0.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.370398643 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 5299027800 ps |
| CPU time | 248.95 seconds |
| Started | Oct 15 04:41:17 PM UTC 24 |
| Finished | Oct 15 04:45:30 PM UTC 24 |
| Peak memory | 659972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703986 43 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 3.chip_p adctrl_attributes.370398643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/3.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2337620663 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 5044245400 ps |
| CPU time | 329.3 seconds |
| Started | Oct 15 04:41:21 PM UTC 24 |
| Finished | Oct 15 04:46:56 PM UTC 24 |
| Peak memory | 668428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337620 663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 4.chip_ padctrl_attributes.2337620663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/4.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2541626455 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 5132317520 ps |
| CPU time | 236.51 seconds |
| Started | Oct 15 04:41:23 PM UTC 24 |
| Finished | Oct 15 04:45:23 PM UTC 24 |
| Peak memory | 658076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541626 455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 5.chip_ padctrl_attributes.2541626455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/5.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2389656765 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 4617365644 ps |
| CPU time | 254.38 seconds |
| Started | Oct 15 04:41:24 PM UTC 24 |
| Finished | Oct 15 04:45:43 PM UTC 24 |
| Peak memory | 672604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389656 765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 6.chip_ padctrl_attributes.2389656765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/6.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.612371195 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 5302896969 ps |
| CPU time | 251.11 seconds |
| Started | Oct 15 04:41:28 PM UTC 24 |
| Finished | Oct 15 04:45:43 PM UTC 24 |
| Peak memory | 674444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6123711 95 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 7.chip_p adctrl_attributes.612371195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/7.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1116460058 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 5307025012 ps |
| CPU time | 286.39 seconds |
| Started | Oct 15 04:41:25 PM UTC 24 |
| Finished | Oct 15 04:46:16 PM UTC 24 |
| Peak memory | 674316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116460 058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 8.chip_ padctrl_attributes.1116460058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/8.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3551832131 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 6165052338 ps |
| CPU time | 292.7 seconds |
| Started | Oct 15 04:41:29 PM UTC 24 |
| Finished | Oct 15 04:46:26 PM UTC 24 |
| Peak memory | 672384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551832 131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 9.chip_ padctrl_attributes.3551832131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/9.chip_padctrl_attributes/latest |
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