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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.67 95.60 94.48 91.84 95.40 97.20 99.53


Total test records in report: 2735
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T1111 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3375300787 May 16 04:26:12 PM PDT 24 May 16 07:46:04 PM PDT 24 255958492892 ps
T1112 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.2783414912 May 16 04:29:41 PM PDT 24 May 16 04:37:26 PM PDT 24 3245225226 ps
T41 /workspace/coverage/default/1.chip_sw_spi_device_tpm.1992470016 May 16 04:08:15 PM PDT 24 May 16 04:14:55 PM PDT 24 3322220953 ps
T1113 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1723910511 May 16 04:22:51 PM PDT 24 May 16 04:26:01 PM PDT 24 2485132080 ps
T627 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2235047751 May 16 04:37:18 PM PDT 24 May 16 04:44:55 PM PDT 24 4142867320 ps
T303 /workspace/coverage/default/0.chip_plic_all_irqs_0.4185778273 May 16 04:06:04 PM PDT 24 May 16 04:27:01 PM PDT 24 6764337656 ps
T707 /workspace/coverage/default/54.chip_sw_all_escalation_resets.82061563 May 16 04:28:47 PM PDT 24 May 16 04:37:01 PM PDT 24 4400578168 ps
T1114 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3172893217 May 16 04:04:12 PM PDT 24 May 16 04:25:14 PM PDT 24 5473996830 ps
T1115 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.233979021 May 16 04:24:59 PM PDT 24 May 16 04:39:24 PM PDT 24 5965887408 ps
T1116 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2761419635 May 16 04:08:40 PM PDT 24 May 16 04:30:59 PM PDT 24 7577598158 ps
T1117 /workspace/coverage/default/2.chip_sw_aes_enc.1907470275 May 16 04:24:43 PM PDT 24 May 16 04:29:35 PM PDT 24 2604460520 ps
T1118 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3232855367 May 16 04:09:25 PM PDT 24 May 16 04:14:59 PM PDT 24 3232117158 ps
T655 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1508194888 May 16 04:33:36 PM PDT 24 May 16 04:40:07 PM PDT 24 3571590728 ps
T1119 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1898399023 May 16 04:31:16 PM PDT 24 May 16 04:43:08 PM PDT 24 3999220356 ps
T125 /workspace/coverage/default/2.chip_sw_alert_test.3864107121 May 16 04:27:45 PM PDT 24 May 16 04:32:40 PM PDT 24 3215636496 ps
T1120 /workspace/coverage/default/81.chip_sw_all_escalation_resets.3228844796 May 16 04:31:28 PM PDT 24 May 16 04:39:11 PM PDT 24 5500694304 ps
T1121 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.3600067387 May 16 04:06:59 PM PDT 24 May 16 04:11:44 PM PDT 24 3162654648 ps
T1122 /workspace/coverage/default/1.chip_tap_straps_dev.202976092 May 16 04:13:21 PM PDT 24 May 16 04:16:56 PM PDT 24 3211789991 ps
T1123 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.417207725 May 16 04:27:50 PM PDT 24 May 16 04:52:06 PM PDT 24 7415710766 ps
T169 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2327907033 May 16 04:06:11 PM PDT 24 May 16 04:52:17 PM PDT 24 20568930356 ps
T1124 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1077255584 May 16 04:28:01 PM PDT 24 May 16 04:34:47 PM PDT 24 5495838350 ps
T651 /workspace/coverage/default/83.chip_sw_all_escalation_resets.922950610 May 16 04:30:26 PM PDT 24 May 16 04:41:03 PM PDT 24 4012774748 ps
T1125 /workspace/coverage/default/59.chip_sw_all_escalation_resets.2762231375 May 16 04:29:56 PM PDT 24 May 16 04:37:56 PM PDT 24 5583753596 ps
T1126 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3854225925 May 16 04:24:09 PM PDT 24 May 16 04:31:39 PM PDT 24 3389247400 ps
T1127 /workspace/coverage/default/2.chip_sw_example_flash.48531048 May 16 04:22:55 PM PDT 24 May 16 04:27:14 PM PDT 24 3414370034 ps
T1128 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3438633690 May 16 04:03:46 PM PDT 24 May 16 04:13:14 PM PDT 24 4956255546 ps
T1129 /workspace/coverage/default/1.chip_sw_kmac_entropy.2619634407 May 16 04:08:27 PM PDT 24 May 16 04:12:55 PM PDT 24 2531167896 ps
T1130 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1227344802 May 16 04:09:33 PM PDT 24 May 16 04:32:13 PM PDT 24 8735851360 ps
T630 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1147156253 May 16 04:31:52 PM PDT 24 May 16 04:38:28 PM PDT 24 4467393920 ps
T1131 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3675122286 May 16 04:23:47 PM PDT 24 May 16 04:39:20 PM PDT 24 6163527450 ps
T1132 /workspace/coverage/default/2.chip_sw_example_concurrency.1991691453 May 16 04:23:24 PM PDT 24 May 16 04:26:52 PM PDT 24 2734087454 ps
T9 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1317498222 May 16 04:02:09 PM PDT 24 May 16 04:06:49 PM PDT 24 2308041022 ps
T677 /workspace/coverage/default/71.chip_sw_all_escalation_resets.4267838478 May 16 04:32:24 PM PDT 24 May 16 04:40:07 PM PDT 24 4709126584 ps
T714 /workspace/coverage/default/7.chip_sw_all_escalation_resets.18645458 May 16 04:26:15 PM PDT 24 May 16 04:35:41 PM PDT 24 5009968328 ps
T1133 /workspace/coverage/default/2.chip_sw_flash_crash_alert.112362160 May 16 04:24:30 PM PDT 24 May 16 04:32:17 PM PDT 24 4365261684 ps
T1134 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1667299074 May 16 04:05:21 PM PDT 24 May 16 04:15:03 PM PDT 24 4480406988 ps
T1135 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1719017981 May 16 04:29:22 PM PDT 24 May 16 04:35:01 PM PDT 24 3631840768 ps
T1136 /workspace/coverage/default/0.chip_sw_otbn_smoketest.1958465860 May 16 04:07:13 PM PDT 24 May 16 04:41:49 PM PDT 24 9303493408 ps
T1137 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.536414336 May 16 04:24:30 PM PDT 24 May 16 04:30:41 PM PDT 24 4990058920 ps
T1138 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.601876475 May 16 04:01:33 PM PDT 24 May 16 07:41:27 PM PDT 24 77728310936 ps
T1139 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2996504267 May 16 04:03:58 PM PDT 24 May 16 04:24:28 PM PDT 24 8381801762 ps
T1140 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3495070244 May 16 04:08:46 PM PDT 24 May 16 04:25:45 PM PDT 24 8942534507 ps
T326 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.298239545 May 16 04:05:26 PM PDT 24 May 16 04:17:19 PM PDT 24 4550849030 ps
T135 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2368201403 May 16 04:26:33 PM PDT 24 May 16 04:33:59 PM PDT 24 3827193172 ps
T1141 /workspace/coverage/default/0.chip_sw_plic_sw_irq.4036461403 May 16 04:04:54 PM PDT 24 May 16 04:09:46 PM PDT 24 2805633260 ps
T342 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3919359577 May 16 04:31:37 PM PDT 24 May 16 04:37:34 PM PDT 24 3624954250 ps
T170 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2122778993 May 16 04:25:51 PM PDT 24 May 16 04:59:00 PM PDT 24 18278459996 ps
T1142 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2932062733 May 16 04:10:06 PM PDT 24 May 16 05:03:58 PM PDT 24 17041515432 ps
T304 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.4243694142 May 16 04:03:01 PM PDT 24 May 16 04:22:19 PM PDT 24 4974883096 ps
T1143 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3438631516 May 16 04:23:09 PM PDT 24 May 16 04:27:20 PM PDT 24 3611557766 ps
T1144 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.562381121 May 16 04:12:04 PM PDT 24 May 16 04:20:01 PM PDT 24 4219536672 ps
T571 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.894746260 May 16 04:05:32 PM PDT 24 May 16 04:13:39 PM PDT 24 4766319940 ps
T1145 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.4289755733 May 16 04:26:25 PM PDT 24 May 16 04:35:42 PM PDT 24 3429366894 ps
T679 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3428843294 May 16 04:28:57 PM PDT 24 May 16 04:35:46 PM PDT 24 3529270280 ps
T392 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2726620210 May 16 04:13:55 PM PDT 24 May 16 04:22:27 PM PDT 24 5190295912 ps
T621 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3275226333 May 16 04:29:30 PM PDT 24 May 16 04:56:27 PM PDT 24 18611912904 ps
T1146 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1558428120 May 16 04:10:18 PM PDT 24 May 16 04:24:27 PM PDT 24 5549380200 ps
T1147 /workspace/coverage/default/2.chip_sw_uart_tx_rx.4012093397 May 16 04:24:10 PM PDT 24 May 16 04:33:24 PM PDT 24 3834258192 ps
T343 /workspace/coverage/default/75.chip_sw_all_escalation_resets.4035082383 May 16 04:33:28 PM PDT 24 May 16 04:43:25 PM PDT 24 4569868364 ps
T1148 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3909086064 May 16 04:23:31 PM PDT 24 May 16 04:35:01 PM PDT 24 5098256760 ps
T313 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.1776405513 May 16 04:04:03 PM PDT 24 May 16 04:33:58 PM PDT 24 8650957210 ps
T1149 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.897137161 May 16 04:25:41 PM PDT 24 May 16 04:31:42 PM PDT 24 7096026902 ps
T1150 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2258017774 May 16 04:07:14 PM PDT 24 May 16 04:19:36 PM PDT 24 5283154864 ps
T1151 /workspace/coverage/default/24.chip_sw_all_escalation_resets.3998525926 May 16 04:27:12 PM PDT 24 May 16 04:36:51 PM PDT 24 5570487094 ps
T695 /workspace/coverage/default/91.chip_sw_all_escalation_resets.1626658756 May 16 04:32:39 PM PDT 24 May 16 04:39:18 PM PDT 24 5417713896 ps
T1152 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.4123700037 May 16 04:24:59 PM PDT 24 May 16 04:34:07 PM PDT 24 4585666088 ps
T1153 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.192145176 May 16 04:27:55 PM PDT 24 May 16 05:06:28 PM PDT 24 13056088808 ps
T1154 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2302529218 May 16 04:26:24 PM PDT 24 May 16 04:45:03 PM PDT 24 6960007224 ps
T1155 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.630310282 May 16 04:28:49 PM PDT 24 May 16 04:41:53 PM PDT 24 4289346390 ps
T354 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2094258649 May 16 04:04:02 PM PDT 24 May 16 04:16:14 PM PDT 24 5062404828 ps
T669 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.4192883187 May 16 04:27:59 PM PDT 24 May 16 04:35:07 PM PDT 24 3912372138 ps
T263 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.12551829 May 16 04:23:50 PM PDT 24 May 16 04:35:53 PM PDT 24 4696073602 ps
T200 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1674834042 May 16 04:06:23 PM PDT 24 May 16 04:14:33 PM PDT 24 3862380563 ps
T1156 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2111994136 May 16 04:11:59 PM PDT 24 May 16 04:15:53 PM PDT 24 2311978544 ps
T664 /workspace/coverage/default/93.chip_sw_all_escalation_resets.771870254 May 16 04:32:56 PM PDT 24 May 16 04:42:09 PM PDT 24 4471752968 ps
T1157 /workspace/coverage/default/84.chip_sw_all_escalation_resets.3176001131 May 16 04:35:25 PM PDT 24 May 16 04:44:21 PM PDT 24 4847284296 ps
T1158 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.748143067 May 16 04:03:51 PM PDT 24 May 16 04:50:30 PM PDT 24 12876283320 ps
T1159 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.4049100897 May 16 04:22:08 PM PDT 24 May 16 04:27:25 PM PDT 24 2580199408 ps
T258 /workspace/coverage/default/2.chip_jtag_mem_access.54408196 May 16 04:15:43 PM PDT 24 May 16 04:36:39 PM PDT 24 13162139402 ps
T1160 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1829255696 May 16 04:12:06 PM PDT 24 May 16 04:17:42 PM PDT 24 3849965008 ps
T1161 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2039768130 May 16 04:29:53 PM PDT 24 May 16 04:42:58 PM PDT 24 4077502374 ps
T1162 /workspace/coverage/default/1.chip_sw_otbn_randomness.784911123 May 16 04:09:43 PM PDT 24 May 16 04:27:43 PM PDT 24 5177082232 ps
T1163 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2617022097 May 16 04:29:05 PM PDT 24 May 16 04:36:26 PM PDT 24 3673306056 ps
T1164 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3170803826 May 16 04:25:53 PM PDT 24 May 16 04:42:51 PM PDT 24 5907842240 ps
T1165 /workspace/coverage/default/89.chip_sw_all_escalation_resets.4050552255 May 16 04:32:18 PM PDT 24 May 16 04:41:45 PM PDT 24 6350904066 ps
T1166 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4036532956 May 16 04:12:22 PM PDT 24 May 16 04:23:22 PM PDT 24 4292503625 ps
T62 /workspace/coverage/cover_reg_top/23.xbar_error_random.3967381454 May 16 03:42:41 PM PDT 24 May 16 03:43:11 PM PDT 24 376042811 ps
T63 /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.730455155 May 16 03:43:09 PM PDT 24 May 16 03:46:29 PM PDT 24 11467284768 ps
T64 /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.2826731520 May 16 03:41:53 PM PDT 24 May 16 03:42:07 PM PDT 24 99715698 ps
T191 /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.935159117 May 16 03:43:57 PM PDT 24 May 16 03:44:07 PM PDT 24 45835094 ps
T192 /workspace/coverage/cover_reg_top/32.xbar_random.2144103818 May 16 03:44:14 PM PDT 24 May 16 03:44:30 PM PDT 24 135286535 ps
T242 /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.1874735834 May 16 03:50:12 PM PDT 24 May 16 03:51:02 PM PDT 24 596959134 ps
T240 /workspace/coverage/cover_reg_top/54.xbar_access_same_device.1588295551 May 16 03:47:41 PM PDT 24 May 16 03:49:47 PM PDT 24 3196974082 ps
T241 /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.920559794 May 16 03:53:54 PM PDT 24 May 16 03:54:35 PM PDT 24 999864755 ps
T485 /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.979794051 May 16 03:42:42 PM PDT 24 May 16 03:44:00 PM PDT 24 7311908842 ps
T493 /workspace/coverage/cover_reg_top/79.xbar_smoke.187181379 May 16 03:51:20 PM PDT 24 May 16 03:51:30 PM PDT 24 174965310 ps
T488 /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.2743462780 May 16 03:49:51 PM PDT 24 May 16 03:51:04 PM PDT 24 6509957203 ps
T486 /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3594360626 May 16 03:38:52 PM PDT 24 May 16 03:39:37 PM PDT 24 1105336182 ps
T479 /workspace/coverage/cover_reg_top/61.xbar_access_same_device.2875241272 May 16 03:48:38 PM PDT 24 May 16 03:50:10 PM PDT 24 2266449287 ps
T497 /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.395773618 May 16 03:39:10 PM PDT 24 May 16 03:56:11 PM PDT 24 57695718915 ps
T483 /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.1443172339 May 16 03:43:42 PM PDT 24 May 16 03:53:03 PM PDT 24 31401506981 ps
T807 /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.271109866 May 16 03:38:53 PM PDT 24 May 16 03:43:43 PM PDT 24 8181213183 ps
T489 /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.2719249734 May 16 03:48:06 PM PDT 24 May 16 03:49:36 PM PDT 24 8607183429 ps
T396 /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.1895205533 May 16 03:41:05 PM PDT 24 May 16 03:45:04 PM PDT 24 5534360016 ps
T480 /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.1469385134 May 16 03:45:53 PM PDT 24 May 16 03:49:19 PM PDT 24 2972129898 ps
T490 /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.3949171934 May 16 03:43:50 PM PDT 24 May 16 03:44:28 PM PDT 24 898809675 ps
T388 /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.3668686107 May 16 03:51:26 PM PDT 24 May 16 04:07:19 PM PDT 24 51373425610 ps
T481 /workspace/coverage/cover_reg_top/55.xbar_error_random.2032167317 May 16 03:47:45 PM PDT 24 May 16 03:48:21 PM PDT 24 448777853 ps
T491 /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.1408530362 May 16 03:53:34 PM PDT 24 May 16 03:53:43 PM PDT 24 56642685 ps
T487 /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.701221458 May 16 03:40:48 PM PDT 24 May 16 03:42:20 PM PDT 24 5589853802 ps
T401 /workspace/coverage/cover_reg_top/94.xbar_stress_all.3271017573 May 16 03:53:45 PM PDT 24 May 16 03:59:19 PM PDT 24 3722847258 ps
T1167 /workspace/coverage/cover_reg_top/26.xbar_smoke.2203000374 May 16 03:43:05 PM PDT 24 May 16 03:43:18 PM PDT 24 189761878 ps
T1168 /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.3198220146 May 16 03:46:28 PM PDT 24 May 16 03:46:37 PM PDT 24 47847641 ps
T612 /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.2649372336 May 16 03:44:51 PM PDT 24 May 16 03:45:00 PM PDT 24 51708423 ps
T482 /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.1872196470 May 16 03:52:35 PM PDT 24 May 16 03:54:01 PM PDT 24 1083193379 ps
T496 /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.1892791257 May 16 03:41:05 PM PDT 24 May 16 03:41:13 PM PDT 24 47223906 ps
T390 /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.3529318226 May 16 03:49:30 PM PDT 24 May 16 04:04:31 PM PDT 24 49503589349 ps
T1169 /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.473761746 May 16 03:43:35 PM PDT 24 May 16 03:44:39 PM PDT 24 6006122064 ps
T484 /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.78616879 May 16 03:52:42 PM PDT 24 May 16 03:54:54 PM PDT 24 985440184 ps
T799 /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.2656260542 May 16 03:43:28 PM PDT 24 May 16 03:44:23 PM PDT 24 173290007 ps
T554 /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.2807748365 May 16 03:50:37 PM PDT 24 May 16 03:57:02 PM PDT 24 20708925168 ps
T494 /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.1150894644 May 16 03:44:53 PM PDT 24 May 16 03:48:49 PM PDT 24 6699026389 ps
T492 /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.951221221 May 16 03:48:44 PM PDT 24 May 16 03:51:23 PM PDT 24 1842123704 ps
T746 /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.3457839117 May 16 03:48:20 PM PDT 24 May 16 03:49:09 PM PDT 24 2825383511 ps
T721 /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1389757115 May 16 03:43:57 PM PDT 24 May 16 03:49:37 PM PDT 24 4833142449 ps
T495 /workspace/coverage/cover_reg_top/81.xbar_error_random.2999319321 May 16 03:51:46 PM PDT 24 May 16 03:52:29 PM PDT 24 558781247 ps
T389 /workspace/coverage/cover_reg_top/3.xbar_stress_all.3606749324 May 16 03:39:12 PM PDT 24 May 16 03:44:31 PM PDT 24 8404674348 ps
T1170 /workspace/coverage/cover_reg_top/86.xbar_smoke.1947613658 May 16 03:52:26 PM PDT 24 May 16 03:52:40 PM PDT 24 171156297 ps
T499 /workspace/coverage/cover_reg_top/28.chip_tl_errors.2289520994 May 16 03:43:29 PM PDT 24 May 16 03:47:20 PM PDT 24 3728844040 ps
T513 /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.3076768805 May 16 03:42:41 PM PDT 24 May 16 03:43:08 PM PDT 24 190549059 ps
T549 /workspace/coverage/cover_reg_top/3.xbar_same_source.691975166 May 16 03:39:13 PM PDT 24 May 16 03:39:26 PM PDT 24 248287223 ps
T514 /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.1748673107 May 16 03:50:20 PM PDT 24 May 16 04:08:50 PM PDT 24 54572060738 ps
T511 /workspace/coverage/cover_reg_top/99.xbar_random.3816159132 May 16 03:54:17 PM PDT 24 May 16 03:55:16 PM PDT 24 609352484 ps
T564 /workspace/coverage/cover_reg_top/21.xbar_smoke.1170803193 May 16 03:42:13 PM PDT 24 May 16 03:42:23 PM PDT 24 155850033 ps
T364 /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.2560818582 May 16 03:38:55 PM PDT 24 May 16 03:48:22 PM PDT 24 4954183944 ps
T560 /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.614914816 May 16 03:42:02 PM PDT 24 May 16 03:43:24 PM PDT 24 4480844019 ps
T1171 /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.3128041671 May 16 03:40:09 PM PDT 24 May 16 03:40:40 PM PDT 24 306121518 ps
T512 /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.1733770813 May 16 03:46:48 PM PDT 24 May 16 03:47:37 PM PDT 24 46497148 ps
T498 /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.4129887809 May 16 03:48:07 PM PDT 24 May 16 03:48:20 PM PDT 24 89602155 ps
T507 /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.3244614872 May 16 03:44:13 PM PDT 24 May 16 03:45:37 PM PDT 24 4645790181 ps
T505 /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.3379087498 May 16 03:53:26 PM PDT 24 May 16 04:03:24 PM PDT 24 32609707033 ps
T402 /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.3861625126 May 16 03:39:07 PM PDT 24 May 16 03:54:35 PM PDT 24 53858045204 ps
T756 /workspace/coverage/cover_reg_top/85.xbar_access_same_device.3094333595 May 16 03:52:20 PM PDT 24 May 16 03:52:30 PM PDT 24 69580786 ps
T1172 /workspace/coverage/cover_reg_top/99.xbar_error_random.3722048533 May 16 03:54:25 PM PDT 24 May 16 03:54:45 PM PDT 24 480834203 ps
T1173 /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3282195555 May 16 03:38:36 PM PDT 24 May 16 03:45:54 PM PDT 24 9458215811 ps
T391 /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.1761103519 May 16 03:51:13 PM PDT 24 May 16 03:59:54 PM PDT 24 51791561520 ps
T522 /workspace/coverage/cover_reg_top/88.xbar_smoke.2552072450 May 16 03:53:48 PM PDT 24 May 16 03:53:56 PM PDT 24 49898796 ps
T559 /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.637486198 May 16 03:50:10 PM PDT 24 May 16 03:50:18 PM PDT 24 38478890 ps
T548 /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.2707463166 May 16 03:39:32 PM PDT 24 May 16 03:41:10 PM PDT 24 6080959556 ps
T587 /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.411321481 May 16 03:38:49 PM PDT 24 May 16 03:41:28 PM PDT 24 1788147663 ps
T474 /workspace/coverage/cover_reg_top/6.xbar_stress_all.2158108114 May 16 03:39:49 PM PDT 24 May 16 03:41:23 PM PDT 24 2543390901 ps
T500 /workspace/coverage/cover_reg_top/2.chip_tl_errors.2328406100 May 16 03:38:53 PM PDT 24 May 16 03:42:22 PM PDT 24 3370936560 ps
T1174 /workspace/coverage/cover_reg_top/17.xbar_error_random.717075147 May 16 03:41:28 PM PDT 24 May 16 03:42:19 PM PDT 24 622548776 ps
T177 /workspace/coverage/cover_reg_top/12.chip_csr_rw.1948155660 May 16 03:40:44 PM PDT 24 May 16 03:51:19 PM PDT 24 6197116361 ps
T178 /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1708605877 May 16 03:40:48 PM PDT 24 May 16 04:19:57 PM PDT 24 16717118103 ps
T517 /workspace/coverage/cover_reg_top/60.xbar_stress_all.1387493578 May 16 03:48:39 PM PDT 24 May 16 03:49:36 PM PDT 24 651559476 ps
T435 /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.1114337618 May 16 03:52:28 PM PDT 24 May 16 04:01:21 PM PDT 24 52331704803 ps
T1175 /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.103164968 May 16 03:49:08 PM PDT 24 May 16 03:49:24 PM PDT 24 235601101 ps
T1176 /workspace/coverage/cover_reg_top/83.xbar_smoke.137843389 May 16 03:52:00 PM PDT 24 May 16 03:52:08 PM PDT 24 50787449 ps
T1177 /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.3391709303 May 16 03:47:58 PM PDT 24 May 16 03:48:40 PM PDT 24 1041512017 ps
T1178 /workspace/coverage/cover_reg_top/70.xbar_error_random.3106492857 May 16 03:51:06 PM PDT 24 May 16 03:51:32 PM PDT 24 306487197 ps
T403 /workspace/coverage/cover_reg_top/36.xbar_stress_all.186702131 May 16 03:44:52 PM PDT 24 May 16 03:49:17 PM PDT 24 3359877983 ps
T786 /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.3663339632 May 16 03:48:46 PM PDT 24 May 16 03:49:47 PM PDT 24 170039514 ps
T407 /workspace/coverage/cover_reg_top/30.xbar_stress_all.3269845422 May 16 03:43:50 PM PDT 24 May 16 03:46:18 PM PDT 24 1968029678 ps
T748 /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.1553988158 May 16 03:49:24 PM PDT 24 May 16 03:49:47 PM PDT 24 109840726 ps
T531 /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.1354214986 May 16 03:52:26 PM PDT 24 May 16 03:52:38 PM PDT 24 46539000 ps
T1179 /workspace/coverage/cover_reg_top/25.xbar_smoke.3812459407 May 16 03:42:59 PM PDT 24 May 16 03:43:12 PM PDT 24 208845236 ps
T726 /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.346361011 May 16 03:40:51 PM PDT 24 May 16 03:55:40 PM PDT 24 19935980225 ps
T404 /workspace/coverage/cover_reg_top/28.xbar_access_same_device.2509945411 May 16 03:43:29 PM PDT 24 May 16 03:44:45 PM PDT 24 999473721 ps
T738 /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.1925280112 May 16 03:49:44 PM PDT 24 May 16 04:09:50 PM PDT 24 62096624098 ps
T425 /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.3042726473 May 16 03:41:28 PM PDT 24 May 16 03:42:27 PM PDT 24 574416932 ps
T97 /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.3062445204 May 16 03:38:54 PM PDT 24 May 16 03:48:24 PM PDT 24 15828731917 ps
T1180 /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.2834362269 May 16 03:39:29 PM PDT 24 May 16 03:41:16 PM PDT 24 10176499985 ps
T437 /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.823750824 May 16 03:48:44 PM PDT 24 May 16 03:49:02 PM PDT 24 139092403 ps
T510 /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.2272695775 May 16 03:47:04 PM PDT 24 May 16 03:47:32 PM PDT 24 550110481 ps
T426 /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.2626768754 May 16 03:42:02 PM PDT 24 May 16 03:49:03 PM PDT 24 37353556983 ps
T588 /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.1143836942 May 16 03:53:26 PM PDT 24 May 16 03:54:18 PM PDT 24 1253838268 ps
T179 /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.1430675720 May 16 03:39:55 PM PDT 24 May 16 04:51:22 PM PDT 24 29460220448 ps
T438 /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.1418710421 May 16 03:51:57 PM PDT 24 May 16 03:52:47 PM PDT 24 590639648 ps
T529 /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.3334407324 May 16 03:52:57 PM PDT 24 May 16 03:53:42 PM PDT 24 1129846636 ps
T520 /workspace/coverage/cover_reg_top/73.xbar_random.2529367325 May 16 03:50:20 PM PDT 24 May 16 03:50:50 PM PDT 24 292370753 ps
T1181 /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.2792420781 May 16 03:54:09 PM PDT 24 May 16 03:55:18 PM PDT 24 4200871912 ps
T744 /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.2925277751 May 16 03:47:23 PM PDT 24 May 16 03:58:48 PM PDT 24 36352716051 ps
T732 /workspace/coverage/cover_reg_top/46.xbar_access_same_device.1599277112 May 16 03:46:27 PM PDT 24 May 16 03:46:49 PM PDT 24 116909275 ps
T1182 /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.3785360074 May 16 03:43:43 PM PDT 24 May 16 03:45:23 PM PDT 24 9238423546 ps
T1183 /workspace/coverage/cover_reg_top/75.xbar_smoke.3962686014 May 16 03:50:43 PM PDT 24 May 16 03:50:54 PM PDT 24 213228140 ps
T569 /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.3597108842 May 16 03:54:17 PM PDT 24 May 16 03:56:05 PM PDT 24 9382722873 ps
T1184 /workspace/coverage/cover_reg_top/82.xbar_smoke.2174832498 May 16 03:51:48 PM PDT 24 May 16 03:52:00 PM PDT 24 216301480 ps
T501 /workspace/coverage/cover_reg_top/8.chip_tl_errors.1663954355 May 16 03:39:53 PM PDT 24 May 16 03:44:35 PM PDT 24 4601555167 ps
T503 /workspace/coverage/cover_reg_top/10.chip_tl_errors.1875304443 May 16 03:40:17 PM PDT 24 May 16 03:46:17 PM PDT 24 3924052812 ps
T1185 /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.83961725 May 16 03:43:28 PM PDT 24 May 16 03:44:59 PM PDT 24 5291020529 ps
T506 /workspace/coverage/cover_reg_top/12.chip_tl_errors.3351713413 May 16 03:40:45 PM PDT 24 May 16 03:45:53 PM PDT 24 4091723900 ps
T504 /workspace/coverage/cover_reg_top/3.chip_tl_errors.2342999628 May 16 03:39:02 PM PDT 24 May 16 03:42:11 PM PDT 24 3148050785 ps
T758 /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.3731277565 May 16 03:39:20 PM PDT 24 May 16 03:43:02 PM PDT 24 3294157239 ps
T463 /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.3516785643 May 16 03:50:41 PM PDT 24 May 16 03:51:37 PM PDT 24 602743266 ps
T1186 /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.4217126099 May 16 03:44:46 PM PDT 24 May 16 03:45:51 PM PDT 24 6229035400 ps
T540 /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.1689088846 May 16 03:51:04 PM PDT 24 May 16 04:12:44 PM PDT 24 104577210304 ps
T1187 /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.929662133 May 16 03:43:03 PM PDT 24 May 16 03:43:19 PM PDT 24 210926116 ps
T747 /workspace/coverage/cover_reg_top/74.xbar_access_same_device.551626798 May 16 03:50:35 PM PDT 24 May 16 03:52:27 PM PDT 24 2847632036 ps
T575 /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.538294432 May 16 03:47:38 PM PDT 24 May 16 04:00:11 PM PDT 24 42600465800 ps
T778 /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3083757125 May 16 03:40:33 PM PDT 24 May 16 03:45:36 PM PDT 24 819952531 ps
T405 /workspace/coverage/cover_reg_top/97.xbar_stress_all.3909081742 May 16 03:54:10 PM PDT 24 May 16 04:01:39 PM PDT 24 10225977758 ps
T741 /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.2508364649 May 16 03:44:04 PM PDT 24 May 16 03:47:20 PM PDT 24 435164536 ps
T350 /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.3347300542 May 16 03:39:03 PM PDT 24 May 16 03:57:42 PM PDT 24 11411677319 ps
T1188 /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.3398450395 May 16 03:52:50 PM PDT 24 May 16 03:52:58 PM PDT 24 51152478 ps
T545 /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.685915779 May 16 03:51:31 PM PDT 24 May 16 03:52:33 PM PDT 24 1576709866 ps
T525 /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.3799847386 May 16 03:43:20 PM PDT 24 May 16 04:27:07 PM PDT 24 138406245425 ps
T471 /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.2864213552 May 16 03:43:58 PM PDT 24 May 16 03:58:46 PM PDT 24 86292702925 ps
T546 /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.3969134617 May 16 03:49:23 PM PDT 24 May 16 03:49:49 PM PDT 24 193950309 ps
T411 /workspace/coverage/cover_reg_top/89.xbar_access_same_device.3151785041 May 16 03:52:52 PM PDT 24 May 16 03:54:51 PM PDT 24 3244605073 ps
T406 /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.895327612 May 16 03:39:46 PM PDT 24 May 16 03:45:04 PM PDT 24 2070392625 ps
T566 /workspace/coverage/cover_reg_top/46.xbar_random.397372172 May 16 03:46:20 PM PDT 24 May 16 03:46:55 PM PDT 24 813618929 ps
T347 /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1594885880 May 16 03:38:29 PM PDT 24 May 16 05:18:33 PM PDT 24 37278997784 ps
T580 /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.1203412948 May 16 03:46:07 PM PDT 24 May 16 03:49:09 PM PDT 24 5203818630 ps
T412 /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.1832475251 May 16 03:39:27 PM PDT 24 May 16 03:40:00 PM PDT 24 295577642 ps
T439 /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.79090029 May 16 03:42:45 PM PDT 24 May 16 03:56:06 PM PDT 24 80709036861 ps
T1189 /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.2474033728 May 16 03:43:29 PM PDT 24 May 16 03:43:41 PM PDT 24 143861102 ps
T755 /workspace/coverage/cover_reg_top/58.xbar_access_same_device.1478661620 May 16 03:48:19 PM PDT 24 May 16 03:48:41 PM PDT 24 217091606 ps
T1190 /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.220670965 May 16 03:46:00 PM PDT 24 May 16 03:48:30 PM PDT 24 4285628129 ps
T558 /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.1515194393 May 16 03:53:36 PM PDT 24 May 16 04:12:46 PM PDT 24 104870501527 ps
T552 /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.606651111 May 16 03:45:05 PM PDT 24 May 16 03:45:30 PM PDT 24 239204077 ps
T727 /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.1062504255 May 16 03:50:40 PM PDT 24 May 16 03:59:58 PM PDT 24 13899643518 ps
T456 /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3603997346 May 16 03:40:27 PM PDT 24 May 16 03:48:54 PM PDT 24 29202828632 ps
T1191 /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.2272610374 May 16 03:49:16 PM PDT 24 May 16 03:50:12 PM PDT 24 3274046765 ps
T414 /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.1061839125 May 16 03:43:46 PM PDT 24 May 16 03:44:36 PM PDT 24 528733676 ps
T769 /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.2523274307 May 16 03:46:32 PM PDT 24 May 16 03:47:41 PM PDT 24 132883804 ps
T449 /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.597494538 May 16 03:39:59 PM PDT 24 May 16 03:41:29 PM PDT 24 4845555177 ps
T461 /workspace/coverage/cover_reg_top/84.xbar_same_source.2822464316 May 16 03:52:10 PM PDT 24 May 16 03:53:02 PM PDT 24 1596769464 ps
T759 /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.1133181011 May 16 03:47:25 PM PDT 24 May 16 03:54:50 PM PDT 24 13971483200 ps
T547 /workspace/coverage/cover_reg_top/35.xbar_same_source.373429959 May 16 03:44:36 PM PDT 24 May 16 03:45:13 PM PDT 24 436995608 ps
T523 /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.2747597091 May 16 03:53:53 PM PDT 24 May 16 04:14:23 PM PDT 24 65901483166 ps
T1192 /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.1487198406 May 16 03:48:00 PM PDT 24 May 16 03:48:08 PM PDT 24 45195149 ps
T1193 /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.1801912111 May 16 03:53:40 PM PDT 24 May 16 03:54:04 PM PDT 24 194574483 ps
T1194 /workspace/coverage/cover_reg_top/0.xbar_error_random.1993451502 May 16 03:38:48 PM PDT 24 May 16 03:39:31 PM PDT 24 527500038 ps
T1195 /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.575013423 May 16 03:42:17 PM PDT 24 May 16 03:43:02 PM PDT 24 1030114959 ps
T1196 /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.248241515 May 16 03:49:02 PM PDT 24 May 16 03:50:34 PM PDT 24 5486758672 ps
T565 /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1824747055 May 16 03:39:27 PM PDT 24 May 16 03:40:22 PM PDT 24 1319511234 ps
T1197 /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.2662268747 May 16 03:53:50 PM PDT 24 May 16 03:55:26 PM PDT 24 8607474382 ps
T1198 /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.1914680360 May 16 03:43:20 PM PDT 24 May 16 03:44:50 PM PDT 24 5270449770 ps
T1199 /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.1972547654 May 16 03:51:03 PM PDT 24 May 16 03:51:18 PM PDT 24 147294734 ps
T1200 /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.3551788282 May 16 03:51:07 PM PDT 24 May 16 03:51:43 PM PDT 24 299426567 ps
T1201 /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.4046376771 May 16 03:44:56 PM PDT 24 May 16 03:45:28 PM PDT 24 796919429 ps
T722 /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.462942317 May 16 03:45:58 PM PDT 24 May 16 04:13:59 PM PDT 24 96304957180 ps
T408 /workspace/coverage/cover_reg_top/43.xbar_stress_all.2235331307 May 16 03:46:00 PM PDT 24 May 16 03:53:19 PM PDT 24 11310540543 ps
T93 /workspace/coverage/cover_reg_top/5.chip_csr_rw.3216228172 May 16 03:39:27 PM PDT 24 May 16 03:44:37 PM PDT 24 3949055645 ps
T537 /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.3054423260 May 16 03:54:27 PM PDT 24 May 16 04:03:57 PM PDT 24 35374431108 ps
T416 /workspace/coverage/cover_reg_top/9.xbar_stress_all.3767233372 May 16 03:40:09 PM PDT 24 May 16 03:48:51 PM PDT 24 11833646929 ps
T1202 /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.3043024460 May 16 03:49:08 PM PDT 24 May 16 03:49:54 PM PDT 24 471487031 ps
T1203 /workspace/coverage/cover_reg_top/87.xbar_smoke.1802056335 May 16 03:52:41 PM PDT 24 May 16 03:52:51 PM PDT 24 178332127 ps
T723 /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.3500969630 May 16 03:53:50 PM PDT 24 May 16 03:58:31 PM PDT 24 3558240530 ps
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