| T1270 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.1785086261 |
|
|
Oct 15 10:00:21 PM UTC 24 |
Oct 15 10:07:57 PM UTC 24 |
6215837988 ps |
| T1271 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4019211768 |
|
|
Oct 15 09:50:15 PM UTC 24 |
Oct 15 10:08:33 PM UTC 24 |
9071883218 ps |
| T1272 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2402048690 |
|
|
Oct 15 10:01:20 PM UTC 24 |
Oct 15 10:08:42 PM UTC 24 |
6411575240 ps |
| T1273 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_rma.2940042627 |
|
|
Oct 15 10:01:42 PM UTC 24 |
Oct 15 10:09:04 PM UTC 24 |
4919488319 ps |
| T1274 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.595486883 |
|
|
Oct 15 08:29:41 PM UTC 24 |
Oct 15 10:09:10 PM UTC 24 |
42851498769 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.4102528765 |
|
|
Oct 15 04:47:51 PM UTC 24 |
Oct 15 10:10:50 PM UTC 24 |
82064048260 ps |
| T1275 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1090646124 |
|
|
Oct 15 08:53:37 PM UTC 24 |
Oct 15 10:10:57 PM UTC 24 |
18880427741 ps |
| T1276 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2131705069 |
|
|
Oct 15 09:58:45 PM UTC 24 |
Oct 15 10:11:43 PM UTC 24 |
4956826650 ps |
| T1277 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.3617618758 |
|
|
Oct 15 10:04:17 PM UTC 24 |
Oct 15 10:12:17 PM UTC 24 |
4092328564 ps |
| T1278 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1215475029 |
|
|
Oct 15 09:18:35 PM UTC 24 |
Oct 15 10:12:25 PM UTC 24 |
22800567829 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1000616921 |
|
|
Oct 15 10:05:36 PM UTC 24 |
Oct 15 10:12:51 PM UTC 24 |
3986497304 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.1327665551 |
|
|
Oct 15 10:03:34 PM UTC 24 |
Oct 15 10:13:30 PM UTC 24 |
5500540812 ps |
| T1279 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.1507905370 |
|
|
Oct 15 10:05:06 PM UTC 24 |
Oct 15 10:13:39 PM UTC 24 |
8068697466 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.390962482 |
|
|
Oct 15 10:01:41 PM UTC 24 |
Oct 15 10:13:39 PM UTC 24 |
5946366440 ps |
| T1280 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.2879419343 |
|
|
Oct 15 09:52:08 PM UTC 24 |
Oct 15 10:14:44 PM UTC 24 |
10514264357 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.507381697 |
|
|
Oct 15 10:08:58 PM UTC 24 |
Oct 15 10:14:48 PM UTC 24 |
3840972632 ps |
| T1281 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.4213252659 |
|
|
Oct 15 08:35:02 PM UTC 24 |
Oct 15 10:16:09 PM UTC 24 |
50529705420 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.432023628 |
|
|
Oct 15 10:06:33 PM UTC 24 |
Oct 15 10:16:51 PM UTC 24 |
4796317180 ps |
| T1282 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_prod.2206000481 |
|
|
Oct 15 09:52:41 PM UTC 24 |
Oct 15 10:17:12 PM UTC 24 |
13948564667 ps |
| T1283 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1021175339 |
|
|
Oct 15 09:49:41 PM UTC 24 |
Oct 15 10:17:21 PM UTC 24 |
8292658968 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3010181257 |
|
|
Oct 15 10:10:06 PM UTC 24 |
Oct 15 10:17:25 PM UTC 24 |
3955000142 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.3248569339 |
|
|
Oct 15 10:03:35 PM UTC 24 |
Oct 15 10:18:02 PM UTC 24 |
6167283948 ps |
| T1284 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.1466236771 |
|
|
Oct 15 10:10:10 PM UTC 24 |
Oct 15 10:18:46 PM UTC 24 |
3426312680 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.2662309608 |
|
|
Oct 15 10:10:10 PM UTC 24 |
Oct 15 10:18:55 PM UTC 24 |
5317612040 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3532515626 |
|
|
Oct 15 10:11:44 PM UTC 24 |
Oct 15 10:19:11 PM UTC 24 |
3686549224 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.178018988 |
|
|
Oct 15 10:08:54 PM UTC 24 |
Oct 15 10:19:24 PM UTC 24 |
3684155570 ps |
| T1285 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.3724466307 |
|
|
Oct 15 08:08:26 PM UTC 24 |
Oct 15 10:19:24 PM UTC 24 |
27644223412 ps |
| T1286 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.177306171 |
|
|
Oct 15 10:11:43 PM UTC 24 |
Oct 15 10:21:04 PM UTC 24 |
5023775669 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.3201048998 |
|
|
Oct 15 10:08:53 PM UTC 24 |
Oct 15 10:21:37 PM UTC 24 |
6258504276 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.616379289 |
|
|
Oct 15 10:14:36 PM UTC 24 |
Oct 15 10:21:43 PM UTC 24 |
4541811966 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3449186825 |
|
|
Oct 15 10:15:35 PM UTC 24 |
Oct 15 10:23:03 PM UTC 24 |
4006900192 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.2483181346 |
|
|
Oct 15 10:09:33 PM UTC 24 |
Oct 15 10:23:08 PM UTC 24 |
5952746132 ps |
| T1287 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.59841402 |
|
|
Oct 15 10:14:36 PM UTC 24 |
Oct 15 10:24:05 PM UTC 24 |
4064587652 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.662945338 |
|
|
Oct 15 10:13:12 PM UTC 24 |
Oct 15 10:24:30 PM UTC 24 |
6058623200 ps |
| T1288 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2496514348 |
|
|
Oct 15 10:18:13 PM UTC 24 |
Oct 15 10:24:33 PM UTC 24 |
3434464456 ps |
| T1289 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.204182585 |
|
|
Oct 15 10:07:45 PM UTC 24 |
Oct 15 10:25:08 PM UTC 24 |
9930382011 ps |
| T1290 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.3727300257 |
|
|
Oct 15 10:18:18 PM UTC 24 |
Oct 15 10:25:11 PM UTC 24 |
5645285237 ps |
| T1291 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.241259437 |
|
|
Oct 15 10:17:34 PM UTC 24 |
Oct 15 10:26:07 PM UTC 24 |
4286863356 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.2908727821 |
|
|
Oct 15 09:10:59 PM UTC 24 |
Oct 15 10:26:19 PM UTC 24 |
16007685384 ps |
| T1292 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.443917744 |
|
|
Oct 15 10:10:09 PM UTC 24 |
Oct 15 10:26:39 PM UTC 24 |
9067523307 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.27839123 |
|
|
Oct 15 10:20:27 PM UTC 24 |
Oct 15 10:27:18 PM UTC 24 |
3679802440 ps |
| T1293 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.1229689052 |
|
|
Oct 15 10:18:42 PM UTC 24 |
Oct 15 10:27:27 PM UTC 24 |
3387401728 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3767851500 |
|
|
Oct 15 10:20:25 PM UTC 24 |
Oct 15 10:28:23 PM UTC 24 |
4049596738 ps |
| T1294 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.3508195654 |
|
|
Oct 15 10:20:29 PM UTC 24 |
Oct 15 10:28:32 PM UTC 24 |
5729419782 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.2040927038 |
|
|
Oct 15 10:16:52 PM UTC 24 |
Oct 15 10:28:57 PM UTC 24 |
6193441520 ps |
| T1295 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.4060134710 |
|
|
Oct 15 10:09:33 PM UTC 24 |
Oct 15 10:29:02 PM UTC 24 |
10109993894 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.492563653 |
|
|
Oct 15 10:22:32 PM UTC 24 |
Oct 15 10:29:14 PM UTC 24 |
3646073626 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.28068873 |
|
|
Oct 15 10:23:59 PM UTC 24 |
Oct 15 10:29:47 PM UTC 24 |
3902897848 ps |
| T1296 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.3959292507 |
|
|
Oct 15 08:36:38 PM UTC 24 |
Oct 15 10:30:00 PM UTC 24 |
46070438860 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.3081544491 |
|
|
Oct 15 10:20:24 PM UTC 24 |
Oct 15 10:30:14 PM UTC 24 |
5023516354 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.2558051558 |
|
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Oct 15 10:18:18 PM UTC 24 |
Oct 15 10:30:55 PM UTC 24 |
6493281880 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3471067837 |
|
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Oct 15 10:25:23 PM UTC 24 |
Oct 15 10:31:26 PM UTC 24 |
3490333918 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.2458382729 |
|
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Oct 15 10:22:32 PM UTC 24 |
Oct 15 10:31:52 PM UTC 24 |
6403417896 ps |
| T1297 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.1513640340 |
|
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Oct 15 10:13:32 PM UTC 24 |
Oct 15 10:32:04 PM UTC 24 |
11210666113 ps |
| T1298 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.568638360 |
|
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Oct 15 10:23:59 PM UTC 24 |
Oct 15 10:32:51 PM UTC 24 |
3940581928 ps |
| T1299 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3341293253 |
|
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Oct 15 09:38:27 PM UTC 24 |
Oct 15 10:33:04 PM UTC 24 |
11621205200 ps |
| T1300 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.2841289991 |
|
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Oct 15 10:15:35 PM UTC 24 |
Oct 15 10:33:14 PM UTC 24 |
10183878993 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1989527254 |
|
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Oct 15 10:27:00 PM UTC 24 |
Oct 15 10:33:32 PM UTC 24 |
4045619400 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.16660305 |
|
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Oct 15 10:21:10 PM UTC 24 |
Oct 15 10:34:18 PM UTC 24 |
6079826100 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.591363062 |
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Oct 15 10:28:12 PM UTC 24 |
Oct 15 10:34:47 PM UTC 24 |
3182026744 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.2595303033 |
|
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Oct 15 10:26:03 PM UTC 24 |
Oct 15 10:34:51 PM UTC 24 |
4195585880 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.677545201 |
|
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Oct 15 10:27:03 PM UTC 24 |
Oct 15 10:35:34 PM UTC 24 |
3845282432 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.2876946232 |
|
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Oct 15 10:24:49 PM UTC 24 |
Oct 15 10:35:36 PM UTC 24 |
5036918928 ps |
| T1301 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.1671695160 |
|
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Oct 15 10:25:23 PM UTC 24 |
Oct 15 10:35:41 PM UTC 24 |
4120638168 ps |
| T1302 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.3605399600 |
|
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Oct 15 10:09:32 PM UTC 24 |
Oct 15 10:35:49 PM UTC 24 |
7628478112 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3704845956 |
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Oct 15 10:29:18 PM UTC 24 |
Oct 15 10:35:57 PM UTC 24 |
3901718792 ps |
| T1303 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.652145862 |
|
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Oct 15 10:10:03 PM UTC 24 |
Oct 15 10:36:16 PM UTC 24 |
8455395400 ps |
| T1304 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.2796502384 |
|
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Oct 15 08:34:51 PM UTC 24 |
Oct 15 10:36:31 PM UTC 24 |
46929011893 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1602693643 |
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Oct 15 10:30:04 PM UTC 24 |
Oct 15 10:36:36 PM UTC 24 |
3494446120 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.3027620644 |
|
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Oct 15 10:28:13 PM UTC 24 |
Oct 15 10:36:48 PM UTC 24 |
4436472764 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.4201940802 |
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Oct 15 10:30:07 PM UTC 24 |
Oct 15 10:38:13 PM UTC 24 |
4087469534 ps |
| T1305 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.4202656165 |
|
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Oct 15 10:07:43 PM UTC 24 |
Oct 15 10:38:17 PM UTC 24 |
8236494950 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3505655100 |
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Oct 15 10:30:43 PM UTC 24 |
Oct 15 10:38:18 PM UTC 24 |
3718763672 ps |
| T1306 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.990005011 |
|
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Oct 15 10:20:24 PM UTC 24 |
Oct 15 10:38:24 PM UTC 24 |
12153899036 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2113796347 |
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Oct 15 10:31:35 PM UTC 24 |
Oct 15 10:38:25 PM UTC 24 |
3936063752 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.3179621641 |
|
|
Oct 15 10:29:19 PM UTC 24 |
Oct 15 10:38:58 PM UTC 24 |
4419994400 ps |
| T1307 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.888879399 |
|
|
Oct 15 09:38:22 PM UTC 24 |
Oct 15 10:39:11 PM UTC 24 |
22712839077 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.527018359 |
|
|
Oct 15 10:32:46 PM UTC 24 |
Oct 15 10:39:31 PM UTC 24 |
3962262554 ps |
| T1308 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.3193090126 |
|
|
Oct 15 10:13:12 PM UTC 24 |
Oct 15 10:39:36 PM UTC 24 |
8732065240 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3597849758 |
|
|
Oct 15 10:34:12 PM UTC 24 |
Oct 15 10:39:58 PM UTC 24 |
2963512466 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.119092272 |
|
|
Oct 15 10:34:18 PM UTC 24 |
Oct 15 10:40:04 PM UTC 24 |
3866214292 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.2161020547 |
|
|
Oct 15 10:30:39 PM UTC 24 |
Oct 15 10:40:24 PM UTC 24 |
5112469568 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2466573803 |
|
|
Oct 15 10:34:12 PM UTC 24 |
Oct 15 10:40:34 PM UTC 24 |
4331924312 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.2334104956 |
|
|
Oct 15 10:30:59 PM UTC 24 |
Oct 15 10:40:42 PM UTC 24 |
6232942086 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.2405015778 |
|
|
Oct 15 10:32:09 PM UTC 24 |
Oct 15 10:40:47 PM UTC 24 |
5999285592 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.1917520292 |
|
|
Oct 15 10:32:49 PM UTC 24 |
Oct 15 10:41:06 PM UTC 24 |
4422611016 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.3153499393 |
|
|
Oct 15 10:30:04 PM UTC 24 |
Oct 15 10:41:57 PM UTC 24 |
5683655082 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3305498976 |
|
|
Oct 15 10:35:41 PM UTC 24 |
Oct 15 10:42:56 PM UTC 24 |
4173669864 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.222370054 |
|
|
Oct 15 10:35:02 PM UTC 24 |
Oct 15 10:43:43 PM UTC 24 |
5215438732 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.2197506262 |
|
|
Oct 15 10:34:01 PM UTC 24 |
Oct 15 10:43:59 PM UTC 24 |
4437632344 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1858436371 |
|
|
Oct 15 10:37:58 PM UTC 24 |
Oct 15 10:44:00 PM UTC 24 |
3837732274 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3545469798 |
|
|
Oct 15 10:37:38 PM UTC 24 |
Oct 15 10:44:06 PM UTC 24 |
4145415736 ps |
| T1309 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.2128110455 |
|
|
Oct 15 09:38:20 PM UTC 24 |
Oct 15 10:45:13 PM UTC 24 |
14089596274 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.1168899229 |
|
|
Oct 15 10:34:17 PM UTC 24 |
Oct 15 10:45:22 PM UTC 24 |
6485521230 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2280897673 |
|
|
Oct 15 10:38:01 PM UTC 24 |
Oct 15 10:45:36 PM UTC 24 |
3200280990 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.102079367 |
|
|
Oct 15 10:37:53 PM UTC 24 |
Oct 15 10:45:40 PM UTC 24 |
5280920360 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3178407757 |
|
|
Oct 15 10:39:58 PM UTC 24 |
Oct 15 10:46:04 PM UTC 24 |
4011025118 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_rst_inputs.602297410 |
|
|
Oct 15 09:35:11 PM UTC 24 |
Oct 15 10:46:12 PM UTC 24 |
25321085272 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1997275097 |
|
|
Oct 15 10:40:01 PM UTC 24 |
Oct 15 10:46:20 PM UTC 24 |
3774582352 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.1402484550 |
|
|
Oct 15 10:35:41 PM UTC 24 |
Oct 15 10:46:24 PM UTC 24 |
5151203308 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.950645652 |
|
|
Oct 15 10:37:58 PM UTC 24 |
Oct 15 10:46:27 PM UTC 24 |
3449419880 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.398366835 |
|
|
Oct 15 10:41:37 PM UTC 24 |
Oct 15 10:47:04 PM UTC 24 |
3794780414 ps |
| T1310 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.1577237869 |
|
|
Oct 15 10:21:45 PM UTC 24 |
Oct 15 10:47:04 PM UTC 24 |
8265202430 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3182184232 |
|
|
Oct 15 10:40:18 PM UTC 24 |
Oct 15 10:47:20 PM UTC 24 |
3481371800 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1086030753 |
|
|
Oct 15 10:41:56 PM UTC 24 |
Oct 15 10:48:32 PM UTC 24 |
3927185800 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2128782994 |
|
|
Oct 15 10:42:10 PM UTC 24 |
Oct 15 10:48:47 PM UTC 24 |
3970058336 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1197410477 |
|
|
Oct 15 10:42:15 PM UTC 24 |
Oct 15 10:48:51 PM UTC 24 |
3739890344 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.3451212320 |
|
|
Oct 15 10:40:17 PM UTC 24 |
Oct 15 10:49:18 PM UTC 24 |
4845297172 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.4197381152 |
|
|
Oct 15 10:27:20 PM UTC 24 |
Oct 15 10:49:35 PM UTC 24 |
8686170586 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1911288685 |
|
|
Oct 15 10:42:09 PM UTC 24 |
Oct 15 10:49:39 PM UTC 24 |
4606625506 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.3142889702 |
|
|
Oct 15 10:37:38 PM UTC 24 |
Oct 15 10:49:54 PM UTC 24 |
5017878040 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.1650984749 |
|
|
Oct 15 09:36:40 PM UTC 24 |
Oct 15 10:50:21 PM UTC 24 |
15252326368 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1873193292 |
|
|
Oct 15 10:43:38 PM UTC 24 |
Oct 15 10:50:23 PM UTC 24 |
4257153934 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.834106135 |
|
|
Oct 15 09:40:23 PM UTC 24 |
Oct 15 10:50:41 PM UTC 24 |
14893165636 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1377784423 |
|
|
Oct 15 09:39:32 PM UTC 24 |
Oct 15 10:50:43 PM UTC 24 |
15924164006 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.220708375 |
|
|
Oct 15 10:37:38 PM UTC 24 |
Oct 15 10:50:48 PM UTC 24 |
5125329700 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3366383931 |
|
|
Oct 15 10:45:04 PM UTC 24 |
Oct 15 10:51:13 PM UTC 24 |
3360424784 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.3589078227 |
|
|
Oct 15 10:38:01 PM UTC 24 |
Oct 15 10:51:16 PM UTC 24 |
5793661616 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.1698128603 |
|
|
Oct 15 10:40:34 PM UTC 24 |
Oct 15 10:51:17 PM UTC 24 |
6105770674 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.2365758647 |
|
|
Oct 15 10:40:37 PM UTC 24 |
Oct 15 10:51:20 PM UTC 24 |
6229419510 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.2895579762 |
|
|
Oct 15 10:41:53 PM UTC 24 |
Oct 15 10:51:32 PM UTC 24 |
5344765838 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.2871328632 |
|
|
Oct 15 10:40:36 PM UTC 24 |
Oct 15 10:51:54 PM UTC 24 |
5160876940 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3560595476 |
|
|
Oct 15 10:45:04 PM UTC 24 |
Oct 15 10:51:54 PM UTC 24 |
3688791224 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.3132211035 |
|
|
Oct 15 10:40:03 PM UTC 24 |
Oct 15 10:52:13 PM UTC 24 |
5395883488 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.3526116750 |
|
|
Oct 15 10:42:40 PM UTC 24 |
Oct 15 10:52:35 PM UTC 24 |
5111219180 ps |
| T1311 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.339706323 |
|
|
Oct 15 09:39:56 PM UTC 24 |
Oct 15 10:52:56 PM UTC 24 |
15763530882 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3798836494 |
|
|
Oct 15 10:46:33 PM UTC 24 |
Oct 15 10:53:13 PM UTC 24 |
3868617320 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1349512080 |
|
|
Oct 15 10:47:20 PM UTC 24 |
Oct 15 10:53:14 PM UTC 24 |
4306073020 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.1365422884 |
|
|
Oct 15 10:41:56 PM UTC 24 |
Oct 15 10:53:16 PM UTC 24 |
5070140400 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1686735615 |
|
|
Oct 15 10:47:35 PM UTC 24 |
Oct 15 10:53:33 PM UTC 24 |
4242827712 ps |
| T1312 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1038757700 |
|
|
Oct 15 09:40:14 PM UTC 24 |
Oct 15 10:53:34 PM UTC 24 |
15251314462 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.3470243632 |
|
|
Oct 15 10:44:27 PM UTC 24 |
Oct 15 10:53:51 PM UTC 24 |
5122193908 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.170880096 |
|
|
Oct 15 10:47:23 PM UTC 24 |
Oct 15 10:53:56 PM UTC 24 |
3394074142 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.555130794 |
|
|
Oct 15 10:45:31 PM UTC 24 |
Oct 15 10:54:18 PM UTC 24 |
5214301368 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.4254099632 |
|
|
Oct 15 10:48:08 PM UTC 24 |
Oct 15 10:54:19 PM UTC 24 |
3596959580 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3203940945 |
|
|
Oct 15 09:35:24 PM UTC 24 |
Oct 15 10:54:45 PM UTC 24 |
24820278400 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.1792008158 |
|
|
Oct 15 10:46:16 PM UTC 24 |
Oct 15 10:54:48 PM UTC 24 |
4317825912 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.4172476632 |
|
|
Oct 15 10:48:23 PM UTC 24 |
Oct 15 10:54:49 PM UTC 24 |
4208301870 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.3628277146 |
|
|
Oct 15 10:44:59 PM UTC 24 |
Oct 15 10:55:12 PM UTC 24 |
5220722328 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.3962169476 |
|
|
Oct 15 10:42:15 PM UTC 24 |
Oct 15 10:55:12 PM UTC 24 |
6501245002 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.632822454 |
|
|
Oct 15 10:47:35 PM UTC 24 |
Oct 15 10:55:15 PM UTC 24 |
5019825460 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.2307870351 |
|
|
Oct 15 10:46:44 PM UTC 24 |
Oct 15 10:55:24 PM UTC 24 |
4999225228 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.4287966346 |
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|
Oct 15 10:48:21 PM UTC 24 |
Oct 15 10:55:26 PM UTC 24 |
3705499870 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3148506608 |
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|
Oct 15 10:49:57 PM UTC 24 |
Oct 15 10:55:55 PM UTC 24 |
3681629514 ps |
| T1313 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.2709814600 |
|
|
Oct 15 09:40:04 PM UTC 24 |
Oct 15 10:55:58 PM UTC 24 |
16134085480 ps |
| T1314 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.273477011 |
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|
Oct 15 09:39:36 PM UTC 24 |
Oct 15 10:55:58 PM UTC 24 |
15041573560 ps |
| T1315 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.3005151917 |
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|
Oct 15 09:38:45 PM UTC 24 |
Oct 15 10:56:00 PM UTC 24 |
15805258223 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.1125165541 |
|
|
Oct 15 10:48:24 PM UTC 24 |
Oct 15 10:56:20 PM UTC 24 |
5415452712 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1639522746 |
|
|
Oct 15 10:50:38 PM UTC 24 |
Oct 15 10:56:26 PM UTC 24 |
3887664696 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2362154924 |
|
|
Oct 15 10:51:08 PM UTC 24 |
Oct 15 10:56:40 PM UTC 24 |
4269291016 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.330841002 |
|
|
Oct 15 10:49:43 PM UTC 24 |
Oct 15 10:56:52 PM UTC 24 |
3915419570 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1166310956 |
|
|
Oct 15 10:51:52 PM UTC 24 |
Oct 15 10:57:05 PM UTC 24 |
3574412596 ps |
| T1316 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.2499127293 |
|
|
Oct 15 09:39:53 PM UTC 24 |
Oct 15 10:58:06 PM UTC 24 |
17408248304 ps |
| T1317 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.3312993625 |
|
|
Oct 15 10:49:43 PM UTC 24 |
Oct 15 10:58:06 PM UTC 24 |
5241610432 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1630914142 |
|
|
Oct 15 10:53:51 PM UTC 24 |
Oct 15 10:58:42 PM UTC 24 |
4099794800 ps |
| T1318 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.764266605 |
|
|
Oct 15 10:48:23 PM UTC 24 |
Oct 15 10:58:54 PM UTC 24 |
5834398440 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2915817259 |
|
|
Oct 15 10:54:54 PM UTC 24 |
Oct 15 10:59:11 PM UTC 24 |
3354000500 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.1013339507 |
|
|
Oct 15 10:48:20 PM UTC 24 |
Oct 15 10:59:15 PM UTC 24 |
5206489264 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2264518898 |
|
|
Oct 15 10:54:42 PM UTC 24 |
Oct 15 10:59:33 PM UTC 24 |
2997541648 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1639480403 |
|
|
Oct 15 10:53:51 PM UTC 24 |
Oct 15 10:59:43 PM UTC 24 |
4034339352 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.2360048889 |
|
|
Oct 15 10:50:41 PM UTC 24 |
Oct 15 11:00:12 PM UTC 24 |
5706825620 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.204979198 |
|
|
Oct 15 10:49:38 PM UTC 24 |
Oct 15 11:00:44 PM UTC 24 |
4872277640 ps |
| T1319 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.1363299788 |
|
|
Oct 15 10:50:42 PM UTC 24 |
Oct 15 11:00:51 PM UTC 24 |
5919351560 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_all_escalation_resets.621482425 |
|
|
Oct 15 10:51:17 PM UTC 24 |
Oct 15 11:01:24 PM UTC 24 |
5686248972 ps |
| T1320 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.2008238552 |
|
|
Oct 15 09:51:41 PM UTC 24 |
Oct 15 11:01:53 PM UTC 24 |
15277956620 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3596164703 |
|
|
Oct 15 10:56:21 PM UTC 24 |
Oct 15 11:01:58 PM UTC 24 |
4215851080 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2334220516 |
|
|
Oct 15 10:55:34 PM UTC 24 |
Oct 15 11:01:59 PM UTC 24 |
3582408500 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.4094483874 |
|
|
Oct 15 10:54:20 PM UTC 24 |
Oct 15 11:02:05 PM UTC 24 |
5064282400 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.193684102 |
|
|
Oct 15 10:55:35 PM UTC 24 |
Oct 15 11:02:38 PM UTC 24 |
4228226850 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.812938731 |
|
|
Oct 15 10:53:37 PM UTC 24 |
Oct 15 11:03:00 PM UTC 24 |
5861313928 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3109344091 |
|
|
Oct 15 10:56:59 PM UTC 24 |
Oct 15 11:03:02 PM UTC 24 |
4487211396 ps |
| T1321 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.730763834 |
|
|
Oct 15 10:52:55 PM UTC 24 |
Oct 15 11:03:10 PM UTC 24 |
6179600150 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.3227320768 |
|
|
Oct 15 10:55:01 PM UTC 24 |
Oct 15 11:03:32 PM UTC 24 |
6040692368 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.34010235 |
|
|
Oct 15 10:56:55 PM UTC 24 |
Oct 15 11:03:37 PM UTC 24 |
3845998616 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.3150889338 |
|
|
Oct 15 10:53:51 PM UTC 24 |
Oct 15 11:03:44 PM UTC 24 |
5142531482 ps |
| T1322 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2915323859 |
|
|
Oct 15 10:58:09 PM UTC 24 |
Oct 15 11:04:02 PM UTC 24 |
3968344436 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.3260543943 |
|
|
Oct 15 10:53:06 PM UTC 24 |
Oct 15 11:04:17 PM UTC 24 |
5500048090 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3853398469 |
|
|
Oct 15 10:58:07 PM UTC 24 |
Oct 15 11:04:17 PM UTC 24 |
4221065064 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2915940205 |
|
|
Oct 15 10:58:25 PM UTC 24 |
Oct 15 11:04:19 PM UTC 24 |
3657751640 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.1119243745 |
|
|
Oct 15 10:54:17 PM UTC 24 |
Oct 15 11:04:30 PM UTC 24 |
5811576496 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.939306642 |
|
|
Oct 15 10:58:22 PM UTC 24 |
Oct 15 11:04:30 PM UTC 24 |
3626442388 ps |
| T1323 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.201392921 |
|
|
Oct 15 10:58:13 PM UTC 24 |
Oct 15 11:04:51 PM UTC 24 |
4008970406 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2326177242 |
|
|
Oct 15 10:58:52 PM UTC 24 |
Oct 15 11:04:57 PM UTC 24 |
3606616716 ps |
| T1324 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.2484842802 |
|
|
Oct 15 10:20:26 PM UTC 24 |
Oct 15 11:05:16 PM UTC 24 |
12933328672 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1370450456 |
|
|
Oct 15 10:58:06 PM UTC 24 |
Oct 15 11:05:24 PM UTC 24 |
4132895608 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3290963762 |
|
|
Oct 15 10:58:12 PM UTC 24 |
Oct 15 11:05:31 PM UTC 24 |
4277552408 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.2076576586 |
|
|
Oct 15 10:56:12 PM UTC 24 |
Oct 15 11:05:34 PM UTC 24 |
4144963360 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1205419174 |
|
|
Oct 15 10:58:10 PM UTC 24 |
Oct 15 11:05:42 PM UTC 24 |
3313833844 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2185260884 |
|
|
Oct 15 10:58:07 PM UTC 24 |
Oct 15 11:05:46 PM UTC 24 |
3859265220 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2000777839 |
|
|
Oct 15 10:58:26 PM UTC 24 |
Oct 15 11:06:00 PM UTC 24 |
4426394024 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1987429364 |
|
|
Oct 15 11:00:00 PM UTC 24 |
Oct 15 11:06:06 PM UTC 24 |
3715356296 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.140877038 |
|
|
Oct 15 10:58:24 PM UTC 24 |
Oct 15 11:06:30 PM UTC 24 |
4833927552 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.1560764974 |
|
|
Oct 15 10:58:18 PM UTC 24 |
Oct 15 11:06:31 PM UTC 24 |
5102780264 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.458649141 |
|
|
Oct 15 10:58:01 PM UTC 24 |
Oct 15 11:06:34 PM UTC 24 |
4386852500 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.3434289561 |
|
|
Oct 15 10:58:13 PM UTC 24 |
Oct 15 11:06:38 PM UTC 24 |
5073294822 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2955508926 |
|
|
Oct 15 11:00:26 PM UTC 24 |
Oct 15 11:06:38 PM UTC 24 |
3908311164 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.3920886767 |
|
|
Oct 15 10:57:00 PM UTC 24 |
Oct 15 11:06:49 PM UTC 24 |
5930192000 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.4191014423 |
|
|
Oct 15 10:57:16 PM UTC 24 |
Oct 15 11:06:55 PM UTC 24 |
5154152896 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.919509276 |
|
|
Oct 15 10:58:19 PM UTC 24 |
Oct 15 11:07:05 PM UTC 24 |
4967954448 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.2101484267 |
|
|
Oct 15 10:58:26 PM UTC 24 |
Oct 15 11:07:09 PM UTC 24 |
4060025254 ps |
| T1325 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3303234551 |
|
|
Oct 15 10:59:35 PM UTC 24 |
Oct 15 11:07:37 PM UTC 24 |
4502778332 ps |
| T1326 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.2191705677 |
|
|
Oct 15 10:58:51 PM UTC 24 |
Oct 15 11:07:38 PM UTC 24 |
5364769240 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.1454342361 |
|
|
Oct 15 10:59:33 PM UTC 24 |
Oct 15 11:07:44 PM UTC 24 |
5484508624 ps |
| T1327 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1635100326 |
|
|
Oct 15 11:01:38 PM UTC 24 |
Oct 15 11:07:48 PM UTC 24 |
3629084264 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.399483852 |
|
|
Oct 15 10:58:03 PM UTC 24 |
Oct 15 11:07:49 PM UTC 24 |
4946909864 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.3781342505 |
|
|
Oct 15 10:58:06 PM UTC 24 |
Oct 15 11:08:01 PM UTC 24 |
6345910278 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.3803035509 |
|
|
Oct 15 11:00:00 PM UTC 24 |
Oct 15 11:08:19 PM UTC 24 |
5667604032 ps |
| T1328 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.3808528124 |
|
|
Oct 15 10:58:18 PM UTC 24 |
Oct 15 11:08:25 PM UTC 24 |
4829692234 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.170185992 |
|
|
Oct 15 11:02:06 PM UTC 24 |
Oct 15 11:08:26 PM UTC 24 |
4104400564 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2973973761 |
|
|
Oct 15 11:03:24 PM UTC 24 |
Oct 15 11:08:54 PM UTC 24 |
4386455118 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.708284735 |
|
|
Oct 15 11:03:26 PM UTC 24 |
Oct 15 11:09:19 PM UTC 24 |
4200919128 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2543311347 |
|
|
Oct 15 11:04:11 PM UTC 24 |
Oct 15 11:09:35 PM UTC 24 |
4202946462 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1725601181 |
|
|
Oct 15 11:05:41 PM UTC 24 |
Oct 15 11:10:17 PM UTC 24 |
3258770876 ps |
| T1329 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.1817424469 |
|
|
Oct 15 11:00:26 PM UTC 24 |
Oct 15 11:10:28 PM UTC 24 |
6385128690 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.1294446426 |
|
|
Oct 15 11:01:08 PM UTC 24 |
Oct 15 11:10:31 PM UTC 24 |
5677287428 ps |
| T1330 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.4155589068 |
|
|
Oct 15 10:26:04 PM UTC 24 |
Oct 15 11:10:46 PM UTC 24 |
13042370728 ps |
| T1331 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.3422062687 |
|
|
Oct 15 11:01:38 PM UTC 24 |
Oct 15 11:11:01 PM UTC 24 |
5795231644 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.596570444 |
|
|
Oct 15 11:05:07 PM UTC 24 |
Oct 15 11:11:17 PM UTC 24 |
4358463416 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.4253013779 |
|
|
Oct 15 11:04:12 PM UTC 24 |
Oct 15 11:11:33 PM UTC 24 |
4700165964 ps |
| T1332 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.1131146301 |
|
|
Oct 15 11:03:25 PM UTC 24 |
Oct 15 11:11:59 PM UTC 24 |
4654069828 ps |
| T1333 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.3971373294 |
|
|
Oct 15 11:03:16 PM UTC 24 |
Oct 15 11:12:13 PM UTC 24 |
6785404268 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3846036497 |
|
|
Oct 15 11:07:01 PM UTC 24 |
Oct 15 11:12:28 PM UTC 24 |
4316701992 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.888964536 |
|
|
Oct 15 11:06:11 PM UTC 24 |
Oct 15 11:12:53 PM UTC 24 |
5083316670 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.3243796038 |
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Oct 15 11:04:56 PM UTC 24 |
Oct 15 11:12:54 PM UTC 24 |
4907967456 ps |
| T1334 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_all_escalation_resets.2362854993 |
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Oct 15 11:06:52 PM UTC 24 |
Oct 15 11:13:01 PM UTC 24 |
4042040312 ps |
| T1335 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.3999264183 |
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Oct 15 11:03:20 PM UTC 24 |
Oct 15 11:13:32 PM UTC 24 |
6397795392 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.2735633508 |
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Oct 15 11:06:53 PM UTC 24 |
Oct 15 11:13:44 PM UTC 24 |
6387062828 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.2527442964 |
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Oct 15 11:07:07 PM UTC 24 |
Oct 15 11:13:47 PM UTC 24 |
4650068124 ps |
| T1336 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.2820231328 |
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Oct 15 11:07:02 PM UTC 24 |
Oct 15 11:14:19 PM UTC 24 |
4853382550 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.309757363 |
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Oct 15 11:05:08 PM UTC 24 |
Oct 15 11:14:19 PM UTC 24 |
6160301896 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.4290475739 |
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Oct 15 11:07:02 PM UTC 24 |
Oct 15 11:14:54 PM UTC 24 |
5459391000 ps |
| T1337 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.1456208283 |
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Oct 15 11:07:09 PM UTC 24 |
Oct 15 11:14:59 PM UTC 24 |
5057304820 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.400749384 |
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Oct 15 11:06:56 PM UTC 24 |
Oct 15 11:15:17 PM UTC 24 |
5193504028 ps |
| T1338 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.3449181592 |
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Oct 15 11:07:08 PM UTC 24 |
Oct 15 11:15:37 PM UTC 24 |
4721317160 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.4293475016 |
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Oct 15 11:06:52 PM UTC 24 |
Oct 15 11:15:41 PM UTC 24 |
6147204310 ps |
| T1339 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.3524399032 |
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Oct 15 11:07:09 PM UTC 24 |
Oct 15 11:15:43 PM UTC 24 |
4821827468 ps |
| T1340 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.2678056663 |
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Oct 15 10:12:23 PM UTC 24 |
Oct 15 11:17:55 PM UTC 24 |
15936818632 ps |
| T1341 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.1954416378 |
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Oct 15 10:09:31 PM UTC 24 |
Oct 15 11:20:14 PM UTC 24 |
16435299948 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_inject_scramble_seed.1470058185 |
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Oct 15 06:54:04 PM UTC 24 |
Oct 15 11:21:14 PM UTC 24 |
65873014680 ps |
| T1342 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.615885212 |
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Oct 15 10:08:58 PM UTC 24 |
Oct 15 11:23:30 PM UTC 24 |
18574289800 ps |
| T1343 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.4210697237 |
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Oct 15 10:10:04 PM UTC 24 |
Oct 15 11:26:54 PM UTC 24 |
18695369260 ps |
| T1344 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.1405776325 |
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Oct 15 09:04:09 PM UTC 24 |
Oct 15 11:27:02 PM UTC 24 |
31665143288 ps |
| T1345 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.1080851244 |
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Oct 15 10:05:55 PM UTC 24 |
Oct 15 11:27:37 PM UTC 24 |
19309028376 ps |
| T1346 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.3403141217 |
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|
Oct 15 09:40:04 PM UTC 24 |
Oct 15 11:31:55 PM UTC 24 |
26761348288 ps |
| T1347 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1572316313 |
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Oct 15 06:53:58 PM UTC 24 |
Oct 15 11:37:13 PM UTC 24 |
80422914904 ps |
| T1348 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1010203851 |
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Oct 15 08:19:17 PM UTC 24 |
Oct 15 11:47:26 PM UTC 24 |
61542809060 ps |
| T1349 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.700340494 |
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Oct 15 10:01:29 PM UTC 24 |
Oct 15 11:58:42 PM UTC 24 |
32579233536 ps |
| T1350 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.2832748041 |
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Oct 15 08:19:39 PM UTC 24 |
Oct 16 12:07:29 AM UTC 24 |
66364218578 ps |
| T1351 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1286656110 |
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Oct 15 08:59:19 PM UTC 24 |
Oct 16 12:25:25 AM UTC 24 |
254456531208 ps |
| T1352 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.640507084 |
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Oct 15 08:19:37 PM UTC 24 |
Oct 16 12:29:39 AM UTC 24 |
81991421442 ps |