| T1263 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.26843215 |
|
|
Feb 09 09:54:28 PM UTC 25 |
Feb 09 11:42:11 PM UTC 25 |
47569463960 ps |
| T1264 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2501647252 |
|
|
Feb 09 11:22:18 PM UTC 25 |
Feb 09 11:42:17 PM UTC 25 |
9083876873 ps |
| T786 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.1710577919 |
|
|
Feb 09 11:27:20 PM UTC 25 |
Feb 09 11:42:21 PM UTC 25 |
5888104340 ps |
| T1265 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2373106051 |
|
|
Feb 09 11:33:55 PM UTC 25 |
Feb 09 11:42:21 PM UTC 25 |
4743112502 ps |
| T1266 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.3512667678 |
|
|
Feb 09 11:01:49 PM UTC 25 |
Feb 09 11:42:25 PM UTC 25 |
19741863827 ps |
| T1267 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.203255277 |
|
|
Feb 09 11:33:55 PM UTC 25 |
Feb 09 11:42:32 PM UTC 25 |
5453532045 ps |
| T211 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.1080613109 |
|
|
Feb 09 09:44:45 PM UTC 25 |
Feb 09 11:43:15 PM UTC 25 |
43262725065 ps |
| T1268 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.2313902493 |
|
|
Feb 09 11:29:19 PM UTC 25 |
Feb 09 11:43:19 PM UTC 25 |
4208241784 ps |
| T1269 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.1264136279 |
|
|
Feb 09 11:32:03 PM UTC 25 |
Feb 09 11:43:20 PM UTC 25 |
3929186712 ps |
| T303 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.472839839 |
|
|
Feb 09 11:27:23 PM UTC 25 |
Feb 09 11:44:44 PM UTC 25 |
6750731340 ps |
| T1270 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_rma.1514970268 |
|
|
Feb 09 11:37:11 PM UTC 25 |
Feb 09 11:45:33 PM UTC 25 |
4490197448 ps |
| T1271 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.743113870 |
|
|
Feb 09 11:33:31 PM UTC 25 |
Feb 09 11:45:41 PM UTC 25 |
4190488888 ps |
| T1272 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.4007727163 |
|
|
Feb 09 11:33:46 PM UTC 25 |
Feb 09 11:45:52 PM UTC 25 |
4302665216 ps |
| T1273 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.493713325 |
|
|
Feb 09 11:32:02 PM UTC 25 |
Feb 09 11:46:07 PM UTC 25 |
4205764930 ps |
| T1274 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.708381213 |
|
|
Feb 09 11:33:34 PM UTC 25 |
Feb 09 11:46:10 PM UTC 25 |
6357100632 ps |
| T141 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_rst_inputs.2906183827 |
|
|
Feb 09 11:02:55 PM UTC 25 |
Feb 09 11:46:17 PM UTC 25 |
18829749394 ps |
| T1275 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.630585944 |
|
|
Feb 09 11:32:38 PM UTC 25 |
Feb 09 11:46:31 PM UTC 25 |
4448668254 ps |
| T1276 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_testunlock0.1522138342 |
|
|
Feb 09 11:36:23 PM UTC 25 |
Feb 09 11:46:40 PM UTC 25 |
6493362838 ps |
| T1277 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.145890549 |
|
|
Feb 09 11:42:20 PM UTC 25 |
Feb 09 11:49:45 PM UTC 25 |
5660873183 ps |
| T287 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.2394003787 |
|
|
Feb 09 11:39:01 PM UTC 25 |
Feb 09 11:50:15 PM UTC 25 |
5415469316 ps |
| T691 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.362728245 |
|
|
Feb 09 11:43:35 PM UTC 25 |
Feb 09 11:50:19 PM UTC 25 |
3130687432 ps |
| T1278 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.3048821945 |
|
|
Feb 09 11:39:15 PM UTC 25 |
Feb 09 11:50:35 PM UTC 25 |
5197253600 ps |
| T1279 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.837091115 |
|
|
Feb 09 11:21:15 PM UTC 25 |
Feb 09 11:50:47 PM UTC 25 |
7981375828 ps |
| T796 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.4033488501 |
|
|
Feb 09 11:44:23 PM UTC 25 |
Feb 09 11:51:51 PM UTC 25 |
3783120250 ps |
| T171 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.202171367 |
|
|
Feb 09 11:34:15 PM UTC 25 |
Feb 09 11:52:23 PM UTC 25 |
6736686738 ps |
| T1280 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.2738610987 |
|
|
Feb 09 11:44:30 PM UTC 25 |
Feb 09 11:52:27 PM UTC 25 |
5099569065 ps |
| T1281 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.841816106 |
|
|
Feb 09 09:52:43 PM UTC 25 |
Feb 09 11:52:40 PM UTC 25 |
47948833386 ps |
| T699 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.37608834 |
|
|
Feb 09 11:45:26 PM UTC 25 |
Feb 09 11:53:03 PM UTC 25 |
3964783000 ps |
| T252 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.238709362 |
|
|
Feb 09 10:33:00 PM UTC 25 |
Feb 09 11:53:37 PM UTC 25 |
16487837368 ps |
| T694 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.1463396499 |
|
|
Feb 09 11:44:24 PM UTC 25 |
Feb 09 11:54:52 PM UTC 25 |
4372144450 ps |
| T1282 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.3617406159 |
|
|
Feb 09 09:15:32 PM UTC 25 |
Feb 09 11:55:01 PM UTC 25 |
30501277956 ps |
| T695 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.2492362586 |
|
|
Feb 09 11:44:34 PM UTC 25 |
Feb 09 11:55:37 PM UTC 25 |
4992466748 ps |
| T1283 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.4018071076 |
|
|
Feb 09 11:44:34 PM UTC 25 |
Feb 09 11:55:54 PM UTC 25 |
4321120302 ps |
| T1284 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.113194228 |
|
|
Feb 09 09:52:47 PM UTC 25 |
Feb 09 11:56:19 PM UTC 25 |
49394435084 ps |
| T1285 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.1460764258 |
|
|
Feb 09 11:44:30 PM UTC 25 |
Feb 09 11:56:38 PM UTC 25 |
10691848629 ps |
| T703 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1738182120 |
|
|
Feb 09 11:47:38 PM UTC 25 |
Feb 09 11:56:43 PM UTC 25 |
4322851940 ps |
| T1286 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.1705273526 |
|
|
Feb 09 11:35:26 PM UTC 25 |
Feb 09 11:57:12 PM UTC 25 |
11363519634 ps |
| T1287 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.600350591 |
|
|
Feb 09 11:47:11 PM UTC 25 |
Feb 09 11:57:29 PM UTC 25 |
5011998138 ps |
| T1288 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1267840516 |
|
|
Feb 09 09:15:33 PM UTC 25 |
Feb 09 11:57:58 PM UTC 25 |
29262424848 ps |
| T741 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2133536846 |
|
|
Feb 09 11:50:59 PM UTC 25 |
Feb 09 11:58:09 PM UTC 25 |
3640846760 ps |
| T1289 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.471237313 |
|
|
Feb 09 09:16:15 PM UTC 25 |
Feb 09 11:58:14 PM UTC 25 |
29168978360 ps |
| T362 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.3877162598 |
|
|
Feb 09 11:47:37 PM UTC 25 |
Feb 09 11:58:54 PM UTC 25 |
5524946560 ps |
| T366 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_prod.533954741 |
|
|
Feb 09 11:25:41 PM UTC 25 |
Feb 09 11:59:52 PM UTC 25 |
14900915424 ps |
| T367 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.1502368976 |
|
|
Feb 09 11:47:41 PM UTC 25 |
Feb 10 12:00:13 AM UTC 25 |
6221643360 ps |
| T368 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1819085519 |
|
|
Feb 09 11:05:30 PM UTC 25 |
Feb 10 12:00:50 AM UTC 25 |
12473250506 ps |
| T369 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.473876550 |
|
|
Feb 09 11:51:22 PM UTC 25 |
Feb 10 12:01:06 AM UTC 25 |
4540746650 ps |
| T370 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2214913486 |
|
|
Feb 09 11:53:29 PM UTC 25 |
Feb 10 12:01:47 AM UTC 25 |
4190705190 ps |
| T371 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1203659597 |
|
|
Feb 09 11:54:17 PM UTC 25 |
Feb 10 12:01:56 AM UTC 25 |
3768026464 ps |
| T372 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.3050792493 |
|
|
Feb 09 11:53:44 PM UTC 25 |
Feb 10 12:02:14 AM UTC 25 |
4446616588 ps |
| T373 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.668106762 |
|
|
Feb 09 11:52:31 PM UTC 25 |
Feb 10 12:02:26 AM UTC 25 |
5938551484 ps |
| T374 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.699670676 |
|
|
Feb 09 11:53:40 PM UTC 25 |
Feb 10 12:02:52 AM UTC 25 |
3803133820 ps |
| T1290 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2495094433 |
|
|
Feb 09 11:56:35 PM UTC 25 |
Feb 10 12:04:15 AM UTC 25 |
3937900140 ps |
| T755 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2429249232 |
|
|
Feb 09 11:57:52 PM UTC 25 |
Feb 10 12:04:41 AM UTC 25 |
3502171888 ps |
| T288 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.501443822 |
|
|
Feb 09 11:55:46 PM UTC 25 |
Feb 10 12:05:08 AM UTC 25 |
4365725424 ps |
| T688 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.426009951 |
|
|
Feb 09 11:58:08 PM UTC 25 |
Feb 10 12:06:54 AM UTC 25 |
5116556904 ps |
| T1291 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.3028039761 |
|
|
Feb 09 11:50:24 PM UTC 25 |
Feb 10 12:07:23 AM UTC 25 |
10989511301 ps |
| T767 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1984816159 |
|
|
Feb 09 11:59:00 PM UTC 25 |
Feb 10 12:08:04 AM UTC 25 |
3924872720 ps |
| T1292 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.3034300286 |
|
|
Feb 09 11:04:18 PM UTC 25 |
Feb 10 12:08:31 AM UTC 25 |
24985519985 ps |
| T758 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1361643955 |
|
|
Feb 10 12:02:41 AM UTC 25 |
Feb 10 12:08:44 AM UTC 25 |
3658713564 ps |
| T1293 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.3097454079 |
|
|
Feb 09 11:57:30 PM UTC 25 |
Feb 10 12:08:55 AM UTC 25 |
8459851940 ps |
| T393 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.519991331 |
|
|
Feb 09 11:57:00 PM UTC 25 |
Feb 10 12:09:22 AM UTC 25 |
4556235708 ps |
| T1294 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.793239066 |
|
|
Feb 10 12:01:47 AM UTC 25 |
Feb 10 12:09:38 AM UTC 25 |
3453484240 ps |
| T690 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.457833832 |
|
|
Feb 10 12:03:08 AM UTC 25 |
Feb 10 12:10:54 AM UTC 25 |
4194463012 ps |
| T1295 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.3775653692 |
|
|
Feb 09 11:56:17 PM UTC 25 |
Feb 10 12:11:00 AM UTC 25 |
11856505201 ps |
| T783 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1201384024 |
|
|
Feb 10 12:00:59 AM UTC 25 |
Feb 10 12:11:17 AM UTC 25 |
4029274440 ps |
| T784 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.1408324837 |
|
|
Feb 09 11:59:37 PM UTC 25 |
Feb 10 12:12:17 AM UTC 25 |
5678239228 ps |
| T1296 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.3618455142 |
|
|
Feb 10 12:03:05 AM UTC 25 |
Feb 10 12:12:36 AM UTC 25 |
3304677078 ps |
| T718 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.2520242317 |
|
|
Feb 10 12:01:31 AM UTC 25 |
Feb 10 12:12:44 AM UTC 25 |
5481606220 ps |
| T721 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1207037991 |
|
|
Feb 10 12:05:20 AM UTC 25 |
Feb 10 12:13:54 AM UTC 25 |
3741314548 ps |
| T734 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.2554081968 |
|
|
Feb 10 12:03:34 AM UTC 25 |
Feb 10 12:14:25 AM UTC 25 |
4202190438 ps |
| T757 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3799086902 |
|
|
Feb 10 12:07:32 AM UTC 25 |
Feb 10 12:15:42 AM UTC 25 |
4109379606 ps |
| T1297 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3682688803 |
|
|
Feb 09 11:22:05 PM UTC 25 |
Feb 10 12:16:36 AM UTC 25 |
13179277335 ps |
| T723 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.784037867 |
|
|
Feb 10 12:10:00 AM UTC 25 |
Feb 10 12:16:42 AM UTC 25 |
3731630690 ps |
| T1298 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.1679194352 |
|
|
Feb 09 11:59:00 PM UTC 25 |
Feb 10 12:16:43 AM UTC 25 |
10065154138 ps |
| T677 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.509553605 |
|
|
Feb 10 12:08:45 AM UTC 25 |
Feb 10 12:16:50 AM UTC 25 |
4220977970 ps |
| T278 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.1810309364 |
|
|
Feb 10 12:02:41 AM UTC 25 |
Feb 10 12:16:56 AM UTC 25 |
5935369776 ps |
| T325 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.276786042 |
|
|
Feb 10 12:09:40 AM UTC 25 |
Feb 10 12:17:28 AM UTC 25 |
4032823104 ps |
| T326 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.2955189792 |
|
|
Feb 10 12:07:58 AM UTC 25 |
Feb 10 12:18:18 AM UTC 25 |
6012676960 ps |
| T327 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.682991969 |
|
|
Feb 09 11:47:45 PM UTC 25 |
Feb 10 12:18:23 AM UTC 25 |
7824211164 ps |
| T328 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.1735736743 |
|
|
Feb 09 11:47:24 PM UTC 25 |
Feb 10 12:18:26 AM UTC 25 |
8143880152 ps |
| T329 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1315952338 |
|
|
Feb 10 12:12:01 AM UTC 25 |
Feb 10 12:18:42 AM UTC 25 |
4085118948 ps |
| T330 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.2926256640 |
|
|
Feb 09 11:05:55 PM UTC 25 |
Feb 10 12:18:43 AM UTC 25 |
15495747844 ps |
| T279 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.2272240118 |
|
|
Feb 10 12:09:41 AM UTC 25 |
Feb 10 12:18:49 AM UTC 25 |
4125364942 ps |
| T331 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3169261707 |
|
|
Feb 10 12:11:57 AM UTC 25 |
Feb 10 12:19:53 AM UTC 25 |
3899213256 ps |
| T332 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.2907021409 |
|
|
Feb 10 12:10:18 AM UTC 25 |
Feb 10 12:20:26 AM UTC 25 |
4566944568 ps |
| T731 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3680873719 |
|
|
Feb 10 12:13:28 AM UTC 25 |
Feb 10 12:20:41 AM UTC 25 |
3800690840 ps |
| T772 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2591224336 |
|
|
Feb 10 12:14:35 AM UTC 25 |
Feb 10 12:20:48 AM UTC 25 |
3529337116 ps |
| T1299 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.3110847879 |
|
|
Feb 09 11:53:39 PM UTC 25 |
Feb 10 12:21:24 AM UTC 25 |
8478472744 ps |
| T709 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.2315941977 |
|
|
Feb 10 12:05:51 AM UTC 25 |
Feb 10 12:21:40 AM UTC 25 |
5880145630 ps |
| T764 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.2558286368 |
|
|
Feb 10 12:09:38 AM UTC 25 |
Feb 10 12:21:55 AM UTC 25 |
5335193228 ps |
| T1300 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.1199170308 |
|
|
Feb 09 11:57:30 PM UTC 25 |
Feb 10 12:22:02 AM UTC 25 |
7913066732 ps |
| T1301 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.411224647 |
|
|
Feb 09 11:05:20 PM UTC 25 |
Feb 10 12:22:26 AM UTC 25 |
16171238059 ps |
| T1302 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2356038152 |
|
|
Feb 09 06:26:27 PM UTC 25 |
Feb 10 12:22:52 AM UTC 25 |
95886055245 ps |
| T752 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.2183030246 |
|
|
Feb 10 12:11:57 AM UTC 25 |
Feb 10 12:23:14 AM UTC 25 |
4949285800 ps |
| T1303 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.2114429310 |
|
|
Feb 09 11:04:15 PM UTC 25 |
Feb 10 12:24:39 AM UTC 25 |
15465767800 ps |
| T1304 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.3639650134 |
|
|
Feb 09 11:04:15 PM UTC 25 |
Feb 10 12:24:42 AM UTC 25 |
14773851735 ps |
| T701 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.4058463449 |
|
|
Feb 10 12:18:16 AM UTC 25 |
Feb 10 12:24:44 AM UTC 25 |
4340275000 ps |
| T711 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.4316027 |
|
|
Feb 10 12:16:22 AM UTC 25 |
Feb 10 12:24:54 AM UTC 25 |
4179735560 ps |
| T404 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1701983175 |
|
|
Feb 10 12:18:22 AM UTC 25 |
Feb 10 12:24:56 AM UTC 25 |
3196211712 ps |
| T407 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.3015937521 |
|
|
Feb 09 11:51:24 PM UTC 25 |
Feb 10 12:25:12 AM UTC 25 |
8390945760 ps |
| T408 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2452193053 |
|
|
Feb 10 12:18:22 AM UTC 25 |
Feb 10 12:25:21 AM UTC 25 |
2936575976 ps |
| T409 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1294938400 |
|
|
Feb 10 12:20:01 AM UTC 25 |
Feb 10 12:25:27 AM UTC 25 |
3370194780 ps |
| T363 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.352692371 |
|
|
Feb 10 12:15:07 AM UTC 25 |
Feb 10 12:25:59 AM UTC 25 |
4701424284 ps |
| T410 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.4011670857 |
|
|
Feb 10 12:20:01 AM UTC 25 |
Feb 10 12:26:13 AM UTC 25 |
4197385700 ps |
| T411 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.2015983956 |
|
|
Feb 10 12:13:28 AM UTC 25 |
Feb 10 12:26:40 AM UTC 25 |
5558650320 ps |
| T412 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.903271611 |
|
|
Feb 09 11:00:37 PM UTC 25 |
Feb 10 12:26:51 AM UTC 25 |
24610535748 ps |
| T413 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3054283734 |
|
|
Feb 10 12:20:01 AM UTC 25 |
Feb 10 12:27:00 AM UTC 25 |
4130556658 ps |
| T414 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.2365418277 |
|
|
Feb 09 11:58:32 PM UTC 25 |
Feb 10 12:27:16 AM UTC 25 |
8436109976 ps |
| T194 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.482841876 |
|
|
Feb 10 12:12:59 AM UTC 25 |
Feb 10 12:27:21 AM UTC 25 |
5965375800 ps |
| T753 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.567804518 |
|
|
Feb 10 12:21:07 AM UTC 25 |
Feb 10 12:27:22 AM UTC 25 |
3584335088 ps |
| T1305 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.735014872 |
|
|
Feb 09 11:05:44 PM UTC 25 |
Feb 10 12:27:23 AM UTC 25 |
16102601311 ps |
| T702 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.3082343978 |
|
|
Feb 10 12:18:14 AM UTC 25 |
Feb 10 12:27:49 AM UTC 25 |
5087209768 ps |
| T289 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.518208300 |
|
|
Feb 10 12:19:59 AM UTC 25 |
Feb 10 12:27:52 AM UTC 25 |
4607529900 ps |
| T792 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.1800026336 |
|
|
Feb 10 12:18:18 AM UTC 25 |
Feb 10 12:28:34 AM UTC 25 |
5221971388 ps |
| T1306 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.3749503406 |
|
|
Feb 10 12:00:33 AM UTC 25 |
Feb 10 12:28:54 AM UTC 25 |
8771556400 ps |
| T781 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2631238820 |
|
|
Feb 10 12:23:33 AM UTC 25 |
Feb 10 12:29:06 AM UTC 25 |
3688166820 ps |
| T684 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.3195258535 |
|
|
Feb 10 12:20:33 AM UTC 25 |
Feb 10 12:29:20 AM UTC 25 |
5145572020 ps |
| T778 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.3031543933 |
|
|
Feb 10 12:18:17 AM UTC 25 |
Feb 10 12:29:21 AM UTC 25 |
5504502794 ps |
| T712 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.4289476168 |
|
|
Feb 10 12:21:34 AM UTC 25 |
Feb 10 12:29:38 AM UTC 25 |
3577620086 ps |
| T788 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1684778587 |
|
|
Feb 10 12:22:48 AM UTC 25 |
Feb 10 12:29:51 AM UTC 25 |
3352383960 ps |
| T280 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.3195766821 |
|
|
Feb 10 12:19:53 AM UTC 25 |
Feb 10 12:29:59 AM UTC 25 |
5099631084 ps |
| T790 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.1989409123 |
|
|
Feb 10 12:22:00 AM UTC 25 |
Feb 10 12:30:49 AM UTC 25 |
5859901456 ps |
| T787 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.478389437 |
|
|
Feb 10 12:20:02 AM UTC 25 |
Feb 10 12:30:51 AM UTC 25 |
5800300776 ps |
| T715 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3290182403 |
|
|
Feb 10 12:22:32 AM UTC 25 |
Feb 10 12:31:08 AM UTC 25 |
4045555976 ps |
| T1307 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.181557638 |
|
|
Feb 09 11:39:58 PM UTC 25 |
Feb 10 12:31:16 AM UTC 25 |
13218234700 ps |
| T1308 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.4148839066 |
|
|
Feb 10 12:05:52 AM UTC 25 |
Feb 10 12:31:50 AM UTC 25 |
8366278472 ps |
| T1309 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.3121025243 |
|
|
Feb 09 11:05:51 PM UTC 25 |
Feb 10 12:31:57 AM UTC 25 |
15985266697 ps |
| T794 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1454156199 |
|
|
Feb 10 12:27:15 AM UTC 25 |
Feb 10 12:32:40 AM UTC 25 |
3570944472 ps |
| T719 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.3841604503 |
|
|
Feb 10 12:23:07 AM UTC 25 |
Feb 10 12:32:40 AM UTC 25 |
4556828260 ps |
| T747 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.3719966174 |
|
|
Feb 10 12:23:57 AM UTC 25 |
Feb 10 12:32:40 AM UTC 25 |
4919883374 ps |
| T675 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2577730185 |
|
|
Feb 10 12:27:02 AM UTC 25 |
Feb 10 12:32:54 AM UTC 25 |
3118015508 ps |
| T1310 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.3451764728 |
|
|
Feb 10 12:04:56 AM UTC 25 |
Feb 10 12:33:03 AM UTC 25 |
7907473460 ps |
| T1311 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.1833334015 |
|
|
Feb 09 11:44:19 PM UTC 25 |
Feb 10 12:33:03 AM UTC 25 |
12693075482 ps |
| T779 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3055094081 |
|
|
Feb 10 12:27:15 AM UTC 25 |
Feb 10 12:33:20 AM UTC 25 |
3475368896 ps |
| T785 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2992521277 |
|
|
Feb 10 12:27:16 AM UTC 25 |
Feb 10 12:33:21 AM UTC 25 |
3897048732 ps |
| T791 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.653660327 |
|
|
Feb 10 12:26:59 AM UTC 25 |
Feb 10 12:34:12 AM UTC 25 |
3462682824 ps |
| T760 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.3620948104 |
|
|
Feb 10 12:21:34 AM UTC 25 |
Feb 10 12:34:26 AM UTC 25 |
5487076504 ps |
| T735 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1233647512 |
|
|
Feb 10 12:27:41 AM UTC 25 |
Feb 10 12:34:48 AM UTC 25 |
4190142424 ps |
| T724 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2074042767 |
|
|
Feb 10 12:28:07 AM UTC 25 |
Feb 10 12:34:57 AM UTC 25 |
3851888652 ps |
| T1312 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.168538308 |
|
|
Feb 09 11:06:22 PM UTC 25 |
Feb 10 12:35:02 AM UTC 25 |
17469327280 ps |
| T290 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.3171265818 |
|
|
Feb 10 12:26:44 AM UTC 25 |
Feb 10 12:35:05 AM UTC 25 |
4954088440 ps |
| T682 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.811066613 |
|
|
Feb 10 12:22:46 AM UTC 25 |
Feb 10 12:35:36 AM UTC 25 |
5445952648 ps |
| T736 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3146502087 |
|
|
Feb 10 12:30:46 AM UTC 25 |
Feb 10 12:36:21 AM UTC 25 |
3456696824 ps |
| T1313 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2385124942 |
|
|
Feb 10 12:29:14 AM UTC 25 |
Feb 10 12:36:27 AM UTC 25 |
4021342810 ps |
| T710 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3207829867 |
|
|
Feb 10 12:30:44 AM UTC 25 |
Feb 10 12:36:30 AM UTC 25 |
3064716692 ps |
| T109 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.743662805 |
|
|
Feb 10 12:31:02 AM UTC 25 |
Feb 10 12:36:50 AM UTC 25 |
3413910486 ps |
| T750 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3835802973 |
|
|
Feb 10 12:30:33 AM UTC 25 |
Feb 10 12:37:28 AM UTC 25 |
4105830776 ps |
| T405 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1682675580 |
|
|
Feb 10 12:31:05 AM UTC 25 |
Feb 10 12:37:52 AM UTC 25 |
3636555092 ps |
| T770 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.3207740241 |
|
|
Feb 10 12:27:17 AM UTC 25 |
Feb 10 12:37:56 AM UTC 25 |
4893078880 ps |
| T320 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.778767819 |
|
|
Feb 10 12:27:07 AM UTC 25 |
Feb 10 12:38:25 AM UTC 25 |
5716521492 ps |
| T110 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.4292047226 |
|
|
Feb 10 12:30:05 AM UTC 25 |
Feb 10 12:38:26 AM UTC 25 |
5424381528 ps |
| T696 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3753550234 |
|
|
Feb 10 12:31:11 AM UTC 25 |
Feb 10 12:39:02 AM UTC 25 |
3982661896 ps |
| T737 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3941199 |
|
|
Feb 10 12:32:42 AM UTC 25 |
Feb 10 12:39:09 AM UTC 25 |
3827287832 ps |
| T768 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.3047999744 |
|
|
Feb 10 12:27:00 AM UTC 25 |
Feb 10 12:39:18 AM UTC 25 |
5963012616 ps |
| T713 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.4288098918 |
|
|
Feb 10 12:26:58 AM UTC 25 |
Feb 10 12:39:23 AM UTC 25 |
5322045620 ps |
| T321 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.171583147 |
|
|
Feb 10 12:32:02 AM UTC 25 |
Feb 10 12:39:30 AM UTC 25 |
4444832054 ps |
| T766 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.2080058861 |
|
|
Feb 10 12:29:31 AM UTC 25 |
Feb 10 12:39:31 AM UTC 25 |
5397550824 ps |
| T782 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.617748582 |
|
|
Feb 10 12:31:08 AM UTC 25 |
Feb 10 12:39:40 AM UTC 25 |
4081003000 ps |
| T683 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.798653324 |
|
|
Feb 10 12:31:56 AM UTC 25 |
Feb 10 12:39:46 AM UTC 25 |
3699810834 ps |
| T273 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.3583254812 |
|
|
Feb 10 12:31:11 AM UTC 25 |
Feb 10 12:40:00 AM UTC 25 |
5063761314 ps |
| T1314 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.221378329 |
|
|
Feb 09 11:01:57 PM UTC 25 |
Feb 10 12:40:51 AM UTC 25 |
26985855157 ps |
| T742 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1319982490 |
|
|
Feb 10 12:34:40 AM UTC 25 |
Feb 10 12:40:58 AM UTC 25 |
3218800640 ps |
| T722 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.3597139504 |
|
|
Feb 10 12:31:10 AM UTC 25 |
Feb 10 12:41:03 AM UTC 25 |
5584931330 ps |
| T680 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.4246042714 |
|
|
Feb 10 12:31:08 AM UTC 25 |
Feb 10 12:41:15 AM UTC 25 |
5499503960 ps |
| T727 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.133249495 |
|
|
Feb 10 12:30:04 AM UTC 25 |
Feb 10 12:41:20 AM UTC 25 |
6432210944 ps |
| T773 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.458132454 |
|
|
Feb 10 12:34:31 AM UTC 25 |
Feb 10 12:41:33 AM UTC 25 |
4026011240 ps |
| T748 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.339445847 |
|
|
Feb 10 12:30:49 AM UTC 25 |
Feb 10 12:41:33 AM UTC 25 |
5186094080 ps |
| T728 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.917426127 |
|
|
Feb 10 12:28:39 AM UTC 25 |
Feb 10 12:41:35 AM UTC 25 |
5688213698 ps |
| T716 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3423551999 |
|
|
Feb 10 12:35:48 AM UTC 25 |
Feb 10 12:42:14 AM UTC 25 |
4122336198 ps |
| T738 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.1555745145 |
|
|
Feb 10 12:32:02 AM UTC 25 |
Feb 10 12:42:35 AM UTC 25 |
5498490280 ps |
| T749 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.2568967685 |
|
|
Feb 10 12:29:30 AM UTC 25 |
Feb 10 12:42:45 AM UTC 25 |
6314875020 ps |
| T743 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.498940890 |
|
|
Feb 10 12:36:17 AM UTC 25 |
Feb 10 12:42:56 AM UTC 25 |
3261515840 ps |
| T771 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.785229763 |
|
|
Feb 10 12:35:11 AM UTC 25 |
Feb 10 12:43:04 AM UTC 25 |
3896655550 ps |
| T681 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.177851463 |
|
|
Feb 10 12:36:18 AM UTC 25 |
Feb 10 12:43:09 AM UTC 25 |
3642082680 ps |
| T720 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1671070805 |
|
|
Feb 10 12:35:40 AM UTC 25 |
Feb 10 12:43:15 AM UTC 25 |
3663435336 ps |
| T291 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.1433237480 |
|
|
Feb 10 12:35:11 AM UTC 25 |
Feb 10 12:43:16 AM UTC 25 |
4642080640 ps |
| T1315 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1297966806 |
|
|
Feb 10 12:38:45 AM UTC 25 |
Feb 10 12:44:07 AM UTC 25 |
3364737400 ps |
| T725 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2936340143 |
|
|
Feb 10 12:37:41 AM UTC 25 |
Feb 10 12:44:08 AM UTC 25 |
3361300792 ps |
| T1316 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.110801874 |
|
|
Feb 10 12:32:00 AM UTC 25 |
Feb 10 12:44:24 AM UTC 25 |
5860382216 ps |
| T777 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_all_escalation_resets.3153528529 |
|
|
Feb 10 12:35:05 AM UTC 25 |
Feb 10 12:44:39 AM UTC 25 |
5610511152 ps |
| T292 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.1168146747 |
|
|
Feb 10 12:35:12 AM UTC 25 |
Feb 10 12:44:42 AM UTC 25 |
4817186640 ps |
| T780 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.834114978 |
|
|
Feb 10 12:38:08 AM UTC 25 |
Feb 10 12:44:43 AM UTC 25 |
3296361640 ps |
| T1317 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.1121231623 |
|
|
Feb 10 12:32:41 AM UTC 25 |
Feb 10 12:44:51 AM UTC 25 |
5345271788 ps |
| T322 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.3790839116 |
|
|
Feb 10 12:36:00 AM UTC 25 |
Feb 10 12:44:57 AM UTC 25 |
4685023788 ps |
| T732 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.109092462 |
|
|
Feb 10 12:37:37 AM UTC 25 |
Feb 10 12:44:58 AM UTC 25 |
4194823510 ps |
| T685 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.323739356 |
|
|
Feb 10 12:37:39 AM UTC 25 |
Feb 10 12:45:10 AM UTC 25 |
4371399344 ps |
| T739 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.3439555648 |
|
|
Feb 10 12:36:21 AM UTC 25 |
Feb 10 12:45:11 AM UTC 25 |
4643026572 ps |
| T1318 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.853502810 |
|
|
Feb 10 12:35:04 AM UTC 25 |
Feb 10 12:45:46 AM UTC 25 |
4639200700 ps |
| T1319 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3930961474 |
|
|
Feb 10 12:41:39 AM UTC 25 |
Feb 10 12:46:14 AM UTC 25 |
3367559804 ps |
| T1320 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3811639808 |
|
|
Feb 10 12:39:18 AM UTC 25 |
Feb 10 12:46:18 AM UTC 25 |
4215628028 ps |
| T1321 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.2137161215 |
|
|
Feb 09 11:55:47 PM UTC 25 |
Feb 10 12:46:35 AM UTC 25 |
13113741750 ps |
| T789 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3125586441 |
|
|
Feb 10 12:41:16 AM UTC 25 |
Feb 10 12:46:41 AM UTC 25 |
3343516436 ps |
| T774 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.2170704285 |
|
|
Feb 10 12:39:18 AM UTC 25 |
Feb 10 12:46:55 AM UTC 25 |
5561362376 ps |
| T704 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3033358250 |
|
|
Feb 10 12:41:18 AM UTC 25 |
Feb 10 12:47:12 AM UTC 25 |
4213370824 ps |
| T769 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.3421470734 |
|
|
Feb 10 12:36:04 AM UTC 25 |
Feb 10 12:47:40 AM UTC 25 |
6328735572 ps |
| T1322 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.3559904537 |
|
|
Feb 10 12:37:38 AM UTC 25 |
Feb 10 12:48:02 AM UTC 25 |
6497679920 ps |
| T756 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.4247274381 |
|
|
Feb 10 12:42:48 AM UTC 25 |
Feb 10 12:48:30 AM UTC 25 |
3459413524 ps |
| T761 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1807758244 |
|
|
Feb 10 12:43:13 AM UTC 25 |
Feb 10 12:48:44 AM UTC 25 |
4119357896 ps |
| T775 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.3888161069 |
|
|
Feb 10 12:42:00 AM UTC 25 |
Feb 10 12:49:27 AM UTC 25 |
4661931320 ps |
| T364 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.3799903063 |
|
|
Feb 10 12:38:44 AM UTC 25 |
Feb 10 12:49:45 AM UTC 25 |
6262546008 ps |
| T686 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.15481209 |
|
|
Feb 10 12:43:32 AM UTC 25 |
Feb 10 12:50:08 AM UTC 25 |
3622926584 ps |
| T793 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3584404986 |
|
|
Feb 10 12:44:24 AM UTC 25 |
Feb 10 12:50:09 AM UTC 25 |
4115360398 ps |
| T689 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.3875993600 |
|
|
Feb 10 12:41:15 AM UTC 25 |
Feb 10 12:50:13 AM UTC 25 |
5748932916 ps |
| T1323 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.2479403899 |
|
|
Feb 09 10:25:08 PM UTC 25 |
Feb 10 12:50:41 AM UTC 25 |
29412301262 ps |
| T714 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2396773746 |
|
|
Feb 10 12:45:15 AM UTC 25 |
Feb 10 12:51:00 AM UTC 25 |
3390720914 ps |
| T762 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2280443080 |
|
|
Feb 10 12:46:14 AM UTC 25 |
Feb 10 12:52:02 AM UTC 25 |
3568561760 ps |
| T726 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.58548566 |
|
|
Feb 10 12:42:46 AM UTC 25 |
Feb 10 12:52:08 AM UTC 25 |
5422093192 ps |
| T1324 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.976715105 |
|
|
Feb 10 12:45:59 AM UTC 25 |
Feb 10 12:52:56 AM UTC 25 |
3319689000 ps |
| T717 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.3428993905 |
|
|
Feb 10 12:44:56 AM UTC 25 |
Feb 10 12:53:00 AM UTC 25 |
5200044560 ps |
| T697 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2157518670 |
|
|
Feb 10 12:45:57 AM UTC 25 |
Feb 10 12:53:12 AM UTC 25 |
4182106884 ps |
| T406 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.4011922150 |
|
|
Feb 10 12:47:05 AM UTC 25 |
Feb 10 12:53:20 AM UTC 25 |
3974097880 ps |
| T698 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1589158022 |
|
|
Feb 10 12:45:58 AM UTC 25 |
Feb 10 12:53:33 AM UTC 25 |
4118852546 ps |
| T707 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.662269067 |
|
|
Feb 10 12:42:47 AM UTC 25 |
Feb 10 12:53:40 AM UTC 25 |
5981246030 ps |
| T759 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.633887783 |
|
|
Feb 10 12:44:22 AM UTC 25 |
Feb 10 12:53:41 AM UTC 25 |
5350103496 ps |
| T1325 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.1837397466 |
|
|
Feb 10 12:45:14 AM UTC 25 |
Feb 10 12:53:45 AM UTC 25 |
6420369584 ps |
| T323 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.2863449407 |
|
|
Feb 10 12:44:28 AM UTC 25 |
Feb 10 12:53:56 AM UTC 25 |
6050022720 ps |
| T795 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1844950033 |
|
|
Feb 10 12:48:01 AM UTC 25 |
Feb 10 12:54:02 AM UTC 25 |
4234833488 ps |
| T1326 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.1476057212 |
|
|
Feb 10 12:43:31 AM UTC 25 |
Feb 10 12:54:02 AM UTC 25 |
5297982752 ps |
| T700 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2914896034 |
|
|
Feb 10 12:47:57 AM UTC 25 |
Feb 10 12:54:08 AM UTC 25 |
3296097484 ps |
| T744 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.1130185173 |
|
|
Feb 10 12:44:23 AM UTC 25 |
Feb 10 12:54:15 AM UTC 25 |
4883845660 ps |
| T1327 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.3816232463 |
|
|
Feb 10 12:44:28 AM UTC 25 |
Feb 10 12:54:31 AM UTC 25 |
4928216080 ps |
| T1328 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.720116108 |
|
|
Feb 10 12:48:00 AM UTC 25 |
Feb 10 12:54:36 AM UTC 25 |
3809194960 ps |
| T1329 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.510280577 |
|
|
Feb 10 12:46:51 AM UTC 25 |
Feb 10 12:54:49 AM UTC 25 |
4509004450 ps |
| T1330 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.1141373775 |
|
|
Feb 10 12:44:30 AM UTC 25 |
Feb 10 12:55:01 AM UTC 25 |
4066262734 ps |
| T745 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.4228067095 |
|
|
Feb 10 12:48:19 AM UTC 25 |
Feb 10 12:55:02 AM UTC 25 |
3337584160 ps |
| T730 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.2712349361 |
|
|
Feb 10 12:44:54 AM UTC 25 |
Feb 10 12:55:28 AM UTC 25 |
5817915320 ps |
| T1331 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1096851122 |
|
|
Feb 10 12:47:31 AM UTC 25 |
Feb 10 12:55:33 AM UTC 25 |
4128263540 ps |
| T765 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1908679792 |
|
|
Feb 10 12:48:21 AM UTC 25 |
Feb 10 12:55:54 AM UTC 25 |
3630240066 ps |
| T1332 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.2413741418 |
|
|
Feb 10 12:47:05 AM UTC 25 |
Feb 10 12:56:01 AM UTC 25 |
5021630658 ps |
| T365 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.2358320113 |
|
|
Feb 10 12:46:38 AM UTC 25 |
Feb 10 12:56:09 AM UTC 25 |
4891157244 ps |
| T1333 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.866889590 |
|
|
Feb 09 11:33:50 PM UTC 25 |
Feb 10 12:56:17 AM UTC 25 |
16185851946 ps |
| T692 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.683794223 |
|
|
Feb 10 12:48:26 AM UTC 25 |
Feb 10 12:56:20 AM UTC 25 |
4312972956 ps |
| T740 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.1892084718 |
|
|
Feb 10 12:47:59 AM UTC 25 |
Feb 10 12:56:21 AM UTC 25 |
4162725184 ps |
| T1334 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.3975623525 |
|
|
Feb 10 12:46:49 AM UTC 25 |
Feb 10 12:56:41 AM UTC 25 |
4813674238 ps |
| T754 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.3053660693 |
|
|
Feb 10 12:48:05 AM UTC 25 |
Feb 10 12:56:52 AM UTC 25 |
5506080392 ps |
| T751 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.428075232 |
|
|
Feb 10 12:49:09 AM UTC 25 |
Feb 10 12:57:14 AM UTC 25 |
5665360750 ps |
| T1335 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.4254013049 |
|
|
Feb 09 11:44:20 PM UTC 25 |
Feb 10 12:57:15 AM UTC 25 |
16139872590 ps |
| T1336 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.3171154828 |
|
|
Feb 09 11:47:12 PM UTC 25 |
Feb 10 12:57:23 AM UTC 25 |
15837501596 ps |
| T324 |
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Feb 10 12:50:59 AM UTC 25 |
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Feb 10 12:50:09 AM UTC 25 |
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Feb 10 12:50:28 AM UTC 25 |
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Feb 10 12:50:59 AM UTC 25 |
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