| T1575 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.1174168527 |
|
|
Feb 09 03:34:10 PM UTC 25 |
Feb 09 03:46:11 PM UTC 25 |
43892355694 ps |
| T1576 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.1357535562 |
|
|
Feb 09 03:32:24 PM UTC 25 |
Feb 09 03:46:30 PM UTC 25 |
85758205811 ps |
| T1577 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.4218280762 |
|
|
Feb 09 03:46:05 PM UTC 25 |
Feb 09 03:46:38 PM UTC 25 |
268583480 ps |
| T1578 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.1866543472 |
|
|
Feb 09 03:45:12 PM UTC 25 |
Feb 09 03:46:45 PM UTC 25 |
2586457315 ps |
| T1579 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.1200431644 |
|
|
Feb 09 03:36:47 PM UTC 25 |
Feb 09 03:46:47 PM UTC 25 |
48724882965 ps |
| T1580 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.1251246206 |
|
|
Feb 09 03:46:27 PM UTC 25 |
Feb 09 03:46:48 PM UTC 25 |
158636982 ps |
| T1581 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.299952873 |
|
|
Feb 09 03:32:24 PM UTC 25 |
Feb 09 03:46:49 PM UTC 25 |
51423622502 ps |
| T1582 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.1898806331 |
|
|
Feb 09 03:46:26 PM UTC 25 |
Feb 09 03:46:49 PM UTC 25 |
340684576 ps |
| T1583 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.151745165 |
|
|
Feb 09 03:46:13 PM UTC 25 |
Feb 09 03:47:01 PM UTC 25 |
2688033425 ps |
| T465 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.1591511189 |
|
|
Feb 09 03:33:34 PM UTC 25 |
Feb 09 03:47:14 PM UTC 25 |
6224411515 ps |
| T1584 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.31681454 |
|
|
Feb 09 03:46:23 PM UTC 25 |
Feb 09 03:47:15 PM UTC 25 |
556900298 ps |
| T1585 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.2482332909 |
|
|
Feb 09 03:31:29 PM UTC 25 |
Feb 09 03:47:23 PM UTC 25 |
10317643742 ps |
| T1586 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.1711486831 |
|
|
Feb 09 03:46:30 PM UTC 25 |
Feb 09 03:47:26 PM UTC 25 |
926278957 ps |
| T1587 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.2143802017 |
|
|
Feb 09 03:47:16 PM UTC 25 |
Feb 09 03:47:27 PM UTC 25 |
53356924 ps |
| T1588 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.1059221845 |
|
|
Feb 09 03:47:14 PM UTC 25 |
Feb 09 03:47:30 PM UTC 25 |
251371855 ps |
| T1589 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.1989452447 |
|
|
Feb 09 03:46:04 PM UTC 25 |
Feb 09 03:47:33 PM UTC 25 |
1819612707 ps |
| T1590 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.145984642 |
|
|
Feb 09 03:47:05 PM UTC 25 |
Feb 09 03:47:39 PM UTC 25 |
863758553 ps |
| T849 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.2039636966 |
|
|
Feb 09 03:46:10 PM UTC 25 |
Feb 09 03:47:51 PM UTC 25 |
1633278283 ps |
| T1591 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.3836184122 |
|
|
Feb 09 03:47:38 PM UTC 25 |
Feb 09 03:47:55 PM UTC 25 |
145007414 ps |
| T1592 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.1471898119 |
|
|
Feb 09 03:45:59 PM UTC 25 |
Feb 09 03:48:04 PM UTC 25 |
5771590250 ps |
| T1593 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.2734633005 |
|
|
Feb 09 03:45:56 PM UTC 25 |
Feb 09 03:48:06 PM UTC 25 |
9489138922 ps |
| T1594 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.2423354559 |
|
|
Feb 09 03:48:05 PM UTC 25 |
Feb 09 03:48:18 PM UTC 25 |
135551195 ps |
| T420 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.2244926018 |
|
|
Feb 09 02:43:03 PM UTC 25 |
Feb 09 03:48:18 PM UTC 25 |
31973570652 ps |
| T858 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2108998015 |
|
|
Feb 09 03:15:33 PM UTC 25 |
Feb 09 03:48:34 PM UTC 25 |
113418086621 ps |
| T1595 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.4163545728 |
|
|
Feb 09 03:39:59 PM UTC 25 |
Feb 09 03:48:35 PM UTC 25 |
29970978196 ps |
| T1596 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.952419279 |
|
|
Feb 09 03:47:59 PM UTC 25 |
Feb 09 03:48:37 PM UTC 25 |
295516766 ps |
| T1597 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.260697266 |
|
|
Feb 09 03:38:55 PM UTC 25 |
Feb 09 03:48:37 PM UTC 25 |
5322524131 ps |
| T665 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.3815402010 |
|
|
Feb 09 03:43:49 PM UTC 25 |
Feb 09 03:48:40 PM UTC 25 |
3776469709 ps |
| T840 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.3711972964 |
|
|
Feb 09 03:42:36 PM UTC 25 |
Feb 09 03:48:43 PM UTC 25 |
21751986243 ps |
| T1598 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.3164641959 |
|
|
Feb 09 03:48:24 PM UTC 25 |
Feb 09 03:48:47 PM UTC 25 |
518636025 ps |
| T1599 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.267094945 |
|
|
Feb 09 03:47:15 PM UTC 25 |
Feb 09 03:48:50 PM UTC 25 |
7798307496 ps |
| T1600 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.3572952829 |
|
|
Feb 09 03:47:50 PM UTC 25 |
Feb 09 03:48:52 PM UTC 25 |
535431765 ps |
| T1601 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.3135090353 |
|
|
Feb 09 03:49:00 PM UTC 25 |
Feb 09 03:49:09 PM UTC 25 |
37948243 ps |
| T1602 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.3099629187 |
|
|
Feb 09 03:47:40 PM UTC 25 |
Feb 09 03:49:10 PM UTC 25 |
2446080713 ps |
| T1603 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.2571472799 |
|
|
Feb 09 03:49:01 PM UTC 25 |
Feb 09 03:49:12 PM UTC 25 |
46131488 ps |
| T1604 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.1158638440 |
|
|
Feb 09 03:46:37 PM UTC 25 |
Feb 09 03:49:11 PM UTC 25 |
3815438450 ps |
| T1605 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.2985869295 |
|
|
Feb 09 03:47:27 PM UTC 25 |
Feb 09 03:49:13 PM UTC 25 |
5972936506 ps |
| T1606 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.327512534 |
|
|
Feb 09 03:48:17 PM UTC 25 |
Feb 09 03:49:28 PM UTC 25 |
1222771707 ps |
| T1607 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.3228174155 |
|
|
Feb 09 03:19:04 PM UTC 25 |
Feb 09 03:49:36 PM UTC 25 |
15718377454 ps |
| T1608 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.2083642180 |
|
|
Feb 09 03:29:38 PM UTC 25 |
Feb 09 03:49:36 PM UTC 25 |
116202931398 ps |
| T1609 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.1097960591 |
|
|
Feb 09 03:35:53 PM UTC 25 |
Feb 09 03:49:44 PM UTC 25 |
7960812176 ps |
| T1610 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.3118318932 |
|
|
Feb 09 03:49:38 PM UTC 25 |
Feb 09 03:49:47 PM UTC 25 |
37237726 ps |
| T1611 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.3581254653 |
|
|
Feb 09 03:47:15 PM UTC 25 |
Feb 09 03:49:52 PM UTC 25 |
4051962720 ps |
| T1612 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.3353535689 |
|
|
Feb 09 03:49:11 PM UTC 25 |
Feb 09 03:49:54 PM UTC 25 |
396334389 ps |
| T1613 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.2590880748 |
|
|
Feb 09 03:49:36 PM UTC 25 |
Feb 09 03:49:56 PM UTC 25 |
289263781 ps |
| T1614 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.3577654295 |
|
|
Feb 09 03:49:56 PM UTC 25 |
Feb 09 03:50:08 PM UTC 25 |
44012958 ps |
| T883 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.2585410583 |
|
|
Feb 09 03:48:33 PM UTC 25 |
Feb 09 03:50:13 PM UTC 25 |
182220903 ps |
| T1615 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.3674709391 |
|
|
Feb 09 03:49:40 PM UTC 25 |
Feb 09 03:50:13 PM UTC 25 |
299209475 ps |
| T1616 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.761448258 |
|
|
Feb 09 03:49:09 PM UTC 25 |
Feb 09 03:50:16 PM UTC 25 |
1668456993 ps |
| T877 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2495352788 |
|
|
Feb 09 03:48:44 PM UTC 25 |
Feb 09 03:50:19 PM UTC 25 |
97599464 ps |
| T509 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.3685323364 |
|
|
Feb 09 03:30:57 PM UTC 25 |
Feb 09 03:50:24 PM UTC 25 |
27095718695 ps |
| T651 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.2322040638 |
|
|
Feb 09 03:45:34 PM UTC 25 |
Feb 09 03:50:25 PM UTC 25 |
3346000464 ps |
| T1617 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.777767887 |
|
|
Feb 09 03:50:18 PM UTC 25 |
Feb 09 03:50:26 PM UTC 25 |
44409147 ps |
| T1618 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.1556379241 |
|
|
Feb 09 03:50:20 PM UTC 25 |
Feb 09 03:50:35 PM UTC 25 |
232445451 ps |
| T1619 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.2757816626 |
|
|
Feb 09 03:49:01 PM UTC 25 |
Feb 09 03:50:42 PM UTC 25 |
6946828119 ps |
| T1620 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.164959651 |
|
|
Feb 09 03:49:06 PM UTC 25 |
Feb 09 03:50:56 PM UTC 25 |
4873602574 ps |
| T878 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.2635412575 |
|
|
Feb 09 03:47:12 PM UTC 25 |
Feb 09 03:51:02 PM UTC 25 |
694018795 ps |
| T1621 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.717287729 |
|
|
Feb 09 03:49:36 PM UTC 25 |
Feb 09 03:51:03 PM UTC 25 |
1020333039 ps |
| T1622 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.827752749 |
|
|
Feb 09 03:50:40 PM UTC 25 |
Feb 09 03:51:08 PM UTC 25 |
547937105 ps |
| T551 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.289640252 |
|
|
Feb 09 03:50:42 PM UTC 25 |
Feb 09 03:51:21 PM UTC 25 |
435288676 ps |
| T554 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.3077664843 |
|
|
Feb 09 03:43:41 PM UTC 25 |
Feb 09 03:51:37 PM UTC 25 |
2643498145 ps |
| T1623 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.3076028205 |
|
|
Feb 09 03:51:02 PM UTC 25 |
Feb 09 03:51:45 PM UTC 25 |
958557695 ps |
| T1624 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.2909171108 |
|
|
Feb 09 03:50:12 PM UTC 25 |
Feb 09 03:51:47 PM UTC 25 |
2673637628 ps |
| T859 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3076114041 |
|
|
Feb 09 03:20:00 PM UTC 25 |
Feb 09 03:51:55 PM UTC 25 |
136142272213 ps |
| T1625 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.2114132564 |
|
|
Feb 09 03:48:31 PM UTC 25 |
Feb 09 03:52:00 PM UTC 25 |
5720798765 ps |
| T1626 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.1261317783 |
|
|
Feb 09 03:51:23 PM UTC 25 |
Feb 09 03:52:05 PM UTC 25 |
284316662 ps |
| T1627 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.3508649767 |
|
|
Feb 09 03:50:35 PM UTC 25 |
Feb 09 03:52:11 PM UTC 25 |
8046150860 ps |
| T1628 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.4198543559 |
|
|
Feb 09 03:51:31 PM UTC 25 |
Feb 09 03:52:18 PM UTC 25 |
812481508 ps |
| T1629 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.4191742533 |
|
|
Feb 09 03:52:15 PM UTC 25 |
Feb 09 03:52:26 PM UTC 25 |
52318285 ps |
| T1630 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.4084847668 |
|
|
Feb 09 03:52:14 PM UTC 25 |
Feb 09 03:52:28 PM UTC 25 |
197121141 ps |
| T1631 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.795808822 |
|
|
Feb 09 03:48:45 PM UTC 25 |
Feb 09 03:52:29 PM UTC 25 |
2862532882 ps |
| T1632 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.3408138412 |
|
|
Feb 09 03:51:08 PM UTC 25 |
Feb 09 03:52:29 PM UTC 25 |
1777260783 ps |
| T1633 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.1477741599 |
|
|
Feb 09 03:51:49 PM UTC 25 |
Feb 09 03:52:34 PM UTC 25 |
62938987 ps |
| T656 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.11834395 |
|
|
Feb 09 03:49:00 PM UTC 25 |
Feb 09 03:52:34 PM UTC 25 |
3672183880 ps |
| T1634 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.3339966005 |
|
|
Feb 09 03:51:41 PM UTC 25 |
Feb 09 03:52:45 PM UTC 25 |
583540153 ps |
| T1635 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.228520878 |
|
|
Feb 09 03:50:38 PM UTC 25 |
Feb 09 03:52:45 PM UTC 25 |
5457135726 ps |
| T1636 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.1165979065 |
|
|
Feb 09 03:46:57 PM UTC 25 |
Feb 09 03:52:59 PM UTC 25 |
3658211006 ps |
| T1637 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.3395116575 |
|
|
Feb 09 03:52:31 PM UTC 25 |
Feb 09 03:53:02 PM UTC 25 |
278546139 ps |
| T1638 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.3100479043 |
|
|
Feb 09 03:50:49 PM UTC 25 |
Feb 09 03:53:03 PM UTC 25 |
3122216068 ps |
| T1639 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.1837729574 |
|
|
Feb 09 03:50:02 PM UTC 25 |
Feb 09 03:53:13 PM UTC 25 |
415156649 ps |
| T1640 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.202972669 |
|
|
Feb 09 03:53:09 PM UTC 25 |
Feb 09 03:53:30 PM UTC 25 |
111577774 ps |
| T1641 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.3902859718 |
|
|
Feb 09 03:51:31 PM UTC 25 |
Feb 09 03:53:34 PM UTC 25 |
3406199080 ps |
| T1642 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.2696228256 |
|
|
Feb 09 03:52:38 PM UTC 25 |
Feb 09 03:53:36 PM UTC 25 |
648982645 ps |
| T1643 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.2232689392 |
|
|
Feb 09 03:52:26 PM UTC 25 |
Feb 09 03:53:40 PM UTC 25 |
3618124742 ps |
| T1644 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.1146792580 |
|
|
Feb 09 03:52:55 PM UTC 25 |
Feb 09 03:53:43 PM UTC 25 |
511892007 ps |
| T1645 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.1781821772 |
|
|
Feb 09 03:52:57 PM UTC 25 |
Feb 09 03:53:47 PM UTC 25 |
577027016 ps |
| T1646 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.2806020374 |
|
|
Feb 09 03:52:19 PM UTC 25 |
Feb 09 03:53:59 PM UTC 25 |
9297498532 ps |
| T1647 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.1210400199 |
|
|
Feb 09 03:53:02 PM UTC 25 |
Feb 09 03:54:02 PM UTC 25 |
1081979408 ps |
| T1648 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.4132088681 |
|
|
Feb 09 03:53:56 PM UTC 25 |
Feb 09 03:54:06 PM UTC 25 |
48878998 ps |
| T1649 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.2209683809 |
|
|
Feb 09 03:54:00 PM UTC 25 |
Feb 09 03:54:08 PM UTC 25 |
57099086 ps |
| T1650 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.311775527 |
|
|
Feb 09 03:53:00 PM UTC 25 |
Feb 09 03:54:16 PM UTC 25 |
2318342991 ps |
| T1651 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.3964295337 |
|
|
Feb 09 03:36:47 PM UTC 25 |
Feb 09 03:54:19 PM UTC 25 |
68321496622 ps |
| T1652 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.2487108469 |
|
|
Feb 09 03:53:30 PM UTC 25 |
Feb 09 03:54:20 PM UTC 25 |
163430364 ps |
| T1653 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.1102196288 |
|
|
Feb 09 03:54:10 PM UTC 25 |
Feb 09 03:54:24 PM UTC 25 |
72819519 ps |
| T1654 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.3570489794 |
|
|
Feb 09 03:50:51 PM UTC 25 |
Feb 09 03:54:43 PM UTC 25 |
11775851238 ps |
| T1655 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.252754180 |
|
|
Feb 09 03:46:10 PM UTC 25 |
Feb 09 03:55:04 PM UTC 25 |
30660231097 ps |
| T1656 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.2468652175 |
|
|
Feb 09 03:54:47 PM UTC 25 |
Feb 09 03:55:06 PM UTC 25 |
226790319 ps |
| T1657 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.2535718895 |
|
|
Feb 09 03:54:53 PM UTC 25 |
Feb 09 03:55:06 PM UTC 25 |
149189354 ps |
| T1658 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.1598175247 |
|
|
Feb 09 03:54:47 PM UTC 25 |
Feb 09 03:55:07 PM UTC 25 |
393315387 ps |
| T1659 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.3755825757 |
|
|
Feb 09 03:54:02 PM UTC 25 |
Feb 09 03:55:07 PM UTC 25 |
6532103063 ps |
| T890 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.1863697489 |
|
|
Feb 09 03:50:12 PM UTC 25 |
Feb 09 03:55:19 PM UTC 25 |
891473539 ps |
| T1660 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.923598783 |
|
|
Feb 09 03:49:19 PM UTC 25 |
Feb 09 03:55:23 PM UTC 25 |
24283866898 ps |
| T1661 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.2090382136 |
|
|
Feb 09 03:53:11 PM UTC 25 |
Feb 09 03:55:26 PM UTC 25 |
1595756381 ps |
| T654 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.1383239754 |
|
|
Feb 09 03:52:03 PM UTC 25 |
Feb 09 03:55:27 PM UTC 25 |
3644697283 ps |
| T1662 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.3573073264 |
|
|
Feb 09 03:54:44 PM UTC 25 |
Feb 09 03:55:35 PM UTC 25 |
1872432656 ps |
| T527 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.3803304314 |
|
|
Feb 09 03:45:19 PM UTC 25 |
Feb 09 03:55:35 PM UTC 25 |
3504849537 ps |
| T1663 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.4199792588 |
|
|
Feb 09 03:55:35 PM UTC 25 |
Feb 09 03:55:46 PM UTC 25 |
55057049 ps |
| T1664 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.431891087 |
|
|
Feb 09 03:50:14 PM UTC 25 |
Feb 09 03:55:47 PM UTC 25 |
3713173376 ps |
| T1665 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.905645435 |
|
|
Feb 09 03:55:34 PM UTC 25 |
Feb 09 03:55:48 PM UTC 25 |
7692193 ps |
| T1666 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.4157722355 |
|
|
Feb 09 03:55:35 PM UTC 25 |
Feb 09 03:55:50 PM UTC 25 |
212541099 ps |
| T1667 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.2011728938 |
|
|
Feb 09 03:45:23 PM UTC 25 |
Feb 09 03:55:50 PM UTC 25 |
13201498181 ps |
| T1668 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.3204391173 |
|
|
Feb 09 03:54:05 PM UTC 25 |
Feb 09 03:55:52 PM UTC 25 |
5504848337 ps |
| T1669 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.1088867786 |
|
|
Feb 09 03:52:54 PM UTC 25 |
Feb 09 03:55:57 PM UTC 25 |
11646381639 ps |
| T1670 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.2683262678 |
|
|
Feb 09 03:54:08 PM UTC 25 |
Feb 09 03:55:57 PM UTC 25 |
2388634983 ps |
| T1671 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.2203827589 |
|
|
Feb 09 03:55:54 PM UTC 25 |
Feb 09 03:56:25 PM UTC 25 |
217979278 ps |
| T1672 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.1888369684 |
|
|
Feb 09 03:56:20 PM UTC 25 |
Feb 09 03:56:34 PM UTC 25 |
249559761 ps |
| T1673 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1557857179 |
|
|
Feb 09 03:53:26 PM UTC 25 |
Feb 09 03:56:35 PM UTC 25 |
244642556 ps |
| T1674 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.2477023980 |
|
|
Feb 09 03:56:13 PM UTC 25 |
Feb 09 03:56:38 PM UTC 25 |
142408249 ps |
| T546 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.2105390771 |
|
|
Feb 09 03:50:01 PM UTC 25 |
Feb 09 03:56:41 PM UTC 25 |
9206907235 ps |
| T854 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.3458336611 |
|
|
Feb 09 03:54:33 PM UTC 25 |
Feb 09 03:56:45 PM UTC 25 |
2440258657 ps |
| T1675 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.3026536201 |
|
|
Feb 09 03:39:55 PM UTC 25 |
Feb 09 03:56:53 PM UTC 25 |
94004488783 ps |
| T1676 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.1037994747 |
|
|
Feb 09 03:56:15 PM UTC 25 |
Feb 09 03:56:55 PM UTC 25 |
468620489 ps |
| T1677 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.3976596994 |
|
|
Feb 09 03:56:18 PM UTC 25 |
Feb 09 03:56:59 PM UTC 25 |
566686203 ps |
| T1678 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.2672140301 |
|
|
Feb 09 03:55:51 PM UTC 25 |
Feb 09 03:57:01 PM UTC 25 |
4272992582 ps |
| T1679 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.2614086664 |
|
|
Feb 09 03:55:54 PM UTC 25 |
Feb 09 03:57:04 PM UTC 25 |
585963445 ps |
| T1680 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.1504061940 |
|
|
Feb 09 03:57:03 PM UTC 25 |
Feb 09 03:57:13 PM UTC 25 |
44629036 ps |
| T1681 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.3919122529 |
|
|
Feb 09 03:57:02 PM UTC 25 |
Feb 09 03:57:16 PM UTC 25 |
203560111 ps |
| T1682 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.1114563108 |
|
|
Feb 09 03:56:16 PM UTC 25 |
Feb 09 03:57:18 PM UTC 25 |
604885185 ps |
| T1683 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.1202246348 |
|
|
Feb 09 03:55:46 PM UTC 25 |
Feb 09 03:57:26 PM UTC 25 |
8382109738 ps |
| T1684 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.2413574330 |
|
|
Feb 09 03:56:25 PM UTC 25 |
Feb 09 03:57:27 PM UTC 25 |
340974404 ps |
| T1685 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.2599868041 |
|
|
Feb 09 03:55:11 PM UTC 25 |
Feb 09 03:57:30 PM UTC 25 |
3082853304 ps |
| T518 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.1030739810 |
|
|
Feb 09 03:56:25 PM UTC 25 |
Feb 09 03:57:30 PM UTC 25 |
1810876049 ps |
| T1686 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.1249134922 |
|
|
Feb 09 03:57:23 PM UTC 25 |
Feb 09 03:57:57 PM UTC 25 |
246564703 ps |
| T1687 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.1684126947 |
|
|
Feb 09 03:57:43 PM UTC 25 |
Feb 09 03:57:58 PM UTC 25 |
81050631 ps |
| T1688 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.4118152250 |
|
|
Feb 09 03:57:02 PM UTC 25 |
Feb 09 03:58:01 PM UTC 25 |
182998641 ps |
| T1689 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.1937210327 |
|
|
Feb 09 02:45:17 PM UTC 25 |
Feb 09 03:58:03 PM UTC 25 |
41969731224 ps |
| T1690 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.450534887 |
|
|
Feb 09 03:53:41 PM UTC 25 |
Feb 09 03:58:10 PM UTC 25 |
3605052990 ps |
| T1691 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.2037374257 |
|
|
Feb 09 03:57:17 PM UTC 25 |
Feb 09 03:58:11 PM UTC 25 |
567932812 ps |
| T1692 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.2197779052 |
|
|
Feb 09 03:57:54 PM UTC 25 |
Feb 09 03:58:13 PM UTC 25 |
273174819 ps |
| T1693 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.2190679993 |
|
|
Feb 09 03:53:30 PM UTC 25 |
Feb 09 03:58:17 PM UTC 25 |
7484600928 ps |
| T431 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.1663953255 |
|
|
Feb 09 02:45:38 PM UTC 25 |
Feb 09 03:58:25 PM UTC 25 |
30421103018 ps |
| T1694 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.1645634388 |
|
|
Feb 09 03:57:31 PM UTC 25 |
Feb 09 03:58:26 PM UTC 25 |
1252131751 ps |
| T1695 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.2190612992 |
|
|
Feb 09 03:58:29 PM UTC 25 |
Feb 09 03:58:40 PM UTC 25 |
52958139 ps |
| T1696 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.2243524050 |
|
|
Feb 09 03:58:30 PM UTC 25 |
Feb 09 03:58:40 PM UTC 25 |
45801816 ps |
| T821 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.3008683180 |
|
|
Feb 09 03:47:57 PM UTC 25 |
Feb 09 03:58:45 PM UTC 25 |
39027744648 ps |
| T1697 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.1686238569 |
|
|
Feb 09 03:57:40 PM UTC 25 |
Feb 09 03:58:48 PM UTC 25 |
2061006423 ps |
| T555 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.2948323512 |
|
|
Feb 09 03:57:52 PM UTC 25 |
Feb 09 03:58:48 PM UTC 25 |
1391639039 ps |
| T1698 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.200765332 |
|
|
Feb 09 03:57:12 PM UTC 25 |
Feb 09 03:58:54 PM UTC 25 |
4234724503 ps |
| T1699 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.2956103680 |
|
|
Feb 09 03:11:46 PM UTC 25 |
Feb 09 03:58:57 PM UTC 25 |
16048656986 ps |
| T1700 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.3329083949 |
|
|
Feb 09 03:58:42 PM UTC 25 |
Feb 09 03:59:04 PM UTC 25 |
449881187 ps |
| T1701 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.4045941080 |
|
|
Feb 09 03:57:08 PM UTC 25 |
Feb 09 03:59:07 PM UTC 25 |
9593707020 ps |
| T1702 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.4209853470 |
|
|
Feb 09 03:58:44 PM UTC 25 |
Feb 09 03:59:15 PM UTC 25 |
238966264 ps |
| T1703 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.1328846939 |
|
|
Feb 09 03:44:38 PM UTC 25 |
Feb 09 03:59:25 PM UTC 25 |
53871442744 ps |
| T1704 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.332357161 |
|
|
Feb 09 03:57:57 PM UTC 25 |
Feb 09 03:59:26 PM UTC 25 |
1117425819 ps |
| T1705 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.3088565618 |
|
|
Feb 09 03:59:12 PM UTC 25 |
Feb 09 03:59:28 PM UTC 25 |
367094874 ps |
| T1706 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.28585113 |
|
|
Feb 09 03:55:31 PM UTC 25 |
Feb 09 03:59:29 PM UTC 25 |
586980594 ps |
| T1707 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.2307440310 |
|
|
Feb 09 03:59:15 PM UTC 25 |
Feb 09 03:59:33 PM UTC 25 |
230322716 ps |
| T1708 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.1758413336 |
|
|
Feb 09 03:41:55 PM UTC 25 |
Feb 09 03:59:38 PM UTC 25 |
84416433511 ps |
| T1709 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.343676854 |
|
|
Feb 09 03:59:14 PM UTC 25 |
Feb 09 03:59:40 PM UTC 25 |
560149520 ps |
| T1710 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.1620529476 |
|
|
Feb 09 03:59:22 PM UTC 25 |
Feb 09 03:59:44 PM UTC 25 |
290108123 ps |
| T1711 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.1910814153 |
|
|
Feb 09 03:24:45 PM UTC 25 |
Feb 09 03:59:50 PM UTC 25 |
16933930224 ps |
| T1712 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.2678360980 |
|
|
Feb 09 03:59:46 PM UTC 25 |
Feb 09 03:59:57 PM UTC 25 |
158350569 ps |
| T1713 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.3137521772 |
|
|
Feb 09 03:59:52 PM UTC 25 |
Feb 09 04:00:01 PM UTC 25 |
51619717 ps |
| T1714 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.158356910 |
|
|
Feb 09 03:59:36 PM UTC 25 |
Feb 09 04:00:02 PM UTC 25 |
517776829 ps |
| T1715 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.3110638608 |
|
|
Feb 09 03:58:38 PM UTC 25 |
Feb 09 04:00:12 PM UTC 25 |
7343520664 ps |
| T1716 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.2302404925 |
|
|
Feb 09 03:59:08 PM UTC 25 |
Feb 09 04:00:13 PM UTC 25 |
607090949 ps |
| T1717 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.2072618928 |
|
|
Feb 09 03:58:38 PM UTC 25 |
Feb 09 04:00:25 PM UTC 25 |
6387842110 ps |
| T1718 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.3979271595 |
|
|
Feb 09 04:00:04 PM UTC 25 |
Feb 09 04:00:41 PM UTC 25 |
277390851 ps |
| T1719 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.2915369598 |
|
|
Feb 09 03:59:59 PM UTC 25 |
Feb 09 04:00:45 PM UTC 25 |
362971526 ps |
| T1720 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.2519656749 |
|
|
Feb 09 04:00:18 PM UTC 25 |
Feb 09 04:00:52 PM UTC 25 |
617353259 ps |
| T1721 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.2371694280 |
|
|
Feb 09 04:00:37 PM UTC 25 |
Feb 09 04:00:57 PM UTC 25 |
113241000 ps |
| T1722 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.255849812 |
|
|
Feb 09 04:00:41 PM UTC 25 |
Feb 09 04:01:03 PM UTC 25 |
124362784 ps |
| T633 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.1691341435 |
|
|
Feb 09 03:55:33 PM UTC 25 |
Feb 09 04:01:09 PM UTC 25 |
4223864510 ps |
| T1723 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.1827391581 |
|
|
Feb 09 03:59:52 PM UTC 25 |
Feb 09 04:01:14 PM UTC 25 |
5051328625 ps |
| T1724 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.2858948834 |
|
|
Feb 09 04:00:35 PM UTC 25 |
Feb 09 04:01:20 PM UTC 25 |
394475110 ps |
| T1725 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.832469277 |
|
|
Feb 09 03:51:36 PM UTC 25 |
Feb 09 04:01:21 PM UTC 25 |
2883248727 ps |
| T1726 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.3508066596 |
|
|
Feb 09 04:00:37 PM UTC 25 |
Feb 09 04:01:33 PM UTC 25 |
1495843391 ps |
| T1727 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.2465723082 |
|
|
Feb 09 04:01:26 PM UTC 25 |
Feb 09 04:01:35 PM UTC 25 |
49967036 ps |
| T1728 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.2539227027 |
|
|
Feb 09 03:28:34 PM UTC 25 |
Feb 09 04:01:37 PM UTC 25 |
15056193500 ps |
| T1729 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.3115347464 |
|
|
Feb 09 04:01:31 PM UTC 25 |
Feb 09 04:01:41 PM UTC 25 |
45773057 ps |
| T1730 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.2759575905 |
|
|
Feb 09 03:59:54 PM UTC 25 |
Feb 09 04:01:42 PM UTC 25 |
8226393879 ps |
| T1731 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2687039501 |
|
|
Feb 09 04:01:20 PM UTC 25 |
Feb 09 04:01:43 PM UTC 25 |
105460313 ps |
| T1732 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.2905060738 |
|
|
Feb 09 03:56:54 PM UTC 25 |
Feb 09 04:02:04 PM UTC 25 |
3896991566 ps |
| T1733 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.3644588971 |
|
|
Feb 09 03:44:32 PM UTC 25 |
Feb 09 04:02:15 PM UTC 25 |
99802401794 ps |
| T1734 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.2959036296 |
|
|
Feb 09 03:49:16 PM UTC 25 |
Feb 09 04:02:18 PM UTC 25 |
63926991003 ps |
| T1735 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.669474459 |
|
|
Feb 09 04:01:41 PM UTC 25 |
Feb 09 04:02:19 PM UTC 25 |
296861061 ps |
| T519 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.3058692188 |
|
|
Feb 09 03:52:46 PM UTC 25 |
Feb 09 04:02:32 PM UTC 25 |
53024310118 ps |
| T1736 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.2091821378 |
|
|
Feb 09 04:01:08 PM UTC 25 |
Feb 09 04:02:46 PM UTC 25 |
225551561 ps |
| T1737 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.762517095 |
|
|
Feb 09 04:01:47 PM UTC 25 |
Feb 09 04:02:50 PM UTC 25 |
547650326 ps |
| T881 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.4030673983 |
|
|
Feb 09 03:59:32 PM UTC 25 |
Feb 09 04:03:08 PM UTC 25 |
2131791260 ps |
| T1738 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.2193191335 |
|
|
Feb 09 04:01:36 PM UTC 25 |
Feb 09 04:03:14 PM UTC 25 |
8016208973 ps |
| T1739 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.1116396158 |
|
|
Feb 09 04:01:41 PM UTC 25 |
Feb 09 04:03:14 PM UTC 25 |
5834501612 ps |
| T1740 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.329267821 |
|
|
Feb 09 04:02:42 PM UTC 25 |
Feb 09 04:03:16 PM UTC 25 |
210355174 ps |
| T1741 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.946676695 |
|
|
Feb 09 04:02:30 PM UTC 25 |
Feb 09 04:03:17 PM UTC 25 |
288659784 ps |
| T1742 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.2039584585 |
|
|
Feb 09 04:02:09 PM UTC 25 |
Feb 09 04:03:23 PM UTC 25 |
1684889009 ps |
| T427 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.370802799 |
|
|
Feb 09 02:51:11 PM UTC 25 |
Feb 09 04:03:25 PM UTC 25 |
30079549659 ps |
| T1743 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.2247027882 |
|
|
Feb 09 03:59:25 PM UTC 25 |
Feb 09 04:03:26 PM UTC 25 |
2531287551 ps |
| T503 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.3543412341 |
|
|
Feb 09 04:03:16 PM UTC 25 |
Feb 09 04:03:27 PM UTC 25 |
52013029 ps |
| T1744 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.1436762344 |
|
|
Feb 09 04:03:29 PM UTC 25 |
Feb 09 04:03:40 PM UTC 25 |
49164606 ps |
| T1745 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.2072650868 |
|
|
Feb 09 04:02:01 PM UTC 25 |
Feb 09 04:03:40 PM UTC 25 |
6937094366 ps |
| T1746 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.1523558722 |
|
|
Feb 09 02:43:00 PM UTC 25 |
Feb 09 04:03:58 PM UTC 25 |
30976330441 ps |
| T1747 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.1561117810 |
|
|
Feb 09 04:02:03 PM UTC 25 |
Feb 09 04:04:01 PM UTC 25 |
2552325556 ps |
| T1748 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.2286455412 |
|
|
Feb 09 04:03:41 PM UTC 25 |
Feb 09 04:04:08 PM UTC 25 |
245393704 ps |
| T1749 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.58844811 |
|
|
Feb 09 04:02:09 PM UTC 25 |
Feb 09 04:04:11 PM UTC 25 |
2520467371 ps |
| T1750 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.4234838969 |
|
|
Feb 09 04:03:44 PM UTC 25 |
Feb 09 04:04:11 PM UTC 25 |
453797651 ps |
| T1751 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.139064228 |
|
|
Feb 09 03:47:49 PM UTC 25 |
Feb 09 04:04:12 PM UTC 25 |
94728611642 ps |
| T1752 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.1379099329 |
|
|
Feb 09 03:47:55 PM UTC 25 |
Feb 09 04:04:38 PM UTC 25 |
66233543830 ps |
| T1753 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.3596529566 |
|
|
Feb 09 04:04:29 PM UTC 25 |
Feb 09 04:04:46 PM UTC 25 |
86574334 ps |
| T1754 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1681377560 |
|
|
Feb 09 04:04:37 PM UTC 25 |
Feb 09 04:04:50 PM UTC 25 |
10236902 ps |
| T1755 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.320539586 |
|
|
Feb 09 04:03:00 PM UTC 25 |
Feb 09 04:04:53 PM UTC 25 |
1224815579 ps |
| T1756 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.883411975 |
|
|
Feb 09 04:03:38 PM UTC 25 |
Feb 09 04:04:56 PM UTC 25 |
3937712456 ps |
| T1757 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.2516812006 |
|
|
Feb 09 04:04:06 PM UTC 25 |
Feb 09 04:04:57 PM UTC 25 |
461254461 ps |
| T1758 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.834061695 |
|
|
Feb 09 04:04:26 PM UTC 25 |
Feb 09 04:05:07 PM UTC 25 |
238747059 ps |
| T1759 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.3363080583 |
|
|
Feb 09 04:03:41 PM UTC 25 |
Feb 09 04:05:13 PM UTC 25 |
8982699538 ps |
| T1760 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.1620169543 |
|
|
Feb 09 04:04:05 PM UTC 25 |
Feb 09 04:05:15 PM UTC 25 |
1566890353 ps |
| T1761 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.2914336727 |
|
|
Feb 09 04:05:06 PM UTC 25 |
Feb 09 04:05:17 PM UTC 25 |
47480347 ps |
| T1762 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.1767045569 |
|
|
Feb 09 03:46:07 PM UTC 25 |
Feb 09 04:05:22 PM UTC 25 |
115796882390 ps |
| T1763 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.478480765 |
|
|
Feb 09 04:00:09 PM UTC 25 |
Feb 09 04:05:23 PM UTC 25 |
16548823601 ps |
| T1764 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.1144798010 |
|
|
Feb 09 02:53:27 PM UTC 25 |
Feb 09 04:05:23 PM UTC 25 |
28892582748 ps |
| T1765 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.3358839113 |
|
|
Feb 09 04:03:53 PM UTC 25 |
Feb 09 04:05:24 PM UTC 25 |
1159403114 ps |
| T1766 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.4201105388 |
|
|
Feb 09 04:05:15 PM UTC 25 |
Feb 09 04:05:25 PM UTC 25 |
43020591 ps |
| T1767 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.1178201909 |
|
|
Feb 09 03:56:02 PM UTC 25 |
Feb 09 04:05:31 PM UTC 25 |
54090629340 ps |
| T1768 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.4288820004 |
|
|
Feb 09 03:58:24 PM UTC 25 |
Feb 09 04:05:34 PM UTC 25 |
12115547434 ps |
| T1769 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.3603048264 |
|
|
Feb 09 04:01:13 PM UTC 25 |
Feb 09 04:05:52 PM UTC 25 |
7176114845 ps |
| T1770 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.928460449 |
|
|
Feb 09 04:05:25 PM UTC 25 |
Feb 09 04:05:59 PM UTC 25 |
957378566 ps |
| T1771 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.3362090945 |
|
|
Feb 09 04:03:47 PM UTC 25 |
Feb 09 04:06:00 PM UTC 25 |
13449237677 ps |
| T1772 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.1869372993 |
|
|
Feb 09 04:12:00 PM UTC 25 |
Feb 09 04:12:11 PM UTC 25 |
49826782 ps |
| T1773 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.2058875422 |
|
|
Feb 09 04:05:25 PM UTC 25 |
Feb 09 04:06:04 PM UTC 25 |
368728927 ps |
| T866 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.2215329799 |
|
|
Feb 09 03:59:43 PM UTC 25 |
Feb 09 04:06:13 PM UTC 25 |
4451954224 ps |
| T1774 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3654871944 |
|
|
Feb 09 04:05:52 PM UTC 25 |
Feb 09 04:06:33 PM UTC 25 |
253520099 ps |
| T1775 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.2115185250 |
|
|
Feb 09 04:05:47 PM UTC 25 |
Feb 09 04:06:33 PM UTC 25 |
535422048 ps |
| T1776 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.4170416972 |
|
|
Feb 09 04:06:23 PM UTC 25 |
Feb 09 04:06:34 PM UTC 25 |
57975120 ps |
| T1777 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.3255525956 |
|
|
Feb 09 04:05:49 PM UTC 25 |
Feb 09 04:06:37 PM UTC 25 |
264996300 ps |
| T1778 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.661622156 |
|
|
Feb 09 04:06:28 PM UTC 25 |
Feb 09 04:06:39 PM UTC 25 |
54434010 ps |
| T1779 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.1432808986 |
|
|
Feb 09 04:04:36 PM UTC 25 |
Feb 09 04:06:40 PM UTC 25 |
3199456287 ps |
| T1780 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.2218591625 |
|
|
Feb 09 04:05:20 PM UTC 25 |
Feb 09 04:07:04 PM UTC 25 |
5011178265 ps |
| T1781 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.5819224 |
|
|
Feb 09 03:58:53 PM UTC 25 |
Feb 09 04:07:04 PM UTC 25 |
48484180440 ps |
| T1782 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.1376000422 |
|
|
Feb 09 04:05:49 PM UTC 25 |
Feb 09 04:07:05 PM UTC 25 |
1628609892 ps |
| T1783 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.774238265 |
|
|
Feb 09 03:56:01 PM UTC 25 |
Feb 09 04:07:12 PM UTC 25 |
33273092474 ps |
| T1784 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.274628777 |
|
|
Feb 09 04:04:40 PM UTC 25 |
Feb 09 04:07:18 PM UTC 25 |
4195411544 ps |
| T1785 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.167285043 |
|
|
Feb 09 03:13:58 PM UTC 25 |
Feb 09 04:07:30 PM UTC 25 |
29794083724 ps |
| T1786 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.2061102427 |
|
|
Feb 09 04:07:07 PM UTC 25 |
Feb 09 04:07:32 PM UTC 25 |
311885627 ps |
| T1787 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.1025744605 |
|
|
Feb 09 04:07:33 PM UTC 25 |
Feb 09 04:07:46 PM UTC 25 |
77059104 ps |
| T528 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.2704239579 |
|
|
Feb 09 04:05:41 PM UTC 25 |
Feb 09 04:07:49 PM UTC 25 |
3112071770 ps |
| T1788 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.2551024317 |
|
|
Feb 09 04:06:42 PM UTC 25 |
Feb 09 04:07:54 PM UTC 25 |
3426794262 ps |
| T1789 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.2540223521 |
|
|
Feb 09 04:07:02 PM UTC 25 |
Feb 09 04:07:55 PM UTC 25 |
441813089 ps |
| T1790 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.3504797948 |
|
|
Feb 09 03:58:53 PM UTC 25 |
Feb 09 04:08:01 PM UTC 25 |
35570699614 ps |
| T1791 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2960772064 |
|
|
Feb 09 03:56:15 PM UTC 25 |
Feb 09 04:08:01 PM UTC 25 |
34393796766 ps |
| T1792 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.304716634 |
|
|
Feb 09 04:05:16 PM UTC 25 |
Feb 09 04:08:03 PM UTC 25 |
11210826429 ps |
| T1793 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.2298867137 |
|
|
Feb 09 04:07:39 PM UTC 25 |
Feb 09 04:08:20 PM UTC 25 |
703530950 ps |