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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.95 95.51 93.50 95.41 94.18 97.57 99.53


Total test records in report: 2918
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T1601 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.3998785047 Oct 15 03:23:45 PM UTC 24 Oct 15 03:24:45 PM UTC 24 2803393369 ps
T1602 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.1749707994 Oct 15 03:24:09 PM UTC 24 Oct 15 03:24:47 PM UTC 24 454723317 ps
T1603 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.1507688988 Oct 15 03:19:02 PM UTC 24 Oct 15 03:24:58 PM UTC 24 5046639226 ps
T1604 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.4049444682 Oct 15 03:24:48 PM UTC 24 Oct 15 03:24:59 PM UTC 24 49967617 ps
T1605 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.1102721507 Oct 15 03:24:12 PM UTC 24 Oct 15 03:25:02 PM UTC 24 810538373 ps
T1606 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.2062051383 Oct 15 03:24:56 PM UTC 24 Oct 15 03:25:05 PM UTC 24 58883039 ps
T1607 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.3110987605 Oct 15 03:24:23 PM UTC 24 Oct 15 03:25:25 PM UTC 24 598678582 ps
T1608 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.3887162803 Oct 15 03:19:44 PM UTC 24 Oct 15 03:25:27 PM UTC 24 24547445880 ps
T1609 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.451374315 Oct 15 03:24:05 PM UTC 24 Oct 15 03:25:37 PM UTC 24 982964107 ps
T1610 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.2275920396 Oct 15 03:25:05 PM UTC 24 Oct 15 03:25:38 PM UTC 24 310098596 ps
T1611 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.3329584504 Oct 15 03:22:25 PM UTC 24 Oct 15 03:25:45 PM UTC 24 3519129412 ps
T1612 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.3268488979 Oct 15 03:25:32 PM UTC 24 Oct 15 03:25:46 PM UTC 24 55641631 ps
T855 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.1094757506 Oct 15 03:22:17 PM UTC 24 Oct 15 03:25:57 PM UTC 24 658498691 ps
T1613 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.582048843 Oct 15 03:25:25 PM UTC 24 Oct 15 03:25:58 PM UTC 24 433508783 ps
T1614 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.4226391496 Oct 15 03:22:51 PM UTC 24 Oct 15 03:26:01 PM UTC 24 3263629324 ps
T1615 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.590535679 Oct 15 02:57:09 PM UTC 24 Oct 15 03:26:01 PM UTC 24 15841163272 ps
T1616 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.2526853413 Oct 15 03:18:52 PM UTC 24 Oct 15 03:26:02 PM UTC 24 5999851244 ps
T1617 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.4093512999 Oct 15 03:22:48 PM UTC 24 Oct 15 03:26:09 PM UTC 24 10428078683 ps
T1618 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.568792738 Oct 15 03:25:02 PM UTC 24 Oct 15 03:26:11 PM UTC 24 5107527970 ps
T1619 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.2211334232 Oct 15 03:25:52 PM UTC 24 Oct 15 03:26:17 PM UTC 24 232816376 ps
T1620 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.1621176005 Oct 15 03:25:28 PM UTC 24 Oct 15 03:26:18 PM UTC 24 446135615 ps
T1621 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.3886527282 Oct 15 03:25:06 PM UTC 24 Oct 15 03:26:24 PM UTC 24 635513651 ps
T1622 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.3737682202 Oct 15 03:25:14 PM UTC 24 Oct 15 03:26:26 PM UTC 24 822844343 ps
T1623 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.1779770359 Oct 15 03:24:45 PM UTC 24 Oct 15 03:26:34 PM UTC 24 2780448950 ps
T1624 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.2397236097 Oct 15 03:26:25 PM UTC 24 Oct 15 03:26:34 PM UTC 24 44350379 ps
T1625 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.2854003317 Oct 15 03:26:23 PM UTC 24 Oct 15 03:26:36 PM UTC 24 154077527 ps
T482 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.1213321808 Oct 15 03:21:19 PM UTC 24 Oct 15 03:26:38 PM UTC 24 3631144980 ps
T1626 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.12724825 Oct 15 03:22:46 PM UTC 24 Oct 15 03:26:46 PM UTC 24 21972460166 ps
T1627 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.1518447547 Oct 15 03:24:56 PM UTC 24 Oct 15 03:26:55 PM UTC 24 9505109956 ps
T1628 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.2286536437 Oct 15 03:26:51 PM UTC 24 Oct 15 03:27:11 PM UTC 24 168520532 ps
T845 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.4252469196 Oct 15 03:22:15 PM UTC 24 Oct 15 03:27:18 PM UTC 24 8049825886 ps
T1629 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.1473717916 Oct 15 03:26:28 PM UTC 24 Oct 15 03:27:19 PM UTC 24 1385100525 ps
T1630 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.3872923995 Oct 15 03:27:02 PM UTC 24 Oct 15 03:27:24 PM UTC 24 403766918 ps
T1631 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.3038772150 Oct 15 03:27:13 PM UTC 24 Oct 15 03:27:25 PM UTC 24 6810756 ps
T1632 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.2269528965 Oct 15 03:25:08 PM UTC 24 Oct 15 03:27:26 PM UTC 24 8296327976 ps
T1633 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.2526472558 Oct 15 03:26:35 PM UTC 24 Oct 15 03:27:28 PM UTC 24 609313633 ps
T1634 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.4009319624 Oct 15 03:26:59 PM UTC 24 Oct 15 03:27:34 PM UTC 24 236229604 ps
T1635 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.1976804444 Oct 15 03:26:26 PM UTC 24 Oct 15 03:27:41 PM UTC 24 4363041343 ps
T1636 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.1257755104 Oct 15 03:26:46 PM UTC 24 Oct 15 03:27:44 PM UTC 24 646844431 ps
T515 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.953828357 Oct 15 03:13:31 PM UTC 24 Oct 15 03:27:49 PM UTC 24 50232632716 ps
T1637 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.1055052493 Oct 15 03:27:01 PM UTC 24 Oct 15 03:27:54 PM UTC 24 1155534372 ps
T1638 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.1414807084 Oct 15 03:27:44 PM UTC 24 Oct 15 03:27:54 PM UTC 24 48660360 ps
T880 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.1332641478 Oct 15 03:26:13 PM UTC 24 Oct 15 03:27:56 PM UTC 24 330502622 ps
T1639 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.71296855 Oct 15 03:27:48 PM UTC 24 Oct 15 03:27:56 PM UTC 24 48008890 ps
T1640 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.621796116 Oct 15 03:20:53 PM UTC 24 Oct 15 03:28:07 PM UTC 24 24738705654 ps
T889 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.688448254 Oct 15 03:26:02 PM UTC 24 Oct 15 03:28:09 PM UTC 24 275866052 ps
T1641 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.4049799130 Oct 15 03:26:27 PM UTC 24 Oct 15 03:28:09 PM UTC 24 8194618420 ps
T645 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.3963597407 Oct 15 03:21:26 PM UTC 24 Oct 15 03:28:24 PM UTC 24 11155253730 ps
T1642 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.2235701338 Oct 15 03:28:01 PM UTC 24 Oct 15 03:28:25 PM UTC 24 154128173 ps
T536 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.3283537269 Oct 15 03:27:53 PM UTC 24 Oct 15 03:28:45 PM UTC 24 512571734 ps
T1643 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.2103736706 Oct 15 03:28:19 PM UTC 24 Oct 15 03:28:47 PM UTC 24 849350200 ps
T1644 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.228174905 Oct 15 03:28:22 PM UTC 24 Oct 15 03:28:50 PM UTC 24 803306047 ps
T1645 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.1909400160 Oct 15 03:22:01 PM UTC 24 Oct 15 03:28:51 PM UTC 24 24945211387 ps
T1646 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.2704470344 Oct 15 03:28:49 PM UTC 24 Oct 15 03:29:00 PM UTC 24 69007632 ps
T1647 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.207428714 Oct 15 03:20:52 PM UTC 24 Oct 15 03:29:17 PM UTC 24 57417753797 ps
T642 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.1440066468 Oct 15 03:23:20 PM UTC 24 Oct 15 03:29:21 PM UTC 24 8362094802 ps
T1648 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.2898683715 Oct 15 03:28:35 PM UTC 24 Oct 15 03:29:22 PM UTC 24 869705183 ps
T1649 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.1502631809 Oct 15 03:29:12 PM UTC 24 Oct 15 03:29:23 PM UTC 24 41116043 ps
T1650 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.3695041093 Oct 15 03:27:52 PM UTC 24 Oct 15 03:29:24 PM UTC 24 8214511683 ps
T1651 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1032678261 Oct 15 03:29:15 PM UTC 24 Oct 15 03:29:26 PM UTC 24 46365992 ps
T1652 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.2771307944 Oct 15 03:24:00 PM UTC 24 Oct 15 03:29:27 PM UTC 24 21222150238 ps
T1653 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.2439856623 Oct 15 03:26:12 PM UTC 24 Oct 15 03:29:33 PM UTC 24 3481396096 ps
T1654 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.1551718037 Oct 15 03:27:53 PM UTC 24 Oct 15 03:29:36 PM UTC 24 5692005332 ps
T1655 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.3579641330 Oct 15 03:23:23 PM UTC 24 Oct 15 03:29:39 PM UTC 24 4924327632 ps
T1656 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.1757160377 Oct 15 03:28:23 PM UTC 24 Oct 15 03:29:43 PM UTC 24 1380318220 ps
T516 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.2421575717 Oct 15 03:23:21 PM UTC 24 Oct 15 03:29:54 PM UTC 24 1916392946 ps
T1657 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.564224597 Oct 15 03:26:05 PM UTC 24 Oct 15 03:30:01 PM UTC 24 6987994091 ps
T1658 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.1034938266 Oct 15 03:26:38 PM UTC 24 Oct 15 03:30:02 PM UTC 24 19294547061 ps
T875 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3643095090 Oct 15 03:27:38 PM UTC 24 Oct 15 03:30:05 PM UTC 24 782288772 ps
T1659 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.1391916192 Oct 15 03:30:06 PM UTC 24 Oct 15 03:30:15 PM UTC 24 23497583 ps
T795 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.1652531616 Oct 15 03:28:15 PM UTC 24 Oct 15 03:30:17 PM UTC 24 2409179020 ps
T1660 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.38648798 Oct 15 03:22:05 PM UTC 24 Oct 15 03:30:18 PM UTC 24 35860802404 ps
T1661 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.1098331793 Oct 15 02:58:56 PM UTC 24 Oct 15 03:30:21 PM UTC 24 14679927492 ps
T1662 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.2887223096 Oct 15 03:18:47 PM UTC 24 Oct 15 03:30:21 PM UTC 24 6140552144 ps
T1663 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.4100748401 Oct 15 03:29:59 PM UTC 24 Oct 15 03:30:31 PM UTC 24 262540017 ps
T474 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.1734360111 Oct 15 03:29:47 PM UTC 24 Oct 15 03:30:35 PM UTC 24 518497340 ps
T1664 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.1300175963 Oct 15 03:27:04 PM UTC 24 Oct 15 03:30:43 PM UTC 24 2319927189 ps
T491 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.1381248412 Oct 15 03:29:43 PM UTC 24 Oct 15 03:30:45 PM UTC 24 1533227073 ps
T1665 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.3314232866 Oct 15 03:30:43 PM UTC 24 Oct 15 03:30:52 PM UTC 24 43136230 ps
T1666 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.1136545726 Oct 15 03:30:43 PM UTC 24 Oct 15 03:30:55 PM UTC 24 169073850 ps
T1667 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.3358475944 Oct 15 03:29:58 PM UTC 24 Oct 15 03:31:03 PM UTC 24 1680871070 ps
T1668 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.2649699981 Oct 15 03:29:55 PM UTC 24 Oct 15 03:31:03 PM UTC 24 2450196341 ps
T1669 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.2414033438 Oct 15 03:29:27 PM UTC 24 Oct 15 03:31:09 PM UTC 24 5648912466 ps
T1670 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.1404832250 Oct 15 03:29:15 PM UTC 24 Oct 15 03:31:09 PM UTC 24 7397977341 ps
T520 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.3635283159 Oct 15 03:25:53 PM UTC 24 Oct 15 03:31:09 PM UTC 24 7979575972 ps
T1671 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.981334744 Oct 15 03:28:06 PM UTC 24 Oct 15 03:31:11 PM UTC 24 11535736479 ps
T1672 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.3412541627 Oct 15 03:30:25 PM UTC 24 Oct 15 03:31:19 PM UTC 24 1102801465 ps
T817 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.2426625825 Oct 15 03:29:49 PM UTC 24 Oct 15 03:31:20 PM UTC 24 1264813397 ps
T1673 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.299551345 Oct 15 03:28:04 PM UTC 24 Oct 15 03:31:27 PM UTC 24 20552406543 ps
T1674 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.2770683422 Oct 15 03:29:11 PM UTC 24 Oct 15 03:31:31 PM UTC 24 3370989094 ps
T1675 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.1946714488 Oct 15 03:31:22 PM UTC 24 Oct 15 03:31:36 PM UTC 24 295816128 ps
T1676 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.1989040642 Oct 15 03:22:00 PM UTC 24 Oct 15 03:31:36 PM UTC 24 53351539569 ps
T1677 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.4017965258 Oct 15 03:23:58 PM UTC 24 Oct 15 03:31:42 PM UTC 24 40308641707 ps
T870 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.631930998 Oct 15 03:30:25 PM UTC 24 Oct 15 03:31:52 PM UTC 24 238050709 ps
T1678 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.4074897820 Oct 15 03:30:46 PM UTC 24 Oct 15 03:31:54 PM UTC 24 2071850848 ps
T1679 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.2734790805 Oct 15 03:31:44 PM UTC 24 Oct 15 03:31:56 PM UTC 24 145435126 ps
T468 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.2761556859 Oct 15 03:30:54 PM UTC 24 Oct 15 03:31:58 PM UTC 24 597816015 ps
T1680 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2131392126 Oct 15 03:31:51 PM UTC 24 Oct 15 03:32:01 PM UTC 24 51290667 ps
T1681 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.151817916 Oct 15 03:31:34 PM UTC 24 Oct 15 03:32:11 PM UTC 24 928256460 ps
T1682 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.3859196736 Oct 15 03:31:28 PM UTC 24 Oct 15 03:32:13 PM UTC 24 1031159946 ps
T833 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.893588012 Oct 15 03:31:05 PM UTC 24 Oct 15 03:32:13 PM UTC 24 920885830 ps
T1683 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.4233302357 Oct 15 03:27:41 PM UTC 24 Oct 15 03:32:15 PM UTC 24 3501513085 ps
T1684 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.3654881942 Oct 15 03:31:28 PM UTC 24 Oct 15 03:32:19 PM UTC 24 1149660437 ps
T1685 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.524224263 Oct 15 03:32:23 PM UTC 24 Oct 15 03:32:31 PM UTC 24 19322345 ps
T829 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.260728188 Oct 15 03:23:21 PM UTC 24 Oct 15 03:32:35 PM UTC 24 14484074875 ps
T1686 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.3373818717 Oct 15 03:32:27 PM UTC 24 Oct 15 03:32:42 PM UTC 24 96205037 ps
T1687 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.1782706230 Oct 15 03:30:45 PM UTC 24 Oct 15 03:32:45 PM UTC 24 10280914139 ps
T1688 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.835884270 Oct 15 03:32:39 PM UTC 24 Oct 15 03:32:53 PM UTC 24 110448235 ps
T1689 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.2198069732 Oct 15 03:30:47 PM UTC 24 Oct 15 03:32:55 PM UTC 24 5791134935 ps
T501 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.3656514874 Oct 15 03:32:07 PM UTC 24 Oct 15 03:32:59 PM UTC 24 436308013 ps
T803 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.2454376042 Oct 15 03:20:58 PM UTC 24 Oct 15 03:33:01 PM UTC 24 42935396136 ps
T1690 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.3063273465 Oct 15 03:31:59 PM UTC 24 Oct 15 03:33:04 PM UTC 24 4849666252 ps
T1691 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.1986136616 Oct 15 03:32:21 PM UTC 24 Oct 15 03:33:11 PM UTC 24 3307989303 ps
T1692 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.2990509880 Oct 15 03:32:39 PM UTC 24 Oct 15 03:33:14 PM UTC 24 666298526 ps
T1693 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.1961777878 Oct 15 03:31:57 PM UTC 24 Oct 15 03:33:19 PM UTC 24 7337640103 ps
T1694 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.2467615347 Oct 15 03:33:08 PM UTC 24 Oct 15 03:33:19 PM UTC 24 141453988 ps
T1695 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.2084858155 Oct 15 03:33:10 PM UTC 24 Oct 15 03:33:20 PM UTC 24 40494641 ps
T1696 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.235244894 Oct 15 03:32:38 PM UTC 24 Oct 15 03:33:20 PM UTC 24 697457125 ps
T503 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.1130674388 Oct 15 03:31:32 PM UTC 24 Oct 15 03:33:22 PM UTC 24 1283910581 ps
T1697 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.3389894241 Oct 15 03:30:21 PM UTC 24 Oct 15 03:33:28 PM UTC 24 195980108 ps
T528 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.944430789 Oct 15 03:32:01 PM UTC 24 Oct 15 03:33:31 PM UTC 24 1988795530 ps
T1698 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.3760172723 Oct 15 03:24:16 PM UTC 24 Oct 15 03:33:39 PM UTC 24 15976307037 ps
T1699 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.1599018517 Oct 15 03:26:40 PM UTC 24 Oct 15 03:33:41 PM UTC 24 27345772817 ps
T834 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.2903063472 Oct 15 03:28:21 PM UTC 24 Oct 15 03:33:45 PM UTC 24 21075829426 ps
T1700 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.90087109 Oct 15 03:33:22 PM UTC 24 Oct 15 03:33:49 PM UTC 24 257838097 ps
T884 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.4177076786 Oct 15 03:28:51 PM UTC 24 Oct 15 03:33:49 PM UTC 24 4565994838 ps
T1701 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.877379128 Oct 15 03:33:44 PM UTC 24 Oct 15 03:33:54 PM UTC 24 178801224 ps
T1702 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.2235211823 Oct 15 03:33:40 PM UTC 24 Oct 15 03:34:02 PM UTC 24 272337089 ps
T1703 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.2813843011 Oct 15 02:38:02 PM UTC 24 Oct 15 03:34:04 PM UTC 24 31300760939 ps
T504 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.1762438343 Oct 15 03:33:24 PM UTC 24 Oct 15 03:34:14 PM UTC 24 569034903 ps
T815 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.2760038309 Oct 15 03:24:06 PM UTC 24 Oct 15 03:34:15 PM UTC 24 39184490573 ps
T1704 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.646822294 Oct 15 03:30:32 PM UTC 24 Oct 15 03:34:15 PM UTC 24 3683451839 ps
T1705 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.2284713639 Oct 15 03:33:42 PM UTC 24 Oct 15 03:34:20 PM UTC 24 710217860 ps
T1706 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.4006791560 Oct 15 03:34:10 PM UTC 24 Oct 15 03:34:21 PM UTC 24 49488550 ps
T1707 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.3005991619 Oct 15 03:34:14 PM UTC 24 Oct 15 03:34:24 PM UTC 24 49808220 ps
T1708 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.821100155 Oct 15 03:33:44 PM UTC 24 Oct 15 03:34:30 PM UTC 24 1615108759 ps
T1709 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.1009361527 Oct 15 03:33:18 PM UTC 24 Oct 15 03:34:47 PM UTC 24 7781482044 ps
T1710 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.1978159221 Oct 15 03:33:46 PM UTC 24 Oct 15 03:34:47 PM UTC 24 1619918727 ps
T1711 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.541088374 Oct 15 03:25:10 PM UTC 24 Oct 15 03:34:51 PM UTC 24 60189176797 ps
T508 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.1367965653 Oct 15 03:34:27 PM UTC 24 Oct 15 03:34:56 PM UTC 24 294432366 ps
T1712 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.1802812747 Oct 15 03:33:39 PM UTC 24 Oct 15 03:34:58 PM UTC 24 5142615056 ps
T1713 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.2390638997 Oct 15 03:30:07 PM UTC 24 Oct 15 03:35:07 PM UTC 24 3119663668 ps
T1714 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.38432613 Oct 15 03:34:57 PM UTC 24 Oct 15 03:35:09 PM UTC 24 44201307 ps
T1715 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.2207391125 Oct 15 03:29:49 PM UTC 24 Oct 15 03:35:10 PM UTC 24 25233875042 ps
T1716 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.2580679711 Oct 15 03:33:20 PM UTC 24 Oct 15 03:35:12 PM UTC 24 5012997546 ps
T1717 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.4169887818 Oct 15 03:34:30 PM UTC 24 Oct 15 03:35:13 PM UTC 24 353533001 ps
T483 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.746682820 Oct 15 03:33:54 PM UTC 24 Oct 15 03:35:22 PM UTC 24 924350316 ps
T1718 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.932425640 Oct 15 03:34:17 PM UTC 24 Oct 15 03:35:24 PM UTC 24 3797249701 ps
T1719 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.1176035963 Oct 15 03:06:11 PM UTC 24 Oct 15 03:35:27 PM UTC 24 16277555067 ps
T1720 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.2194789558 Oct 15 03:34:48 PM UTC 24 Oct 15 03:35:36 PM UTC 24 1468442079 ps
T1721 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.3003807561 Oct 15 03:34:52 PM UTC 24 Oct 15 03:35:36 PM UTC 24 1124721235 ps
T1722 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.508476688 Oct 15 03:35:15 PM UTC 24 Oct 15 03:35:37 PM UTC 24 339876602 ps
T1723 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.1699097676 Oct 15 03:35:37 PM UTC 24 Oct 15 03:35:47 PM UTC 24 47719041 ps
T1724 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.1543625207 Oct 15 03:35:34 PM UTC 24 Oct 15 03:35:49 PM UTC 24 235277779 ps
T1725 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.891699572 Oct 15 03:35:41 PM UTC 24 Oct 15 03:35:52 PM UTC 24 87819753 ps
T1726 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.1176065931 Oct 15 03:31:37 PM UTC 24 Oct 15 03:35:56 PM UTC 24 6069032755 ps
T1727 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.3439971004 Oct 15 03:31:09 PM UTC 24 Oct 15 03:36:05 PM UTC 24 20937895907 ps
T1728 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.812884198 Oct 15 03:32:56 PM UTC 24 Oct 15 03:36:08 PM UTC 24 6319657091 ps
T1729 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.1563152563 Oct 15 03:31:01 PM UTC 24 Oct 15 03:36:13 PM UTC 24 33329488040 ps
T1730 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.3743674932 Oct 15 03:03:58 PM UTC 24 Oct 15 03:36:13 PM UTC 24 15196755777 ps
T509 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.3562353885 Oct 15 03:24:23 PM UTC 24 Oct 15 03:36:17 PM UTC 24 4349697808 ps
T1731 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.2816816343 Oct 15 03:29:48 PM UTC 24 Oct 15 03:36:21 PM UTC 24 22805252080 ps
T1732 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.181185901 Oct 15 03:33:56 PM UTC 24 Oct 15 03:36:25 PM UTC 24 923214873 ps
T1733 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.1746443126 Oct 15 03:34:04 PM UTC 24 Oct 15 03:36:28 PM UTC 24 835317532 ps
T1734 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.1923526891 Oct 15 03:28:32 PM UTC 24 Oct 15 03:36:32 PM UTC 24 5278254331 ps
T1735 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.854571305 Oct 15 03:36:03 PM UTC 24 Oct 15 03:36:45 PM UTC 24 415374396 ps
T1736 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.1362628563 Oct 15 03:36:36 PM UTC 24 Oct 15 03:36:45 PM UTC 24 53139368 ps
T492 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.2033613782 Oct 15 03:28:34 PM UTC 24 Oct 15 03:36:45 PM UTC 24 14735936629 ps
T1737 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.206351212 Oct 15 03:36:16 PM UTC 24 Oct 15 03:36:47 PM UTC 24 663326709 ps
T1738 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.3317332839 Oct 15 03:35:49 PM UTC 24 Oct 15 03:36:48 PM UTC 24 583994600 ps
T1739 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.3548272262 Oct 15 03:36:42 PM UTC 24 Oct 15 03:36:49 PM UTC 24 41400396 ps
T1740 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.3110596836 Oct 15 03:34:17 PM UTC 24 Oct 15 03:36:53 PM UTC 24 9913146669 ps
T1741 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.367489827 Oct 15 03:35:35 PM UTC 24 Oct 15 03:36:55 PM UTC 24 8278975189 ps
T1742 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.3902981238 Oct 15 03:36:19 PM UTC 24 Oct 15 03:36:56 PM UTC 24 239571933 ps
T1743 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.1920736490 Oct 15 03:34:41 PM UTC 24 Oct 15 03:36:57 PM UTC 24 13398330704 ps
T1744 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.3795215314 Oct 15 03:35:33 PM UTC 24 Oct 15 03:37:04 PM UTC 24 4729665937 ps
T488 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.2774071319 Oct 15 03:34:42 PM UTC 24 Oct 15 03:37:08 PM UTC 24 3061100945 ps
T1745 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.1448836748 Oct 15 03:36:54 PM UTC 24 Oct 15 03:37:10 PM UTC 24 112900367 ps
T1746 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.1974684923 Oct 15 03:36:05 PM UTC 24 Oct 15 03:37:12 PM UTC 24 1706268050 ps
T1747 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.238307541 Oct 15 03:39:20 PM UTC 24 Oct 15 03:39:43 PM UTC 24 212214458 ps
T1748 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.198300839 Oct 15 03:31:44 PM UTC 24 Oct 15 03:37:29 PM UTC 24 1635114281 ps
T1749 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.3641125408 Oct 15 03:37:13 PM UTC 24 Oct 15 03:37:32 PM UTC 24 373413959 ps
T885 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.3938295025 Oct 15 03:36:36 PM UTC 24 Oct 15 03:37:33 PM UTC 24 249629143 ps
T510 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.3887321709 Oct 15 03:35:47 PM UTC 24 Oct 15 03:37:44 PM UTC 24 10764609185 ps
T1750 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.1029497748 Oct 15 03:36:59 PM UTC 24 Oct 15 03:37:46 PM UTC 24 533683349 ps
T1751 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.820967764 Oct 15 03:36:14 PM UTC 24 Oct 15 03:37:47 PM UTC 24 2453431489 ps
T830 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.224935658 Oct 15 03:32:42 PM UTC 24 Oct 15 03:37:47 PM UTC 24 4549264234 ps
T1752 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.2743579057 Oct 15 03:37:20 PM UTC 24 Oct 15 03:37:47 PM UTC 24 246467225 ps
T1753 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.1711906365 Oct 15 03:37:39 PM UTC 24 Oct 15 03:37:49 PM UTC 24 43484848 ps
T1754 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.1344775564 Oct 15 03:37:37 PM UTC 24 Oct 15 03:37:51 PM UTC 24 202190471 ps
T823 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2510901069 Oct 15 03:22:55 PM UTC 24 Oct 15 03:37:51 PM UTC 24 59682726362 ps
T1755 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.1190293425 Oct 15 03:37:12 PM UTC 24 Oct 15 03:37:53 PM UTC 24 288011629 ps
T805 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.1103678490 Oct 15 03:25:25 PM UTC 24 Oct 15 03:37:58 PM UTC 24 49405133622 ps
T1756 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.3623986144 Oct 15 03:37:20 PM UTC 24 Oct 15 03:38:04 PM UTC 24 891415706 ps
T1757 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.2754893109 Oct 15 03:34:03 PM UTC 24 Oct 15 03:38:06 PM UTC 24 3270442014 ps
T831 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.3797101082 Oct 15 03:29:52 PM UTC 24 Oct 15 03:38:08 PM UTC 24 31694008499 ps
T1758 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.2725932584 Oct 15 03:36:48 PM UTC 24 Oct 15 03:38:16 PM UTC 24 7664543661 ps
T1759 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3232453764 Oct 15 03:36:31 PM UTC 24 Oct 15 03:38:30 PM UTC 24 199963983 ps
T1760 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.3331246601 Oct 15 03:38:15 PM UTC 24 Oct 15 03:38:31 PM UTC 24 388877486 ps
T1761 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.2547883432 Oct 15 03:38:08 PM UTC 24 Oct 15 03:38:32 PM UTC 24 253380759 ps
T1762 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.2135492636 Oct 15 02:41:10 PM UTC 24 Oct 15 03:39:43 PM UTC 24 30966313512 ps
T1763 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.1513793609 Oct 15 03:37:17 PM UTC 24 Oct 15 03:38:32 PM UTC 24 2372282034 ps
T1764 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.1596524262 Oct 15 03:36:50 PM UTC 24 Oct 15 03:38:36 PM UTC 24 6303517513 ps
T1765 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.1701837884 Oct 15 03:38:14 PM UTC 24 Oct 15 03:38:37 PM UTC 24 295717728 ps
T1766 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.2774068480 Oct 15 03:38:15 PM UTC 24 Oct 15 03:38:43 PM UTC 24 227123353 ps
T1767 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.1938528626 Oct 15 03:33:31 PM UTC 24 Oct 15 03:38:51 PM UTC 24 30321814711 ps
T1768 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.2637350906 Oct 15 03:38:41 PM UTC 24 Oct 15 03:38:52 PM UTC 24 51084516 ps
T1769 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.4236878709 Oct 15 03:38:10 PM UTC 24 Oct 15 03:38:54 PM UTC 24 750102623 ps
T1770 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.3474780887 Oct 15 03:38:14 PM UTC 24 Oct 15 03:38:58 PM UTC 24 729455189 ps
T1771 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.1827261703 Oct 15 03:38:55 PM UTC 24 Oct 15 03:39:05 PM UTC 24 39724691 ps
T860 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.33766363 Oct 15 03:33:02 PM UTC 24 Oct 15 03:39:10 PM UTC 24 810151022 ps
T1772 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.850931203 Oct 15 03:37:54 PM UTC 24 Oct 15 03:39:12 PM UTC 24 8722600887 ps
T1773 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.2002125756 Oct 15 03:38:59 PM UTC 24 Oct 15 03:39:14 PM UTC 24 284354038 ps
T1774 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.297033934 Oct 15 03:35:24 PM UTC 24 Oct 15 03:39:20 PM UTC 24 7040245286 ps
T1775 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.3030458033 Oct 15 03:37:57 PM UTC 24 Oct 15 03:39:39 PM UTC 24 2572682005 ps
T1776 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.1127711153 Oct 15 03:39:33 PM UTC 24 Oct 15 03:39:42 PM UTC 24 74968780 ps
T1777 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.1670687032 Oct 15 03:37:58 PM UTC 24 Oct 15 03:39:43 PM UTC 24 6071921084 ps
T1778 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.3469868131 Oct 15 03:35:24 PM UTC 24 Oct 15 03:39:44 PM UTC 24 904839521 ps
T1779 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.2101527600 Oct 15 03:39:02 PM UTC 24 Oct 15 03:39:49 PM UTC 24 597553147 ps
T1780 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.3696489649 Oct 15 03:37:11 PM UTC 24 Oct 15 03:40:05 PM UTC 24 11084331511 ps
T866 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.2677906189 Oct 15 03:24:41 PM UTC 24 Oct 15 03:40:13 PM UTC 24 21458661987 ps
T1781 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.2983561439 Oct 15 03:39:24 PM UTC 24 Oct 15 03:40:14 PM UTC 24 1303072766 ps
T1782 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.2956028499 Oct 15 03:35:13 PM UTC 24 Oct 15 03:40:16 PM UTC 24 3569841029 ps
T835 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.2738819842 Oct 15 03:39:18 PM UTC 24 Oct 15 03:40:17 PM UTC 24 1528642628 ps
T1783 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.1840307398 Oct 15 03:40:08 PM UTC 24 Oct 15 03:40:18 PM UTC 24 39107627 ps
T1784 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.1654380663 Oct 15 03:40:05 PM UTC 24 Oct 15 03:40:20 PM UTC 24 231268292 ps
T1785 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.711296791 Oct 15 03:38:58 PM UTC 24 Oct 15 03:40:21 PM UTC 24 5479113710 ps
T1786 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.3340916271 Oct 15 03:37:23 PM UTC 24 Oct 15 03:40:21 PM UTC 24 493041648 ps
T818 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.1255132894 Oct 15 03:37:24 PM UTC 24 Oct 15 03:40:22 PM UTC 24 1857113469 ps
T1787 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.440022584 Oct 15 03:39:38 PM UTC 24 Oct 15 03:40:23 PM UTC 24 819100726 ps
T1788 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.1657589560 Oct 15 03:38:33 PM UTC 24 Oct 15 03:40:27 PM UTC 24 2938996206 ps
T1789 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.318839320 Oct 15 03:37:14 PM UTC 24 Oct 15 03:40:27 PM UTC 24 13783686274 ps
T867 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.2592805031 Oct 15 03:31:34 PM UTC 24 Oct 15 03:40:28 PM UTC 24 6326470199 ps
T1790 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.3804902694 Oct 15 03:40:15 PM UTC 24 Oct 15 03:40:32 PM UTC 24 165423530 ps
T1791 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.824023840 Oct 15 03:38:58 PM UTC 24 Oct 15 03:40:32 PM UTC 24 9001686295 ps
T846 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.1797869459 Oct 15 03:27:21 PM UTC 24 Oct 15 03:40:39 PM UTC 24 23052200162 ps
T1792 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.3971207508 Oct 15 03:08:42 PM UTC 24 Oct 15 03:40:40 PM UTC 24 15749404118 ps
T1793 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.821018534 Oct 15 03:40:53 PM UTC 24 Oct 15 03:41:00 PM UTC 24 38177446 ps
T1794 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.132961417 Oct 15 03:39:48 PM UTC 24 Oct 15 03:41:01 PM UTC 24 709528743 ps
T1795 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.2437889311 Oct 15 03:40:53 PM UTC 24 Oct 15 03:41:01 PM UTC 24 52324570 ps
T1796 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.4142484079 Oct 15 03:40:07 PM UTC 24 Oct 15 03:41:01 PM UTC 24 562182670 ps
T1797 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.115544719 Oct 15 03:40:46 PM UTC 24 Oct 15 03:41:02 PM UTC 24 96047598 ps
T1798 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.3808991649 Oct 15 03:40:43 PM UTC 24 Oct 15 03:41:03 PM UTC 24 219863627 ps
T1799 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.3767131356 Oct 15 03:40:42 PM UTC 24 Oct 15 03:41:05 PM UTC 24 131427190 ps
T1800 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.1302879775 Oct 15 03:40:08 PM UTC 24 Oct 15 03:41:10 PM UTC 24 4012980638 ps
T1801 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.4259002758 Oct 15 03:32:19 PM UTC 24 Oct 15 03:41:14 PM UTC 24 52106177313 ps
T1802 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.1585673803 Oct 15 03:41:06 PM UTC 24 Oct 15 03:41:17 PM UTC 24 138370386 ps
T532 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.4282854505 Oct 15 03:35:54 PM UTC 24 Oct 15 03:41:22 PM UTC 24 18485170808 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.1600214059 Oct 15 02:35:32 PM UTC 24 Oct 15 03:41:24 PM UTC 24 33979069606 ps
T524 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.2798105554 Oct 15 03:40:41 PM UTC 24 Oct 15 03:41:28 PM UTC 24 510888073 ps
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