Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.95 95.51 93.50 95.41 94.18 97.57 99.53


Total test records in report: 2918
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html
T2513 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.1285890785 Oct 15 04:23:04 PM UTC 24 Oct 15 04:23:37 PM UTC 24 425134510 ps
T2514 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.1024587618 Oct 15 04:23:28 PM UTC 24 Oct 15 04:23:39 PM UTC 24 47310610 ps
T2515 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.3792007864 Oct 15 04:22:34 PM UTC 24 Oct 15 04:23:41 PM UTC 24 1620749333 ps
T2516 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.3043838411 Oct 15 04:23:26 PM UTC 24 Oct 15 04:23:41 PM UTC 24 252960751 ps
T2517 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.884786581 Oct 15 04:22:51 PM UTC 24 Oct 15 04:23:43 PM UTC 24 625764722 ps
T2518 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.182712926 Oct 15 04:20:13 PM UTC 24 Oct 15 04:24:03 PM UTC 24 15778103496 ps
T2519 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.2343385660 Oct 15 04:23:22 PM UTC 24 Oct 15 04:24:06 PM UTC 24 212372683 ps
T2520 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.1563010455 Oct 15 04:23:49 PM UTC 24 Oct 15 04:24:07 PM UTC 24 165205274 ps
T2521 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.2735190524 Oct 15 04:23:56 PM UTC 24 Oct 15 04:24:09 PM UTC 24 51178952 ps
T2522 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.1785520922 Oct 15 04:23:47 PM UTC 24 Oct 15 04:24:10 PM UTC 24 214921153 ps
T2523 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.1988631979 Oct 15 04:23:04 PM UTC 24 Oct 15 04:24:11 PM UTC 24 1383123433 ps
T2524 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.3856426082 Oct 15 04:22:33 PM UTC 24 Oct 15 04:24:12 PM UTC 24 9098940371 ps
T2525 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.2086609409 Oct 15 04:16:03 PM UTC 24 Oct 15 04:24:16 PM UTC 24 35543073739 ps
T2526 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.1685403218 Oct 15 04:20:32 PM UTC 24 Oct 15 04:24:16 PM UTC 24 6502028169 ps
T2527 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.1475930692 Oct 15 04:19:34 PM UTC 24 Oct 15 04:24:19 PM UTC 24 17813676051 ps
T2528 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.3653484954 Oct 15 04:24:01 PM UTC 24 Oct 15 04:24:21 PM UTC 24 106152976 ps
T2529 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.3472719770 Oct 15 04:24:03 PM UTC 24 Oct 15 04:24:21 PM UTC 24 89382487 ps
T2530 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.2205683142 Oct 15 04:11:39 PM UTC 24 Oct 15 04:24:31 PM UTC 24 55934589421 ps
T2531 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.2639755824 Oct 15 04:21:21 PM UTC 24 Oct 15 04:24:38 PM UTC 24 2207607998 ps
T2532 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.1668799437 Oct 15 04:23:57 PM UTC 24 Oct 15 04:24:39 PM UTC 24 1521866779 ps
T2533 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.2213406414 Oct 15 04:23:45 PM UTC 24 Oct 15 04:24:39 PM UTC 24 579812050 ps
T2534 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.766162415 Oct 15 04:22:34 PM UTC 24 Oct 15 04:24:41 PM UTC 24 5546759090 ps
T2535 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.475174941 Oct 15 04:24:29 PM UTC 24 Oct 15 04:24:41 PM UTC 24 192008552 ps
T2536 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.729707061 Oct 15 04:19:27 PM UTC 24 Oct 15 04:24:41 PM UTC 24 23651747344 ps
T2537 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.1655571439 Oct 15 04:23:28 PM UTC 24 Oct 15 04:24:44 PM UTC 24 7461065534 ps
T2538 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.1611956523 Oct 15 04:23:32 PM UTC 24 Oct 15 04:24:44 PM UTC 24 4414408873 ps
T2539 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.755693838 Oct 15 04:24:33 PM UTC 24 Oct 15 04:24:44 PM UTC 24 50957327 ps
T2540 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.14485881 Oct 15 04:16:10 PM UTC 24 Oct 15 04:24:46 PM UTC 24 33282227750 ps
T2541 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.2379790686 Oct 15 04:21:40 PM UTC 24 Oct 15 04:24:47 PM UTC 24 12755665178 ps
T2542 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.2492828020 Oct 15 04:23:37 PM UTC 24 Oct 15 04:24:49 PM UTC 24 2117987335 ps
T2543 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.28136561 Oct 15 04:20:56 PM UTC 24 Oct 15 04:24:50 PM UTC 24 14386909988 ps
T2544 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.2077006506 Oct 15 04:24:37 PM UTC 24 Oct 15 04:24:53 PM UTC 24 99031712 ps
T2545 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.129061644 Oct 15 04:24:38 PM UTC 24 Oct 15 04:24:56 PM UTC 24 117715003 ps
T2546 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.2141568062 Oct 15 04:18:18 PM UTC 24 Oct 15 04:25:04 PM UTC 24 29089424280 ps
T2547 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.3357695586 Oct 15 04:24:55 PM UTC 24 Oct 15 04:25:05 PM UTC 24 95816567 ps
T2548 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.2554451854 Oct 15 04:24:46 PM UTC 24 Oct 15 04:25:11 PM UTC 24 365777671 ps
T2549 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.285945502 Oct 15 04:25:04 PM UTC 24 Oct 15 04:25:16 PM UTC 24 59975842 ps
T2550 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.225451639 Oct 15 04:25:07 PM UTC 24 Oct 15 04:25:18 PM UTC 24 51440434 ps
T2551 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.3095358406 Oct 15 04:24:04 PM UTC 24 Oct 15 04:25:21 PM UTC 24 223858157 ps
T2552 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.359838649 Oct 15 04:25:05 PM UTC 24 Oct 15 04:25:28 PM UTC 24 168613708 ps
T2553 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.1533986788 Oct 15 04:20:35 PM UTC 24 Oct 15 04:25:28 PM UTC 24 7265758209 ps
T2554 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.2812973756 Oct 15 04:25:10 PM UTC 24 Oct 15 04:25:33 PM UTC 24 154360059 ps
T438 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.728425858 Oct 15 03:12:33 PM UTC 24 Oct 15 04:25:33 PM UTC 24 29395314408 ps
T2555 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.1168446622 Oct 15 04:24:34 PM UTC 24 Oct 15 04:25:38 PM UTC 24 6336388481 ps
T2556 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.2973292662 Oct 15 04:25:29 PM UTC 24 Oct 15 04:25:42 PM UTC 24 62379797 ps
T2557 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.1038636750 Oct 15 04:24:36 PM UTC 24 Oct 15 04:25:44 PM UTC 24 4979690850 ps
T2558 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.2873522016 Oct 15 04:24:48 PM UTC 24 Oct 15 04:25:44 PM UTC 24 1881915632 ps
T2559 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.1750487538 Oct 15 04:18:30 PM UTC 24 Oct 15 04:25:46 PM UTC 24 30285299467 ps
T2560 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.1940677236 Oct 15 04:24:43 PM UTC 24 Oct 15 04:25:53 PM UTC 24 1872543074 ps
T2561 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.1681803066 Oct 15 04:25:12 PM UTC 24 Oct 15 04:25:57 PM UTC 24 486814048 ps
T2562 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.567808543 Oct 15 04:25:28 PM UTC 24 Oct 15 04:26:02 PM UTC 24 358821533 ps
T2563 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.1208133527 Oct 15 04:25:08 PM UTC 24 Oct 15 04:26:03 PM UTC 24 3856513192 ps
T2564 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.1022495786 Oct 15 04:25:57 PM UTC 24 Oct 15 04:26:05 PM UTC 24 45491158 ps
T2565 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_large_delays.466844911 Oct 15 04:25:12 PM UTC 24 Oct 15 04:26:07 PM UTC 24 4430151940 ps
T2566 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.2905394549 Oct 15 04:23:19 PM UTC 24 Oct 15 04:26:09 PM UTC 24 2217833008 ps
T2567 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.1682359301 Oct 15 04:25:39 PM UTC 24 Oct 15 04:26:11 PM UTC 24 749855630 ps
T2568 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.2443007870 Oct 15 04:25:58 PM UTC 24 Oct 15 04:26:14 PM UTC 24 259812852 ps
T2569 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.3945134813 Oct 15 04:25:20 PM UTC 24 Oct 15 04:26:14 PM UTC 24 638928727 ps
T2570 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.572726336 Oct 15 04:25:00 PM UTC 24 Oct 15 04:26:30 PM UTC 24 286900308 ps
T2571 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.1711678171 Oct 15 04:20:58 PM UTC 24 Oct 15 04:26:34 PM UTC 24 22104142907 ps
T2572 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.3411435525 Oct 15 04:25:32 PM UTC 24 Oct 15 04:26:35 PM UTC 24 1452241239 ps
T2573 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.1300467683 Oct 15 04:25:07 PM UTC 24 Oct 15 04:26:36 PM UTC 24 8497801946 ps
T2574 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.523684897 Oct 15 04:23:48 PM UTC 24 Oct 15 04:26:37 PM UTC 24 11060906784 ps
T2575 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.3685241921 Oct 15 04:17:40 PM UTC 24 Oct 15 04:26:38 PM UTC 24 14651999466 ps
T2576 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.491156232 Oct 15 04:13:56 PM UTC 24 Oct 15 04:26:40 PM UTC 24 46845252619 ps
T2577 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.3763002684 Oct 15 04:25:02 PM UTC 24 Oct 15 04:26:48 PM UTC 24 2650692371 ps
T2578 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.2512554906 Oct 15 04:26:11 PM UTC 24 Oct 15 04:26:50 PM UTC 24 440804065 ps
T2579 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.1959551434 Oct 15 04:20:11 PM UTC 24 Oct 15 04:26:51 PM UTC 24 43182858130 ps
T2580 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.1528605955 Oct 15 04:26:28 PM UTC 24 Oct 15 04:26:56 PM UTC 24 219990884 ps
T2581 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.2017236213 Oct 15 04:26:35 PM UTC 24 Oct 15 04:26:57 PM UTC 24 308151575 ps
T2582 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.1510924779 Oct 15 04:26:32 PM UTC 24 Oct 15 04:26:58 PM UTC 24 279162651 ps
T2583 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.653838185 Oct 15 04:26:59 PM UTC 24 Oct 15 04:27:09 PM UTC 24 48452418 ps
T2584 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.3264233429 Oct 15 04:27:03 PM UTC 24 Oct 15 04:27:12 PM UTC 24 37312844 ps
T2585 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.1320618498 Oct 15 04:25:39 PM UTC 24 Oct 15 04:27:12 PM UTC 24 1275477522 ps
T2586 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.3681238905 Oct 15 04:19:25 PM UTC 24 Oct 15 04:27:13 PM UTC 24 48263078457 ps
T2587 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.2508637393 Oct 15 04:22:01 PM UTC 24 Oct 15 04:27:19 PM UTC 24 3914122361 ps
T2588 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.3189884597 Oct 15 04:26:04 PM UTC 24 Oct 15 04:27:21 PM UTC 24 8160465788 ps
T2589 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_large_delays.4264809664 Oct 15 04:26:10 PM UTC 24 Oct 15 04:27:24 PM UTC 24 5136319712 ps
T2590 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.1047976768 Oct 15 04:27:17 PM UTC 24 Oct 15 04:27:29 PM UTC 24 105597914 ps
T2591 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.3872335063 Oct 15 04:26:37 PM UTC 24 Oct 15 04:27:33 PM UTC 24 1385078879 ps
T2592 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.1470249929 Oct 15 04:26:09 PM UTC 24 Oct 15 04:27:35 PM UTC 24 2284148991 ps
T2593 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.599270697 Oct 15 04:27:22 PM UTC 24 Oct 15 04:27:36 PM UTC 24 142635643 ps
T2594 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.2557925817 Oct 15 04:26:08 PM UTC 24 Oct 15 04:27:43 PM UTC 24 5474961112 ps
T2595 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.2563207439 Oct 15 04:27:38 PM UTC 24 Oct 15 04:27:45 PM UTC 24 5545596 ps
T2596 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.2140163192 Oct 15 04:27:06 PM UTC 24 Oct 15 04:27:46 PM UTC 24 374468474 ps
T2597 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.2235211204 Oct 15 04:22:07 PM UTC 24 Oct 15 04:27:52 PM UTC 24 4051860139 ps
T2598 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.4170677279 Oct 15 04:27:45 PM UTC 24 Oct 15 04:27:55 PM UTC 24 49543417 ps
T2599 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.3993177732 Oct 15 04:27:25 PM UTC 24 Oct 15 04:27:56 PM UTC 24 390539176 ps
T2600 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_slow_rsp.3091407140 Oct 15 04:24:41 PM UTC 24 Oct 15 04:27:57 PM UTC 24 12508130614 ps
T2601 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.2799881293 Oct 15 04:27:39 PM UTC 24 Oct 15 04:28:01 PM UTC 24 544697605 ps
T2602 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.4178705317 Oct 15 04:27:52 PM UTC 24 Oct 15 04:28:01 PM UTC 24 51103890 ps
T2603 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.1040874733 Oct 15 04:27:06 PM UTC 24 Oct 15 04:28:07 PM UTC 24 540643891 ps
T2604 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.787812560 Oct 15 04:27:48 PM UTC 24 Oct 15 04:28:07 PM UTC 24 35732070 ps
T2605 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.1807413784 Oct 15 04:27:00 PM UTC 24 Oct 15 04:28:08 PM UTC 24 4362122192 ps
T2606 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.3959162088 Oct 15 04:26:24 PM UTC 24 Oct 15 04:28:10 PM UTC 24 2601164017 ps
T2607 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.363339193 Oct 15 04:28:01 PM UTC 24 Oct 15 04:28:20 PM UTC 24 282481427 ps
T2608 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.4188974644 Oct 15 04:27:34 PM UTC 24 Oct 15 04:28:20 PM UTC 24 700855097 ps
T2609 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.803882852 Oct 15 04:25:52 PM UTC 24 Oct 15 04:28:29 PM UTC 24 518092431 ps
T2610 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_large_delays.1213674524 Oct 15 04:23:45 PM UTC 24 Oct 15 04:28:32 PM UTC 24 19716562384 ps
T2611 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.1269971746 Oct 15 04:19:52 PM UTC 24 Oct 15 04:28:32 PM UTC 24 17920909196 ps
T2612 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.568917816 Oct 15 04:27:02 PM UTC 24 Oct 15 04:28:34 PM UTC 24 9089136179 ps
T2613 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.3518906607 Oct 15 04:28:19 PM UTC 24 Oct 15 04:28:39 PM UTC 24 226742916 ps
T2614 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_slow_rsp.2069302936 Oct 15 04:27:15 PM UTC 24 Oct 15 04:28:42 PM UTC 24 5945732486 ps
T2615 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.473570071 Oct 15 04:28:23 PM UTC 24 Oct 15 04:28:46 PM UTC 24 428710580 ps
T2616 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.3135531766 Oct 15 04:28:42 PM UTC 24 Oct 15 04:28:49 PM UTC 24 53264299 ps
T2617 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.1504889949 Oct 15 04:27:58 PM UTC 24 Oct 15 04:28:54 PM UTC 24 5104609825 ps
T2618 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2280098796 Oct 15 04:27:20 PM UTC 24 Oct 15 04:28:55 PM UTC 24 4239765605 ps
T2619 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.191909602 Oct 15 04:28:46 PM UTC 24 Oct 15 04:28:55 PM UTC 24 53342634 ps
T2620 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.731296975 Oct 15 04:28:09 PM UTC 24 Oct 15 04:28:57 PM UTC 24 368504027 ps
T2621 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.3026410401 Oct 15 04:24:02 PM UTC 24 Oct 15 04:28:58 PM UTC 24 3410254511 ps
T2622 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.3582331065 Oct 15 04:28:26 PM UTC 24 Oct 15 04:29:00 PM UTC 24 212788000 ps
T2623 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.4165935922 Oct 15 04:26:42 PM UTC 24 Oct 15 04:29:05 PM UTC 24 1913261360 ps
T2624 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.988896829 Oct 15 04:25:03 PM UTC 24 Oct 15 04:29:06 PM UTC 24 5368257627 ps
T2625 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_slow_rsp.1883042663 Oct 15 04:28:09 PM UTC 24 Oct 15 04:29:09 PM UTC 24 3890575763 ps
T2626 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.298663271 Oct 15 04:28:26 PM UTC 24 Oct 15 04:29:12 PM UTC 24 278997430 ps
T2627 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1689050183 Oct 15 04:23:15 PM UTC 24 Oct 15 04:29:14 PM UTC 24 6950240915 ps
T2628 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.1048426802 Oct 15 04:29:01 PM UTC 24 Oct 15 04:29:14 PM UTC 24 71105390 ps
T2629 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.937236787 Oct 15 04:28:15 PM UTC 24 Oct 15 04:29:17 PM UTC 24 1096828157 ps
T2630 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.2798172946 Oct 15 04:27:59 PM UTC 24 Oct 15 04:29:26 PM UTC 24 5558912661 ps
T2631 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.3146738020 Oct 15 04:25:48 PM UTC 24 Oct 15 04:29:31 PM UTC 24 619686275 ps
T2632 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.736916031 Oct 15 04:25:02 PM UTC 24 Oct 15 04:29:33 PM UTC 24 3760953613 ps
T2633 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.245484950 Oct 15 04:23:16 PM UTC 24 Oct 15 04:29:35 PM UTC 24 10947826229 ps
T2634 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.1707650628 Oct 15 04:29:20 PM UTC 24 Oct 15 04:29:36 PM UTC 24 170548242 ps
T2635 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.4056636379 Oct 15 04:21:17 PM UTC 24 Oct 15 04:29:37 PM UTC 24 13870825557 ps
T2636 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.2377304808 Oct 15 04:30:31 PM UTC 24 Oct 15 04:30:40 PM UTC 24 43977160 ps
T2637 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.278790992 Oct 15 04:29:00 PM UTC 24 Oct 15 04:29:42 PM UTC 24 911749983 ps
T2638 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.28292469 Oct 15 04:18:39 PM UTC 24 Oct 15 04:29:46 PM UTC 24 19516056829 ps
T2639 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.565709220 Oct 15 04:29:39 PM UTC 24 Oct 15 04:29:48 PM UTC 24 41169444 ps
T2640 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.4159665272 Oct 15 04:29:33 PM UTC 24 Oct 15 04:29:48 PM UTC 24 237751756 ps
T2641 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.2777841750 Oct 15 04:22:04 PM UTC 24 Oct 15 04:29:55 PM UTC 24 12709711523 ps
T2642 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.2417288975 Oct 15 04:29:42 PM UTC 24 Oct 15 04:29:56 PM UTC 24 92169914 ps
T2643 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.2981534399 Oct 15 04:28:55 PM UTC 24 Oct 15 04:30:01 PM UTC 24 6372739738 ps
T2644 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.1069701547 Oct 15 04:28:56 PM UTC 24 Oct 15 04:30:06 PM UTC 24 4664547292 ps
T2645 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.284217495 Oct 15 04:29:23 PM UTC 24 Oct 15 04:30:09 PM UTC 24 855021068 ps
T2646 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.2008294874 Oct 15 04:29:18 PM UTC 24 Oct 15 04:30:13 PM UTC 24 1190966914 ps
T2647 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.2476827251 Oct 15 04:20:47 PM UTC 24 Oct 15 04:30:15 PM UTC 24 5257670016 ps
T2648 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.857630400 Oct 15 04:23:00 PM UTC 24 Oct 15 04:30:16 PM UTC 24 30261970060 ps
T2649 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.996931719 Oct 15 04:29:19 PM UTC 24 Oct 15 04:30:18 PM UTC 24 1442993345 ps
T2650 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2732606433 Oct 15 04:21:21 PM UTC 24 Oct 15 04:30:19 PM UTC 24 3450059697 ps
T2651 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_large_delays.1894898743 Oct 15 04:22:57 PM UTC 24 Oct 15 04:30:20 PM UTC 24 45576508822 ps
T2652 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3487969345 Oct 15 04:26:41 PM UTC 24 Oct 15 04:30:35 PM UTC 24 4464497786 ps
T2653 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.1299471870 Oct 15 04:30:15 PM UTC 24 Oct 15 04:30:35 PM UTC 24 127774307 ps
T2654 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.2424671096 Oct 15 04:29:51 PM UTC 24 Oct 15 04:30:35 PM UTC 24 399746331 ps
T2655 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_large_delays.3231381789 Oct 15 04:24:39 PM UTC 24 Oct 15 04:30:36 PM UTC 24 35497431489 ps
T2656 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.562138386 Oct 15 04:29:10 PM UTC 24 Oct 15 04:30:42 PM UTC 24 1723794438 ps
T2657 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.2888793772 Oct 15 04:30:28 PM UTC 24 Oct 15 04:30:42 PM UTC 24 188928849 ps
T2658 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.205536875 Oct 15 04:30:09 PM UTC 24 Oct 15 04:30:44 PM UTC 24 926636536 ps
T2659 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.183082238 Oct 15 04:30:13 PM UTC 24 Oct 15 04:30:46 PM UTC 24 296310535 ps
T2660 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.583333844 Oct 15 04:30:00 PM UTC 24 Oct 15 04:30:46 PM UTC 24 439596766 ps
T2661 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_large_delays.1667500512 Oct 15 04:28:11 PM UTC 24 Oct 15 04:30:49 PM UTC 24 14714425138 ps
T2662 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.835157919 Oct 15 04:29:42 PM UTC 24 Oct 15 04:30:50 PM UTC 24 6965138591 ps
T2663 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.4149622590 Oct 15 04:30:43 PM UTC 24 Oct 15 04:30:57 PM UTC 24 71927655 ps
T2664 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.2975242377 Oct 15 04:29:58 PM UTC 24 Oct 15 04:31:01 PM UTC 24 1408326102 ps
T2665 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_large_delays.1234694940 Oct 15 04:27:14 PM UTC 24 Oct 15 04:31:06 PM UTC 24 21700872370 ps
T2666 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.4081169004 Oct 15 04:28:31 PM UTC 24 Oct 15 04:31:07 PM UTC 24 354451821 ps
T2667 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.2201762993 Oct 15 04:30:26 PM UTC 24 Oct 15 04:31:11 PM UTC 24 9563443 ps
T2668 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.1204929801 Oct 15 04:29:37 PM UTC 24 Oct 15 04:31:13 PM UTC 24 4357800472 ps
T2669 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.707052641 Oct 15 04:30:40 PM UTC 24 Oct 15 04:31:23 PM UTC 24 511384558 ps
T2670 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.3347794892 Oct 15 04:31:02 PM UTC 24 Oct 15 04:31:23 PM UTC 24 386360877 ps
T2671 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.3898576625 Oct 15 04:31:14 PM UTC 24 Oct 15 04:31:24 PM UTC 24 51466006 ps
T2672 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.2179805749 Oct 15 04:31:13 PM UTC 24 Oct 15 04:31:24 PM UTC 24 50108313 ps
T2673 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_slow_rsp.3884358596 Oct 15 04:26:18 PM UTC 24 Oct 15 04:31:26 PM UTC 24 20265838036 ps
T2674 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.647608062 Oct 15 04:31:01 PM UTC 24 Oct 15 04:31:28 PM UTC 24 218901930 ps
T2675 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.1337434092 Oct 15 04:29:15 PM UTC 24 Oct 15 04:31:28 PM UTC 24 8337906679 ps
T2676 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.1183984332 Oct 15 04:31:07 PM UTC 24 Oct 15 04:31:30 PM UTC 24 366855191 ps
T2677 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_large_delays.522337856 Oct 15 04:21:45 PM UTC 24 Oct 15 04:31:37 PM UTC 24 56975076477 ps
T2678 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_large_delays.1568111152 Oct 15 04:29:55 PM UTC 24 Oct 15 04:31:44 PM UTC 24 8954549241 ps
T2679 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.3483813530 Oct 15 04:31:30 PM UTC 24 Oct 15 04:31:47 PM UTC 24 159883672 ps
T2680 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.2405358094 Oct 15 04:31:00 PM UTC 24 Oct 15 04:31:48 PM UTC 24 1563027484 ps
T2681 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.3655842124 Oct 15 04:31:30 PM UTC 24 Oct 15 04:31:51 PM UTC 24 166384732 ps
T2682 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.93290809 Oct 15 04:30:36 PM UTC 24 Oct 15 04:31:54 PM UTC 24 5014827276 ps
T2683 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.960305611 Oct 15 04:16:31 PM UTC 24 Oct 15 04:32:06 PM UTC 24 10108455500 ps
T2684 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.1092588173 Oct 15 04:32:11 PM UTC 24 Oct 15 04:32:21 PM UTC 24 40093507 ps
T2685 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.1549705476 Oct 15 04:32:11 PM UTC 24 Oct 15 04:32:24 PM UTC 24 221956761 ps
T2686 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.2663437715 Oct 15 04:26:23 PM UTC 24 Oct 15 04:32:28 PM UTC 24 26260151969 ps
T2687 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.4208387231 Oct 15 04:31:50 PM UTC 24 Oct 15 04:32:30 PM UTC 24 2516805312 ps
T2688 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.1534855539 Oct 15 04:31:22 PM UTC 24 Oct 15 04:32:31 PM UTC 24 6111080071 ps
T2689 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.3347275561 Oct 15 04:31:22 PM UTC 24 Oct 15 04:32:31 PM UTC 24 5228131472 ps
T2690 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.3175239658 Oct 15 04:31:51 PM UTC 24 Oct 15 04:32:38 PM UTC 24 311987715 ps
T2691 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.3078057053 Oct 15 04:28:36 PM UTC 24 Oct 15 04:32:39 PM UTC 24 3681577388 ps
T2692 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.3812677359 Oct 15 04:30:37 PM UTC 24 Oct 15 04:32:41 PM UTC 24 11298406124 ps
T2693 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.1220868596 Oct 15 04:31:48 PM UTC 24 Oct 15 04:32:41 PM UTC 24 1430409812 ps
T2694 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.397519858 Oct 15 04:26:35 PM UTC 24 Oct 15 04:32:45 PM UTC 24 11681369331 ps
T2695 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all.4013802968 Oct 15 04:31:52 PM UTC 24 Oct 15 04:32:49 PM UTC 24 2096968251 ps
T2696 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.2671585402 Oct 15 04:31:48 PM UTC 24 Oct 15 04:32:53 PM UTC 24 1333497496 ps
T2697 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_slow_rsp.1329307796 Oct 15 04:31:37 PM UTC 24 Oct 15 04:32:55 PM UTC 24 4103833293 ps
T2698 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_large_delays.4136040791 Oct 15 04:29:04 PM UTC 24 Oct 15 04:32:57 PM UTC 24 23612405308 ps
T2699 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.3654607102 Oct 15 04:31:52 PM UTC 24 Oct 15 04:33:00 PM UTC 24 1449875192 ps
T2700 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.4131289902 Oct 15 04:31:09 PM UTC 24 Oct 15 04:33:02 PM UTC 24 316532266 ps
T2701 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.432300080 Oct 15 04:31:47 PM UTC 24 Oct 15 04:33:07 PM UTC 24 2625611606 ps
T2702 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.1191208896 Oct 15 04:33:05 PM UTC 24 Oct 15 04:33:11 PM UTC 24 23406828 ps
T2703 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.1209354483 Oct 15 04:30:55 PM UTC 24 Oct 15 04:33:17 PM UTC 24 3042032142 ps
T2704 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.3644913784 Oct 15 04:32:31 PM UTC 24 Oct 15 04:33:19 PM UTC 24 892317089 ps
T2705 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.4031240508 Oct 15 04:32:47 PM UTC 24 Oct 15 04:33:22 PM UTC 24 292162561 ps
T2706 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.434729310 Oct 15 04:33:17 PM UTC 24 Oct 15 04:33:27 PM UTC 24 41955296 ps
T2707 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all.3386419538 Oct 15 04:31:07 PM UTC 24 Oct 15 04:33:27 PM UTC 24 1965682261 ps
T2708 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.2935669916 Oct 15 04:33:20 PM UTC 24 Oct 15 04:33:30 PM UTC 24 45317377 ps
T2709 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.3902928291 Oct 15 04:33:04 PM UTC 24 Oct 15 04:33:31 PM UTC 24 255444037 ps
T2710 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_large_delays.3048620118 Oct 15 04:31:37 PM UTC 24 Oct 15 04:33:44 PM UTC 24 12122032563 ps
T2711 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.3848629962 Oct 15 04:28:33 PM UTC 24 Oct 15 04:33:46 PM UTC 24 9781301140 ps
T2712 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.1392975685 Oct 15 04:32:19 PM UTC 24 Oct 15 04:33:51 PM UTC 24 9106099338 ps
T2713 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.759917486 Oct 15 04:32:56 PM UTC 24 Oct 15 04:33:51 PM UTC 24 512150102 ps
T2714 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.1190872714 Oct 15 04:33:06 PM UTC 24 Oct 15 04:33:53 PM UTC 24 1119621947 ps
T2715 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.438260935 Oct 15 04:32:21 PM UTC 24 Oct 15 04:33:56 PM UTC 24 5618923428 ps
T2716 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.3588673769 Oct 15 04:33:36 PM UTC 24 Oct 15 04:34:01 PM UTC 24 208312417 ps
T2717 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.2182000787 Oct 15 04:15:10 PM UTC 24 Oct 15 04:34:04 PM UTC 24 75965839161 ps
T2718 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.3810175141 Oct 15 04:32:07 PM UTC 24 Oct 15 04:34:08 PM UTC 24 2812597877 ps
T2719 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all.3746004379 Oct 15 04:33:05 PM UTC 24 Oct 15 04:34:09 PM UTC 24 868846813 ps
T2720 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.3568818721 Oct 15 04:28:32 PM UTC 24 Oct 15 04:34:11 PM UTC 24 8340455118 ps
T2721 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.2545159087 Oct 15 04:23:00 PM UTC 24 Oct 15 04:34:14 PM UTC 24 40014092097 ps
T2722 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.1443412716 Oct 15 04:33:34 PM UTC 24 Oct 15 04:34:19 PM UTC 24 381307585 ps
T2723 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.2282458709 Oct 15 04:33:56 PM UTC 24 Oct 15 04:34:20 PM UTC 24 305078625 ps
T2724 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.3849799205 Oct 15 04:33:47 PM UTC 24 Oct 15 04:34:25 PM UTC 24 498067555 ps
T2725 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.3395243486 Oct 15 04:34:09 PM UTC 24 Oct 15 04:34:28 PM UTC 24 149623824 ps
T2726 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.3877657430 Oct 15 04:33:59 PM UTC 24 Oct 15 04:34:29 PM UTC 24 351524464 ps
T2727 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.1012099114 Oct 15 04:34:25 PM UTC 24 Oct 15 04:34:35 PM UTC 24 44426782 ps
T2728 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.3418724223 Oct 15 04:34:22 PM UTC 24 Oct 15 04:34:36 PM UTC 24 220392319 ps
T2729 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.2470807236 Oct 15 04:32:58 PM UTC 24 Oct 15 04:34:50 PM UTC 24 5392144739 ps
T2730 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.1405047699 Oct 15 04:33:53 PM UTC 24 Oct 15 04:34:52 PM UTC 24 2120690528 ps
T2731 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.83187769 Oct 15 04:29:31 PM UTC 24 Oct 15 04:34:57 PM UTC 24 7191905124 ps
T2732 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.1832989615 Oct 15 04:33:22 PM UTC 24 Oct 15 04:35:00 PM UTC 24 9124826704 ps
T2733 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.1488063679 Oct 15 04:32:53 PM UTC 24 Oct 15 04:35:08 PM UTC 24 3449689399 ps
T2734 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.2266753076 Oct 15 04:17:04 PM UTC 24 Oct 15 04:35:09 PM UTC 24 67987181803 ps
T2735 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.3702791826 Oct 15 04:34:52 PM UTC 24 Oct 15 04:35:09 PM UTC 24 308734406 ps
T2736 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.2889426105 Oct 15 04:30:23 PM UTC 24 Oct 15 04:35:16 PM UTC 24 2832339830 ps
T2737 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.1669034640 Oct 15 04:33:27 PM UTC 24 Oct 15 04:35:16 PM UTC 24 6246350660 ps
T2738 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_unmapped_addr.3692429694 Oct 15 04:35:01 PM UTC 24 Oct 15 04:35:17 PM UTC 24 57126408 ps
T2739 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.3816032728 Oct 15 04:29:25 PM UTC 24 Oct 15 04:35:18 PM UTC 24 4118038614 ps
T2740 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.325809650 Oct 15 04:25:53 PM UTC 24 Oct 15 04:35:20 PM UTC 24 17888371449 ps
T2741 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.482507878 Oct 15 04:35:03 PM UTC 24 Oct 15 04:35:27 PM UTC 24 147466825 ps
T2742 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.2740255839 Oct 15 04:27:37 PM UTC 24 Oct 15 04:35:28 PM UTC 24 11347398853 ps
T2743 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.2327757433 Oct 15 04:24:09 PM UTC 24 Oct 15 04:35:28 PM UTC 24 17734616547 ps
T2744 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.29264359 Oct 15 04:34:33 PM UTC 24 Oct 15 04:35:28 PM UTC 24 462579308 ps
T2745 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.3967024326 Oct 15 04:34:56 PM UTC 24 Oct 15 04:35:35 PM UTC 24 526479463 ps
T2746 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_large_delays.1722012774 Oct 15 04:34:23 PM UTC 24 Oct 15 04:35:36 PM UTC 24 8195085803 ps
T2747 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.1600733937 Oct 15 04:34:32 PM UTC 24 Oct 15 04:35:39 PM UTC 24 1971373720 ps
T2748 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.3533173401 Oct 15 04:35:35 PM UTC 24 Oct 15 04:35:43 PM UTC 24 39238475 ps
T2749 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all.3628276742 Oct 15 04:30:12 PM UTC 24 Oct 15 04:35:45 PM UTC 24 7587572739 ps
T2750 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_slow_rsp.2256932626 Oct 15 04:29:09 PM UTC 24 Oct 15 04:35:45 PM UTC 24 30154561041 ps
T2751 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.1360023441 Oct 15 04:35:37 PM UTC 24 Oct 15 04:35:50 PM UTC 24 230017072 ps
T2752 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.2146302000 Oct 15 04:29:33 PM UTC 24 Oct 15 04:35:53 PM UTC 24 12453546735 ps
T2753 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_error.239335493 Oct 15 04:34:15 PM UTC 24 Oct 15 04:35:53 PM UTC 24 1030981453 ps
T2754 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.825815210 Oct 15 04:34:31 PM UTC 24 Oct 15 04:35:57 PM UTC 24 5394938006 ps
T2755 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_zero_delays.2569338787 Oct 15 04:35:43 PM UTC 24 Oct 15 04:36:01 PM UTC 24 120844019 ps
T2756 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_same_source.4120909336 Oct 15 04:35:54 PM UTC 24 Oct 15 04:36:11 PM UTC 24 297718017 ps
T2757 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3551073275 Oct 15 04:26:56 PM UTC 24 Oct 15 04:36:16 PM UTC 24 8931946544 ps
T2758 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_slow_rsp.3927226173 Oct 15 04:25:13 PM UTC 24 Oct 15 04:36:20 PM UTC 24 33260810383 ps
T2759 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_slow_rsp.1829494548 Oct 15 04:29:55 PM UTC 24 Oct 15 04:36:20 PM UTC 24 28821767751 ps
T2760 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.427220818 Oct 15 04:35:59 PM UTC 24 Oct 15 04:36:22 PM UTC 24 517921615 ps
T2761 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke.3746286895 Oct 15 04:36:18 PM UTC 24 Oct 15 04:36:25 PM UTC 24 41155945 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%