| T2516 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.3327565370 |
|
|
Feb 09 04:57:53 PM UTC 25 |
Feb 09 04:59:30 PM UTC 25 |
5083969684 ps |
| T2517 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.235596616 |
|
|
Feb 09 04:59:17 PM UTC 25 |
Feb 09 04:59:41 PM UTC 25 |
726118949 ps |
| T2518 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.3667700013 |
|
|
Feb 09 04:57:01 PM UTC 25 |
Feb 09 04:59:42 PM UTC 25 |
3193365955 ps |
| T2519 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.672624447 |
|
|
Feb 09 04:59:48 PM UTC 25 |
Feb 09 04:59:55 PM UTC 25 |
38129091 ps |
| T2520 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.4135785265 |
|
|
Feb 09 04:55:22 PM UTC 25 |
Feb 09 05:00:01 PM UTC 25 |
4057006635 ps |
| T2521 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.3149031683 |
|
|
Feb 09 04:59:50 PM UTC 25 |
Feb 09 05:00:01 PM UTC 25 |
55712202 ps |
| T879 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.2782013276 |
|
|
Feb 09 04:59:37 PM UTC 25 |
Feb 09 05:00:20 PM UTC 25 |
87403869 ps |
| T2522 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.225854713 |
|
|
Feb 09 04:58:24 PM UTC 25 |
Feb 09 05:00:21 PM UTC 25 |
1224020271 ps |
| T2523 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.2358839909 |
|
|
Feb 09 04:59:47 PM UTC 25 |
Feb 09 05:00:24 PM UTC 25 |
7687959 ps |
| T2524 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.521354062 |
|
|
Feb 09 04:59:27 PM UTC 25 |
Feb 09 05:00:29 PM UTC 25 |
971010129 ps |
| T2525 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.432004829 |
|
|
Feb 09 04:29:03 PM UTC 25 |
Feb 09 05:00:29 PM UTC 25 |
117175792095 ps |
| T2526 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.3288980325 |
|
|
Feb 09 04:58:02 PM UTC 25 |
Feb 09 05:00:29 PM UTC 25 |
2961274871 ps |
| T2527 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.2395557768 |
|
|
Feb 09 04:58:59 PM UTC 25 |
Feb 09 05:00:33 PM UTC 25 |
5376133496 ps |
| T2528 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.2218048057 |
|
|
Feb 09 04:59:21 PM UTC 25 |
Feb 09 05:00:36 PM UTC 25 |
2138330161 ps |
| T2529 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.3428408770 |
|
|
Feb 09 04:59:38 PM UTC 25 |
Feb 09 05:00:38 PM UTC 25 |
1708370724 ps |
| T2530 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.4255014329 |
|
|
Feb 09 04:58:59 PM UTC 25 |
Feb 09 05:00:40 PM UTC 25 |
2478860835 ps |
| T2531 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.2145989310 |
|
|
Feb 09 04:59:31 PM UTC 25 |
Feb 09 05:00:42 PM UTC 25 |
1373158269 ps |
| T2532 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.4201031753 |
|
|
Feb 09 04:58:52 PM UTC 25 |
Feb 09 05:00:43 PM UTC 25 |
6792475103 ps |
| T2533 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.3700678346 |
|
|
Feb 09 04:56:13 PM UTC 25 |
Feb 09 05:00:51 PM UTC 25 |
3191330900 ps |
| T2534 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.1599420434 |
|
|
Feb 09 04:55:05 PM UTC 25 |
Feb 09 05:00:51 PM UTC 25 |
10546579043 ps |
| T2535 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2679167180 |
|
|
Feb 09 04:58:03 PM UTC 25 |
Feb 09 05:00:53 PM UTC 25 |
9619914115 ps |
| T2536 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.2631119672 |
|
|
Feb 09 04:59:08 PM UTC 25 |
Feb 09 05:00:58 PM UTC 25 |
2262121195 ps |
| T2537 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.3474494438 |
|
|
Feb 09 05:00:07 PM UTC 25 |
Feb 09 05:00:59 PM UTC 25 |
1370850328 ps |
| T2538 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.3079724189 |
|
|
Feb 09 04:47:36 PM UTC 25 |
Feb 09 05:01:00 PM UTC 25 |
49212452824 ps |
| T2539 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.1726212199 |
|
|
Feb 09 05:00:24 PM UTC 25 |
Feb 09 05:01:03 PM UTC 25 |
490361361 ps |
| T2540 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1286405827 |
|
|
Feb 09 04:58:49 PM UTC 25 |
Feb 09 05:01:10 PM UTC 25 |
288720423 ps |
| T2541 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.85419810 |
|
|
Feb 09 04:57:38 PM UTC 25 |
Feb 09 05:01:11 PM UTC 25 |
5546315258 ps |
| T2542 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.1576966446 |
|
|
Feb 09 05:00:53 PM UTC 25 |
Feb 09 05:01:15 PM UTC 25 |
257439529 ps |
| T2543 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.2447002947 |
|
|
Feb 09 04:58:24 PM UTC 25 |
Feb 09 05:01:16 PM UTC 25 |
1330842434 ps |
| T2544 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.146296043 |
|
|
Feb 09 04:59:59 PM UTC 25 |
Feb 09 05:01:16 PM UTC 25 |
6282577317 ps |
| T2545 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.2899235135 |
|
|
Feb 09 05:01:09 PM UTC 25 |
Feb 09 05:01:19 PM UTC 25 |
47468264 ps |
| T2546 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.3226221889 |
|
|
Feb 09 04:57:21 PM UTC 25 |
Feb 09 05:01:20 PM UTC 25 |
6983515463 ps |
| T2547 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.1423932678 |
|
|
Feb 09 05:00:57 PM UTC 25 |
Feb 09 05:01:21 PM UTC 25 |
166171385 ps |
| T2548 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.4192885944 |
|
|
Feb 09 05:01:11 PM UTC 25 |
Feb 09 05:01:22 PM UTC 25 |
59468227 ps |
| T2549 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.2959836107 |
|
|
Feb 09 04:56:26 PM UTC 25 |
Feb 09 05:01:24 PM UTC 25 |
1171032074 ps |
| T2550 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2296305260 |
|
|
Feb 09 05:00:55 PM UTC 25 |
Feb 09 05:01:25 PM UTC 25 |
587650910 ps |
| T2551 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2887306411 |
|
|
Feb 09 05:01:04 PM UTC 25 |
Feb 09 05:01:31 PM UTC 25 |
47088749 ps |
| T2552 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.940118463 |
|
|
Feb 09 05:00:08 PM UTC 25 |
Feb 09 05:01:42 PM UTC 25 |
5812215800 ps |
| T2553 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.1880271360 |
|
|
Feb 09 05:01:18 PM UTC 25 |
Feb 09 05:01:46 PM UTC 25 |
210674723 ps |
| T2554 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.2802558192 |
|
|
Feb 09 04:53:46 PM UTC 25 |
Feb 09 05:01:52 PM UTC 25 |
46468851169 ps |
| T2555 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.2274208454 |
|
|
Feb 09 05:01:23 PM UTC 25 |
Feb 09 05:01:56 PM UTC 25 |
331099876 ps |
| T2556 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.1048479671 |
|
|
Feb 09 05:01:50 PM UTC 25 |
Feb 09 05:02:00 PM UTC 25 |
211816977 ps |
| T2557 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.815085191 |
|
|
Feb 09 05:01:50 PM UTC 25 |
Feb 09 05:02:00 PM UTC 25 |
45900900 ps |
| T2558 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.1136774474 |
|
|
Feb 09 04:55:09 PM UTC 25 |
Feb 09 05:02:03 PM UTC 25 |
2924640813 ps |
| T2559 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.2328468634 |
|
|
Feb 09 05:01:44 PM UTC 25 |
Feb 09 05:02:04 PM UTC 25 |
146056639 ps |
| T2560 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.605778113 |
|
|
Feb 09 05:00:48 PM UTC 25 |
Feb 09 05:02:04 PM UTC 25 |
768410696 ps |
| T2561 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.182768213 |
|
|
Feb 09 05:01:38 PM UTC 25 |
Feb 09 05:02:08 PM UTC 25 |
956146646 ps |
| T2562 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.3781376070 |
|
|
Feb 09 05:01:47 PM UTC 25 |
Feb 09 05:02:09 PM UTC 25 |
216369144 ps |
| T2563 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.3281592874 |
|
|
Feb 09 05:01:25 PM UTC 25 |
Feb 09 05:02:16 PM UTC 25 |
740049264 ps |
| T2564 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.892148788 |
|
|
Feb 09 05:01:44 PM UTC 25 |
Feb 09 05:02:19 PM UTC 25 |
225461467 ps |
| T2565 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.2436475448 |
|
|
Feb 09 05:00:56 PM UTC 25 |
Feb 09 05:02:34 PM UTC 25 |
2049774199 ps |
| T2566 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.349441261 |
|
|
Feb 09 05:02:18 PM UTC 25 |
Feb 09 05:02:41 PM UTC 25 |
251043018 ps |
| T2567 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.948531004 |
|
|
Feb 09 05:01:39 PM UTC 25 |
Feb 09 05:02:46 PM UTC 25 |
2258350365 ps |
| T2568 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.2292258364 |
|
|
Feb 09 05:02:35 PM UTC 25 |
Feb 09 05:02:47 PM UTC 25 |
188883401 ps |
| T2569 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.3259990269 |
|
|
Feb 09 05:01:15 PM UTC 25 |
Feb 09 05:02:55 PM UTC 25 |
5705883273 ps |
| T2570 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.1077816189 |
|
|
Feb 09 05:02:12 PM UTC 25 |
Feb 09 05:02:59 PM UTC 25 |
441351081 ps |
| T2571 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.4009630007 |
|
|
Feb 09 05:01:17 PM UTC 25 |
Feb 09 05:03:05 PM UTC 25 |
10656719014 ps |
| T2572 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.2646324259 |
|
|
Feb 09 05:01:43 PM UTC 25 |
Feb 09 05:03:08 PM UTC 25 |
1025802134 ps |
| T2573 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.3184998246 |
|
|
Feb 09 05:02:28 PM UTC 25 |
Feb 09 05:03:10 PM UTC 25 |
1026702378 ps |
| T2574 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.3421786289 |
|
|
Feb 09 05:02:24 PM UTC 25 |
Feb 09 05:03:12 PM UTC 25 |
455057818 ps |
| T2575 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.1924416172 |
|
|
Feb 09 05:02:10 PM UTC 25 |
Feb 09 05:03:12 PM UTC 25 |
3752603881 ps |
| T2576 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.70569473 |
|
|
Feb 09 05:01:59 PM UTC 25 |
Feb 09 05:03:16 PM UTC 25 |
6751088926 ps |
| T2577 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.4145008561 |
|
|
Feb 09 04:51:27 PM UTC 25 |
Feb 09 05:03:20 PM UTC 25 |
40829269788 ps |
| T2578 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.1176723937 |
|
|
Feb 09 05:03:12 PM UTC 25 |
Feb 09 05:03:21 PM UTC 25 |
46869657 ps |
| T2579 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.660619584 |
|
|
Feb 09 05:02:37 PM UTC 25 |
Feb 09 05:03:22 PM UTC 25 |
334857225 ps |
| T2580 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.2442211152 |
|
|
Feb 09 05:03:13 PM UTC 25 |
Feb 09 05:03:23 PM UTC 25 |
44834522 ps |
| T2581 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.297983451 |
|
|
Feb 09 05:02:31 PM UTC 25 |
Feb 09 05:03:24 PM UTC 25 |
1456406066 ps |
| T2582 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.384647249 |
|
|
Feb 09 04:56:22 PM UTC 25 |
Feb 09 05:03:32 PM UTC 25 |
649562024 ps |
| T2583 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.396818448 |
|
|
Feb 09 05:03:48 PM UTC 25 |
Feb 09 05:03:58 PM UTC 25 |
26676922 ps |
| T2584 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.3255676363 |
|
|
Feb 09 04:57:01 PM UTC 25 |
Feb 09 05:04:08 PM UTC 25 |
28530946279 ps |
| T2585 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.3632439734 |
|
|
Feb 09 05:03:50 PM UTC 25 |
Feb 09 05:04:09 PM UTC 25 |
99382894 ps |
| T2586 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.1080526269 |
|
|
Feb 09 05:03:46 PM UTC 25 |
Feb 09 05:04:09 PM UTC 25 |
286305104 ps |
| T2587 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.3933465669 |
|
|
Feb 09 05:03:29 PM UTC 25 |
Feb 09 05:04:23 PM UTC 25 |
557719088 ps |
| T2588 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.3890157193 |
|
|
Feb 09 05:03:34 PM UTC 25 |
Feb 09 05:04:23 PM UTC 25 |
411459080 ps |
| T2589 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.750747395 |
|
|
Feb 09 05:03:21 PM UTC 25 |
Feb 09 05:04:38 PM UTC 25 |
7636843822 ps |
| T2590 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.6251996 |
|
|
Feb 09 05:04:38 PM UTC 25 |
Feb 09 05:04:46 PM UTC 25 |
58177994 ps |
| T2591 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_large_delays.3480553572 |
|
|
Feb 09 04:57:59 PM UTC 25 |
Feb 09 05:04:46 PM UTC 25 |
37327402040 ps |
| T2592 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.1191570440 |
|
|
Feb 09 05:04:38 PM UTC 25 |
Feb 09 05:04:48 PM UTC 25 |
49388840 ps |
| T2593 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.3651544379 |
|
|
Feb 09 05:03:47 PM UTC 25 |
Feb 09 05:04:52 PM UTC 25 |
1592414684 ps |
| T2594 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.4162043157 |
|
|
Feb 09 05:02:44 PM UTC 25 |
Feb 09 05:05:09 PM UTC 25 |
1828190248 ps |
| T2595 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_slow_rsp.4044983119 |
|
|
Feb 09 05:03:39 PM UTC 25 |
Feb 09 05:05:09 PM UTC 25 |
3958657416 ps |
| T2596 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.1124268369 |
|
|
Feb 09 04:31:37 PM UTC 25 |
Feb 09 05:05:11 PM UTC 25 |
134988556674 ps |
| T2597 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.356839868 |
|
|
Feb 09 05:03:39 PM UTC 25 |
Feb 09 05:05:20 PM UTC 25 |
1062121054 ps |
| T2598 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_large_delays.2394637671 |
|
|
Feb 09 04:59:02 PM UTC 25 |
Feb 09 05:05:20 PM UTC 25 |
37979801447 ps |
| T2599 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.2088630543 |
|
|
Feb 09 04:47:32 PM UTC 25 |
Feb 09 05:05:24 PM UTC 25 |
61863159309 ps |
| T2600 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.3763080119 |
|
|
Feb 09 04:58:31 PM UTC 25 |
Feb 09 05:05:31 PM UTC 25 |
13917984742 ps |
| T2601 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.2535600337 |
|
|
Feb 09 04:59:33 PM UTC 25 |
Feb 09 05:05:35 PM UTC 25 |
3881171597 ps |
| T2602 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_large_delays.1199700340 |
|
|
Feb 09 05:03:37 PM UTC 25 |
Feb 09 05:05:39 PM UTC 25 |
13819023623 ps |
| T2603 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.2573451762 |
|
|
Feb 09 05:01:49 PM UTC 25 |
Feb 09 05:05:39 PM UTC 25 |
606233208 ps |
| T2604 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.2267149376 |
|
|
Feb 09 04:51:26 PM UTC 25 |
Feb 09 05:05:42 PM UTC 25 |
55012107029 ps |
| T2605 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.2223112988 |
|
|
Feb 09 05:03:27 PM UTC 25 |
Feb 09 05:05:47 PM UTC 25 |
7365857626 ps |
| T2606 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.2229879640 |
|
|
Feb 09 05:00:50 PM UTC 25 |
Feb 09 05:05:55 PM UTC 25 |
18269459189 ps |
| T2607 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.944853759 |
|
|
Feb 09 05:05:40 PM UTC 25 |
Feb 09 05:05:59 PM UTC 25 |
197125508 ps |
| T2608 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.2742074460 |
|
|
Feb 09 05:01:07 PM UTC 25 |
Feb 09 05:06:10 PM UTC 25 |
3827587241 ps |
| T2609 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.1283058780 |
|
|
Feb 09 05:05:14 PM UTC 25 |
Feb 09 05:06:12 PM UTC 25 |
529193874 ps |
| T2610 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.3227169818 |
|
|
Feb 09 05:04:50 PM UTC 25 |
Feb 09 05:06:15 PM UTC 25 |
4068927677 ps |
| T2611 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.51644810 |
|
|
Feb 09 05:06:11 PM UTC 25 |
Feb 09 05:06:22 PM UTC 25 |
53522397 ps |
| T2612 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.497771624 |
|
|
Feb 09 05:06:08 PM UTC 25 |
Feb 09 05:06:23 PM UTC 25 |
230867987 ps |
| T2613 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.222255339 |
|
|
Feb 09 05:05:46 PM UTC 25 |
Feb 09 05:06:26 PM UTC 25 |
258768369 ps |
| T2614 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.3041275714 |
|
|
Feb 09 05:04:52 PM UTC 25 |
Feb 09 05:06:36 PM UTC 25 |
8700028073 ps |
| T2615 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.1113122074 |
|
|
Feb 09 05:05:49 PM UTC 25 |
Feb 09 05:06:36 PM UTC 25 |
1136530104 ps |
| T2616 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.156806000 |
|
|
Feb 09 05:05:07 PM UTC 25 |
Feb 09 05:06:38 PM UTC 25 |
2363679825 ps |
| T2617 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.1803035248 |
|
|
Feb 09 05:06:28 PM UTC 25 |
Feb 09 05:06:39 PM UTC 25 |
38062026 ps |
| T2618 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.2841957883 |
|
|
Feb 09 05:01:45 PM UTC 25 |
Feb 09 05:06:38 PM UTC 25 |
696567225 ps |
| T2619 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.2572470461 |
|
|
Feb 09 05:05:22 PM UTC 25 |
Feb 09 05:06:41 PM UTC 25 |
1590906779 ps |
| T2620 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.2303136932 |
|
|
Feb 09 05:03:04 PM UTC 25 |
Feb 09 05:06:42 PM UTC 25 |
4954647650 ps |
| T2621 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.1398260627 |
|
|
Feb 09 05:04:26 PM UTC 25 |
Feb 09 05:06:55 PM UTC 25 |
1916078981 ps |
| T2622 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.2477376735 |
|
|
Feb 09 05:05:39 PM UTC 25 |
Feb 09 05:07:01 PM UTC 25 |
2340787561 ps |
| T2623 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.3390241716 |
|
|
Feb 09 05:06:36 PM UTC 25 |
Feb 09 05:07:14 PM UTC 25 |
287420230 ps |
| T2624 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.1817538140 |
|
|
Feb 09 04:52:51 PM UTC 25 |
Feb 09 05:07:18 PM UTC 25 |
58028489399 ps |
| T2625 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_large_delays.3736891776 |
|
|
Feb 09 05:06:41 PM UTC 25 |
Feb 09 05:07:25 PM UTC 25 |
4049834547 ps |
| T2626 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.2063917147 |
|
|
Feb 09 05:07:05 PM UTC 25 |
Feb 09 05:07:27 PM UTC 25 |
375927554 ps |
| T2627 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.1851271207 |
|
|
Feb 09 05:07:05 PM UTC 25 |
Feb 09 05:07:29 PM UTC 25 |
397509326 ps |
| T2628 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.1537877119 |
|
|
Feb 09 05:01:08 PM UTC 25 |
Feb 09 05:07:30 PM UTC 25 |
2024432935 ps |
| T2629 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.662858810 |
|
|
Feb 09 05:06:48 PM UTC 25 |
Feb 09 05:07:33 PM UTC 25 |
420093409 ps |
| T2630 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.3316145681 |
|
|
Feb 09 05:07:23 PM UTC 25 |
Feb 09 05:07:33 PM UTC 25 |
46690284 ps |
| T2631 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.2016170551 |
|
|
Feb 09 05:07:04 PM UTC 25 |
Feb 09 05:07:38 PM UTC 25 |
187332132 ps |
| T2632 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.1083969363 |
|
|
Feb 09 05:07:29 PM UTC 25 |
Feb 09 05:07:40 PM UTC 25 |
50054930 ps |
| T2633 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.2179987482 |
|
|
Feb 09 05:06:51 PM UTC 25 |
Feb 09 05:07:50 PM UTC 25 |
589371065 ps |
| T662 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.1871395120 |
|
|
Feb 09 05:03:08 PM UTC 25 |
Feb 09 05:07:54 PM UTC 25 |
650576405 ps |
| T2634 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.498026614 |
|
|
Feb 09 05:07:11 PM UTC 25 |
Feb 09 05:07:55 PM UTC 25 |
101691845 ps |
| T2635 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.2341485248 |
|
|
Feb 09 05:06:16 PM UTC 25 |
Feb 09 05:07:57 PM UTC 25 |
9638349777 ps |
| T2636 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.49877458 |
|
|
Feb 09 05:06:24 PM UTC 25 |
Feb 09 05:08:00 PM UTC 25 |
5810618323 ps |
| T2637 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.1334784459 |
|
|
Feb 09 04:30:19 PM UTC 25 |
Feb 09 05:08:03 PM UTC 25 |
127030628863 ps |
| T2638 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.3327189292 |
|
|
Feb 09 04:46:16 PM UTC 25 |
Feb 09 05:08:15 PM UTC 25 |
95054658617 ps |
| T2639 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.959247276 |
|
|
Feb 09 05:07:54 PM UTC 25 |
Feb 09 05:08:19 PM UTC 25 |
446282876 ps |
| T2640 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.2299634682 |
|
|
Feb 09 05:08:09 PM UTC 25 |
Feb 09 05:08:24 PM UTC 25 |
135005915 ps |
| T2641 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.2058051139 |
|
|
Feb 09 05:04:37 PM UTC 25 |
Feb 09 05:08:27 PM UTC 25 |
371948299 ps |
| T2642 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.2133636040 |
|
|
Feb 09 04:57:58 PM UTC 25 |
Feb 09 05:08:40 PM UTC 25 |
41961123919 ps |
| T2643 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.438132778 |
|
|
Feb 09 05:06:00 PM UTC 25 |
Feb 09 05:08:41 PM UTC 25 |
3082107352 ps |
| T2644 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.2476078724 |
|
|
Feb 09 04:35:34 PM UTC 25 |
Feb 09 05:08:41 PM UTC 25 |
118573347894 ps |
| T2645 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.3908671265 |
|
|
Feb 09 05:08:00 PM UTC 25 |
Feb 09 05:08:50 PM UTC 25 |
860973786 ps |
| T2646 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.703728567 |
|
|
Feb 09 05:07:56 PM UTC 25 |
Feb 09 05:08:50 PM UTC 25 |
452231901 ps |
| T2647 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.2852653345 |
|
|
Feb 09 05:08:39 PM UTC 25 |
Feb 09 05:08:53 PM UTC 25 |
202602026 ps |
| T2648 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.2070441617 |
|
|
Feb 09 05:08:45 PM UTC 25 |
Feb 09 05:08:55 PM UTC 25 |
57397429 ps |
| T2649 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_slow_rsp.3108516420 |
|
|
Feb 09 05:05:17 PM UTC 25 |
Feb 09 05:09:12 PM UTC 25 |
11993815532 ps |
| T2650 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.16168624 |
|
|
Feb 09 05:01:00 PM UTC 25 |
Feb 09 05:09:14 PM UTC 25 |
15291158165 ps |
| T2651 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3464496940 |
|
|
Feb 09 05:08:21 PM UTC 25 |
Feb 09 05:09:17 PM UTC 25 |
1238005483 ps |
| T2652 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.399616976 |
|
|
Feb 09 05:08:17 PM UTC 25 |
Feb 09 05:09:25 PM UTC 25 |
1476108639 ps |
| T2653 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.3938632721 |
|
|
Feb 09 05:07:42 PM UTC 25 |
Feb 09 05:09:29 PM UTC 25 |
5025379733 ps |
| T2654 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.425829018 |
|
|
Feb 09 05:07:43 PM UTC 25 |
Feb 09 05:09:31 PM UTC 25 |
8580014565 ps |
| T2655 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.1401518271 |
|
|
Feb 09 05:09:09 PM UTC 25 |
Feb 09 05:09:44 PM UTC 25 |
370457172 ps |
| T2656 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.577707072 |
|
|
Feb 09 05:08:08 PM UTC 25 |
Feb 09 05:09:48 PM UTC 25 |
2677938889 ps |
| T2657 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.4261475813 |
|
|
Feb 09 05:09:23 PM UTC 25 |
Feb 09 05:09:52 PM UTC 25 |
850931868 ps |
| T2658 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.4016651172 |
|
|
Feb 09 05:05:57 PM UTC 25 |
Feb 09 05:09:54 PM UTC 25 |
2692893463 ps |
| T2659 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.4019092689 |
|
|
Feb 09 05:09:07 PM UTC 25 |
Feb 09 05:10:05 PM UTC 25 |
1114397510 ps |
| T2660 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3302239226 |
|
|
Feb 09 05:03:59 PM UTC 25 |
Feb 09 05:10:11 PM UTC 25 |
2102494419 ps |
| T2661 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.530418541 |
|
|
Feb 09 05:09:46 PM UTC 25 |
Feb 09 05:10:14 PM UTC 25 |
212915550 ps |
| T2662 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.366275452 |
|
|
Feb 09 04:53:48 PM UTC 25 |
Feb 09 05:10:16 PM UTC 25 |
64214409006 ps |
| T2663 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.1701407484 |
|
|
Feb 09 05:09:37 PM UTC 25 |
Feb 09 05:10:22 PM UTC 25 |
850659838 ps |
| T2664 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.3921284638 |
|
|
Feb 09 05:09:18 PM UTC 25 |
Feb 09 05:10:22 PM UTC 25 |
1422162468 ps |
| T2665 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.2983640243 |
|
|
Feb 09 05:05:51 PM UTC 25 |
Feb 09 05:10:22 PM UTC 25 |
3433359645 ps |
| T2666 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.2681931002 |
|
|
Feb 09 05:03:49 PM UTC 25 |
Feb 09 05:10:23 PM UTC 25 |
10095450705 ps |
| T2667 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.3591354103 |
|
|
Feb 09 05:10:15 PM UTC 25 |
Feb 09 05:10:25 PM UTC 25 |
188589601 ps |
| T2668 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.1350017472 |
|
|
Feb 09 05:09:40 PM UTC 25 |
Feb 09 05:10:25 PM UTC 25 |
1360770178 ps |
| T2669 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.4011832152 |
|
|
Feb 09 05:10:15 PM UTC 25 |
Feb 09 05:10:25 PM UTC 25 |
47331330 ps |
| T2670 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.3372469084 |
|
|
Feb 09 04:34:08 PM UTC 25 |
Feb 09 05:10:31 PM UTC 25 |
132276710792 ps |
| T2671 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.635482931 |
|
|
Feb 09 05:08:54 PM UTC 25 |
Feb 09 05:10:33 PM UTC 25 |
4398740693 ps |
| T2672 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.70761437 |
|
|
Feb 09 05:08:22 PM UTC 25 |
Feb 09 05:10:35 PM UTC 25 |
1337176498 ps |
| T2673 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.2881918070 |
|
|
Feb 09 05:01:38 PM UTC 25 |
Feb 09 05:10:36 PM UTC 25 |
23441671738 ps |
| T2674 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.800414820 |
|
|
Feb 09 04:59:06 PM UTC 25 |
Feb 09 05:10:42 PM UTC 25 |
42137515515 ps |
| T2675 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.1429841285 |
|
|
Feb 09 05:07:05 PM UTC 25 |
Feb 09 05:10:48 PM UTC 25 |
2975008876 ps |
| T2676 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.3957009208 |
|
|
Feb 09 05:08:51 PM UTC 25 |
Feb 09 05:10:51 PM UTC 25 |
9574052261 ps |
| T2677 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.681605119 |
|
|
Feb 09 05:08:29 PM UTC 25 |
Feb 09 05:11:00 PM UTC 25 |
1725433301 ps |
| T2678 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.187854826 |
|
|
Feb 09 05:10:50 PM UTC 25 |
Feb 09 05:11:04 PM UTC 25 |
100112045 ps |
| T2679 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.2666618391 |
|
|
Feb 09 05:10:40 PM UTC 25 |
Feb 09 05:11:06 PM UTC 25 |
173246633 ps |
| T2680 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.2716400157 |
|
|
Feb 09 05:10:49 PM UTC 25 |
Feb 09 05:11:07 PM UTC 25 |
478342337 ps |
| T2681 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3370369361 |
|
|
Feb 09 04:56:01 PM UTC 25 |
Feb 09 05:11:11 PM UTC 25 |
49606769855 ps |
| T2682 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_slow_rsp.2701797055 |
|
|
Feb 09 05:07:59 PM UTC 25 |
Feb 09 05:11:15 PM UTC 25 |
12379552926 ps |
| T2683 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.948220329 |
|
|
Feb 09 05:02:49 PM UTC 25 |
Feb 09 05:11:20 PM UTC 25 |
2640016486 ps |
| T2684 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.1967589939 |
|
|
Feb 09 05:11:07 PM UTC 25 |
Feb 09 05:11:22 PM UTC 25 |
248574703 ps |
| T2685 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.4230920117 |
|
|
Feb 09 05:11:12 PM UTC 25 |
Feb 09 05:11:22 PM UTC 25 |
42424959 ps |
| T2686 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.3338578994 |
|
|
Feb 09 05:10:50 PM UTC 25 |
Feb 09 05:11:23 PM UTC 25 |
481091971 ps |
| T2687 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_large_delays.1932294982 |
|
|
Feb 09 05:02:21 PM UTC 25 |
Feb 09 05:11:25 PM UTC 25 |
53969017690 ps |
| T2688 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.1134104479 |
|
|
Feb 09 05:07:07 PM UTC 25 |
Feb 09 05:11:28 PM UTC 25 |
2714275009 ps |
| T2689 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.3046321949 |
|
|
Feb 09 05:10:51 PM UTC 25 |
Feb 09 05:11:30 PM UTC 25 |
1306730238 ps |
| T2690 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.3627073637 |
|
|
Feb 09 04:59:11 PM UTC 25 |
Feb 09 05:11:30 PM UTC 25 |
46546986711 ps |
| T2691 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all.3343473788 |
|
|
Feb 09 05:09:52 PM UTC 25 |
Feb 09 05:11:30 PM UTC 25 |
1165448454 ps |
| T2692 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.312937072 |
|
|
Feb 09 05:10:36 PM UTC 25 |
Feb 09 05:11:31 PM UTC 25 |
1144102362 ps |
| T2693 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.724005587 |
|
|
Feb 09 05:06:05 PM UTC 25 |
Feb 09 05:11:38 PM UTC 25 |
2725503276 ps |
| T2694 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.3041335163 |
|
|
Feb 09 05:10:50 PM UTC 25 |
Feb 09 05:11:40 PM UTC 25 |
956394507 ps |
| T2695 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.1344267197 |
|
|
Feb 09 05:10:34 PM UTC 25 |
Feb 09 05:11:50 PM UTC 25 |
5090026663 ps |
| T2696 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.3500180455 |
|
|
Feb 09 05:11:39 PM UTC 25 |
Feb 09 05:11:54 PM UTC 25 |
179444630 ps |
| T2697 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.1346911928 |
|
|
Feb 09 05:11:29 PM UTC 25 |
Feb 09 05:12:01 PM UTC 25 |
350042064 ps |
| T868 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.3675140487 |
|
|
Feb 09 05:07:08 PM UTC 25 |
Feb 09 05:12:07 PM UTC 25 |
7745511218 ps |
| T2698 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.3757143264 |
|
|
Feb 09 04:55:55 PM UTC 25 |
Feb 09 05:12:11 PM UTC 25 |
64468165836 ps |
| T2699 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.2053139807 |
|
|
Feb 09 05:12:01 PM UTC 25 |
Feb 09 05:12:11 PM UTC 25 |
38453401 ps |
| T2700 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.3756654266 |
|
|
Feb 09 05:12:00 PM UTC 25 |
Feb 09 05:12:15 PM UTC 25 |
236093459 ps |
| T2701 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_large_delays.278677527 |
|
|
Feb 09 05:05:15 PM UTC 25 |
Feb 09 05:12:17 PM UTC 25 |
31834377947 ps |
| T2702 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.3459842530 |
|
|
Feb 09 05:11:32 PM UTC 25 |
Feb 09 05:12:18 PM UTC 25 |
1281029404 ps |
| T2703 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.1881213453 |
|
|
Feb 09 05:10:23 PM UTC 25 |
Feb 09 05:12:19 PM UTC 25 |
9267722561 ps |
| T2704 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.4286523166 |
|
|
Feb 09 05:10:05 PM UTC 25 |
Feb 09 05:12:19 PM UTC 25 |
1629100236 ps |
| T2705 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.1478843877 |
|
|
Feb 09 05:11:53 PM UTC 25 |
Feb 09 05:12:22 PM UTC 25 |
735113444 ps |
| T2706 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.2122241037 |
|
|
Feb 09 05:11:47 PM UTC 25 |
Feb 09 05:12:27 PM UTC 25 |
1153198092 ps |
| T2707 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.1306414597 |
|
|
Feb 09 05:12:20 PM UTC 25 |
Feb 09 05:12:38 PM UTC 25 |
171124738 ps |
| T2708 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.1349158318 |
|
|
Feb 09 05:11:46 PM UTC 25 |
Feb 09 05:12:38 PM UTC 25 |
896990899 ps |
| T2709 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.114521316 |
|
|
Feb 09 05:11:28 PM UTC 25 |
Feb 09 05:12:44 PM UTC 25 |
4406133736 ps |
| T2710 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.2908236461 |
|
|
Feb 09 05:12:28 PM UTC 25 |
Feb 09 05:12:50 PM UTC 25 |
211225936 ps |
| T2711 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.2510638381 |
|
|
Feb 09 05:11:20 PM UTC 25 |
Feb 09 05:12:50 PM UTC 25 |
8728226078 ps |
| T2712 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.4207972010 |
|
|
Feb 09 05:11:43 PM UTC 25 |
Feb 09 05:12:51 PM UTC 25 |
1992945703 ps |
| T2713 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.1332564550 |
|
|
Feb 09 05:12:46 PM UTC 25 |
Feb 09 05:13:03 PM UTC 25 |
76457560 ps |
| T2714 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.438905066 |
|
|
Feb 09 05:12:46 PM UTC 25 |
Feb 09 05:13:09 PM UTC 25 |
450434981 ps |
| T2715 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.2309285656 |
|
|
Feb 09 05:12:52 PM UTC 25 |
Feb 09 05:13:12 PM UTC 25 |
90160383 ps |
| T2716 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.1562871582 |
|
|
Feb 09 05:12:36 PM UTC 25 |
Feb 09 05:13:17 PM UTC 25 |
708295830 ps |
| T2717 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.1329346406 |
|
|
Feb 09 05:12:46 PM UTC 25 |
Feb 09 05:13:22 PM UTC 25 |
326066127 ps |
| T2718 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.3632710063 |
|
|
Feb 09 05:13:12 PM UTC 25 |
Feb 09 05:13:23 PM UTC 25 |
212329462 ps |
| T2719 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.3792609053 |
|
|
Feb 09 05:13:19 PM UTC 25 |
Feb 09 05:13:29 PM UTC 25 |
44256996 ps |
| T2720 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.933157113 |
|
|
Feb 09 05:11:57 PM UTC 25 |
Feb 09 05:13:36 PM UTC 25 |
295185721 ps |
| T2721 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_large_delays.3140676378 |
|
|
Feb 09 05:00:30 PM UTC 25 |
Feb 09 05:13:37 PM UTC 25 |
73574591529 ps |
| T2722 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_slow_rsp.39301569 |
|
|
Feb 09 05:01:23 PM UTC 25 |
Feb 09 05:13:50 PM UTC 25 |
47218447022 ps |
| T2723 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.1941526611 |
|
|
Feb 09 05:12:42 PM UTC 25 |
Feb 09 05:13:52 PM UTC 25 |
1894301200 ps |
| T2724 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.1452782577 |
|
|
Feb 09 05:12:08 PM UTC 25 |
Feb 09 05:13:53 PM UTC 25 |
8967167958 ps |
| T2725 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.3259323329 |
|
|
Feb 09 05:12:18 PM UTC 25 |
Feb 09 05:13:58 PM UTC 25 |
4701625915 ps |
| T2726 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.2408388998 |
|
|
Feb 09 05:08:31 PM UTC 25 |
Feb 09 05:14:04 PM UTC 25 |
2127715461 ps |
| T2727 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.1103330819 |
|
|
Feb 09 05:13:30 PM UTC 25 |
Feb 09 05:14:05 PM UTC 25 |
417128239 ps |
| T2728 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.3992806802 |
|
|
Feb 09 05:13:35 PM UTC 25 |
Feb 09 05:14:16 PM UTC 25 |
375880020 ps |
| T2729 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.2696930487 |
|
|
Feb 09 05:14:05 PM UTC 25 |
Feb 09 05:14:24 PM UTC 25 |
84202406 ps |
| T2730 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all.1792249327 |
|
|
Feb 09 05:10:58 PM UTC 25 |
Feb 09 05:14:29 PM UTC 25 |
6860260417 ps |
| T2731 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.3679710890 |
|
|
Feb 09 05:08:25 PM UTC 25 |
Feb 09 05:14:30 PM UTC 25 |
4557343225 ps |
| T2732 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.3031944600 |
|
|
Feb 09 04:57:05 PM UTC 25 |
Feb 09 05:14:35 PM UTC 25 |
63039376563 ps |
| T2733 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.85709684 |
|
|
Feb 09 05:14:18 PM UTC 25 |
Feb 09 05:14:36 PM UTC 25 |
94386205 ps |
| T2734 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.3824926128 |
|
|
Feb 09 05:10:53 PM UTC 25 |
Feb 09 05:14:41 PM UTC 25 |
4323430727 ps |
| T2735 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.2736476320 |
|
|
Feb 09 05:14:32 PM UTC 25 |
Feb 09 05:14:45 PM UTC 25 |
156401949 ps |
| T2736 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.2386137190 |
|
|
Feb 09 05:13:57 PM UTC 25 |
Feb 09 05:14:46 PM UTC 25 |
503714686 ps |
| T2737 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.931845115 |
|
|
Feb 09 05:14:04 PM UTC 25 |
Feb 09 05:14:47 PM UTC 25 |
461127032 ps |
| T2738 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.392071395 |
|
|
Feb 09 05:14:37 PM UTC 25 |
Feb 09 05:14:48 PM UTC 25 |
47332869 ps |
| T2739 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_error.17997954 |
|
|
Feb 09 05:11:01 PM UTC 25 |
Feb 09 05:14:57 PM UTC 25 |
6783018902 ps |
| T2740 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.916521163 |
|
|
Feb 09 05:05:38 PM UTC 25 |
Feb 09 05:14:58 PM UTC 25 |
31774251166 ps |
| T2741 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_slow_rsp.3658143044 |
|
|
Feb 09 05:06:42 PM UTC 25 |
Feb 09 05:15:07 PM UTC 25 |
29161679679 ps |
| T2742 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.3321960085 |
|
|
Feb 09 05:15:04 PM UTC 25 |
Feb 09 05:15:12 PM UTC 25 |
21523373 ps |
| T2743 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.4132892766 |
|
|
Feb 09 05:13:45 PM UTC 25 |
Feb 09 05:15:12 PM UTC 25 |
2190193338 ps |
| T2744 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.2536930633 |
|
|
Feb 09 05:13:18 PM UTC 25 |
Feb 09 05:15:17 PM UTC 25 |
5305051798 ps |
| T2745 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device.1727762367 |
|
|
Feb 09 05:20:21 PM UTC 25 |
Feb 09 05:20:43 PM UTC 25 |
474249533 ps |
| T2746 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.1482323195 |
|
|
Feb 09 05:13:05 PM UTC 25 |
Feb 09 05:15:18 PM UTC 25 |
382179066 ps |
| T2747 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.2075660051 |
|
|
Feb 09 05:13:14 PM UTC 25 |
Feb 09 05:15:27 PM UTC 25 |
8985138047 ps |
| T2748 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all.1216453543 |
|
|
Feb 09 05:11:53 PM UTC 25 |
Feb 09 05:15:28 PM UTC 25 |
7047305568 ps |
| T2749 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_unmapped_addr.503216603 |
|
|
Feb 09 05:15:26 PM UTC 25 |
Feb 09 05:15:38 PM UTC 25 |
158032714 ps |
| T2750 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_error.4153807221 |
|
|
Feb 09 05:09:59 PM UTC 25 |
Feb 09 05:15:41 PM UTC 25 |
9078300608 ps |
| T2751 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.3102522897 |
|
|
Feb 09 05:14:59 PM UTC 25 |
Feb 09 05:15:42 PM UTC 25 |
465794289 ps |
| T2752 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.3528852059 |
|
|
Feb 09 05:15:23 PM UTC 25 |
Feb 09 05:15:42 PM UTC 25 |
227590697 ps |
| T2753 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.1238719553 |
|
|
Feb 09 05:15:15 PM UTC 25 |
Feb 09 05:15:44 PM UTC 25 |
565426532 ps |
| T2754 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.1628261931 |
|
|
Feb 09 04:40:27 PM UTC 25 |
Feb 09 05:15:55 PM UTC 25 |
120009526723 ps |
| T2755 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.4224710078 |
|
|
Feb 09 05:15:13 PM UTC 25 |
Feb 09 05:15:56 PM UTC 25 |
1236072385 ps |
| T2756 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.1167431197 |
|
|
Feb 09 05:15:47 PM UTC 25 |
Feb 09 05:15:57 PM UTC 25 |
52335393 ps |
| T2757 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.981793985 |
|
|
Feb 09 05:14:19 PM UTC 25 |
Feb 09 05:16:00 PM UTC 25 |
132033602 ps |
| T2758 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.1910357480 |
|
|
Feb 09 05:15:56 PM UTC 25 |
Feb 09 05:16:07 PM UTC 25 |
59924830 ps |
| T2759 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random.2383733647 |
|
|
Feb 09 05:20:08 PM UTC 25 |
Feb 09 05:20:55 PM UTC 25 |
444238885 ps |
| T2760 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.4159870333 |
|
|
Feb 09 04:43:17 PM UTC 25 |
Feb 09 05:16:12 PM UTC 25 |
118932078613 ps |
| T2761 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device.2177310680 |
|
|
Feb 09 05:15:12 PM UTC 25 |
Feb 09 05:16:15 PM UTC 25 |
785050089 ps |
| T2762 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.456961928 |
|
|
Feb 09 05:14:58 PM UTC 25 |
Feb 09 05:16:27 PM UTC 25 |
5305806905 ps |