T78 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_virus.1995874118 |
|
|
Feb 09 09:11:45 PM UTC 25 |
Feb 09 09:38:34 PM UTC 25 |
5940367256 ps |
T108 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.3719019060 |
|
|
Feb 09 09:28:40 PM UTC 25 |
Feb 09 09:39:05 PM UTC 25 |
4795141358 ps |
T1081 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2294625829 |
|
|
Feb 09 09:29:12 PM UTC 25 |
Feb 09 09:39:07 PM UTC 25 |
4448378920 ps |
T125 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3408967555 |
|
|
Feb 09 09:00:59 PM UTC 25 |
Feb 09 09:39:26 PM UTC 25 |
23684291992 ps |
T1082 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_smoketest.2476998996 |
|
|
Feb 09 09:23:29 PM UTC 25 |
Feb 09 09:41:01 PM UTC 25 |
5474872332 ps |
T1083 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx1.4005775574 |
|
|
Feb 09 09:31:53 PM UTC 25 |
Feb 09 09:41:24 PM UTC 25 |
4847038132 ps |
T386 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx.2000352281 |
|
|
Feb 09 09:31:52 PM UTC 25 |
Feb 09 09:42:00 PM UTC 25 |
4439524654 ps |
T1084 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx2.419353505 |
|
|
Feb 09 09:32:34 PM UTC 25 |
Feb 09 09:42:03 PM UTC 25 |
4727041500 ps |
T251 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_otbn.1354818333 |
|
|
Feb 09 08:41:08 PM UTC 25 |
Feb 09 09:42:12 PM UTC 25 |
12249205408 ps |
T314 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.4293442813 |
|
|
Feb 09 09:30:11 PM UTC 25 |
Feb 09 09:42:48 PM UTC 25 |
4940041380 ps |
T1085 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2616193958 |
|
|
Feb 09 08:22:03 PM UTC 25 |
Feb 09 09:43:43 PM UTC 25 |
17335813100 ps |
T57 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.3847555591 |
|
|
Feb 09 09:38:58 PM UTC 25 |
Feb 09 09:44:13 PM UTC 25 |
2581356920 ps |
T1086 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1350856982 |
|
|
Feb 09 09:08:45 PM UTC 25 |
Feb 09 09:44:26 PM UTC 25 |
12562020684 ps |
T1087 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2720832463 |
|
|
Feb 09 09:34:44 PM UTC 25 |
Feb 09 09:45:00 PM UTC 25 |
4927115597 ps |
T87 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.4021401547 |
|
|
Feb 09 09:39:14 PM UTC 25 |
Feb 09 09:46:17 PM UTC 25 |
3131205908 ps |
T59 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.3441245787 |
|
|
Feb 09 09:37:58 PM UTC 25 |
Feb 09 09:46:23 PM UTC 25 |
3639711098 ps |
T1088 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx3.3614547239 |
|
|
Feb 09 09:33:10 PM UTC 25 |
Feb 09 09:46:55 PM UTC 25 |
4744695968 ps |
T260 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init_reduced_freq.3428285738 |
|
|
Feb 09 09:08:44 PM UTC 25 |
Feb 09 09:47:48 PM UTC 25 |
18165676148 ps |
T228 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through.1993528287 |
|
|
Feb 09 09:40:09 PM UTC 25 |
Feb 09 09:47:59 PM UTC 25 |
4964976942 ps |
T1089 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1525796640 |
|
|
Feb 09 09:43:27 PM UTC 25 |
Feb 09 09:49:28 PM UTC 25 |
3862849404 ps |
T379 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.1915082726 |
|
|
Feb 09 09:37:58 PM UTC 25 |
Feb 09 09:50:12 PM UTC 25 |
4388300160 ps |
T391 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx.4055016508 |
|
|
Feb 09 09:36:01 PM UTC 25 |
Feb 09 09:50:13 PM UTC 25 |
4887281048 ps |
T52 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.544984516 |
|
|
Feb 09 09:40:09 PM UTC 25 |
Feb 09 09:50:54 PM UTC 25 |
4101516720 ps |
T378 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2456413831 |
|
|
Feb 09 09:37:16 PM UTC 25 |
Feb 09 09:51:28 PM UTC 25 |
5726912650 ps |
T229 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through_collision.2008281028 |
|
|
Feb 09 09:40:09 PM UTC 25 |
Feb 09 09:51:50 PM UTC 25 |
4994145807 ps |
T1090 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3375717681 |
|
|
Feb 09 09:47:07 PM UTC 25 |
Feb 09 09:51:50 PM UTC 25 |
3368559330 ps |
T261 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.653413304 |
|
|
Feb 09 09:43:01 PM UTC 25 |
Feb 09 09:52:03 PM UTC 25 |
4304323325 ps |
T1091 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_self_hash.1130248901 |
|
|
Feb 09 07:32:07 PM UTC 25 |
Feb 09 09:52:26 PM UTC 25 |
27202639592 ps |
T392 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.74387920 |
|
|
Feb 09 09:37:16 PM UTC 25 |
Feb 09 09:53:47 PM UTC 25 |
4555452972 ps |
T1092 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops.2823916543 |
|
|
Feb 09 09:41:42 PM UTC 25 |
Feb 09 09:54:02 PM UTC 25 |
3655222496 ps |
T190 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1113959095 |
|
|
Feb 09 09:50:07 PM UTC 25 |
Feb 09 09:54:06 PM UTC 25 |
2687371647 ps |
T396 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3821590417 |
|
|
Feb 09 09:42:03 PM UTC 25 |
Feb 09 09:54:11 PM UTC 25 |
4135495864 ps |
T1093 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3825608991 |
|
|
Feb 09 09:53:02 PM UTC 25 |
Feb 09 09:55:20 PM UTC 25 |
2551251690 ps |
T1094 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.357087515 |
|
|
Feb 09 09:51:04 PM UTC 25 |
Feb 09 09:56:07 PM UTC 25 |
2365435088 ps |
T1095 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3132951835 |
|
|
Feb 09 09:53:58 PM UTC 25 |
Feb 09 09:56:34 PM UTC 25 |
2074682198 ps |
T1096 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.4011668990 |
|
|
Feb 09 09:52:04 PM UTC 25 |
Feb 09 09:57:01 PM UTC 25 |
3101682642 ps |
T1097 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2295532961 |
|
|
Feb 09 09:47:08 PM UTC 25 |
Feb 09 09:57:43 PM UTC 25 |
3699516800 ps |
T1098 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pwm_pulses.2333931700 |
|
|
Feb 09 09:31:54 PM UTC 25 |
Feb 09 09:58:06 PM UTC 25 |
8625234384 ps |
T1099 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access.44210656 |
|
|
Feb 09 09:43:02 PM UTC 25 |
Feb 09 09:58:49 PM UTC 25 |
6232678406 ps |
T1100 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1466000303 |
|
|
Feb 09 07:12:53 PM UTC 25 |
Feb 09 09:59:53 PM UTC 25 |
29567090826 ps |
T1101 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_rst.1814044159 |
|
|
Feb 09 09:55:04 PM UTC 25 |
Feb 09 10:00:13 PM UTC 25 |
3189351940 ps |
T1102 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_rand_baudrate.1259118669 |
|
|
Feb 09 09:34:02 PM UTC 25 |
Feb 09 10:00:19 PM UTC 25 |
7803796674 ps |
T1103 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_req.3297675349 |
|
|
Feb 09 09:55:04 PM UTC 25 |
Feb 09 10:01:54 PM UTC 25 |
4333248908 ps |
T1104 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.4072348380 |
|
|
Feb 09 09:42:59 PM UTC 25 |
Feb 09 10:02:08 PM UTC 25 |
6078954686 ps |
T1105 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_descrambling.708037657 |
|
|
Feb 09 09:51:07 PM UTC 25 |
Feb 09 10:03:01 PM UTC 25 |
3987108980 ps |
T1106 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.273910878 |
|
|
Feb 09 09:45:02 PM UTC 25 |
Feb 09 10:03:21 PM UTC 25 |
6095421562 ps |
T1107 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1420734738 |
|
|
Feb 09 09:34:02 PM UTC 25 |
Feb 09 10:03:27 PM UTC 25 |
8352221102 ps |
T1108 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.590997912 |
|
|
Feb 09 08:06:53 PM UTC 25 |
Feb 09 10:03:59 PM UTC 25 |
52258047395 ps |
T1109 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2629160445 |
|
|
Feb 09 09:56:47 PM UTC 25 |
Feb 09 10:04:57 PM UTC 25 |
6640393230 ps |
T1110 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2574740308 |
|
|
Feb 09 09:57:12 PM UTC 25 |
Feb 09 10:05:48 PM UTC 25 |
3871788768 ps |
T664 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2628797790 |
|
|
Feb 09 10:04:10 PM UTC 25 |
Feb 09 10:09:23 PM UTC 25 |
3415647246 ps |
T1111 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3515544269 |
|
|
Feb 09 09:47:35 PM UTC 25 |
Feb 09 10:10:02 PM UTC 25 |
6940149992 ps |
T1112 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.4129526319 |
|
|
Feb 09 10:01:04 PM UTC 25 |
Feb 09 10:10:50 PM UTC 25 |
4662946184 ps |
T1113 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_irq.3205645184 |
|
|
Feb 09 10:04:37 PM UTC 25 |
Feb 09 10:11:01 PM UTC 25 |
3537439944 ps |
T1114 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2638887610 |
|
|
Feb 09 10:02:48 PM UTC 25 |
Feb 09 10:11:04 PM UTC 25 |
6263372030 ps |
T1115 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3340161097 |
|
|
Feb 09 09:48:36 PM UTC 25 |
Feb 09 10:11:15 PM UTC 25 |
9260167672 ps |
T1116 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1149011230 |
|
|
Feb 09 07:30:06 PM UTC 25 |
Feb 09 10:11:36 PM UTC 25 |
29226175864 ps |
T1117 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_transition.3560822011 |
|
|
Feb 09 09:51:29 PM UTC 25 |
Feb 09 10:11:36 PM UTC 25 |
8971480317 ps |
T1118 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3189211457 |
|
|
Feb 09 10:01:04 PM UTC 25 |
Feb 09 10:11:53 PM UTC 25 |
10026739936 ps |
T1119 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3821020702 |
|
|
Feb 09 09:48:39 PM UTC 25 |
Feb 09 10:12:30 PM UTC 25 |
8790354010 ps |
T1120 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1659346760 |
|
|
Feb 09 10:02:34 PM UTC 25 |
Feb 09 10:12:39 PM UTC 25 |
5989931990 ps |
T271 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_cpu_info.245511083 |
|
|
Feb 09 09:55:59 PM UTC 25 |
Feb 09 10:13:03 PM UTC 25 |
7150192296 ps |
T210 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.1636698975 |
|
|
Feb 09 08:00:51 PM UTC 25 |
Feb 09 10:13:05 PM UTC 25 |
45399214615 ps |
T1121 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1686701522 |
|
|
Feb 09 10:06:28 PM UTC 25 |
Feb 09 10:13:17 PM UTC 25 |
2492605277 ps |
T1122 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_test_unlocked0.581036306 |
|
|
Feb 09 09:13:04 PM UTC 25 |
Feb 09 10:13:20 PM UTC 25 |
11977132955 ps |
T1123 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.4272540842 |
|
|
Feb 09 10:04:11 PM UTC 25 |
Feb 09 10:13:56 PM UTC 25 |
4614316540 ps |
T1124 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_rma.724591438 |
|
|
Feb 09 08:07:39 PM UTC 25 |
Feb 09 10:14:26 PM UTC 25 |
47718863064 ps |
T254 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_dev.2914294591 |
|
|
Feb 09 08:06:09 PM UTC 25 |
Feb 09 10:14:40 PM UTC 25 |
48822336280 ps |
T1125 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1726535418 |
|
|
Feb 09 07:30:07 PM UTC 25 |
Feb 09 10:14:56 PM UTC 25 |
28796246378 ps |
T1126 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prodend.1342892548 |
|
|
Feb 09 09:52:47 PM UTC 25 |
Feb 09 10:16:45 PM UTC 25 |
10524376033 ps |
T55 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3970301548 |
|
|
Feb 09 10:10:41 PM UTC 25 |
Feb 09 10:17:11 PM UTC 25 |
5766556736 ps |
T1127 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.914064923 |
|
|
Feb 09 10:12:31 PM UTC 25 |
Feb 09 10:18:54 PM UTC 25 |
4222733630 ps |
T1128 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_outputs.812208580 |
|
|
Feb 09 10:11:58 PM UTC 25 |
Feb 09 10:19:19 PM UTC 25 |
3338969844 ps |
T1129 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc.2699306900 |
|
|
Feb 09 10:15:04 PM UTC 25 |
Feb 09 10:19:21 PM UTC 25 |
3241168716 ps |
T140 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_rst_inputs.2053559404 |
|
|
Feb 09 09:11:24 PM UTC 25 |
Feb 09 10:19:25 PM UTC 25 |
22113501431 ps |
T1130 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.437176635 |
|
|
Feb 09 10:12:38 PM UTC 25 |
Feb 09 10:19:58 PM UTC 25 |
6890574560 ps |
T1131 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.491156179 |
|
|
Feb 09 09:57:40 PM UTC 25 |
Feb 09 10:20:11 PM UTC 25 |
7396278841 ps |
T1132 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en.582356070 |
|
|
Feb 09 10:15:20 PM UTC 25 |
Feb 09 10:21:12 PM UTC 25 |
2854612172 ps |
T1133 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_idle.2583777905 |
|
|
Feb 09 10:15:34 PM UTC 25 |
Feb 09 10:21:51 PM UTC 25 |
2987765216 ps |
T1134 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.907243119 |
|
|
Feb 09 10:13:18 PM UTC 25 |
Feb 09 10:21:53 PM UTC 25 |
4778170450 ps |
T1135 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_mem_scramble.2605061177 |
|
|
Feb 09 10:14:23 PM UTC 25 |
Feb 09 10:23:11 PM UTC 25 |
3614400016 ps |
T1136 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3624583145 |
|
|
Feb 09 10:10:04 PM UTC 25 |
Feb 09 10:23:14 PM UTC 25 |
4538294919 ps |
T255 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init.309138524 |
|
|
Feb 09 09:44:16 PM UTC 25 |
Feb 09 10:23:29 PM UTC 25 |
18029567844 ps |
T1137 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_entropy.3176406883 |
|
|
Feb 09 09:45:39 PM UTC 25 |
Feb 09 10:23:30 PM UTC 25 |
9211701404 ps |
T85 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_test.805940535 |
|
|
Feb 09 10:17:49 PM UTC 25 |
Feb 09 10:23:38 PM UTC 25 |
3076631218 ps |
T1138 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_masking_off.1380672330 |
|
|
Feb 09 10:17:23 PM UTC 25 |
Feb 09 10:23:40 PM UTC 25 |
3683412257 ps |
T1139 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3013726478 |
|
|
Feb 09 10:12:37 PM UTC 25 |
Feb 09 10:23:49 PM UTC 25 |
6842222236 ps |
T1140 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2021219704 |
|
|
Feb 09 10:12:39 PM UTC 25 |
Feb 09 10:23:51 PM UTC 25 |
4585907568 ps |
T1141 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.522032865 |
|
|
Feb 09 09:59:29 PM UTC 25 |
Feb 09 10:25:12 PM UTC 25 |
16725841581 ps |
T1142 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_smoke.2879461901 |
|
|
Feb 09 09:11:47 PM UTC 25 |
Feb 09 10:25:57 PM UTC 25 |
15404015360 ps |
T1143 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_exception_c.2790011618 |
|
|
Feb 09 09:12:36 PM UTC 25 |
Feb 09 10:26:19 PM UTC 25 |
15128442416 ps |
T1144 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2536573575 |
|
|
Feb 09 10:13:19 PM UTC 25 |
Feb 09 10:26:42 PM UTC 25 |
19771949188 ps |
T1145 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod_end.3897993683 |
|
|
Feb 09 09:14:22 PM UTC 25 |
Feb 09 10:27:29 PM UTC 25 |
16095761013 ps |
T105 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_entropy.1140870315 |
|
|
Feb 09 10:22:41 PM UTC 25 |
Feb 09 10:27:47 PM UTC 25 |
3174185737 ps |
T1146 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_randomness.827534409 |
|
|
Feb 09 10:14:13 PM UTC 25 |
Feb 09 10:28:46 PM UTC 25 |
6002306676 ps |
T1147 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2221767159 |
|
|
Feb 09 10:00:33 PM UTC 25 |
Feb 09 10:29:06 PM UTC 25 |
13469771788 ps |
T1148 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_entropy.2658185212 |
|
|
Feb 09 10:25:06 PM UTC 25 |
Feb 09 10:29:45 PM UTC 25 |
3138098024 ps |
T474 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3089329611 |
|
|
Feb 09 10:20:49 PM UTC 25 |
Feb 09 10:29:47 PM UTC 25 |
4135775704 ps |
T1149 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_timeout.2775762008 |
|
|
Feb 09 10:20:24 PM UTC 25 |
Feb 09 10:29:48 PM UTC 25 |
4585910120 ps |
T1150 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_kat_test.2066225777 |
|
|
Feb 09 10:25:00 PM UTC 25 |
Feb 09 10:29:56 PM UTC 25 |
2617305096 ps |
T476 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3869942927 |
|
|
Feb 09 10:14:39 PM UTC 25 |
Feb 09 10:29:57 PM UTC 25 |
5135659788 ps |
T1151 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_output.1960465359 |
|
|
Feb 09 09:13:14 PM UTC 25 |
Feb 09 10:30:00 PM UTC 25 |
26107969642 ps |
T1152 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3904748588 |
|
|
Feb 09 10:26:53 PM UTC 25 |
Feb 09 10:31:14 PM UTC 25 |
2818152072 ps |
T1153 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.812025110 |
|
|
Feb 09 09:58:23 PM UTC 25 |
Feb 09 10:31:43 PM UTC 25 |
10934792881 ps |
T1154 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_kat_test.2227274194 |
|
|
Feb 09 10:25:51 PM UTC 25 |
Feb 09 10:31:44 PM UTC 25 |
2773082392 ps |
T1155 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_rnd.393892916 |
|
|
Feb 09 10:14:38 PM UTC 25 |
Feb 09 10:32:05 PM UTC 25 |
5341891220 ps |
T1156 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_escalation.1848874655 |
|
|
Feb 09 10:19:33 PM UTC 25 |
Feb 09 10:32:12 PM UTC 25 |
5349189446 ps |
T1157 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_rma.560155102 |
|
|
Feb 09 09:14:21 PM UTC 25 |
Feb 09 10:32:16 PM UTC 25 |
14618934116 ps |
T376 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.1198559322 |
|
|
Feb 09 09:55:04 PM UTC 25 |
Feb 09 10:33:07 PM UTC 25 |
12956520622 ps |
T642 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_boot_mode.3111211161 |
|
|
Feb 09 10:24:54 PM UTC 25 |
Feb 09 10:33:47 PM UTC 25 |
3073730400 ps |
T1158 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en.3995879684 |
|
|
Feb 09 10:29:25 PM UTC 25 |
Feb 09 10:33:53 PM UTC 25 |
2532052528 ps |
T1159 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc.3029380241 |
|
|
Feb 09 10:29:21 PM UTC 25 |
Feb 09 10:34:01 PM UTC 25 |
3382288436 ps |
T1160 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_idle.2718411164 |
|
|
Feb 09 10:29:44 PM UTC 25 |
Feb 09 10:34:20 PM UTC 25 |
2838661032 ps |
T1161 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_kat.878096834 |
|
|
Feb 09 10:25:04 PM UTC 25 |
Feb 09 10:34:38 PM UTC 25 |
3733259114 ps |
T1162 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2541045131 |
|
|
Feb 09 09:54:37 PM UTC 25 |
Feb 09 10:35:16 PM UTC 25 |
25884679213 ps |
T1163 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.458691393 |
|
|
Feb 09 10:25:07 PM UTC 25 |
Feb 09 10:35:58 PM UTC 25 |
7688263508 ps |
T1164 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod.679034513 |
|
|
Feb 09 09:13:20 PM UTC 25 |
Feb 09 10:36:03 PM UTC 25 |
15813134040 ps |
T1165 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.325921264 |
|
|
Feb 09 10:26:34 PM UTC 25 |
Feb 09 10:36:51 PM UTC 25 |
4048009632 ps |
T1166 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_oneshot.4190630371 |
|
|
Feb 09 10:31:10 PM UTC 25 |
Feb 09 10:37:19 PM UTC 25 |
2848043608 ps |
T1167 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_dev.1949806520 |
|
|
Feb 09 09:13:18 PM UTC 25 |
Feb 09 10:37:23 PM UTC 25 |
15385641648 ps |
T1168 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_cshake.1365615131 |
|
|
Feb 09 10:33:03 PM UTC 25 |
Feb 09 10:38:22 PM UTC 25 |
3397797104 ps |
T1169 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_idle.3793730869 |
|
|
Feb 09 10:33:45 PM UTC 25 |
Feb 09 10:38:33 PM UTC 25 |
2474131920 ps |
T1170 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_app_rom.1838979362 |
|
|
Feb 09 10:33:08 PM UTC 25 |
Feb 09 10:38:51 PM UTC 25 |
2877109604 ps |
T1171 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3796953327 |
|
|
Feb 09 10:33:09 PM UTC 25 |
Feb 09 10:38:53 PM UTC 25 |
3381320859 ps |
T1172 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac.3408817155 |
|
|
Feb 09 10:33:08 PM UTC 25 |
Feb 09 10:38:54 PM UTC 25 |
2513079432 ps |
T646 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.321060436 |
|
|
Feb 09 09:08:48 PM UTC 25 |
Feb 09 10:39:12 PM UTC 25 |
25011706550 ps |
T1173 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1463722039 |
|
|
Feb 09 09:58:46 PM UTC 25 |
Feb 09 10:39:12 PM UTC 25 |
25093281413 ps |
T1174 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_static_critical.3643116576 |
|
|
Feb 09 09:14:32 PM UTC 25 |
Feb 09 10:41:11 PM UTC 25 |
16745732222 ps |
T1175 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_status.3280644893 |
|
|
Feb 09 10:36:49 PM UTC 25 |
Feb 09 10:42:32 PM UTC 25 |
2645287647 ps |
T1176 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_ok.2118982603 |
|
|
Feb 09 10:20:24 PM UTC 25 |
Feb 09 10:43:28 PM UTC 25 |
7662511460 ps |
T441 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2919074498 |
|
|
Feb 09 10:34:58 PM UTC 25 |
Feb 09 10:43:40 PM UTC 25 |
9008042431 ps |
T1177 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3962005563 |
|
|
Feb 09 10:35:18 PM UTC 25 |
Feb 09 10:46:01 PM UTC 25 |
7877175912 ps |
T1178 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_reset.3944294652 |
|
|
Feb 09 10:12:21 PM UTC 25 |
Feb 09 10:46:11 PM UTC 25 |
22422964400 ps |
T172 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2195561307 |
|
|
Feb 09 10:37:31 PM UTC 25 |
Feb 09 10:46:22 PM UTC 25 |
5012324128 ps |
T1179 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1538690660 |
|
|
Feb 09 10:34:59 PM UTC 25 |
Feb 09 10:46:26 PM UTC 25 |
4762061570 ps |
T1180 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3505492849 |
|
|
Feb 09 10:28:27 PM UTC 25 |
Feb 09 10:46:46 PM UTC 25 |
6971377766 ps |
T345 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_plic_sw_irq.1432770367 |
|
|
Feb 09 10:40:14 PM UTC 25 |
Feb 09 10:47:09 PM UTC 25 |
3132791944 ps |
T1181 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1475295925 |
|
|
Feb 09 10:40:12 PM UTC 25 |
Feb 09 10:47:16 PM UTC 25 |
4124828920 ps |
T1182 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1458730230 |
|
|
Feb 09 10:35:02 PM UTC 25 |
Feb 09 10:47:18 PM UTC 25 |
5347465513 ps |
T647 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.1791226947 |
|
|
Feb 09 08:32:58 PM UTC 25 |
Feb 09 10:47:52 PM UTC 25 |
24925871940 ps |
T1183 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2618466157 |
|
|
Feb 09 10:40:13 PM UTC 25 |
Feb 09 10:48:26 PM UTC 25 |
4525082800 ps |
T1184 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2097396764 |
|
|
Feb 09 10:40:12 PM UTC 25 |
Feb 09 10:48:56 PM UTC 25 |
5811073512 ps |
T377 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.3463732815 |
|
|
Feb 09 10:27:20 PM UTC 25 |
Feb 09 10:49:12 PM UTC 25 |
5912419860 ps |
T340 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_execution_main.1305796850 |
|
|
Feb 09 10:35:02 PM UTC 25 |
Feb 09 10:49:32 PM UTC 25 |
7210501276 ps |
T1185 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_auto_mode.3602576622 |
|
|
Feb 09 10:24:58 PM UTC 25 |
Feb 09 10:50:23 PM UTC 25 |
5817268388 ps |
T187 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.1364429604 |
|
|
Feb 09 10:39:14 PM UTC 25 |
Feb 09 10:50:46 PM UTC 25 |
4113454304 ps |
T1186 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs.3260947447 |
|
|
Feb 09 10:28:09 PM UTC 25 |
Feb 09 10:51:04 PM UTC 25 |
7183356080 ps |
T1187 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2280714534 |
|
|
Feb 09 10:35:55 PM UTC 25 |
Feb 09 10:51:04 PM UTC 25 |
7572549784 ps |
T1188 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.441238266 |
|
|
Feb 09 10:41:51 PM UTC 25 |
Feb 09 10:51:15 PM UTC 25 |
4131238924 ps |
T170 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.2049706332 |
|
|
Feb 09 10:36:49 PM UTC 25 |
Feb 09 10:52:10 PM UTC 25 |
6830934560 ps |
T1189 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter.2457114028 |
|
|
Feb 09 10:48:09 PM UTC 25 |
Feb 09 10:52:38 PM UTC 25 |
2470767397 ps |
T353 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.1064575497 |
|
|
Feb 09 10:39:15 PM UTC 25 |
Feb 09 10:52:59 PM UTC 25 |
5064718626 ps |
T1190 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3003010357 |
|
|
Feb 09 10:44:17 PM UTC 25 |
Feb 09 10:53:27 PM UTC 25 |
3710160920 ps |
T1191 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3908517669 |
|
|
Feb 09 10:44:20 PM UTC 25 |
Feb 09 10:56:05 PM UTC 25 |
4449669140 ps |
T1192 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_reset_frequency.2155553897 |
|
|
Feb 09 10:47:27 PM UTC 25 |
Feb 09 10:56:13 PM UTC 25 |
3850117405 ps |
T1193 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.44465437 |
|
|
Feb 09 10:46:50 PM UTC 25 |
Feb 09 10:56:51 PM UTC 25 |
3843233540 ps |
T1194 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1504497954 |
|
|
Feb 09 10:47:11 PM UTC 25 |
Feb 09 10:56:53 PM UTC 25 |
4293418400 ps |
T1195 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3516746686 |
|
|
Feb 09 10:22:40 PM UTC 25 |
Feb 09 10:57:09 PM UTC 25 |
7488354986 ps |
T1196 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_dev.1912196893 |
|
|
Feb 09 10:54:25 PM UTC 25 |
Feb 09 10:57:33 PM UTC 25 |
2899301258 ps |
T1197 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_kmac.1639215008 |
|
|
Feb 09 10:31:20 PM UTC 25 |
Feb 09 10:57:39 PM UTC 25 |
8791485708 ps |
T1198 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1473756809 |
|
|
Feb 09 10:47:24 PM UTC 25 |
Feb 09 10:57:47 PM UTC 25 |
3953020600 ps |
T1199 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2279250827 |
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|
Feb 09 10:47:26 PM UTC 25 |
Feb 09 10:58:22 PM UTC 25 |
4019985856 ps |
T381 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2612955004 |
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|
Feb 09 10:51:02 PM UTC 25 |
Feb 09 10:58:35 PM UTC 25 |
3481554440 ps |
T455 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4175293938 |
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|
Feb 09 10:50:12 PM UTC 25 |
Feb 09 10:58:59 PM UTC 25 |
6976291080 ps |
T1200 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.1237926995 |
|
|
Feb 09 10:53:37 PM UTC 25 |
Feb 09 10:59:47 PM UTC 25 |
5460004342 ps |
T200 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_program_error.1544357865 |
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|
Feb 09 10:49:53 PM UTC 25 |
Feb 09 10:59:59 PM UTC 25 |
5419332148 ps |
T1201 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2398939868 |
|
|
Feb 09 10:31:24 PM UTC 25 |
Feb 09 11:00:01 PM UTC 25 |
9090484992 ps |
T91 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_testunlock0.2165593214 |
|
|
Feb 09 10:56:38 PM UTC 25 |
Feb 09 11:00:03 PM UTC 25 |
2321518476 ps |
T124 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_rv_dm_ndm_reset_req.3736681722 |
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|
Feb 09 10:52:49 PM UTC 25 |
Feb 09 11:00:18 PM UTC 25 |
5076043860 ps |
T426 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3971279052 |
|
|
Feb 09 10:57:47 PM UTC 25 |
Feb 09 11:00:34 PM UTC 25 |
2623627560 ps |
T1202 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_prod.280166213 |
|
|
Feb 09 10:57:33 PM UTC 25 |
Feb 09 11:00:36 PM UTC 25 |
2794441367 ps |
T1203 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3359005902 |
|
|
Feb 09 10:21:52 PM UTC 25 |
Feb 09 11:00:38 PM UTC 25 |
9315530440 ps |
T403 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1366809429 |
|
|
Feb 09 10:52:08 PM UTC 25 |
Feb 09 11:01:06 PM UTC 25 |
6223914384 ps |
T1204 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1097252976 |
|
|
Feb 09 10:43:11 PM UTC 25 |
Feb 09 11:01:34 PM UTC 25 |
12896257358 ps |
T1205 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation.1975877664 |
|
|
Feb 09 10:31:19 PM UTC 25 |
Feb 09 11:01:51 PM UTC 25 |
8367612100 ps |
T1206 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_sleep_frequency.204001033 |
|
|
Feb 09 10:48:10 PM UTC 25 |
Feb 09 11:02:00 PM UTC 25 |
5267051358 ps |
T1207 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.456358245 |
|
|
Feb 09 10:52:05 PM UTC 25 |
Feb 09 11:02:03 PM UTC 25 |
6790762008 ps |
T272 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3521769234 |
|
|
Feb 09 10:57:45 PM UTC 25 |
Feb 09 11:02:27 PM UTC 25 |
2855500800 ps |
T334 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.638394578 |
|
|
Feb 09 10:58:30 PM UTC 25 |
Feb 09 11:02:40 PM UTC 25 |
3350036446 ps |
T1208 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.1108570266 |
|
|
Feb 09 10:58:59 PM UTC 25 |
Feb 09 11:02:55 PM UTC 25 |
2411440495 ps |
T355 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.2299073423 |
|
|
Feb 09 10:38:12 PM UTC 25 |
Feb 09 11:03:13 PM UTC 25 |
6382058450 ps |
T1209 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_frequency.771687530 |
|
|
Feb 09 10:48:11 PM UTC 25 |
Feb 09 11:03:52 PM UTC 25 |
4969449018 ps |
T264 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2269108025 |
|
|
Feb 09 10:53:18 PM UTC 25 |
Feb 09 11:04:00 PM UTC 25 |
4978288814 ps |
T1210 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_write_clear.1078602354 |
|
|
Feb 09 10:58:33 PM UTC 25 |
Feb 09 11:04:03 PM UTC 25 |
3239493460 ps |
T1211 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_peri.1602484246 |
|
|
Feb 09 10:40:10 PM UTC 25 |
Feb 09 11:04:45 PM UTC 25 |
9438438184 ps |
T74 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.4240540198 |
|
|
Feb 09 10:48:17 PM UTC 25 |
Feb 09 11:04:59 PM UTC 25 |
9209374358 ps |
T1212 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3267851372 |
|
|
Feb 09 11:01:10 PM UTC 25 |
Feb 09 11:05:35 PM UTC 25 |
3048169177 ps |
T1213 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.808147078 |
|
|
Feb 09 10:03:42 PM UTC 25 |
Feb 09 11:06:15 PM UTC 25 |
39027733120 ps |
T1214 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.83769607 |
|
|
Feb 09 11:01:52 PM UTC 25 |
Feb 09 11:06:36 PM UTC 25 |
2684908993 ps |
T1215 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_sw_mode.2808463373 |
|
|
Feb 09 10:25:09 PM UTC 25 |
Feb 09 11:06:45 PM UTC 25 |
10694579728 ps |
T1216 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_multistream.3337998890 |
|
|
Feb 09 10:31:20 PM UTC 25 |
Feb 09 11:06:52 PM UTC 25 |
8407108380 ps |
T1217 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.962866403 |
|
|
Feb 09 11:01:59 PM UTC 25 |
Feb 09 11:07:27 PM UTC 25 |
3806957809 ps |
T1218 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_outputs.4229657897 |
|
|
Feb 09 10:49:36 PM UTC 25 |
Feb 09 11:07:49 PM UTC 25 |
7829049096 ps |
T1219 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_scrambling_smoketest.3379735099 |
|
|
Feb 09 11:04:02 PM UTC 25 |
Feb 09 11:07:55 PM UTC 25 |
2717562688 ps |
T249 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_aes.2147926635 |
|
|
Feb 09 10:31:51 PM UTC 25 |
Feb 09 11:08:13 PM UTC 25 |
11908021192 ps |
T1220 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1792144514 |
|
|
Feb 09 10:59:16 PM UTC 25 |
Feb 09 11:09:55 PM UTC 25 |
5472511542 ps |
T1221 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_volatile_raw_unlock.2890531152 |
|
|
Feb 09 11:08:07 PM UTC 25 |
Feb 09 11:10:05 PM UTC 25 |
2732545427 ps |
T1222 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.4219804825 |
|
|
Feb 09 10:31:21 PM UTC 25 |
Feb 09 11:10:46 PM UTC 25 |
12820539702 ps |
T1223 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1809644892 |
|
|
Feb 09 11:01:59 PM UTC 25 |
Feb 09 11:11:42 PM UTC 25 |
4109716856 ps |
T670 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_raw_unlock.3537790600 |
|
|
Feb 09 11:08:10 PM UTC 25 |
Feb 09 11:11:44 PM UTC 25 |
4359369518 ps |
T394 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_crash_alert.1799255899 |
|
|
Feb 09 10:58:33 PM UTC 25 |
Feb 09 11:12:28 PM UTC 25 |
6207740750 ps |
T1224 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_idle_load.3472300952 |
|
|
Feb 09 11:01:58 PM UTC 25 |
Feb 09 11:13:12 PM UTC 25 |
4183132946 ps |
T1225 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_smoketest.4243151284 |
|
|
Feb 09 11:08:57 PM UTC 25 |
Feb 09 11:14:05 PM UTC 25 |
3222543932 ps |
T1226 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_sleep_load.936923737 |
|
|
Feb 09 11:02:13 PM UTC 25 |
Feb 09 11:14:17 PM UTC 25 |
10377262362 ps |
T1227 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_smoketest.1221332956 |
|
|
Feb 09 11:08:52 PM UTC 25 |
Feb 09 11:14:43 PM UTC 25 |
3584392612 ps |
T1228 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_smoketest.4139885770 |
|
|
Feb 09 11:10:32 PM UTC 25 |
Feb 09 11:15:01 PM UTC 25 |
2715999096 ps |
T126 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.165533296 |
|
|
Feb 09 10:52:05 PM UTC 25 |
Feb 09 11:15:29 PM UTC 25 |
23382321184 ps |
T1229 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_smoketest.1629624913 |
|
|
Feb 09 11:10:44 PM UTC 25 |
Feb 09 11:15:59 PM UTC 25 |
3406369968 ps |
T1230 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3185489220 |
|
|
Feb 09 10:12:02 PM UTC 25 |
Feb 09 11:16:01 PM UTC 25 |
20643685087 ps |
T1231 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.602672583 |
|
|
Feb 09 10:56:45 PM UTC 25 |
Feb 09 11:17:06 PM UTC 25 |
10138358653 ps |
T1232 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio_smoketest.3887552891 |
|
|
Feb 09 11:12:32 PM UTC 25 |
Feb 09 11:17:21 PM UTC 25 |
2188895663 ps |
T1233 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_keymgr_functest.721042194 |
|
|
Feb 09 11:08:53 PM UTC 25 |
Feb 09 11:17:42 PM UTC 25 |
3877017940 ps |
T1234 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_smoketest.412199540 |
|
|
Feb 09 11:13:04 PM UTC 25 |
Feb 09 11:17:52 PM UTC 25 |
2635025606 ps |
T231 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_mem_access.1254839865 |
|
|
Feb 09 10:48:51 PM UTC 25 |
Feb 09 11:18:45 PM UTC 25 |
14230613880 ps |
T1235 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_smoketest.1147793717 |
|
|
Feb 09 11:12:32 PM UTC 25 |
Feb 09 11:19:26 PM UTC 25 |
3388738740 ps |
T1236 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_smoketest.3855521180 |
|
|
Feb 09 11:14:52 PM UTC 25 |
Feb 09 11:19:31 PM UTC 25 |
2848604350 ps |
T1237 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_smoketest.3012239489 |
|
|
Feb 09 11:16:47 PM UTC 25 |
Feb 09 11:20:33 PM UTC 25 |
3376879220 ps |
T1238 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_smoketest.2891880533 |
|
|
Feb 09 11:16:47 PM UTC 25 |
Feb 09 11:21:14 PM UTC 25 |
2848600252 ps |
T1239 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.4073576646 |
|
|
Feb 09 10:38:11 PM UTC 25 |
Feb 09 11:21:31 PM UTC 25 |
21676485960 ps |
T1240 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1017762714 |
|
|
Feb 09 10:59:39 PM UTC 25 |
Feb 09 11:21:43 PM UTC 25 |
7730082276 ps |
T1241 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_smoketest.2691185280 |
|
|
Feb 09 11:16:09 PM UTC 25 |
Feb 09 11:21:55 PM UTC 25 |
3591528552 ps |
T1242 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_plic_smoketest.1898189811 |
|
|
Feb 09 11:15:39 PM UTC 25 |
Feb 09 11:22:06 PM UTC 25 |
2713483056 ps |
T1243 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_smoketest.747624529 |
|
|
Feb 09 11:11:25 PM UTC 25 |
Feb 09 11:22:29 PM UTC 25 |
3881532760 ps |
T1244 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_smoketest.2313569229 |
|
|
Feb 09 11:14:56 PM UTC 25 |
Feb 09 11:23:04 PM UTC 25 |
5881005852 ps |
T1245 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_smoketest.814461532 |
|
|
Feb 09 11:17:46 PM UTC 25 |
Feb 09 11:23:07 PM UTC 25 |
2868930480 ps |
T1246 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.550949163 |
|
|
Feb 09 11:01:48 PM UTC 25 |
Feb 09 11:23:14 PM UTC 25 |
7638715859 ps |
T1247 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.950317882 |
|
|
Feb 09 11:15:20 PM UTC 25 |
Feb 09 11:24:52 PM UTC 25 |
6920266000 ps |
T1248 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2237746080 |
|
|
Feb 09 11:03:40 PM UTC 25 |
Feb 09 11:25:07 PM UTC 25 |
6211053834 ps |
T456 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4224748141 |
|
|
Feb 09 10:51:23 PM UTC 25 |
Feb 09 11:26:30 PM UTC 25 |
21233280720 ps |
T763 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_all_escalation_resets.1001252497 |
|
|
Feb 09 11:18:03 PM UTC 25 |
Feb 09 11:26:43 PM UTC 25 |
4898990720 ps |
T238 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.4026283714 |
|
|
Feb 09 05:35:04 PM UTC 25 |
Feb 09 11:28:38 PM UTC 25 |
82790847852 ps |
T130 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_virus.2074210899 |
|
|
Feb 09 11:03:57 PM UTC 25 |
Feb 09 11:31:09 PM UTC 25 |
5908985960 ps |
T708 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2041673165 |
|
|
Feb 09 11:22:46 PM UTC 25 |
Feb 09 11:31:12 PM UTC 25 |
4176376440 ps |
T1249 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx2.2280621290 |
|
|
Feb 09 11:20:18 PM UTC 25 |
Feb 09 11:31:48 PM UTC 25 |
3827021384 ps |
T1250 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx3.2574589905 |
|
|
Feb 09 11:20:18 PM UTC 25 |
Feb 09 11:32:00 PM UTC 25 |
4312866120 ps |
T1251 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.1960879707 |
|
|
Feb 09 09:17:13 PM UTC 25 |
Feb 09 11:32:06 PM UTC 25 |
26919214988 ps |
T1252 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx1.3938867419 |
|
|
Feb 09 11:19:25 PM UTC 25 |
Feb 09 11:32:13 PM UTC 25 |
4441998804 ps |
T1253 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx.118797191 |
|
|
Feb 09 11:18:32 PM UTC 25 |
Feb 09 11:32:29 PM UTC 25 |
4179745816 ps |
T1254 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_lc_ctrl_transition.2999565471 |
|
|
Feb 09 11:22:21 PM UTC 25 |
Feb 09 11:32:29 PM UTC 25 |
7330462556 ps |
T1255 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_rma.522523017 |
|
|
Feb 09 11:25:25 PM UTC 25 |
Feb 09 11:32:41 PM UTC 25 |
4578590413 ps |
T302 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.1212939796 |
|
|
Feb 09 11:18:31 PM UTC 25 |
Feb 09 11:32:44 PM UTC 25 |
5087951020 ps |
T1256 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1807911837 |
|
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Feb 09 11:22:44 PM UTC 25 |
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T1257 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_testunlock0.2379426369 |
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Feb 09 11:23:52 PM UTC 25 |
Feb 09 11:35:49 PM UTC 25 |
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T1258 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.3945635052 |
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Feb 09 11:13:51 PM UTC 25 |
Feb 09 11:36:38 PM UTC 25 |
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T1259 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.608012405 |
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Feb 09 10:14:23 PM UTC 25 |
Feb 09 11:38:11 PM UTC 25 |
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T1260 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1950049870 |
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Feb 09 10:14:24 PM UTC 25 |
Feb 09 11:38:19 PM UTC 25 |
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T168 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.288146841 |
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Feb 09 11:23:56 PM UTC 25 |
Feb 09 11:38:35 PM UTC 25 |
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T1261 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.3049844814 |
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Feb 09 11:23:55 PM UTC 25 |
Feb 09 11:39:18 PM UTC 25 |
7596747340 ps |
T1262 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.987441341 |
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Feb 09 11:38:45 PM UTC 25 |
Feb 09 11:41:41 PM UTC 25 |
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T687 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2630575109 |
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Feb 09 11:33:50 PM UTC 25 |
Feb 09 11:42:03 PM UTC 25 |
4019455320 ps |