| T1082 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx2.1194721220 |
|
|
Oct 15 08:18:36 PM UTC 24 |
Oct 15 08:28:32 PM UTC 24 |
4117197664 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.104767758 |
|
|
Oct 15 08:16:17 PM UTC 24 |
Oct 15 08:28:34 PM UTC 24 |
4986374184 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.1338689358 |
|
|
Oct 15 08:20:39 PM UTC 24 |
Oct 15 08:28:38 PM UTC 24 |
3940066490 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx3.1933525515 |
|
|
Oct 15 08:19:00 PM UTC 24 |
Oct 15 08:28:38 PM UTC 24 |
4457708700 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_rand_baudrate.67740227 |
|
|
Oct 15 08:20:17 PM UTC 24 |
Oct 15 08:28:40 PM UTC 24 |
3815670912 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.41744117 |
|
|
Oct 15 08:20:35 PM UTC 24 |
Oct 15 08:29:23 PM UTC 24 |
3636416619 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx1.1335708534 |
|
|
Oct 15 08:19:19 PM UTC 24 |
Oct 15 08:29:31 PM UTC 24 |
4447490232 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx.2875580090 |
|
|
Oct 15 08:20:04 PM UTC 24 |
Oct 15 08:29:32 PM UTC 24 |
4186926724 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init_reduced_freq.2762699080 |
|
|
Oct 15 08:01:48 PM UTC 24 |
Oct 15 08:31:14 PM UTC 24 |
20346799269 ps |
| T41 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.1196680088 |
|
|
Oct 15 08:25:19 PM UTC 24 |
Oct 15 08:32:41 PM UTC 24 |
4046627264 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through.1366520750 |
|
|
Oct 15 08:23:11 PM UTC 24 |
Oct 15 08:32:51 PM UTC 24 |
6683531962 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.2997783656 |
|
|
Oct 15 07:01:30 PM UTC 24 |
Oct 15 08:33:02 PM UTC 24 |
42195556639 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_entropy.3991144749 |
|
|
Oct 15 08:29:43 PM UTC 24 |
Oct 15 08:33:37 PM UTC 24 |
2387083472 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.4186710271 |
|
|
Oct 15 08:20:07 PM UTC 24 |
Oct 15 08:33:45 PM UTC 24 |
5267832108 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_smoketest.2716945987 |
|
|
Oct 15 08:10:47 PM UTC 24 |
Oct 15 08:33:48 PM UTC 24 |
7411249888 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3075111012 |
|
|
Oct 15 08:20:36 PM UTC 24 |
Oct 15 08:33:59 PM UTC 24 |
5134494384 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through_collision.3850677184 |
|
|
Oct 15 08:24:45 PM UTC 24 |
Oct 15 08:34:23 PM UTC 24 |
4973515013 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1745021381 |
|
|
Oct 15 08:26:59 PM UTC 24 |
Oct 15 08:34:44 PM UTC 24 |
5327222444 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3477353429 |
|
|
Oct 15 07:42:07 PM UTC 24 |
Oct 15 08:34:44 PM UTC 24 |
28176631300 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx.1181184083 |
|
|
Oct 15 08:20:36 PM UTC 24 |
Oct 15 08:35:00 PM UTC 24 |
4534263064 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1520793238 |
|
|
Oct 15 08:28:35 PM UTC 24 |
Oct 15 08:35:02 PM UTC 24 |
3561298348 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.667466296 |
|
|
Oct 15 07:21:59 PM UTC 24 |
Oct 15 08:35:13 PM UTC 24 |
17079042360 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops.3917617988 |
|
|
Oct 15 08:25:40 PM UTC 24 |
Oct 15 08:35:24 PM UTC 24 |
3702597650 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.698810513 |
|
|
Oct 15 08:29:47 PM UTC 24 |
Oct 15 08:35:27 PM UTC 24 |
3426346576 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.22062186 |
|
|
Oct 15 08:33:31 PM UTC 24 |
Oct 15 08:35:42 PM UTC 24 |
2907071833 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2289955101 |
|
|
Oct 15 07:21:58 PM UTC 24 |
Oct 15 08:35:44 PM UTC 24 |
18591891567 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1394989935 |
|
|
Oct 15 08:33:43 PM UTC 24 |
Oct 15 08:37:35 PM UTC 24 |
3053179216 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3210524471 |
|
|
Oct 15 08:36:30 PM UTC 24 |
Oct 15 08:38:27 PM UTC 24 |
2694037406 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2581442935 |
|
|
Oct 15 08:26:08 PM UTC 24 |
Oct 15 08:38:48 PM UTC 24 |
4345967805 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2668242039 |
|
|
Oct 15 08:36:52 PM UTC 24 |
Oct 15 08:39:35 PM UTC 24 |
2272898507 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2561815443 |
|
|
Oct 15 08:20:17 PM UTC 24 |
Oct 15 08:39:45 PM UTC 24 |
9195672256 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3190372291 |
|
|
Oct 15 08:34:52 PM UTC 24 |
Oct 15 08:40:23 PM UTC 24 |
3169554437 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_rst.3338372384 |
|
|
Oct 15 08:36:52 PM UTC 24 |
Oct 15 08:41:02 PM UTC 24 |
3131996710 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pwm_pulses.3436380171 |
|
|
Oct 15 08:19:32 PM UTC 24 |
Oct 15 08:41:31 PM UTC 24 |
9810738848 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1725335134 |
|
|
Oct 15 08:30:26 PM UTC 24 |
Oct 15 08:41:41 PM UTC 24 |
4859595376 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_descrambling.3354395872 |
|
|
Oct 15 08:33:53 PM UTC 24 |
Oct 15 08:42:01 PM UTC 24 |
3856151452 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access.2777416890 |
|
|
Oct 15 08:27:00 PM UTC 24 |
Oct 15 08:42:38 PM UTC 24 |
5384512112 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_self_hash.2662292477 |
|
|
Oct 15 06:32:18 PM UTC 24 |
Oct 15 08:42:57 PM UTC 24 |
26212992072 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3887743831 |
|
|
Oct 15 08:37:00 PM UTC 24 |
Oct 15 08:43:31 PM UTC 24 |
8567784733 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.875985135 |
|
|
Oct 15 08:38:15 PM UTC 24 |
Oct 15 08:43:50 PM UTC 24 |
3823343792 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.3040524989 |
|
|
Oct 15 05:11:22 PM UTC 24 |
Oct 15 08:44:51 PM UTC 24 |
41143602472 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.268245474 |
|
|
Oct 15 08:27:55 PM UTC 24 |
Oct 15 08:45:05 PM UTC 24 |
5832568623 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_transition.2835964273 |
|
|
Oct 15 08:34:49 PM UTC 24 |
Oct 15 08:45:11 PM UTC 24 |
6883003778 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1141728656 |
|
|
Oct 15 08:29:46 PM UTC 24 |
Oct 15 08:46:28 PM UTC 24 |
6291848657 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2591385794 |
|
|
Oct 15 08:20:03 PM UTC 24 |
Oct 15 08:46:37 PM UTC 24 |
7544043784 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_req.2571016122 |
|
|
Oct 15 08:36:49 PM UTC 24 |
Oct 15 08:46:53 PM UTC 24 |
5060046130 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_cpu_info.1913041150 |
|
|
Oct 15 08:36:54 PM UTC 24 |
Oct 15 08:46:59 PM UTC 24 |
4924210840 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2396276431 |
|
|
Oct 15 08:30:26 PM UTC 24 |
Oct 15 08:47:38 PM UTC 24 |
8941622532 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.3564526793 |
|
|
Oct 15 07:07:21 PM UTC 24 |
Oct 15 08:47:48 PM UTC 24 |
50949084505 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3835380697 |
|
|
Oct 15 08:43:36 PM UTC 24 |
Oct 15 08:48:55 PM UTC 24 |
3001742416 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_irq.688242772 |
|
|
Oct 15 08:44:31 PM UTC 24 |
Oct 15 08:48:55 PM UTC 24 |
3012800898 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.4135374450 |
|
|
Oct 15 08:30:25 PM UTC 24 |
Oct 15 08:49:30 PM UTC 24 |
7403602446 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.500057067 |
|
|
Oct 15 08:42:39 PM UTC 24 |
Oct 15 08:49:56 PM UTC 24 |
7861740736 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2578613357 |
|
|
Oct 15 08:44:08 PM UTC 24 |
Oct 15 08:51:12 PM UTC 24 |
5458970992 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1121617830 |
|
|
Oct 15 08:41:43 PM UTC 24 |
Oct 15 08:52:26 PM UTC 24 |
7383450264 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2193206126 |
|
|
Oct 15 08:42:20 PM UTC 24 |
Oct 15 08:52:39 PM UTC 24 |
7077715606 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2986258223 |
|
|
Oct 15 08:31:56 PM UTC 24 |
Oct 15 08:52:45 PM UTC 24 |
8276956014 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3654006103 |
|
|
Oct 15 08:45:58 PM UTC 24 |
Oct 15 08:52:46 PM UTC 24 |
3501771640 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prodend.1394218685 |
|
|
Oct 15 08:35:06 PM UTC 24 |
Oct 15 08:53:11 PM UTC 24 |
9062372856 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.548766947 |
|
|
Oct 15 08:47:45 PM UTC 24 |
Oct 15 08:53:28 PM UTC 24 |
3702496600 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2017548614 |
|
|
Oct 15 08:47:19 PM UTC 24 |
Oct 15 08:54:10 PM UTC 24 |
3869286232 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2785331598 |
|
|
Oct 15 08:46:09 PM UTC 24 |
Oct 15 08:55:50 PM UTC 24 |
6211228220 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1954144134 |
|
|
Oct 15 08:45:59 PM UTC 24 |
Oct 15 08:56:55 PM UTC 24 |
4393296992 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc.1334553023 |
|
|
Oct 15 08:54:05 PM UTC 24 |
Oct 15 08:58:07 PM UTC 24 |
3223697832 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2811670115 |
|
|
Oct 15 08:39:08 PM UTC 24 |
Oct 15 08:58:08 PM UTC 24 |
8995554646 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_rma.762279229 |
|
|
Oct 15 07:07:50 PM UTC 24 |
Oct 15 08:58:11 PM UTC 24 |
45994222664 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en.2543159552 |
|
|
Oct 15 08:54:09 PM UTC 24 |
Oct 15 08:58:42 PM UTC 24 |
2449053645 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1492880976 |
|
|
Oct 15 08:49:48 PM UTC 24 |
Oct 15 08:58:48 PM UTC 24 |
5218532958 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_dev.1789134167 |
|
|
Oct 15 07:06:45 PM UTC 24 |
Oct 15 08:59:11 PM UTC 24 |
48180544716 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3525129185 |
|
|
Oct 15 08:48:30 PM UTC 24 |
Oct 15 08:59:18 PM UTC 24 |
8005860440 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3758469720 |
|
|
Oct 15 08:41:05 PM UTC 24 |
Oct 15 08:59:32 PM UTC 24 |
9423433860 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2346811313 |
|
|
Oct 15 08:49:48 PM UTC 24 |
Oct 15 08:59:43 PM UTC 24 |
4594253800 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_idle.1138139091 |
|
|
Oct 15 08:54:46 PM UTC 24 |
Oct 15 09:00:40 PM UTC 24 |
2780589500 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2374309467 |
|
|
Oct 15 08:50:10 PM UTC 24 |
Oct 15 09:00:43 PM UTC 24 |
19002559604 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2678949716 |
|
|
Oct 15 08:48:31 PM UTC 24 |
Oct 15 09:00:43 PM UTC 24 |
6819496100 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_test_unlocked0.27041677 |
|
|
Oct 15 08:07:47 PM UTC 24 |
Oct 15 09:01:43 PM UTC 24 |
11454954264 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_mem_scramble.2625949837 |
|
|
Oct 15 08:53:49 PM UTC 24 |
Oct 15 09:02:45 PM UTC 24 |
3673885472 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2751532065 |
|
|
Oct 15 08:39:26 PM UTC 24 |
Oct 15 09:02:59 PM UTC 24 |
9912191042 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_masking_off.1800968401 |
|
|
Oct 15 08:56:31 PM UTC 24 |
Oct 15 09:03:01 PM UTC 24 |
3203655046 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_otbn.3350366029 |
|
|
Oct 15 07:36:45 PM UTC 24 |
Oct 15 09:03:09 PM UTC 24 |
16226738840 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_test.719085772 |
|
|
Oct 15 08:57:23 PM UTC 24 |
Oct 15 09:03:34 PM UTC 24 |
3042041772 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_kat_test.2435125418 |
|
|
Oct 15 09:00:41 PM UTC 24 |
Oct 15 09:04:14 PM UTC 24 |
2647350680 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_entropy.910450109 |
|
|
Oct 15 09:00:27 PM UTC 24 |
Oct 15 09:05:52 PM UTC 24 |
2759801112 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1117293690 |
|
|
Oct 15 08:59:57 PM UTC 24 |
Oct 15 09:06:04 PM UTC 24 |
3683749906 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_entropy.2000044016 |
|
|
Oct 15 09:00:27 PM UTC 24 |
Oct 15 09:06:24 PM UTC 24 |
3468338680 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_timeout.697010080 |
|
|
Oct 15 08:59:22 PM UTC 24 |
Oct 15 09:06:30 PM UTC 24 |
3783807188 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_escalation.3382316397 |
|
|
Oct 15 08:57:36 PM UTC 24 |
Oct 15 09:06:46 PM UTC 24 |
5429585020 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1892876902 |
|
|
Oct 15 09:04:15 PM UTC 24 |
Oct 15 09:07:36 PM UTC 24 |
2457830184 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1835796023 |
|
|
Oct 15 08:53:53 PM UTC 24 |
Oct 15 09:07:42 PM UTC 24 |
4695966200 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_kat_test.583119950 |
|
|
Oct 15 09:03:58 PM UTC 24 |
Oct 15 09:07:45 PM UTC 24 |
2306305668 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init.2185495789 |
|
|
Oct 15 08:29:09 PM UTC 24 |
Oct 15 09:07:46 PM UTC 24 |
20598006752 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_randomness.3313057386 |
|
|
Oct 15 08:50:32 PM UTC 24 |
Oct 15 09:07:51 PM UTC 24 |
6088319632 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_output.3049723390 |
|
|
Oct 15 08:06:51 PM UTC 24 |
Oct 15 09:10:05 PM UTC 24 |
28559443500 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_boot_mode.2598162597 |
|
|
Oct 15 09:01:44 PM UTC 24 |
Oct 15 09:10:11 PM UTC 24 |
2952486360 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_kat.3462120979 |
|
|
Oct 15 09:01:44 PM UTC 24 |
Oct 15 09:10:37 PM UTC 24 |
3154815360 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc.2788975551 |
|
|
Oct 15 09:06:48 PM UTC 24 |
Oct 15 09:11:00 PM UTC 24 |
2420286928 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1036937769 |
|
|
Oct 15 09:04:11 PM UTC 24 |
Oct 15 09:11:22 PM UTC 24 |
4298936620 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en.3792938360 |
|
|
Oct 15 09:07:12 PM UTC 24 |
Oct 15 09:11:23 PM UTC 24 |
2636103328 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_idle.45925146 |
|
|
Oct 15 09:07:22 PM UTC 24 |
Oct 15 09:11:25 PM UTC 24 |
3055969358 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.1878584718 |
|
|
Oct 15 08:36:59 PM UTC 24 |
Oct 15 09:11:27 PM UTC 24 |
12526121516 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_rnd.2269531550 |
|
|
Oct 15 08:53:49 PM UTC 24 |
Oct 15 09:11:28 PM UTC 24 |
5779076006 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_oneshot.1071028619 |
|
|
Oct 15 09:07:26 PM UTC 24 |
Oct 15 09:12:43 PM UTC 24 |
3111457240 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_exception_c.3906639375 |
|
|
Oct 15 08:07:56 PM UTC 24 |
Oct 15 09:14:02 PM UTC 24 |
14688577319 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_cshake.1243494175 |
|
|
Oct 15 09:11:11 PM UTC 24 |
Oct 15 09:14:40 PM UTC 24 |
2102586128 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1517341959 |
|
|
Oct 15 09:03:53 PM UTC 24 |
Oct 15 09:15:43 PM UTC 24 |
6134007000 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_smoke.1744528226 |
|
|
Oct 15 08:05:14 PM UTC 24 |
Oct 15 09:16:50 PM UTC 24 |
15806753354 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.242435470 |
|
|
Oct 15 08:59:59 PM UTC 24 |
Oct 15 09:16:52 PM UTC 24 |
10356262956 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_idle.415536528 |
|
|
Oct 15 09:12:40 PM UTC 24 |
Oct 15 09:17:03 PM UTC 24 |
2874099346 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_app_rom.3641143767 |
|
|
Oct 15 09:12:44 PM UTC 24 |
Oct 15 09:17:04 PM UTC 24 |
2540263270 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac.3640757634 |
|
|
Oct 15 09:11:39 PM UTC 24 |
Oct 15 09:17:16 PM UTC 24 |
3078211456 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_reset.2929743570 |
|
|
Oct 15 08:47:15 PM UTC 24 |
Oct 15 09:17:46 PM UTC 24 |
25478472688 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_dev.1128343604 |
|
|
Oct 15 08:07:53 PM UTC 24 |
Oct 15 09:17:53 PM UTC 24 |
15524602677 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_auto_mode.268039972 |
|
|
Oct 15 09:01:44 PM UTC 24 |
Oct 15 09:17:57 PM UTC 24 |
4413721864 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1724901543 |
|
|
Oct 15 09:12:40 PM UTC 24 |
Oct 15 09:18:15 PM UTC 24 |
2812375896 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1658037018 |
|
|
Oct 15 08:07:27 PM UTC 24 |
Oct 15 09:19:49 PM UTC 24 |
15164107876 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3903774051 |
|
|
Oct 15 08:08:07 PM UTC 24 |
Oct 15 09:20:38 PM UTC 24 |
16105236516 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_status.1609635184 |
|
|
Oct 15 09:16:22 PM UTC 24 |
Oct 15 09:20:41 PM UTC 24 |
3111862676 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3648390505 |
|
|
Oct 15 08:08:05 PM UTC 24 |
Oct 15 09:20:45 PM UTC 24 |
14897627942 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1519025587 |
|
|
Oct 15 09:12:38 PM UTC 24 |
Oct 15 09:20:49 PM UTC 24 |
3705399568 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.4112899806 |
|
|
Oct 15 08:36:54 PM UTC 24 |
Oct 15 09:20:50 PM UTC 24 |
25671716068 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_outputs.1625357045 |
|
|
Oct 15 09:25:13 PM UTC 24 |
Oct 15 09:41:40 PM UTC 24 |
7162901024 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3882667137 |
|
|
Oct 15 08:00:09 PM UTC 24 |
Oct 15 09:21:07 PM UTC 24 |
25305740031 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rom_ctrl_integrity_check.68048186 |
|
|
Oct 15 09:12:43 PM UTC 24 |
Oct 15 09:21:09 PM UTC 24 |
9128650826 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_execution_main.3653269279 |
|
|
Oct 15 09:13:22 PM UTC 24 |
Oct 15 09:21:47 PM UTC 24 |
7722783320 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.1183200842 |
|
|
Oct 15 07:30:55 PM UTC 24 |
Oct 15 09:22:15 PM UTC 24 |
23201980656 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2572644946 |
|
|
Oct 15 09:13:02 PM UTC 24 |
Oct 15 09:22:38 PM UTC 24 |
5154406750 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_plic_sw_irq.964834255 |
|
|
Oct 15 09:19:09 PM UTC 24 |
Oct 15 09:23:32 PM UTC 24 |
2855375866 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod_end.2447408727 |
|
|
Oct 15 08:06:50 PM UTC 24 |
Oct 15 09:23:56 PM UTC 24 |
15665513264 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod.2055199326 |
|
|
Oct 15 08:08:05 PM UTC 24 |
Oct 15 09:24:01 PM UTC 24 |
16161223934 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_ok.3348929296 |
|
|
Oct 15 08:59:35 PM UTC 24 |
Oct 15 09:24:11 PM UTC 24 |
7619036280 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_rma.369540668 |
|
|
Oct 15 08:08:01 PM UTC 24 |
Oct 15 09:24:31 PM UTC 24 |
14871920056 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1929913340 |
|
|
Oct 15 09:06:45 PM UTC 24 |
Oct 15 09:25:11 PM UTC 24 |
7255102125 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2836522811 |
|
|
Oct 15 09:18:58 PM UTC 24 |
Oct 15 09:25:26 PM UTC 24 |
5166386880 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3892064427 |
|
|
Oct 15 09:19:07 PM UTC 24 |
Oct 15 09:25:28 PM UTC 24 |
5375647994 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3961357005 |
|
|
Oct 15 09:00:22 PM UTC 24 |
Oct 15 09:25:29 PM UTC 24 |
7682310492 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3159055839 |
|
|
Oct 15 09:00:24 PM UTC 24 |
Oct 15 09:25:44 PM UTC 24 |
7265416300 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3222503832 |
|
|
Oct 15 09:14:51 PM UTC 24 |
Oct 15 09:25:52 PM UTC 24 |
8190517066 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1814044314 |
|
|
Oct 15 09:19:08 PM UTC 24 |
Oct 15 09:26:26 PM UTC 24 |
4183115648 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.2164972895 |
|
|
Oct 15 09:15:20 PM UTC 24 |
Oct 15 09:27:02 PM UTC 24 |
6074474418 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs.1776418472 |
|
|
Oct 15 09:06:32 PM UTC 24 |
Oct 15 09:27:09 PM UTC 24 |
6873783876 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1329420398 |
|
|
Oct 15 09:14:51 PM UTC 24 |
Oct 15 09:27:20 PM UTC 24 |
6896103070 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.2736840894 |
|
|
Oct 15 09:18:21 PM UTC 24 |
Oct 15 09:27:50 PM UTC 24 |
4280786168 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2249372431 |
|
|
Oct 15 08:40:29 PM UTC 24 |
Oct 15 09:27:51 PM UTC 24 |
21982654519 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_inject_scramble_seed.3876849537 |
|
|
Oct 15 04:50:32 PM UTC 24 |
Oct 15 09:28:20 PM UTC 24 |
67957306943 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter.998437282 |
|
|
Oct 15 09:24:14 PM UTC 24 |
Oct 15 09:28:34 PM UTC 24 |
2796595605 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.827045481 |
|
|
Oct 15 09:20:30 PM UTC 24 |
Oct 15 09:29:11 PM UTC 24 |
4427778272 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.1927605377 |
|
|
Oct 15 09:24:28 PM UTC 24 |
Oct 15 09:29:14 PM UTC 24 |
4037355099 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3983885698 |
|
|
Oct 15 09:22:17 PM UTC 24 |
Oct 15 09:29:57 PM UTC 24 |
4914481656 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_static_critical.3160851826 |
|
|
Oct 15 08:08:06 PM UTC 24 |
Oct 15 09:30:54 PM UTC 24 |
17663889938 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_reset_frequency.1090995423 |
|
|
Oct 15 09:22:55 PM UTC 24 |
Oct 15 09:31:16 PM UTC 24 |
3953100708 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1142384897 |
|
|
Oct 15 09:22:07 PM UTC 24 |
Oct 15 09:31:24 PM UTC 24 |
5821705403 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2795902542 |
|
|
Oct 15 09:23:18 PM UTC 24 |
Oct 15 09:31:35 PM UTC 24 |
3848020632 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4144677554 |
|
|
Oct 15 09:22:19 PM UTC 24 |
Oct 15 09:31:39 PM UTC 24 |
4179703352 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3151320041 |
|
|
Oct 15 09:22:31 PM UTC 24 |
Oct 15 09:31:46 PM UTC 24 |
3554177860 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_prod.2188592416 |
|
|
Oct 15 09:29:54 PM UTC 24 |
Oct 15 09:31:55 PM UTC 24 |
2414103127 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3138252700 |
|
|
Oct 15 09:22:37 PM UTC 24 |
Oct 15 09:31:59 PM UTC 24 |
5339148560 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.111812432 |
|
|
Oct 15 09:22:40 PM UTC 24 |
Oct 15 09:32:04 PM UTC 24 |
3923045260 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.872858121 |
|
|
Oct 15 09:19:08 PM UTC 24 |
Oct 15 09:32:07 PM UTC 24 |
4695221150 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2535815288 |
|
|
Oct 15 09:22:40 PM UTC 24 |
Oct 15 09:32:33 PM UTC 24 |
4598024688 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.548925751 |
|
|
Oct 15 09:27:06 PM UTC 24 |
Oct 15 09:32:47 PM UTC 24 |
7068396664 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3266644917 |
|
|
Oct 15 09:22:36 PM UTC 24 |
Oct 15 09:33:01 PM UTC 24 |
3691840144 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2196802821 |
|
|
Oct 15 09:27:04 PM UTC 24 |
Oct 15 09:33:09 PM UTC 24 |
4128957308 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_program_error.149268452 |
|
|
Oct 15 09:25:49 PM UTC 24 |
Oct 15 09:33:19 PM UTC 24 |
5426826600 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2329385182 |
|
|
Oct 15 09:27:09 PM UTC 24 |
Oct 15 09:33:33 PM UTC 24 |
5369585816 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_dev.4090896045 |
|
|
Oct 15 09:28:32 PM UTC 24 |
Oct 15 09:33:37 PM UTC 24 |
4087281529 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3201891970 |
|
|
Oct 15 09:27:10 PM UTC 24 |
Oct 15 09:33:41 PM UTC 24 |
5197769696 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3817941680 |
|
|
Oct 15 09:30:35 PM UTC 24 |
Oct 15 09:34:24 PM UTC 24 |
2605915664 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3713948030 |
|
|
Oct 15 09:24:36 PM UTC 24 |
Oct 15 09:34:40 PM UTC 24 |
4478525504 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1964068121 |
|
|
Oct 15 09:29:58 PM UTC 24 |
Oct 15 09:34:48 PM UTC 24 |
2917489908 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2969315128 |
|
|
Oct 15 09:28:07 PM UTC 24 |
Oct 15 09:34:56 PM UTC 24 |
5932676080 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3652343904 |
|
|
Oct 15 09:28:03 PM UTC 24 |
Oct 15 09:35:13 PM UTC 24 |
4474045700 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.2898480671 |
|
|
Oct 15 09:04:54 PM UTC 24 |
Oct 15 09:35:28 PM UTC 24 |
7983317520 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.1149762103 |
|
|
Oct 15 09:32:48 PM UTC 24 |
Oct 15 09:35:40 PM UTC 24 |
3222113979 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3662622199 |
|
|
Oct 15 09:31:35 PM UTC 24 |
Oct 15 09:35:58 PM UTC 24 |
3276333732 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_testunlock0.3215045775 |
|
|
Oct 15 09:28:53 PM UTC 24 |
Oct 15 09:36:05 PM UTC 24 |
4695321478 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_sw_mode.4118054792 |
|
|
Oct 15 09:02:24 PM UTC 24 |
Oct 15 09:36:23 PM UTC 24 |
9481483140 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.2348272035 |
|
|
Oct 15 09:18:55 PM UTC 24 |
Oct 15 09:36:30 PM UTC 24 |
6197494552 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.3977920965 |
|
|
Oct 15 09:29:05 PM UTC 24 |
Oct 15 09:36:45 PM UTC 24 |
5240797168 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_rv_dm_ndm_reset_req.1965324213 |
|
|
Oct 15 09:28:06 PM UTC 24 |
Oct 15 09:36:49 PM UTC 24 |
5363032084 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_multistream.2888486657 |
|
|
Oct 15 09:09:04 PM UTC 24 |
Oct 15 09:36:50 PM UTC 24 |
7181575768 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_kmac.936579708 |
|
|
Oct 15 09:09:09 PM UTC 24 |
Oct 15 09:37:18 PM UTC 24 |
10185259878 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_peri.2355394829 |
|
|
Oct 15 09:19:04 PM UTC 24 |
Oct 15 09:37:26 PM UTC 24 |
10671334626 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3295560691 |
|
|
Oct 15 09:28:36 PM UTC 24 |
Oct 15 09:37:29 PM UTC 24 |
5904152081 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3535010652 |
|
|
Oct 15 09:33:33 PM UTC 24 |
Oct 15 09:37:34 PM UTC 24 |
3181204734 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3394699948 |
|
|
Oct 15 09:35:25 PM UTC 24 |
Oct 15 09:38:39 PM UTC 24 |
2625199877 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_write_clear.2334544197 |
|
|
Oct 15 09:34:58 PM UTC 24 |
Oct 15 09:39:38 PM UTC 24 |
3607070288 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_crash_alert.459142630 |
|
|
Oct 15 09:32:25 PM UTC 24 |
Oct 15 09:39:44 PM UTC 24 |
4688061352 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_mem_access.2349170880 |
|
|
Oct 15 09:24:36 PM UTC 24 |
Oct 15 09:41:28 PM UTC 24 |
13324969756 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_scrambling_smoketest.4025495220 |
|
|
Oct 15 09:38:26 PM UTC 24 |
Oct 15 09:42:14 PM UTC 24 |
2436292912 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_volatile_raw_unlock.761765319 |
|
|
Oct 15 09:40:01 PM UTC 24 |
Oct 15 09:42:25 PM UTC 24 |
1913254293 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3692209618 |
|
|
Oct 15 09:36:37 PM UTC 24 |
Oct 15 09:42:31 PM UTC 24 |
3890206239 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_smoketest.3567051528 |
|
|
Oct 15 09:40:30 PM UTC 24 |
Oct 15 09:44:12 PM UTC 24 |
2041166140 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_raw_unlock.2049170345 |
|
|
Oct 15 09:39:25 PM UTC 24 |
Oct 15 09:44:29 PM UTC 24 |
5894782827 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_sleep_load.2256633699 |
|
|
Oct 15 09:36:39 PM UTC 24 |
Oct 15 09:44:40 PM UTC 24 |
11277817382 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_smoketest.2500997072 |
|
|
Oct 15 09:39:59 PM UTC 24 |
Oct 15 09:44:44 PM UTC 24 |
3255358376 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3452109691 |
|
|
Oct 15 09:34:58 PM UTC 24 |
Oct 15 09:44:47 PM UTC 24 |
4155359848 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_smoketest.661682894 |
|
|
Oct 15 09:39:56 PM UTC 24 |
Oct 15 09:45:07 PM UTC 24 |
2948182372 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1323510116 |
|
|
Oct 15 09:26:51 PM UTC 24 |
Oct 15 09:45:14 PM UTC 24 |
24249682254 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_smoketest.591592760 |
|
|
Oct 15 09:40:27 PM UTC 24 |
Oct 15 09:46:12 PM UTC 24 |
2699968360 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1834298338 |
|
|
Oct 15 09:33:35 PM UTC 24 |
Oct 15 09:46:54 PM UTC 24 |
4604149299 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_idle_load.3896393749 |
|
|
Oct 15 09:36:10 PM UTC 24 |
Oct 15 09:47:16 PM UTC 24 |
4423372482 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_keymgr_functest.821237147 |
|
|
Oct 15 09:39:35 PM UTC 24 |
Oct 15 09:48:05 PM UTC 24 |
4356290550 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio_smoketest.3946220750 |
|
|
Oct 15 09:42:20 PM UTC 24 |
Oct 15 09:48:19 PM UTC 24 |
2816232778 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_smoketest.3102411752 |
|
|
Oct 15 09:43:25 PM UTC 24 |
Oct 15 09:48:25 PM UTC 24 |
2578315500 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3921238665 |
|
|
Oct 15 08:02:11 PM UTC 24 |
Oct 15 09:48:47 PM UTC 24 |
30039378415 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_smoketest.2759492065 |
|
|
Oct 15 09:43:23 PM UTC 24 |
Oct 15 09:49:03 PM UTC 24 |
3402705898 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_plic_smoketest.220322266 |
|
|
Oct 15 09:45:57 PM UTC 24 |
Oct 15 09:49:24 PM UTC 24 |
2527972632 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_smoketest.171922799 |
|
|
Oct 15 09:46:01 PM UTC 24 |
Oct 15 09:49:31 PM UTC 24 |
2741284056 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_smoketest.360450667 |
|
|
Oct 15 09:43:24 PM UTC 24 |
Oct 15 09:50:04 PM UTC 24 |
3371608960 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_aes.3606728524 |
|
|
Oct 15 09:10:58 PM UTC 24 |
Oct 15 09:50:50 PM UTC 24 |
10792577848 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_smoketest.2156800187 |
|
|
Oct 15 09:45:59 PM UTC 24 |
Oct 15 09:50:58 PM UTC 24 |
3275528560 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.181338636 |
|
|
Oct 15 09:45:26 PM UTC 24 |
Oct 15 09:51:35 PM UTC 24 |
5539268550 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_smoketest.1205114775 |
|
|
Oct 15 09:46:06 PM UTC 24 |
Oct 15 09:51:43 PM UTC 24 |
3444471420 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_smoketest.2220271027 |
|
|
Oct 15 09:42:17 PM UTC 24 |
Oct 15 09:52:04 PM UTC 24 |
3697818766 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_smoketest.2438094290 |
|
|
Oct 15 09:46:05 PM UTC 24 |
Oct 15 09:52:08 PM UTC 24 |
3060020736 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.988814062 |
|
|
Oct 15 09:33:35 PM UTC 24 |
Oct 15 09:52:50 PM UTC 24 |
7654132027 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2044727302 |
|
|
Oct 15 08:47:44 PM UTC 24 |
Oct 15 09:52:50 PM UTC 24 |
20599248792 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_smoketest.3467391004 |
|
|
Oct 15 09:44:52 PM UTC 24 |
Oct 15 09:52:53 PM UTC 24 |
5894210230 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_all_escalation_resets.2685949889 |
|
|
Oct 15 09:46:55 PM UTC 24 |
Oct 15 09:55:50 PM UTC 24 |
4153629464 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.187148891 |
|
|
Oct 15 09:26:54 PM UTC 24 |
Oct 15 09:56:06 PM UTC 24 |
21498766300 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_testunlock0.3030275514 |
|
|
Oct 15 09:52:16 PM UTC 24 |
Oct 15 09:56:11 PM UTC 24 |
3031587769 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2410507854 |
|
|
Oct 15 09:36:25 PM UTC 24 |
Oct 15 09:56:38 PM UTC 24 |
6162698570 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx3.350124592 |
|
|
Oct 15 09:49:12 PM UTC 24 |
Oct 15 09:57:52 PM UTC 24 |
4715695374 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.4166187486 |
|
|
Oct 15 09:50:56 PM UTC 24 |
Oct 15 09:58:01 PM UTC 24 |
3275737946 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3579404017 |
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|
Oct 15 09:50:56 PM UTC 24 |
Oct 15 09:59:40 PM UTC 24 |
6966436760 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.3895639081 |
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|
Oct 15 09:47:36 PM UTC 24 |
Oct 15 10:00:05 PM UTC 24 |
4984185088 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx.2299101165 |
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|
Oct 15 09:47:58 PM UTC 24 |
Oct 15 10:00:07 PM UTC 24 |
3940336300 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx2.2327635400 |
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|
Oct 15 09:49:12 PM UTC 24 |
Oct 15 10:00:25 PM UTC 24 |
4677781460 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.2335503721 |
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|
Oct 15 09:43:23 PM UTC 24 |
Oct 15 10:00:32 PM UTC 24 |
5250353462 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.2400058332 |
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|
Oct 15 09:49:25 PM UTC 24 |
Oct 15 10:00:34 PM UTC 24 |
4985638152 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx1.1491452552 |
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|
Oct 15 09:49:08 PM UTC 24 |
Oct 15 10:01:08 PM UTC 24 |
4742071006 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.3184614360 |
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Oct 15 09:51:42 PM UTC 24 |
Oct 15 10:02:21 PM UTC 24 |
8116057624 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3103306937 |
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|
Oct 15 08:51:54 PM UTC 24 |
Oct 15 10:02:44 PM UTC 24 |
17012092716 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.4076217586 |
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|
Oct 15 09:53:54 PM UTC 24 |
Oct 15 10:02:47 PM UTC 24 |
4659896014 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3482463737 |
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|
Oct 15 09:35:55 PM UTC 24 |
Oct 15 10:03:35 PM UTC 24 |
9173251127 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_virus.438911153 |
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|
Oct 15 09:37:08 PM UTC 24 |
Oct 15 10:04:24 PM UTC 24 |
5720533270 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_testunlock0.762142353 |
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|
Oct 15 10:01:41 PM UTC 24 |
Oct 15 10:04:55 PM UTC 24 |
2892907850 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_rma.228436932 |
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|
Oct 15 09:52:41 PM UTC 24 |
Oct 15 10:05:16 PM UTC 24 |
7121206561 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.4020269557 |
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|
Oct 15 09:35:00 PM UTC 24 |
Oct 15 10:05:49 PM UTC 24 |
22453655243 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_lc_ctrl_transition.569140879 |
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|
Oct 15 09:50:15 PM UTC 24 |
Oct 15 10:06:20 PM UTC 24 |
12466527904 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.2605538637 |
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|
Oct 15 09:53:55 PM UTC 24 |
Oct 15 10:06:30 PM UTC 24 |
4583735372 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.1696730152 |
|
|
Oct 15 09:56:58 PM UTC 24 |
Oct 15 10:06:37 PM UTC 24 |
3802623620 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2088096342 |
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|
Oct 15 10:01:24 PM UTC 24 |
Oct 15 10:06:44 PM UTC 24 |
3125880768 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.1020244969 |
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|
Oct 15 09:57:19 PM UTC 24 |
Oct 15 10:07:03 PM UTC 24 |
3884604240 ps |
| T1265 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.2083323245 |
|
|
Oct 15 10:01:24 PM UTC 24 |
Oct 15 10:07:13 PM UTC 24 |
4262182782 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.604316447 |
|
|
Oct 15 09:53:55 PM UTC 24 |
Oct 15 10:07:18 PM UTC 24 |
5146830496 ps |
| T1266 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.544490305 |
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|
Oct 15 09:58:46 PM UTC 24 |
Oct 15 10:07:20 PM UTC 24 |
4201287221 ps |
| T1267 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.409720072 |
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|
Oct 15 09:56:58 PM UTC 24 |
Oct 15 10:07:25 PM UTC 24 |
4267555380 ps |
| T1268 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.2831816919 |
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|
Oct 15 10:02:54 PM UTC 24 |
Oct 15 10:07:43 PM UTC 24 |
3557535631 ps |
| T1269 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.301399381 |
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|
Oct 15 09:56:29 PM UTC 24 |
Oct 15 10:07:43 PM UTC 24 |
4446459144 ps |