| T1428 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.1475296853 |
|
|
Oct 15 03:07:58 PM UTC 24 |
Oct 15 03:11:17 PM UTC 24 |
2782313000 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.2326247711 |
|
|
Oct 15 03:02:18 PM UTC 24 |
Oct 15 03:03:51 PM UTC 24 |
1952792966 ps |
| T1429 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.185886403 |
|
|
Oct 15 03:03:41 PM UTC 24 |
Oct 15 03:04:10 PM UTC 24 |
464055961 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2367494868 |
|
|
Oct 15 02:57:55 PM UTC 24 |
Oct 15 03:04:17 PM UTC 24 |
24094111397 ps |
| T1430 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.1223834731 |
|
|
Oct 15 03:03:48 PM UTC 24 |
Oct 15 03:04:18 PM UTC 24 |
248560961 ps |
| T1431 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.963881628 |
|
|
Oct 15 02:55:53 PM UTC 24 |
Oct 15 03:04:20 PM UTC 24 |
55196299051 ps |
| T1432 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.2657891547 |
|
|
Oct 15 03:04:09 PM UTC 24 |
Oct 15 03:04:23 PM UTC 24 |
203102676 ps |
| T1433 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.3480960862 |
|
|
Oct 15 02:59:50 PM UTC 24 |
Oct 15 03:04:27 PM UTC 24 |
14183013279 ps |
| T1434 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3185674912 |
|
|
Oct 15 03:04:19 PM UTC 24 |
Oct 15 03:04:29 PM UTC 24 |
36275348 ps |
| T1435 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.2126712918 |
|
|
Oct 15 02:58:50 PM UTC 24 |
Oct 15 03:04:39 PM UTC 24 |
3628211696 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.3991326269 |
|
|
Oct 15 02:57:13 PM UTC 24 |
Oct 15 03:04:57 PM UTC 24 |
4289407257 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.1921903601 |
|
|
Oct 15 03:01:22 PM UTC 24 |
Oct 15 03:04:57 PM UTC 24 |
3092923750 ps |
| T1436 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.2000384417 |
|
|
Oct 15 03:04:44 PM UTC 24 |
Oct 15 03:05:01 PM UTC 24 |
105486057 ps |
| T1437 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.1669920869 |
|
|
Oct 15 02:57:47 PM UTC 24 |
Oct 15 03:05:04 PM UTC 24 |
43801081415 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3292614211 |
|
|
Oct 15 03:00:36 PM UTC 24 |
Oct 15 03:05:15 PM UTC 24 |
1884692233 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.2934392937 |
|
|
Oct 15 02:59:08 PM UTC 24 |
Oct 15 03:05:21 PM UTC 24 |
4767897981 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.1377558922 |
|
|
Oct 15 02:54:07 PM UTC 24 |
Oct 15 03:05:21 PM UTC 24 |
48418982807 ps |
| T1438 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.2388989641 |
|
|
Oct 15 02:53:17 PM UTC 24 |
Oct 15 03:05:29 PM UTC 24 |
10301633496 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.664015620 |
|
|
Oct 15 03:05:23 PM UTC 24 |
Oct 15 03:05:36 PM UTC 24 |
171685923 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.2822136880 |
|
|
Oct 15 03:04:46 PM UTC 24 |
Oct 15 03:05:41 PM UTC 24 |
534026444 ps |
| T1439 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3199977924 |
|
|
Oct 15 03:05:31 PM UTC 24 |
Oct 15 03:05:45 PM UTC 24 |
55786628 ps |
| T1440 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.3607987900 |
|
|
Oct 15 03:04:37 PM UTC 24 |
Oct 15 03:05:51 PM UTC 24 |
5564277015 ps |
| T1441 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.1896913099 |
|
|
Oct 15 03:05:20 PM UTC 24 |
Oct 15 03:06:04 PM UTC 24 |
1128553512 ps |
| T1442 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1275882981 |
|
|
Oct 15 03:04:43 PM UTC 24 |
Oct 15 03:06:05 PM UTC 24 |
4640368191 ps |
| T1443 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.942017784 |
|
|
Oct 15 03:02:04 PM UTC 24 |
Oct 15 03:06:16 PM UTC 24 |
19897246000 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.2236251780 |
|
|
Oct 15 03:05:28 PM UTC 24 |
Oct 15 03:06:19 PM UTC 24 |
331497998 ps |
| T1444 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.1853703966 |
|
|
Oct 15 02:57:03 PM UTC 24 |
Oct 15 03:06:20 PM UTC 24 |
5525452350 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.1620476636 |
|
|
Oct 15 02:55:07 PM UTC 24 |
Oct 15 03:06:23 PM UTC 24 |
6774397160 ps |
| T1445 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.3568761433 |
|
|
Oct 15 03:06:27 PM UTC 24 |
Oct 15 03:06:38 PM UTC 24 |
157682170 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1569927737 |
|
|
Oct 15 03:03:48 PM UTC 24 |
Oct 15 03:06:39 PM UTC 24 |
565351045 ps |
| T1446 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.240339710 |
|
|
Oct 15 03:06:32 PM UTC 24 |
Oct 15 03:06:41 PM UTC 24 |
42022175 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.4040651302 |
|
|
Oct 15 03:00:39 PM UTC 24 |
Oct 15 03:06:52 PM UTC 24 |
10033806046 ps |
| T1447 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.2493010865 |
|
|
Oct 15 02:51:07 PM UTC 24 |
Oct 15 03:07:03 PM UTC 24 |
12354036356 ps |
| T1448 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.683861576 |
|
|
Oct 15 03:06:43 PM UTC 24 |
Oct 15 03:07:09 PM UTC 24 |
258328856 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.1674754665 |
|
|
Oct 15 03:04:56 PM UTC 24 |
Oct 15 03:07:20 PM UTC 24 |
3391237176 ps |
| T1449 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.1792031676 |
|
|
Oct 15 03:06:48 PM UTC 24 |
Oct 15 03:07:26 PM UTC 24 |
711176377 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.3305589034 |
|
|
Oct 15 02:52:59 PM UTC 24 |
Oct 15 03:07:29 PM UTC 24 |
10860749183 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.597515003 |
|
|
Oct 15 03:05:42 PM UTC 24 |
Oct 15 03:07:30 PM UTC 24 |
1159437737 ps |
| T1450 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1959181662 |
|
|
Oct 15 03:03:43 PM UTC 24 |
Oct 15 03:07:34 PM UTC 24 |
374433953 ps |
| T1451 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.716394922 |
|
|
Oct 15 02:58:57 PM UTC 24 |
Oct 15 03:07:46 PM UTC 24 |
5701010550 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.3151323335 |
|
|
Oct 15 03:07:27 PM UTC 24 |
Oct 15 03:08:05 PM UTC 24 |
1084117682 ps |
| T1452 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.2351145391 |
|
|
Oct 15 03:07:44 PM UTC 24 |
Oct 15 03:08:08 PM UTC 24 |
116610405 ps |
| T1453 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.3626625654 |
|
|
Oct 15 02:55:31 PM UTC 24 |
Oct 15 03:08:15 PM UTC 24 |
7914802139 ps |
| T1454 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.1806612504 |
|
|
Oct 15 03:07:49 PM UTC 24 |
Oct 15 03:08:16 PM UTC 24 |
366826264 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.3315961131 |
|
|
Oct 15 02:56:07 PM UTC 24 |
Oct 15 03:08:21 PM UTC 24 |
52540688256 ps |
| T1455 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.344265545 |
|
|
Oct 15 03:06:46 PM UTC 24 |
Oct 15 03:08:24 PM UTC 24 |
6163782120 ps |
| T1456 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.147724291 |
|
|
Oct 15 03:07:35 PM UTC 24 |
Oct 15 03:08:25 PM UTC 24 |
443381840 ps |
| T1457 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.1408063879 |
|
|
Oct 15 03:06:40 PM UTC 24 |
Oct 15 03:08:28 PM UTC 24 |
9699420480 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.604594041 |
|
|
Oct 15 03:00:27 PM UTC 24 |
Oct 15 03:08:29 PM UTC 24 |
11413100153 ps |
| T1458 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3840724346 |
|
|
Oct 15 03:08:12 PM UTC 24 |
Oct 15 03:08:37 PM UTC 24 |
73488247 ps |
| T1459 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.3675796261 |
|
|
Oct 15 03:04:53 PM UTC 24 |
Oct 15 03:08:49 PM UTC 24 |
16279501801 ps |
| T1460 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.3645437194 |
|
|
Oct 15 03:08:45 PM UTC 24 |
Oct 15 03:08:53 PM UTC 24 |
52313442 ps |
| T1461 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.1993553881 |
|
|
Oct 15 03:08:50 PM UTC 24 |
Oct 15 03:08:58 PM UTC 24 |
51185474 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.3972992667 |
|
|
Oct 15 03:07:04 PM UTC 24 |
Oct 15 03:08:59 PM UTC 24 |
2065806614 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.1175948277 |
|
|
Oct 15 02:38:16 PM UTC 24 |
Oct 15 03:09:11 PM UTC 24 |
14775355353 ps |
| T1462 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.263025203 |
|
|
Oct 15 02:43:27 PM UTC 24 |
Oct 15 03:09:13 PM UTC 24 |
13969947818 ps |
| T1463 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.1224203074 |
|
|
Oct 15 03:07:06 PM UTC 24 |
Oct 15 03:09:14 PM UTC 24 |
7107921411 ps |
| T1464 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.3869254133 |
|
|
Oct 15 03:07:04 PM UTC 24 |
Oct 15 03:09:17 PM UTC 24 |
14032943145 ps |
| T1465 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.1416275778 |
|
|
Oct 15 03:08:55 PM UTC 24 |
Oct 15 03:09:20 PM UTC 24 |
269996949 ps |
| T1466 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.2440466966 |
|
|
Oct 15 03:09:03 PM UTC 24 |
Oct 15 03:09:23 PM UTC 24 |
180847181 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.1326859303 |
|
|
Oct 15 03:05:47 PM UTC 24 |
Oct 15 03:09:29 PM UTC 24 |
4862204122 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.2901552940 |
|
|
Oct 15 03:06:17 PM UTC 24 |
Oct 15 03:09:51 PM UTC 24 |
3167268954 ps |
| T1467 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.1626207478 |
|
|
Oct 15 03:09:38 PM UTC 24 |
Oct 15 03:10:04 PM UTC 24 |
825097666 ps |
| T1468 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.3321242855 |
|
|
Oct 15 03:09:40 PM UTC 24 |
Oct 15 03:10:07 PM UTC 24 |
593908976 ps |
| T1469 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.228557966 |
|
|
Oct 15 03:08:52 PM UTC 24 |
Oct 15 03:10:17 PM UTC 24 |
8706772068 ps |
| T1470 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.2687690473 |
|
|
Oct 15 03:03:47 PM UTC 24 |
Oct 15 03:10:19 PM UTC 24 |
4447582746 ps |
| T1471 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.1768666195 |
|
|
Oct 15 03:09:39 PM UTC 24 |
Oct 15 03:10:20 PM UTC 24 |
1023421842 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.1072926205 |
|
|
Oct 15 03:03:42 PM UTC 24 |
Oct 15 03:10:27 PM UTC 24 |
10622268389 ps |
| T1472 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.3371907125 |
|
|
Oct 15 03:09:45 PM UTC 24 |
Oct 15 03:10:34 PM UTC 24 |
955279891 ps |
| T1473 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.24463891 |
|
|
Oct 15 03:04:50 PM UTC 24 |
Oct 15 03:10:34 PM UTC 24 |
36319454974 ps |
| T1474 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2775235611 |
|
|
Oct 15 03:08:52 PM UTC 24 |
Oct 15 03:10:40 PM UTC 24 |
5313481801 ps |
| T1475 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.3281432823 |
|
|
Oct 15 03:10:46 PM UTC 24 |
Oct 15 03:10:56 PM UTC 24 |
171669713 ps |
| T1476 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.2495715217 |
|
|
Oct 15 03:10:47 PM UTC 24 |
Oct 15 03:10:59 PM UTC 24 |
58186314 ps |
| T1477 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.1131839287 |
|
|
Oct 15 03:02:05 PM UTC 24 |
Oct 15 03:11:06 PM UTC 24 |
27105639399 ps |
| T1478 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.3882765001 |
|
|
Oct 15 03:00:45 PM UTC 24 |
Oct 15 03:11:09 PM UTC 24 |
5779993325 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.224558455 |
|
|
Oct 15 03:09:26 PM UTC 24 |
Oct 15 03:11:10 PM UTC 24 |
1160414685 ps |
| T1479 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.1749868855 |
|
|
Oct 15 03:10:59 PM UTC 24 |
Oct 15 03:11:19 PM UTC 24 |
96537783 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.3311358701 |
|
|
Oct 15 03:07:54 PM UTC 24 |
Oct 15 03:11:21 PM UTC 24 |
2233742539 ps |
| T1480 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.2302898272 |
|
|
Oct 15 03:11:07 PM UTC 24 |
Oct 15 03:11:28 PM UTC 24 |
131147086 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.3436145455 |
|
|
Oct 15 02:43:34 PM UTC 24 |
Oct 15 03:11:32 PM UTC 24 |
14858367659 ps |
| T1481 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.999197778 |
|
|
Oct 15 03:03:46 PM UTC 24 |
Oct 15 03:11:38 PM UTC 24 |
5614611168 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.199508307 |
|
|
Oct 15 03:05:55 PM UTC 24 |
Oct 15 03:11:39 PM UTC 24 |
3739626745 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1301841266 |
|
|
Oct 15 03:05:47 PM UTC 24 |
Oct 15 03:11:48 PM UTC 24 |
5302428171 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.550123788 |
|
|
Oct 15 03:09:15 PM UTC 24 |
Oct 15 03:12:02 PM UTC 24 |
17178106509 ps |
| T1482 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.21919235 |
|
|
Oct 15 03:11:42 PM UTC 24 |
Oct 15 03:12:06 PM UTC 24 |
463071495 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.1066727521 |
|
|
Oct 15 03:04:03 PM UTC 24 |
Oct 15 03:12:06 PM UTC 24 |
5181601960 ps |
| T1483 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.4115358101 |
|
|
Oct 15 03:11:01 PM UTC 24 |
Oct 15 03:12:16 PM UTC 24 |
4605575156 ps |
| T1484 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.2217761246 |
|
|
Oct 15 03:11:44 PM UTC 24 |
Oct 15 03:12:20 PM UTC 24 |
987084607 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2377448916 |
|
|
Oct 15 03:05:04 PM UTC 24 |
Oct 15 03:12:25 PM UTC 24 |
23380199911 ps |
| T1485 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.3719894796 |
|
|
Oct 15 03:11:45 PM UTC 24 |
Oct 15 03:12:32 PM UTC 24 |
324462528 ps |
| T1486 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.614336978 |
|
|
Oct 15 03:11:36 PM UTC 24 |
Oct 15 03:12:43 PM UTC 24 |
2047718073 ps |
| T1487 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.3046839604 |
|
|
Oct 15 03:12:42 PM UTC 24 |
Oct 15 03:12:52 PM UTC 24 |
188139007 ps |
| T1488 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.3255546880 |
|
|
Oct 15 03:12:46 PM UTC 24 |
Oct 15 03:12:53 PM UTC 24 |
50761175 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.222019219 |
|
|
Oct 15 02:56:42 PM UTC 24 |
Oct 15 03:12:56 PM UTC 24 |
15842015118 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.605023003 |
|
|
Oct 15 03:09:25 PM UTC 24 |
Oct 15 03:13:03 PM UTC 24 |
12258907063 ps |
| T1489 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.258587331 |
|
|
Oct 15 02:57:05 PM UTC 24 |
Oct 15 03:13:07 PM UTC 24 |
10277610234 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.3541664037 |
|
|
Oct 15 03:09:46 PM UTC 24 |
Oct 15 03:13:07 PM UTC 24 |
5540544980 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3298353582 |
|
|
Oct 15 03:07:55 PM UTC 24 |
Oct 15 03:13:12 PM UTC 24 |
1210100767 ps |
| T1490 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.3971496638 |
|
|
Oct 15 03:10:53 PM UTC 24 |
Oct 15 03:13:15 PM UTC 24 |
9754306549 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.2977872360 |
|
|
Oct 15 03:11:33 PM UTC 24 |
Oct 15 03:13:28 PM UTC 24 |
2389413004 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.325693060 |
|
|
Oct 15 03:10:18 PM UTC 24 |
Oct 15 03:13:35 PM UTC 24 |
592140528 ps |
| T1491 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.808220022 |
|
|
Oct 15 03:13:24 PM UTC 24 |
Oct 15 03:13:49 PM UTC 24 |
895843941 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.3114269556 |
|
|
Oct 15 03:10:47 PM UTC 24 |
Oct 15 03:13:57 PM UTC 24 |
3861602707 ps |
| T1492 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.548011207 |
|
|
Oct 15 03:13:42 PM UTC 24 |
Oct 15 03:13:58 PM UTC 24 |
103461399 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1112842940 |
|
|
Oct 15 03:07:14 PM UTC 24 |
Oct 15 03:13:59 PM UTC 24 |
28459294066 ps |
| T1493 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.3058070470 |
|
|
Oct 15 03:00:47 PM UTC 24 |
Oct 15 03:14:00 PM UTC 24 |
8566657763 ps |
| T1494 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.3694295970 |
|
|
Oct 15 03:13:39 PM UTC 24 |
Oct 15 03:14:06 PM UTC 24 |
292736353 ps |
| T1495 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.1920517792 |
|
|
Oct 15 03:13:18 PM UTC 24 |
Oct 15 03:14:12 PM UTC 24 |
5033849621 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.3207935950 |
|
|
Oct 15 03:13:17 PM UTC 24 |
Oct 15 03:14:15 PM UTC 24 |
607809218 ps |
| T1496 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.2800003126 |
|
|
Oct 15 03:13:07 PM UTC 24 |
Oct 15 03:14:17 PM UTC 24 |
1523571248 ps |
| T1497 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.2381548448 |
|
|
Oct 15 03:12:58 PM UTC 24 |
Oct 15 03:14:20 PM UTC 24 |
5368339546 ps |
| T1498 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.415081461 |
|
|
Oct 15 03:12:51 PM UTC 24 |
Oct 15 03:14:21 PM UTC 24 |
6675418146 ps |
| T1499 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2600995808 |
|
|
Oct 15 03:13:54 PM UTC 24 |
Oct 15 03:14:30 PM UTC 24 |
265903717 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.2165487949 |
|
|
Oct 15 03:09:16 PM UTC 24 |
Oct 15 03:14:40 PM UTC 24 |
22298068277 ps |
| T1500 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.565912474 |
|
|
Oct 15 03:14:41 PM UTC 24 |
Oct 15 03:14:51 PM UTC 24 |
44150602 ps |
| T1501 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.3682422813 |
|
|
Oct 15 03:06:03 PM UTC 24 |
Oct 15 03:14:52 PM UTC 24 |
5520035388 ps |
| T1502 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1555541524 |
|
|
Oct 15 03:14:44 PM UTC 24 |
Oct 15 03:14:54 PM UTC 24 |
47473200 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.2102591441 |
|
|
Oct 15 03:12:04 PM UTC 24 |
Oct 15 03:14:54 PM UTC 24 |
976020339 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.3799183598 |
|
|
Oct 15 03:13:27 PM UTC 24 |
Oct 15 03:15:02 PM UTC 24 |
1301864729 ps |
| T1503 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.3095065219 |
|
|
Oct 15 03:10:25 PM UTC 24 |
Oct 15 03:15:03 PM UTC 24 |
4296962104 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.3618386424 |
|
|
Oct 15 03:08:42 PM UTC 24 |
Oct 15 03:15:13 PM UTC 24 |
4655143090 ps |
| T1504 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.2249142136 |
|
|
Oct 15 03:14:57 PM UTC 24 |
Oct 15 03:15:24 PM UTC 24 |
280390036 ps |
| T1505 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.671379885 |
|
|
Oct 15 03:15:07 PM UTC 24 |
Oct 15 03:15:33 PM UTC 24 |
183888951 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1094898002 |
|
|
Oct 15 03:11:33 PM UTC 24 |
Oct 15 03:15:42 PM UTC 24 |
14475292815 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3698069791 |
|
|
Oct 15 02:59:57 PM UTC 24 |
Oct 15 03:15:43 PM UTC 24 |
53494571893 ps |
| T1506 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.1999022632 |
|
|
Oct 15 03:15:29 PM UTC 24 |
Oct 15 03:15:45 PM UTC 24 |
86916046 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.207886458 |
|
|
Oct 15 03:15:20 PM UTC 24 |
Oct 15 03:15:48 PM UTC 24 |
707429258 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.147958393 |
|
|
Oct 15 02:36:05 PM UTC 24 |
Oct 15 03:15:53 PM UTC 24 |
14914968292 ps |
| T1507 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.1206229008 |
|
|
Oct 15 03:15:30 PM UTC 24 |
Oct 15 03:15:58 PM UTC 24 |
150027973 ps |
| T1508 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2318640518 |
|
|
Oct 15 03:15:40 PM UTC 24 |
Oct 15 03:16:09 PM UTC 24 |
176435930 ps |
| T1509 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.2129997500 |
|
|
Oct 15 03:08:35 PM UTC 24 |
Oct 15 03:16:14 PM UTC 24 |
6808664170 ps |
| T1510 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.4166948735 |
|
|
Oct 15 03:15:21 PM UTC 24 |
Oct 15 03:16:17 PM UTC 24 |
2041868208 ps |
| T1511 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.1611037126 |
|
|
Oct 15 03:09:49 PM UTC 24 |
Oct 15 03:16:17 PM UTC 24 |
5971238302 ps |
| T1512 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.2579292654 |
|
|
Oct 15 03:14:46 PM UTC 24 |
Oct 15 03:16:22 PM UTC 24 |
8577754856 ps |
| T1513 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.1333703727 |
|
|
Oct 15 03:14:48 PM UTC 24 |
Oct 15 03:16:39 PM UTC 24 |
6425939681 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.2573457949 |
|
|
Oct 15 03:11:50 PM UTC 24 |
Oct 15 03:16:39 PM UTC 24 |
2609037657 ps |
| T1514 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.2467963710 |
|
|
Oct 15 03:16:37 PM UTC 24 |
Oct 15 03:16:50 PM UTC 24 |
173755317 ps |
| T1515 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.3423833159 |
|
|
Oct 15 03:16:40 PM UTC 24 |
Oct 15 03:16:50 PM UTC 24 |
53988395 ps |
| T1516 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.3493187579 |
|
|
Oct 15 03:17:06 PM UTC 24 |
Oct 15 03:17:23 PM UTC 24 |
86136103 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.3571006043 |
|
|
Oct 15 03:14:01 PM UTC 24 |
Oct 15 03:17:35 PM UTC 24 |
2472116830 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.2639182894 |
|
|
Oct 15 03:12:01 PM UTC 24 |
Oct 15 03:17:35 PM UTC 24 |
7723344311 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.3115200121 |
|
|
Oct 15 03:16:49 PM UTC 24 |
Oct 15 03:17:40 PM UTC 24 |
401920598 ps |
| T1517 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.2895110137 |
|
|
Oct 15 03:12:32 PM UTC 24 |
Oct 15 03:17:43 PM UTC 24 |
3788870810 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.866184671 |
|
|
Oct 15 03:14:24 PM UTC 24 |
Oct 15 03:17:53 PM UTC 24 |
1882445635 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1129413028 |
|
|
Oct 15 03:02:26 PM UTC 24 |
Oct 15 03:17:53 PM UTC 24 |
60163588494 ps |
| T1518 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.505456491 |
|
|
Oct 15 03:08:32 PM UTC 24 |
Oct 15 03:18:06 PM UTC 24 |
5557795228 ps |
| T1519 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2673437810 |
|
|
Oct 15 03:16:43 PM UTC 24 |
Oct 15 03:18:17 PM UTC 24 |
6596696107 ps |
| T1520 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.1512300392 |
|
|
Oct 15 03:18:10 PM UTC 24 |
Oct 15 03:18:21 PM UTC 24 |
49733429 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.2099451887 |
|
|
Oct 15 02:41:16 PM UTC 24 |
Oct 15 03:18:25 PM UTC 24 |
17086453985 ps |
| T1521 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.3090774535 |
|
|
Oct 15 03:18:02 PM UTC 24 |
Oct 15 03:18:36 PM UTC 24 |
302932515 ps |
| T1522 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.1512454539 |
|
|
Oct 15 03:11:26 PM UTC 24 |
Oct 15 03:18:39 PM UTC 24 |
23824186930 ps |
| T1523 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.1030010639 |
|
|
Oct 15 03:16:44 PM UTC 24 |
Oct 15 03:18:52 PM UTC 24 |
7896065494 ps |
| T1524 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.1182159813 |
|
|
Oct 15 03:18:01 PM UTC 24 |
Oct 15 03:19:00 PM UTC 24 |
557615246 ps |
| T1525 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.2459034561 |
|
|
Oct 15 03:18:06 PM UTC 24 |
Oct 15 03:19:18 PM UTC 24 |
1166416026 ps |
| T1526 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.3347566238 |
|
|
Oct 15 03:18:31 PM UTC 24 |
Oct 15 03:19:01 PM UTC 24 |
234616248 ps |
| T1527 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.3423250566 |
|
|
Oct 15 03:11:23 PM UTC 24 |
Oct 15 03:19:05 PM UTC 24 |
48819656456 ps |
| T1528 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.266247514 |
|
|
Oct 15 03:16:01 PM UTC 24 |
Oct 15 03:19:18 PM UTC 24 |
596466990 ps |
| T1529 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.1896160133 |
|
|
Oct 15 03:19:06 PM UTC 24 |
Oct 15 03:19:20 PM UTC 24 |
234220935 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.2363953689 |
|
|
Oct 15 03:14:24 PM UTC 24 |
Oct 15 03:19:22 PM UTC 24 |
4799673639 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.4092503568 |
|
|
Oct 15 03:15:51 PM UTC 24 |
Oct 15 03:19:22 PM UTC 24 |
4693016956 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.2866596990 |
|
|
Oct 15 03:09:56 PM UTC 24 |
Oct 15 03:19:23 PM UTC 24 |
14483066846 ps |
| T1530 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.901373216 |
|
|
Oct 15 03:13:21 PM UTC 24 |
Oct 15 03:19:29 PM UTC 24 |
22448870955 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.148040680 |
|
|
Oct 15 03:17:17 PM UTC 24 |
Oct 15 03:19:30 PM UTC 24 |
2434137104 ps |
| T1531 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.3037900781 |
|
|
Oct 15 03:19:20 PM UTC 24 |
Oct 15 03:19:31 PM UTC 24 |
54411021 ps |
| T1532 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.598729985 |
|
|
Oct 15 03:14:38 PM UTC 24 |
Oct 15 03:19:39 PM UTC 24 |
3824621413 ps |
| T1533 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.1092411072 |
|
|
Oct 15 02:46:35 PM UTC 24 |
Oct 15 03:19:41 PM UTC 24 |
15910574352 ps |
| T1534 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.4169089918 |
|
|
Oct 15 03:19:33 PM UTC 24 |
Oct 15 03:19:46 PM UTC 24 |
253720514 ps |
| T1535 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.954120051 |
|
|
Oct 15 03:14:26 PM UTC 24 |
Oct 15 03:19:47 PM UTC 24 |
4171455932 ps |
| T1536 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.165741445 |
|
|
Oct 15 03:15:17 PM UTC 24 |
Oct 15 03:19:48 PM UTC 24 |
19207671612 ps |
| T1537 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.3671607902 |
|
|
Oct 15 03:10:35 PM UTC 24 |
Oct 15 03:19:53 PM UTC 24 |
7139011656 ps |
| T1538 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.2041661914 |
|
|
Oct 15 03:19:49 PM UTC 24 |
Oct 15 03:20:10 PM UTC 24 |
360141170 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.1691030373 |
|
|
Oct 15 03:18:44 PM UTC 24 |
Oct 15 03:20:12 PM UTC 24 |
259360395 ps |
| T1539 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.1695201862 |
|
|
Oct 15 03:19:27 PM UTC 24 |
Oct 15 03:20:15 PM UTC 24 |
3331345797 ps |
| T1540 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.1175495321 |
|
|
Oct 15 03:20:16 PM UTC 24 |
Oct 15 03:20:23 PM UTC 24 |
54165175 ps |
| T1541 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.3754405688 |
|
|
Oct 15 03:20:14 PM UTC 24 |
Oct 15 03:20:26 PM UTC 24 |
145491799 ps |
| T1542 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.2276872110 |
|
|
Oct 15 03:19:53 PM UTC 24 |
Oct 15 03:20:27 PM UTC 24 |
802463785 ps |
| T1543 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.144711670 |
|
|
Oct 15 03:18:21 PM UTC 24 |
Oct 15 03:20:28 PM UTC 24 |
181774617 ps |
| T1544 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.2591290606 |
|
|
Oct 15 03:19:50 PM UTC 24 |
Oct 15 03:20:32 PM UTC 24 |
1035578247 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.1976505793 |
|
|
Oct 15 03:14:14 PM UTC 24 |
Oct 15 03:20:33 PM UTC 24 |
9071977844 ps |
| T1545 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.911186139 |
|
|
Oct 15 03:06:08 PM UTC 24 |
Oct 15 03:20:42 PM UTC 24 |
9076467195 ps |
| T1546 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.582635147 |
|
|
Oct 15 03:20:05 PM UTC 24 |
Oct 15 03:20:42 PM UTC 24 |
263012618 ps |
| T1547 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.4233879018 |
|
|
Oct 15 03:19:45 PM UTC 24 |
Oct 15 03:20:43 PM UTC 24 |
520329683 ps |
| T1548 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.3089890128 |
|
|
Oct 15 03:17:06 PM UTC 24 |
Oct 15 03:20:52 PM UTC 24 |
22304755266 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.3784665427 |
|
|
Oct 15 03:19:56 PM UTC 24 |
Oct 15 03:20:56 PM UTC 24 |
1175147695 ps |
| T1549 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.3273032558 |
|
|
Oct 15 03:19:53 PM UTC 24 |
Oct 15 03:21:01 PM UTC 24 |
614741495 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.4198028274 |
|
|
Oct 15 03:16:24 PM UTC 24 |
Oct 15 03:21:04 PM UTC 24 |
3734286258 ps |
| T1550 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.2924677903 |
|
|
Oct 15 03:19:26 PM UTC 24 |
Oct 15 03:21:05 PM UTC 24 |
8825806449 ps |
| T1551 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.4274126040 |
|
|
Oct 15 03:12:26 PM UTC 24 |
Oct 15 03:21:08 PM UTC 24 |
5850160521 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.649725305 |
|
|
Oct 15 03:20:53 PM UTC 24 |
Oct 15 03:21:17 PM UTC 24 |
337964736 ps |
| T1552 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.3262234308 |
|
|
Oct 15 03:20:59 PM UTC 24 |
Oct 15 03:21:25 PM UTC 24 |
276283445 ps |
| T1553 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.2275455212 |
|
|
Oct 15 03:20:40 PM UTC 24 |
Oct 15 03:21:30 PM UTC 24 |
1000903945 ps |
| T1554 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.3019096891 |
|
|
Oct 15 03:20:34 PM UTC 24 |
Oct 15 03:21:31 PM UTC 24 |
3482846955 ps |
| T1555 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.1805407157 |
|
|
Oct 15 03:19:45 PM UTC 24 |
Oct 15 03:21:31 PM UTC 24 |
11979663325 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.1567159321 |
|
|
Oct 15 03:20:05 PM UTC 24 |
Oct 15 03:21:34 PM UTC 24 |
311867447 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.1274454738 |
|
|
Oct 15 03:11:56 PM UTC 24 |
Oct 15 03:21:36 PM UTC 24 |
9137001641 ps |
| T1556 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.2398141280 |
|
|
Oct 15 03:20:50 PM UTC 24 |
Oct 15 03:21:38 PM UTC 24 |
515426712 ps |
| T1557 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.2459106369 |
|
|
Oct 15 03:12:15 PM UTC 24 |
Oct 15 03:21:41 PM UTC 24 |
5536424064 ps |
| T1558 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.577318555 |
|
|
Oct 15 03:21:34 PM UTC 24 |
Oct 15 03:21:45 PM UTC 24 |
48678798 ps |
| T1559 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.2843459967 |
|
|
Oct 15 03:15:17 PM UTC 24 |
Oct 15 03:21:49 PM UTC 24 |
27088921177 ps |
| T1560 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.3237596572 |
|
|
Oct 15 03:21:10 PM UTC 24 |
Oct 15 03:21:50 PM UTC 24 |
331718626 ps |
| T1561 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.2818852378 |
|
|
Oct 15 03:20:37 PM UTC 24 |
Oct 15 03:21:51 PM UTC 24 |
7541813080 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.1228763579 |
|
|
Oct 15 03:16:09 PM UTC 24 |
Oct 15 03:21:52 PM UTC 24 |
9136097656 ps |
| T1562 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.1876053864 |
|
|
Oct 15 03:21:43 PM UTC 24 |
Oct 15 03:21:54 PM UTC 24 |
45195208 ps |
| T1563 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.3461774019 |
|
|
Oct 15 03:21:07 PM UTC 24 |
Oct 15 03:22:03 PM UTC 24 |
1579097758 ps |
| T1564 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.441226921 |
|
|
Oct 15 03:21:10 PM UTC 24 |
Oct 15 03:22:04 PM UTC 24 |
1310707414 ps |
| T1565 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.3106042153 |
|
|
Oct 15 03:21:26 PM UTC 24 |
Oct 15 03:22:04 PM UTC 24 |
119134521 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.932851876 |
|
|
Oct 15 03:18:19 PM UTC 24 |
Oct 15 03:22:17 PM UTC 24 |
4391939450 ps |
| T1566 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.3122734164 |
|
|
Oct 15 02:53:18 PM UTC 24 |
Oct 15 03:22:18 PM UTC 24 |
15766096662 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.1114766870 |
|
|
Oct 15 03:21:56 PM UTC 24 |
Oct 15 03:22:19 PM UTC 24 |
149772667 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.3757664711 |
|
|
Oct 15 03:16:09 PM UTC 24 |
Oct 15 03:22:20 PM UTC 24 |
5328173229 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.333487202 |
|
|
Oct 15 03:16:10 PM UTC 24 |
Oct 15 03:22:20 PM UTC 24 |
4618232863 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.2589638547 |
|
|
Oct 15 03:15:21 PM UTC 24 |
Oct 15 03:22:20 PM UTC 24 |
27128872956 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.3026199789 |
|
|
Oct 15 03:14:25 PM UTC 24 |
Oct 15 03:22:23 PM UTC 24 |
6494460250 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.3163688082 |
|
|
Oct 15 03:22:16 PM UTC 24 |
Oct 15 03:22:27 PM UTC 24 |
77769906 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.266042148 |
|
|
Oct 15 03:22:13 PM UTC 24 |
Oct 15 03:22:28 PM UTC 24 |
159683375 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.3554533734 |
|
|
Oct 15 03:22:26 PM UTC 24 |
Oct 15 03:22:32 PM UTC 24 |
45592557 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.1945775385 |
|
|
Oct 15 03:22:09 PM UTC 24 |
Oct 15 03:22:40 PM UTC 24 |
942370052 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.2911423253 |
|
|
Oct 15 03:17:16 PM UTC 24 |
Oct 15 03:22:43 PM UTC 24 |
20797192701 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.1950945754 |
|
|
Oct 15 03:21:54 PM UTC 24 |
Oct 15 03:22:52 PM UTC 24 |
1598102958 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.2573469606 |
|
|
Oct 15 03:22:44 PM UTC 24 |
Oct 15 03:22:55 PM UTC 24 |
40755059 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.38208234 |
|
|
Oct 15 03:22:44 PM UTC 24 |
Oct 15 03:22:55 PM UTC 24 |
47730690 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.1785390849 |
|
|
Oct 15 03:22:46 PM UTC 24 |
Oct 15 03:22:56 PM UTC 24 |
68994753 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.982181314 |
|
|
Oct 15 03:22:25 PM UTC 24 |
Oct 15 03:22:58 PM UTC 24 |
66401852 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.4277988676 |
|
|
Oct 15 03:20:02 PM UTC 24 |
Oct 15 03:22:59 PM UTC 24 |
5048305416 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1670405863 |
|
|
Oct 15 03:22:15 PM UTC 24 |
Oct 15 03:23:08 PM UTC 24 |
1057447461 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.2403122577 |
|
|
Oct 15 03:21:32 PM UTC 24 |
Oct 15 03:23:10 PM UTC 24 |
3063527241 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.2964069375 |
|
|
Oct 15 03:22:04 PM UTC 24 |
Oct 15 03:23:15 PM UTC 24 |
1407789501 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.3652394594 |
|
|
Oct 15 03:23:02 PM UTC 24 |
Oct 15 03:23:21 PM UTC 24 |
394609213 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.437916660 |
|
|
Oct 15 03:20:14 PM UTC 24 |
Oct 15 03:23:23 PM UTC 24 |
3143582280 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.664611953 |
|
|
Oct 15 03:21:54 PM UTC 24 |
Oct 15 03:23:29 PM UTC 24 |
5670092651 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.3246405183 |
|
|
Oct 15 03:22:59 PM UTC 24 |
Oct 15 03:23:32 PM UTC 24 |
258547932 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.3188732904 |
|
|
Oct 15 03:19:49 PM UTC 24 |
Oct 15 03:23:33 PM UTC 24 |
13846426398 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.341228197 |
|
|
Oct 15 03:21:50 PM UTC 24 |
Oct 15 03:23:38 PM UTC 24 |
10345439584 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.2636353155 |
|
|
Oct 15 03:23:09 PM UTC 24 |
Oct 15 03:23:41 PM UTC 24 |
758275463 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.2985812580 |
|
|
Oct 15 03:23:32 PM UTC 24 |
Oct 15 03:23:43 PM UTC 24 |
191929781 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.3372273089 |
|
|
Oct 15 03:23:19 PM UTC 24 |
Oct 15 03:23:44 PM UTC 24 |
171463863 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.1549768199 |
|
|
Oct 15 03:23:34 PM UTC 24 |
Oct 15 03:23:45 PM UTC 24 |
44455074 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.1331203121 |
|
|
Oct 15 03:20:07 PM UTC 24 |
Oct 15 03:23:45 PM UTC 24 |
2135203892 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.3998215717 |
|
|
Oct 15 03:22:44 PM UTC 24 |
Oct 15 03:23:50 PM UTC 24 |
6190662980 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.1557086888 |
|
|
Oct 15 03:22:46 PM UTC 24 |
Oct 15 03:23:56 PM UTC 24 |
4242689268 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.3418099070 |
|
|
Oct 15 03:23:18 PM UTC 24 |
Oct 15 03:23:58 PM UTC 24 |
900161428 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2154220635 |
|
|
Oct 15 03:17:48 PM UTC 24 |
Oct 15 03:24:14 PM UTC 24 |
23819757835 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.3852389740 |
|
|
Oct 15 03:16:15 PM UTC 24 |
Oct 15 03:24:21 PM UTC 24 |
5756135628 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.1774854627 |
|
|
Oct 15 03:21:23 PM UTC 24 |
Oct 15 03:24:22 PM UTC 24 |
1674883239 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.3516801842 |
|
|
Oct 15 03:23:51 PM UTC 24 |
Oct 15 03:24:28 PM UTC 24 |
899069043 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.3424844609 |
|
|
Oct 15 03:24:10 PM UTC 24 |
Oct 15 03:24:29 PM UTC 24 |
168059265 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.505938055 |
|
|
Oct 15 03:23:55 PM UTC 24 |
Oct 15 03:24:37 PM UTC 24 |
467544020 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.756581763 |
|
|
Oct 15 03:23:38 PM UTC 24 |
Oct 15 03:24:39 PM UTC 24 |
6364550413 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.473382257 |
|
|
Oct 15 03:22:21 PM UTC 24 |
Oct 15 03:24:40 PM UTC 24 |
1604667607 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.1356602587 |
|
|
Oct 15 03:24:10 PM UTC 24 |
Oct 15 03:24:44 PM UTC 24 |
780691300 ps |