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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.96 95.39 93.47 95.36 94.22 97.71 99.60


Total test records in report: 2930
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T1409 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.1606627221 Feb 09 03:14:55 PM UTC 25 Feb 09 03:15:47 PM UTC 25 428047438 ps
T569 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.3811021255 Feb 09 03:11:47 PM UTC 25 Feb 09 03:15:51 PM UTC 25 3017296807 ps
T537 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.1593771844 Feb 09 03:14:51 PM UTC 25 Feb 09 03:15:55 PM UTC 25 1411404249 ps
T1410 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.1863990589 Feb 09 03:09:41 PM UTC 25 Feb 09 03:16:00 PM UTC 25 39424710389 ps
T1411 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.1125674058 Feb 09 03:15:53 PM UTC 25 Feb 09 03:16:02 PM UTC 25 159061043 ps
T1412 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.5741320 Feb 09 03:16:03 PM UTC 25 Feb 09 03:16:28 PM UTC 25 159303135 ps
T1413 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.1854713375 Feb 09 03:14:45 PM UTC 25 Feb 09 03:16:28 PM UTC 25 7090061856 ps
T1414 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3797435242 Feb 09 03:14:48 PM UTC 25 Feb 09 03:16:34 PM UTC 25 5905382061 ps
T536 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.514590936 Feb 09 03:15:56 PM UTC 25 Feb 09 03:16:43 PM UTC 25 249769183 ps
T831 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.909609237 Feb 09 03:15:20 PM UTC 25 Feb 09 03:16:47 PM UTC 25 1523265547 ps
T1415 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.4258293748 Feb 09 03:16:27 PM UTC 25 Feb 09 03:16:54 PM UTC 25 16546432 ps
T1416 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.3100086595 Feb 09 03:01:09 PM UTC 25 Feb 09 03:17:01 PM UTC 25 9428375650 ps
T661 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.30551187 Feb 09 03:08:07 PM UTC 25 Feb 09 03:17:02 PM UTC 25 5637639290 ps
T805 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.877113180 Feb 09 03:11:16 PM UTC 25 Feb 09 03:17:07 PM UTC 25 12010393963 ps
T1417 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.659234429 Feb 09 03:15:50 PM UTC 25 Feb 09 03:17:12 PM UTC 25 2048250353 ps
T1418 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.4049388466 Feb 09 03:17:11 PM UTC 25 Feb 09 03:17:21 PM UTC 25 40682078 ps
T1419 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.2957781139 Feb 09 03:17:10 PM UTC 25 Feb 09 03:17:23 PM UTC 25 209982825 ps
T1420 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.1810086294 Feb 09 03:15:17 PM UTC 25 Feb 09 03:17:30 PM UTC 25 6061753445 ps
T815 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2606443689 Feb 09 02:44:07 PM UTC 25 Feb 09 03:17:41 PM UTC 25 118482317795 ps
T1421 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.1015873240 Feb 09 03:17:34 PM UTC 25 Feb 09 03:17:44 PM UTC 25 39254856 ps
T835 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.3508151469 Feb 09 03:07:03 PM UTC 25 Feb 09 03:17:54 PM UTC 25 38695041028 ps
T860 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3181228992 Feb 09 03:13:33 PM UTC 25 Feb 09 03:17:56 PM UTC 25 1157854474 ps
T1422 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.3111039243 Feb 09 03:12:14 PM UTC 25 Feb 09 03:17:56 PM UTC 25 29434758459 ps
T544 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.2207304139 Feb 09 03:17:29 PM UTC 25 Feb 09 03:18:10 PM UTC 25 393258622 ps
T484 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.2881451438 Feb 09 03:11:44 PM UTC 25 Feb 09 03:18:28 PM UTC 25 6815658885 ps
T806 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.2082576719 Feb 09 03:02:06 PM UTC 25 Feb 09 03:18:32 PM UTC 25 68811811319 ps
T1423 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.1994551512 Feb 09 03:18:22 PM UTC 25 Feb 09 03:18:32 PM UTC 25 77109690 ps
T638 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.530149925 Feb 09 03:18:09 PM UTC 25 Feb 09 03:18:32 PM UTC 25 184941787 ps
T592 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.4189207598 Feb 09 03:18:21 PM UTC 25 Feb 09 03:18:40 PM UTC 25 110028269 ps
T1424 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.2226346266 Feb 09 03:18:09 PM UTC 25 Feb 09 03:18:40 PM UTC 25 699045517 ps
T1425 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.2464459837 Feb 09 03:17:21 PM UTC 25 Feb 09 03:18:51 PM UTC 25 8364684318 ps
T500 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.617832996 Feb 09 03:18:24 PM UTC 25 Feb 09 03:18:54 PM UTC 25 154333663 ps
T1426 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1102751294 Feb 09 03:17:29 PM UTC 25 Feb 09 03:19:01 PM UTC 25 5872716150 ps
T417 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.1054663669 Feb 09 02:48:53 PM UTC 25 Feb 09 03:19:04 PM UTC 25 15581611656 ps
T813 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.2461250389 Feb 09 03:13:41 PM UTC 25 Feb 09 03:19:05 PM UTC 25 7925979508 ps
T807 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.186320410 Feb 09 03:17:49 PM UTC 25 Feb 09 03:19:19 PM UTC 25 2206814914 ps
T1427 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.120601898 Feb 09 03:19:15 PM UTC 25 Feb 09 03:19:25 PM UTC 25 219600046 ps
T1428 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.3564520319 Feb 09 02:53:21 PM UTC 25 Feb 09 03:19:30 PM UTC 25 11671332489 ps
T1429 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.234759176 Feb 09 03:19:20 PM UTC 25 Feb 09 03:19:30 PM UTC 25 47615297 ps
T1430 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.1185653631 Feb 09 03:08:26 PM UTC 25 Feb 09 03:19:33 PM UTC 25 5743730055 ps
T539 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2710618550 Feb 09 03:16:17 PM UTC 25 Feb 09 03:19:45 PM UTC 25 304364525 ps
T1431 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.978568024 Feb 09 03:19:32 PM UTC 25 Feb 09 03:20:13 PM UTC 25 799256584 ps
T874 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1875901175 Feb 09 03:18:59 PM UTC 25 Feb 09 03:20:28 PM UTC 25 181816397 ps
T1432 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.1184576331 Feb 09 03:20:11 PM UTC 25 Feb 09 03:20:29 PM UTC 25 112711476 ps
T1433 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.4243485299 Feb 09 03:19:55 PM UTC 25 Feb 09 03:20:34 PM UTC 25 592571245 ps
T552 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.602202495 Feb 09 03:09:53 PM UTC 25 Feb 09 03:20:36 PM UTC 25 46625104665 ps
T576 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.1114693959 Feb 09 03:14:04 PM UTC 25 Feb 09 03:20:38 PM UTC 25 4341628060 ps
T1434 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.1040809494 Feb 09 03:05:58 PM UTC 25 Feb 09 03:20:46 PM UTC 25 11261079748 ps
T1435 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.2060928385 Feb 09 03:19:03 PM UTC 25 Feb 09 03:20:48 PM UTC 25 2344616999 ps
T603 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.2336651937 Feb 09 03:19:46 PM UTC 25 Feb 09 03:21:00 PM UTC 25 617738631 ps
T1436 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.3434885830 Feb 09 03:20:39 PM UTC 25 Feb 09 03:21:02 PM UTC 25 215449905 ps
T1437 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.166557854 Feb 09 03:19:28 PM UTC 25 Feb 09 03:21:04 PM UTC 25 8390702256 ps
T1438 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.360424279 Feb 09 03:21:02 PM UTC 25 Feb 09 03:21:08 PM UTC 25 6189043 ps
T1439 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2869879760 Feb 09 03:20:55 PM UTC 25 Feb 09 03:21:11 PM UTC 25 75906037 ps
T1440 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.745548037 Feb 09 03:19:29 PM UTC 25 Feb 09 03:21:12 PM UTC 25 6715714139 ps
T819 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.1546797943 Feb 09 03:18:54 PM UTC 25 Feb 09 03:21:32 PM UTC 25 3877955879 ps
T820 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.2100421079 Feb 09 03:16:23 PM UTC 25 Feb 09 03:21:33 PM UTC 25 7741313131 ps
T602 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.3951076492 Feb 09 03:20:53 PM UTC 25 Feb 09 03:21:40 PM UTC 25 359167509 ps
T1441 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.3901456832 Feb 09 03:21:36 PM UTC 25 Feb 09 03:21:46 PM UTC 25 40734684 ps
T1442 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.3385114885 Feb 09 03:21:38 PM UTC 25 Feb 09 03:21:47 PM UTC 25 48021312 ps
T1443 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.224706096 Feb 09 03:21:02 PM UTC 25 Feb 09 03:21:55 PM UTC 25 58131889 ps
T501 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.863617255 Feb 09 03:10:57 PM UTC 25 Feb 09 03:22:00 PM UTC 25 18456876964 ps
T1444 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.916620695 Feb 09 03:22:07 PM UTC 25 Feb 09 03:22:33 PM UTC 25 193958035 ps
T604 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.506572941 Feb 09 03:17:00 PM UTC 25 Feb 09 03:22:47 PM UTC 25 3773225160 ps
T1445 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.3097347327 Feb 09 03:22:00 PM UTC 25 Feb 09 03:22:54 PM UTC 25 518850215 ps
T1446 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.3785750428 Feb 09 03:21:38 PM UTC 25 Feb 09 03:22:58 PM UTC 25 8247849927 ps
T492 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.899462360 Feb 09 02:47:34 PM UTC 25 Feb 09 03:23:02 PM UTC 25 135147977106 ps
T1447 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3070960988 Feb 09 03:21:59 PM UTC 25 Feb 09 03:23:53 PM UTC 25 4790504184 ps
T1448 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.3366266586 Feb 09 03:23:11 PM UTC 25 Feb 09 03:23:58 PM UTC 25 379715291 ps
T1449 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2580459434 Feb 09 03:23:25 PM UTC 25 Feb 09 03:24:03 PM UTC 25 243101714 ps
T1450 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.1859987192 Feb 09 03:23:21 PM UTC 25 Feb 09 03:24:05 PM UTC 25 873249595 ps
T1451 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3594576303 Feb 09 03:16:55 PM UTC 25 Feb 09 03:24:07 PM UTC 25 6923446393 ps
T1452 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.1899983839 Feb 09 03:11:25 PM UTC 25 Feb 09 03:24:18 PM UTC 25 6013859936 ps
T1453 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.126022988 Feb 09 03:23:00 PM UTC 25 Feb 09 03:24:28 PM UTC 25 2049205447 ps
T1454 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.4162195198 Feb 09 03:22:13 PM UTC 25 Feb 09 03:25:14 PM UTC 25 19052657135 ps
T1455 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.2873959804 Feb 09 03:08:31 PM UTC 25 Feb 09 03:25:19 PM UTC 25 9079069676 ps
T828 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.700684607 Feb 09 03:20:58 PM UTC 25 Feb 09 03:25:44 PM UTC 25 7206915040 ps
T887 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1139561918 Feb 09 03:18:37 PM UTC 25 Feb 09 03:25:47 PM UTC 25 580921737 ps
T801 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.408536591 Feb 09 03:22:22 PM UTC 25 Feb 09 03:25:49 PM UTC 25 3635477853 ps
T1456 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.581931703 Feb 09 03:21:10 PM UTC 25 Feb 09 03:25:52 PM UTC 25 3110339199 ps
T1457 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.831674881 Feb 09 03:25:40 PM UTC 25 Feb 09 03:25:55 PM UTC 25 195257081 ps
T1458 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.2791443759 Feb 09 03:25:44 PM UTC 25 Feb 09 03:25:56 PM UTC 25 57875159 ps
T1459 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.3629080174 Feb 09 03:16:25 PM UTC 25 Feb 09 03:26:16 PM UTC 25 5388656125 ps
T547 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.1150030768 Feb 09 03:06:33 PM UTC 25 Feb 09 03:26:21 PM UTC 25 91339945602 ps
T1460 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.3987091783 Feb 09 03:26:15 PM UTC 25 Feb 09 03:26:48 PM UTC 25 567995468 ps
T825 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3437851241 Feb 09 03:17:53 PM UTC 25 Feb 09 03:26:51 PM UTC 25 37058295689 ps
T584 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.1936770744 Feb 09 03:21:30 PM UTC 25 Feb 09 03:26:55 PM UTC 25 3325623203 ps
T1461 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.3313812945 Feb 09 03:26:19 PM UTC 25 Feb 09 03:27:15 PM UTC 25 556923294 ps
T523 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.81810302 Feb 09 03:23:27 PM UTC 25 Feb 09 03:27:16 PM UTC 25 7485967654 ps
T1462 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.1293149868 Feb 09 03:22:14 PM UTC 25 Feb 09 03:27:29 PM UTC 25 16823349291 ps
T1463 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.3435374436 Feb 09 03:26:13 PM UTC 25 Feb 09 03:27:41 PM UTC 25 5399920761 ps
T1464 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.98339314 Feb 09 03:27:13 PM UTC 25 Feb 09 03:27:56 PM UTC 25 828199543 ps
T1465 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.789116150 Feb 09 03:27:22 PM UTC 25 Feb 09 03:28:01 PM UTC 25 229925890 ps
T1466 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.3721668241 Feb 09 03:27:18 PM UTC 25 Feb 09 03:28:07 PM UTC 25 462458890 ps
T1467 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.3868480556 Feb 09 03:27:41 PM UTC 25 Feb 09 03:28:08 PM UTC 25 377389659 ps
T1468 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.4172613487 Feb 09 03:13:45 PM UTC 25 Feb 09 03:28:26 PM UTC 25 6453811216 ps
T1469 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.3861263101 Feb 09 03:26:11 PM UTC 25 Feb 09 03:28:35 PM UTC 25 9701064809 ps
T590 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.3509052011 Feb 09 03:24:56 PM UTC 25 Feb 09 03:28:38 PM UTC 25 3840793500 ps
T1470 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.3964584423 Feb 09 03:18:58 PM UTC 25 Feb 09 03:28:53 PM UTC 25 9694347788 ps
T1471 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.1539420801 Feb 09 03:17:37 PM UTC 25 Feb 09 03:28:55 PM UTC 25 50821282889 ps
T1472 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.669495500 Feb 09 03:18:58 PM UTC 25 Feb 09 03:28:59 PM UTC 25 5421163650 ps
T548 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3586345544 Feb 09 03:24:18 PM UTC 25 Feb 09 03:29:01 PM UTC 25 1172292132 ps
T1473 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.1674499388 Feb 09 03:29:01 PM UTC 25 Feb 09 03:29:11 PM UTC 25 211290374 ps
T1474 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.388946569 Feb 09 03:29:03 PM UTC 25 Feb 09 03:29:14 PM UTC 25 50239452 ps
T619 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.2690677358 Feb 09 03:27:42 PM UTC 25 Feb 09 03:29:19 PM UTC 25 976639700 ps
T1475 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.2723511722 Feb 09 03:28:06 PM UTC 25 Feb 09 03:29:39 PM UTC 25 1169368689 ps
T816 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.2861712782 Feb 09 03:26:43 PM UTC 25 Feb 09 03:29:46 PM UTC 25 3438214761 ps
T808 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.529758393 Feb 09 02:55:15 PM UTC 25 Feb 09 03:30:12 PM UTC 25 126940711431 ps
T516 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.2864507741 Feb 09 03:29:28 PM UTC 25 Feb 09 03:30:14 PM UTC 25 372071360 ps
T1476 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.1581343536 Feb 09 03:24:33 PM UTC 25 Feb 09 03:30:17 PM UTC 25 4136882676 ps
T875 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.669578101 Feb 09 03:24:28 PM UTC 25 Feb 09 03:30:23 PM UTC 25 2995185213 ps
T1477 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.2447976961 Feb 09 03:29:20 PM UTC 25 Feb 09 03:30:29 PM UTC 25 2710528473 ps
T839 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.1245226635 Feb 09 03:24:23 PM UTC 25 Feb 09 03:30:51 PM UTC 25 9422517608 ps
T1478 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.1144025177 Feb 09 03:21:27 PM UTC 25 Feb 09 03:30:52 PM UTC 25 7013045516 ps
T1479 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.2493647584 Feb 09 03:30:12 PM UTC 25 Feb 09 03:30:55 PM UTC 25 995242092 ps
T1480 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.2296372900 Feb 09 03:29:26 PM UTC 25 Feb 09 03:31:02 PM UTC 25 2390041156 ps
T1481 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.3730917400 Feb 09 03:30:39 PM UTC 25 Feb 09 03:31:03 PM UTC 25 210529330 ps
T1482 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.3906426771 Feb 09 03:29:19 PM UTC 25 Feb 09 03:31:13 PM UTC 25 10677249101 ps
T508 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.1471829848 Feb 09 03:04:38 PM UTC 25 Feb 09 03:31:17 PM UTC 25 115697321901 ps
T535 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.4085371627 Feb 09 03:30:41 PM UTC 25 Feb 09 03:31:23 PM UTC 25 313465218 ps
T851 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.1301828955 Feb 09 03:29:45 PM UTC 25 Feb 09 03:31:25 PM UTC 25 1236393988 ps
T1483 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.3127192101 Feb 09 03:19:56 PM UTC 25 Feb 09 03:31:36 PM UTC 25 40606731739 ps
T809 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.83128704 Feb 09 03:12:29 PM UTC 25 Feb 09 03:31:53 PM UTC 25 81037794012 ps
T1484 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.1953506055 Feb 09 03:31:44 PM UTC 25 Feb 09 03:31:56 PM UTC 25 232774452 ps
T1485 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.456794477 Feb 09 03:30:44 PM UTC 25 Feb 09 03:31:58 PM UTC 25 1431280692 ps
T1486 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.2959645914 Feb 09 03:31:49 PM UTC 25 Feb 09 03:31:59 PM UTC 25 46487331 ps
T1487 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.80697511 Feb 09 03:24:34 PM UTC 25 Feb 09 03:32:16 PM UTC 25 6204774192 ps
T1488 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.988747222 Feb 09 03:21:16 PM UTC 25 Feb 09 03:32:20 PM UTC 25 5115705289 ps
T597 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.3843123552 Feb 09 03:28:53 PM UTC 25 Feb 09 03:32:24 PM UTC 25 3496517296 ps
T430 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.3746192180 Feb 09 02:59:02 PM UTC 25 Feb 09 03:32:31 PM UTC 25 15652752430 ps
T502 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.2256580624 Feb 09 03:16:14 PM UTC 25 Feb 09 03:32:33 PM UTC 25 19766717322 ps
T1489 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.4276743480 Feb 09 03:32:19 PM UTC 25 Feb 09 03:32:34 PM UTC 25 101811360 ps
T1490 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.129314771 Feb 09 03:13:54 PM UTC 25 Feb 09 03:32:34 PM UTC 25 13368606545 ps
T1491 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.1117646157 Feb 09 03:32:23 PM UTC 25 Feb 09 03:32:58 PM UTC 25 264099708 ps
T1492 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.1187226541 Feb 09 03:15:14 PM UTC 25 Feb 09 03:33:03 PM UTC 25 90204180098 ps
T889 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.3219492124 Feb 09 03:31:18 PM UTC 25 Feb 09 03:33:05 PM UTC 25 406193907 ps
T802 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3984986067 Feb 09 03:22:27 PM UTC 25 Feb 09 03:33:07 PM UTC 25 41227248170 ps
T1493 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.1896213420 Feb 09 03:19:51 PM UTC 25 Feb 09 03:33:16 PM UTC 25 74921246343 ps
T1494 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2746009644 Feb 09 03:32:57 PM UTC 25 Feb 09 03:33:16 PM UTC 25 284715935 ps
T1495 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.2526029307 Feb 09 03:32:58 PM UTC 25 Feb 09 03:33:18 PM UTC 25 149991551 ps
T1496 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.2132309477 Feb 09 03:31:40 PM UTC 25 Feb 09 03:33:21 PM UTC 25 3398029588 ps
T799 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.93005010 Feb 09 02:49:38 PM UTC 25 Feb 09 03:33:25 PM UTC 25 147986136991 ps
T1497 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.3452863185 Feb 09 03:31:48 PM UTC 25 Feb 09 03:33:26 PM UTC 25 6967724748 ps
T1498 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.1591871602 Feb 09 03:32:51 PM UTC 25 Feb 09 03:33:29 PM UTC 25 1187078064 ps
T1499 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.616008382 Feb 09 03:33:01 PM UTC 25 Feb 09 03:33:33 PM UTC 25 553689768 ps
T810 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.1522806913 Feb 09 03:30:50 PM UTC 25 Feb 09 03:33:37 PM UTC 25 1992350114 ps
T1500 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.2299807959 Feb 09 03:32:01 PM UTC 25 Feb 09 03:33:40 PM UTC 25 5158205797 ps
T856 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.125082134 Feb 09 03:32:40 PM UTC 25 Feb 09 03:33:49 PM UTC 25 505118656 ps
T1501 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.802497502 Feb 09 03:33:49 PM UTC 25 Feb 09 03:33:59 PM UTC 25 47469093 ps
T1502 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.3353778520 Feb 09 03:33:47 PM UTC 25 Feb 09 03:34:03 PM UTC 25 229521575 ps
T1503 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.875499489 Feb 09 03:34:04 PM UTC 25 Feb 09 03:34:23 PM UTC 25 125348811 ps
T1504 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.915080329 Feb 09 03:26:22 PM UTC 25 Feb 09 03:34:24 PM UTC 25 43368087951 ps
T1505 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1670454749 Feb 09 03:26:48 PM UTC 25 Feb 09 03:34:40 PM UTC 25 27273232342 ps
T517 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.1973726293 Feb 09 03:17:47 PM UTC 25 Feb 09 03:34:48 PM UTC 25 56812735524 ps
T1506 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.3626061521 Feb 09 03:33:56 PM UTC 25 Feb 09 03:35:03 PM UTC 25 1511678777 ps
T1507 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.2344547051 Feb 09 03:29:42 PM UTC 25 Feb 09 03:35:16 PM UTC 25 14711883307 ps
T880 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1761744824 Feb 09 03:28:20 PM UTC 25 Feb 09 03:35:16 PM UTC 25 4249003828 ps
T1508 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.316565915 Feb 09 03:34:50 PM UTC 25 Feb 09 03:35:23 PM UTC 25 344396072 ps
T1509 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.940305711 Feb 09 03:35:01 PM UTC 25 Feb 09 03:35:26 PM UTC 25 363440745 ps
T1510 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.313128970 Feb 09 03:33:53 PM UTC 25 Feb 09 03:35:30 PM UTC 25 9354031260 ps
T1511 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.3567601029 Feb 09 03:34:50 PM UTC 25 Feb 09 03:35:41 PM UTC 25 573828384 ps
T489 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.1680166547 Feb 09 03:34:25 PM UTC 25 Feb 09 03:35:49 PM UTC 25 772292677 ps
T1512 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.1202369632 Feb 09 03:34:56 PM UTC 25 Feb 09 03:35:51 PM UTC 25 1306766274 ps
T1513 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2576953758 Feb 09 03:33:54 PM UTC 25 Feb 09 03:35:56 PM UTC 25 5504146764 ps
T1514 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.583254228 Feb 09 03:33:29 PM UTC 25 Feb 09 03:36:05 PM UTC 25 2015227355 ps
T852 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.3250159950 Feb 09 03:33:00 PM UTC 25 Feb 09 03:36:12 PM UTC 25 1882258572 ps
T1515 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.3674670281 Feb 09 03:31:17 PM UTC 25 Feb 09 03:36:20 PM UTC 25 7320445102 ps
T1516 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.1323392892 Feb 09 03:36:12 PM UTC 25 Feb 09 03:36:21 PM UTC 25 37910543 ps
T1517 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.3877864336 Feb 09 03:36:07 PM UTC 25 Feb 09 03:36:21 PM UTC 25 218940235 ps
T1518 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.2174525000 Feb 09 03:36:36 PM UTC 25 Feb 09 03:36:53 PM UTC 25 89791859 ps
T1519 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.2249744711 Feb 09 03:28:33 PM UTC 25 Feb 09 03:37:04 PM UTC 25 5559341002 ps
T846 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.1555893584 Feb 09 03:36:47 PM UTC 25 Feb 09 03:37:04 PM UTC 25 150324404 ps
T1520 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.1183202035 Feb 09 03:36:15 PM UTC 25 Feb 09 03:37:19 PM UTC 25 5703005996 ps
T550 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.2136911836 Feb 09 03:35:14 PM UTC 25 Feb 09 03:37:22 PM UTC 25 1453816281 ps
T1521 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.3260986705 Feb 09 03:36:32 PM UTC 25 Feb 09 03:37:27 PM UTC 25 453762485 ps
T876 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1210140421 Feb 09 03:33:23 PM UTC 25 Feb 09 03:37:30 PM UTC 25 810275292 ps
T1522 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2468946684 Feb 09 03:36:19 PM UTC 25 Feb 09 03:38:08 PM UTC 25 5281054285 ps
T1523 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.3930944366 Feb 09 03:37:31 PM UTC 25 Feb 09 03:38:29 PM UTC 25 1856921157 ps
T1524 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.731078575 Feb 09 03:31:22 PM UTC 25 Feb 09 03:38:33 PM UTC 25 4289765947 ps
T1525 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.3556738723 Feb 09 03:37:45 PM UTC 25 Feb 09 03:38:49 PM UTC 25 1389569141 ps
T1526 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.2744857303 Feb 09 03:37:49 PM UTC 25 Feb 09 03:38:51 PM UTC 25 1124269848 ps
T800 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.1442389734 Feb 09 03:00:10 PM UTC 25 Feb 09 03:38:53 PM UTC 25 117600073358 ps
T845 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3268869967 Feb 09 03:32:42 PM UTC 25 Feb 09 03:38:55 PM UTC 25 24109706662 ps
T1527 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.3855061257 Feb 09 03:37:30 PM UTC 25 Feb 09 03:39:24 PM UTC 25 2491357000 ps
T1528 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.3450038719 Feb 09 03:39:16 PM UTC 25 Feb 09 03:39:25 PM UTC 25 39236293 ps
T1529 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.2382550527 Feb 09 03:39:14 PM UTC 25 Feb 09 03:39:29 PM UTC 25 210205538 ps
T1530 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.30013058 Feb 09 03:34:04 PM UTC 25 Feb 09 03:39:32 PM UTC 25 27028683346 ps
T490 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.2738965226 Feb 09 03:27:57 PM UTC 25 Feb 09 03:39:45 PM UTC 25 11028587264 ps
T637 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.3749118659 Feb 09 03:35:51 PM UTC 25 Feb 09 03:39:56 PM UTC 25 3918504200 ps
T1531 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.3297722646 Feb 09 03:28:29 PM UTC 25 Feb 09 03:40:01 PM UTC 25 5125999363 ps
T897 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3860045428 Feb 09 03:35:43 PM UTC 25 Feb 09 03:40:02 PM UTC 25 2465830804 ps
T418 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.1459673053 Feb 09 02:56:31 PM UTC 25 Feb 09 03:40:19 PM UTC 25 15662108003 ps
T857 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.4043375902 Feb 09 03:35:43 PM UTC 25 Feb 09 03:40:27 PM UTC 25 9274961823 ps
T600 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.1618387383 Feb 09 03:33:40 PM UTC 25 Feb 09 03:40:27 PM UTC 25 4970274704 ps
T1532 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.3058549940 Feb 09 03:39:51 PM UTC 25 Feb 09 03:40:37 PM UTC 25 376262946 ps
T1533 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.859686578 Feb 09 03:40:27 PM UTC 25 Feb 09 03:40:38 PM UTC 25 115521375 ps
T1534 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.928315445 Feb 09 03:39:19 PM UTC 25 Feb 09 03:40:44 PM UTC 25 5040434847 ps
T1535 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.3200840468 Feb 09 03:39:49 PM UTC 25 Feb 09 03:40:48 PM UTC 25 577657051 ps
T1536 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.3479555697 Feb 09 03:40:26 PM UTC 25 Feb 09 03:40:57 PM UTC 25 649806367 ps
T1537 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.3012946948 Feb 09 03:39:19 PM UTC 25 Feb 09 03:40:58 PM UTC 25 9283633692 ps
T1538 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.3926939492 Feb 09 03:40:55 PM UTC 25 Feb 09 03:41:09 PM UTC 25 286752191 ps
T1539 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.565683204 Feb 09 03:40:46 PM UTC 25 Feb 09 03:41:26 PM UTC 25 734204089 ps
T529 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.3387388649 Feb 09 03:37:55 PM UTC 25 Feb 09 03:41:35 PM UTC 25 1304626484 ps
T1540 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.3204268922 Feb 09 03:41:22 PM UTC 25 Feb 09 03:41:36 PM UTC 25 182639795 ps
T1541 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.3343073048 Feb 09 03:41:26 PM UTC 25 Feb 09 03:41:36 PM UTC 25 39723001 ps
T895 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.2257372985 Feb 09 03:41:02 PM UTC 25 Feb 09 03:41:56 PM UTC 25 121723212 ps
T863 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.789642814 Feb 09 03:33:32 PM UTC 25 Feb 09 03:42:05 PM UTC 25 4949173960 ps
T1542 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.1299494310 Feb 09 03:42:02 PM UTC 25 Feb 09 03:42:15 PM UTC 25 58708974 ps
T1543 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.3499088249 Feb 09 03:40:08 PM UTC 25 Feb 09 03:42:19 PM UTC 25 1282646877 ps
T601 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.7130793 Feb 09 03:41:58 PM UTC 25 Feb 09 03:42:35 PM UTC 25 661275267 ps
T419 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.3239868601 Feb 09 03:05:58 PM UTC 25 Feb 09 03:42:38 PM UTC 25 16848844380 ps
T853 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.774418177 Feb 09 03:34:31 PM UTC 25 Feb 09 03:42:42 PM UTC 25 24356834321 ps
T1544 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.324746981 Feb 09 03:42:32 PM UTC 25 Feb 09 03:43:10 PM UTC 25 154992116 ps
T1545 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.2153419116 Feb 09 03:42:45 PM UTC 25 Feb 09 03:43:15 PM UTC 25 235669073 ps
T1546 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.3270971415 Feb 09 03:41:53 PM UTC 25 Feb 09 03:43:16 PM UTC 25 5018939967 ps
T1547 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.2608538820 Feb 09 03:43:09 PM UTC 25 Feb 09 03:43:19 PM UTC 25 38452993 ps
T1548 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.4240951980 Feb 09 03:41:35 PM UTC 25 Feb 09 03:43:21 PM UTC 25 8168583822 ps
T1549 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.2220602461 Feb 09 03:42:23 PM UTC 25 Feb 09 03:43:26 PM UTC 25 2718260501 ps
T1550 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.494354797 Feb 09 03:33:42 PM UTC 25 Feb 09 03:43:29 PM UTC 25 7247196064 ps
T1551 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.3039957709 Feb 09 03:43:02 PM UTC 25 Feb 09 03:43:39 PM UTC 25 987861986 ps
T829 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.3105470890 Feb 09 03:35:30 PM UTC 25 Feb 09 03:43:44 PM UTC 25 5747573751 ps
T526 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.4150943218 Feb 09 03:37:54 PM UTC 25 Feb 09 03:43:48 PM UTC 25 3684926865 ps
T1552 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.3335965999 Feb 09 03:43:53 PM UTC 25 Feb 09 03:44:04 PM UTC 25 57845296 ps
T1553 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.1131597068 Feb 09 03:43:56 PM UTC 25 Feb 09 03:44:06 PM UTC 25 37798187 ps
T1554 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.67030193 Feb 09 03:43:47 PM UTC 25 Feb 09 03:44:06 PM UTC 25 66152745 ps
T1555 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.870854465 Feb 09 03:43:36 PM UTC 25 Feb 09 03:44:10 PM UTC 25 309026430 ps
T832 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2547787352 Feb 09 03:10:01 PM UTC 25 Feb 09 03:44:11 PM UTC 25 139773551760 ps
T872 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.4154101928 Feb 09 03:41:10 PM UTC 25 Feb 09 03:44:12 PM UTC 25 479078170 ps
T1556 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.3495177553 Feb 09 03:26:23 PM UTC 25 Feb 09 03:44:22 PM UTC 25 56596595778 ps
T1557 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.3816254926 Feb 09 03:43:06 PM UTC 25 Feb 09 03:44:27 PM UTC 25 1366289274 ps
T848 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.168975028 Feb 09 03:38:33 PM UTC 25 Feb 09 03:44:33 PM UTC 25 9576093590 ps
T1558 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.2386630814 Feb 09 03:40:51 PM UTC 25 Feb 09 03:44:45 PM UTC 25 4644872793 ps
T636 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.3507936907 Feb 09 03:38:59 PM UTC 25 Feb 09 03:44:52 PM UTC 25 4090292691 ps
T1559 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.4269609688 Feb 09 03:44:39 PM UTC 25 Feb 09 03:44:53 PM UTC 25 175279488 ps
T1560 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.579506647 Feb 09 03:41:04 PM UTC 25 Feb 09 03:45:04 PM UTC 25 2372349469 ps
T1561 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.1142352308 Feb 09 03:44:15 PM UTC 25 Feb 09 03:45:06 PM UTC 25 960877307 ps
T1562 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.3446925508 Feb 09 03:44:29 PM UTC 25 Feb 09 03:45:10 PM UTC 25 303249222 ps
T1563 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.3469298500 Feb 09 03:44:50 PM UTC 25 Feb 09 03:45:19 PM UTC 25 211861924 ps
T1564 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.3703107431 Feb 09 03:44:33 PM UTC 25 Feb 09 03:45:29 PM UTC 25 2709844254 ps
T1565 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.2276018046 Feb 09 03:45:00 PM UTC 25 Feb 09 03:45:33 PM UTC 25 554019237 ps
T1566 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.1453833819 Feb 09 03:35:50 PM UTC 25 Feb 09 03:45:38 PM UTC 25 5411646562 ps
T1567 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.1911713127 Feb 09 03:43:42 PM UTC 25 Feb 09 03:45:40 PM UTC 25 2613956367 ps
T1568 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.3450066450 Feb 09 03:44:05 PM UTC 25 Feb 09 03:45:40 PM UTC 25 5965349683 ps
T1569 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.541499146 Feb 09 03:44:55 PM UTC 25 Feb 09 03:45:43 PM UTC 25 846425500 ps
T1570 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.2117191407 Feb 09 03:44:36 PM UTC 25 Feb 09 03:45:43 PM UTC 25 1184481560 ps
T1571 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.327529502 Feb 09 03:45:37 PM UTC 25 Feb 09 03:45:47 PM UTC 25 153287753 ps
T487 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.1063805504 Feb 09 03:45:45 PM UTC 25 Feb 09 03:45:56 PM UTC 25 55137278 ps
T1572 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.386927588 Feb 09 03:45:20 PM UTC 25 Feb 09 03:46:00 PM UTC 25 824560260 ps
T1573 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.4119936815 Feb 09 03:44:07 PM UTC 25 Feb 09 03:46:02 PM UTC 25 9619154779 ps
T1574 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.834288053 Feb 09 03:41:15 PM UTC 25 Feb 09 03:46:04 PM UTC 25 4406649331 ps
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