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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.96 95.39 93.47 95.36 94.22 97.71 99.60


Total test records in report: 2930
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T1794 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.2762262268 Feb 09 04:07:33 PM UTC 25 Feb 09 04:08:23 PM UTC 25 786497057 ps
T1795 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.2864348409 Feb 09 04:08:16 PM UTC 25 Feb 09 04:08:27 PM UTC 25 52389093 ps
T1796 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.1350018973 Feb 09 04:06:59 PM UTC 25 Feb 09 04:08:29 PM UTC 25 1760678887 ps
T861 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.345248433 Feb 09 04:05:57 PM UTC 25 Feb 09 04:08:30 PM UTC 25 364353035 ps
T1797 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.489369922 Feb 09 04:06:31 PM UTC 25 Feb 09 04:08:33 PM UTC 25 8851606992 ps
T1798 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.3170523728 Feb 09 04:08:22 PM UTC 25 Feb 09 04:08:33 PM UTC 25 56306747 ps
T1799 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.4260276735 Feb 09 04:07:31 PM UTC 25 Feb 09 04:08:37 PM UTC 25 1546016102 ps
T1800 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.1849017382 Feb 09 03:54:28 PM UTC 25 Feb 09 04:08:49 PM UTC 25 55791358165 ps
T1801 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.16957314 Feb 09 04:02:47 PM UTC 25 Feb 09 04:08:50 PM UTC 25 3338275269 ps
T1802 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.1704652037 Feb 09 04:08:12 PM UTC 25 Feb 09 04:08:52 PM UTC 25 132841037 ps
T1803 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.3086578313 Feb 09 04:06:19 PM UTC 25 Feb 09 04:08:54 PM UTC 25 887142927 ps
T1804 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.1315500823 Feb 09 04:08:55 PM UTC 25 Feb 09 04:09:12 PM UTC 25 134847467 ps
T1805 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.102855769 Feb 09 04:08:30 PM UTC 25 Feb 09 04:09:17 PM UTC 25 406377215 ps
T1806 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.2143604053 Feb 09 04:09:00 PM UTC 25 Feb 09 04:09:19 PM UTC 25 202002756 ps
T1807 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.3448307983 Feb 09 04:07:47 PM UTC 25 Feb 09 04:09:20 PM UTC 25 1324082257 ps
T1808 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.1491465141 Feb 09 04:08:58 PM UTC 25 Feb 09 04:09:24 PM UTC 25 703500509 ps
T1809 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.3579021376 Feb 09 04:05:58 PM UTC 25 Feb 09 04:09:25 PM UTC 25 2266029063 ps
T1810 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2220441234 Feb 09 04:03:14 PM UTC 25 Feb 09 04:09:31 PM UTC 25 3982585909 ps
T1811 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.2808144990 Feb 09 04:08:29 PM UTC 25 Feb 09 04:09:33 PM UTC 25 1459316903 ps
T1812 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.3149390113 Feb 09 03:57:26 PM UTC 25 Feb 09 04:09:35 PM UTC 25 59859737954 ps
T1813 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.4030511867 Feb 09 04:08:58 PM UTC 25 Feb 09 04:09:41 PM UTC 25 303071753 ps
T1814 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2846076908 Feb 09 04:09:21 PM UTC 25 Feb 09 04:09:45 PM UTC 25 62408572 ps
T1815 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.4139345547 Feb 09 04:09:37 PM UTC 25 Feb 09 04:09:49 PM UTC 25 182090048 ps
T1816 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.1511897905 Feb 09 04:09:44 PM UTC 25 Feb 09 04:09:55 PM UTC 25 51540806 ps
T1817 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.2767908602 Feb 09 03:50:46 PM UTC 25 Feb 09 04:09:57 PM UTC 25 103892536555 ps
T504 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.2660873854 Feb 09 04:02:47 PM UTC 25 Feb 09 04:10:02 PM UTC 25 12761734190 ps
T1818 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.3639369419 Feb 09 04:09:51 PM UTC 25 Feb 09 04:10:15 PM UTC 25 195470221 ps
T1819 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.2313834854 Feb 09 04:08:28 PM UTC 25 Feb 09 04:10:17 PM UTC 25 5120914964 ps
T1820 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.3934824928 Feb 09 04:08:59 PM UTC 25 Feb 09 04:10:26 PM UTC 25 1518196083 ps
T1821 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.2304996863 Feb 09 04:08:23 PM UTC 25 Feb 09 04:10:26 PM UTC 25 9841299868 ps
T1822 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.2194206730 Feb 09 04:05:43 PM UTC 25 Feb 09 04:10:29 PM UTC 25 17656697453 ps
T1823 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.657036468 Feb 09 04:10:04 PM UTC 25 Feb 09 04:10:34 PM UTC 25 249575256 ps
T1824 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.1508655970 Feb 09 04:09:51 PM UTC 25 Feb 09 04:10:41 PM UTC 25 1095731364 ps
T1825 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_aliasing.3492418100 Feb 09 02:48:52 PM UTC 25 Feb 09 04:10:48 PM UTC 25 27724481007 ps
T1826 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.1146252353 Feb 09 04:10:10 PM UTC 25 Feb 09 04:10:54 PM UTC 25 1000871838 ps
T1827 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.1202717164 Feb 09 04:10:53 PM UTC 25 Feb 09 04:11:03 PM UTC 25 41169242 ps
T867 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1457070300 Feb 09 03:57:59 PM UTC 25 Feb 09 04:11:03 PM UTC 25 5117544676 ps
T1828 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.2059470478 Feb 09 04:10:57 PM UTC 25 Feb 09 04:11:06 PM UTC 25 50261893 ps
T1829 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.2351104691 Feb 09 04:09:47 PM UTC 25 Feb 09 04:11:07 PM UTC 25 3529357540 ps
T1830 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.3218251289 Feb 09 04:10:54 PM UTC 25 Feb 09 04:11:09 PM UTC 25 83602356 ps
T1831 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.2067708638 Feb 09 04:10:18 PM UTC 25 Feb 09 04:11:10 PM UTC 25 1121654676 ps
T1832 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.1419560143 Feb 09 04:10:20 PM UTC 25 Feb 09 04:11:14 PM UTC 25 1093427162 ps
T1833 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.2172268004 Feb 09 04:10:26 PM UTC 25 Feb 09 04:11:15 PM UTC 25 846580927 ps
T1834 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.3044108791 Feb 09 04:09:43 PM UTC 25 Feb 09 04:11:16 PM UTC 25 8194716904 ps
T1835 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.4267956158 Feb 09 04:08:00 PM UTC 25 Feb 09 04:11:29 PM UTC 25 5857665511 ps
T1836 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.1666795477 Feb 09 04:00:51 PM UTC 25 Feb 09 04:11:31 PM UTC 25 17075713035 ps
T1837 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.3939101143 Feb 09 04:07:05 PM UTC 25 Feb 09 04:11:31 PM UTC 25 18857114418 ps
T623 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.2952086382 Feb 09 04:10:46 PM UTC 25 Feb 09 04:11:32 PM UTC 25 1408202767 ps
T1838 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.677180039 Feb 09 04:04:39 PM UTC 25 Feb 09 04:11:41 PM UTC 25 2369016548 ps
T1839 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.1837222081 Feb 09 04:11:23 PM UTC 25 Feb 09 04:11:45 PM UTC 25 146557076 ps
T1840 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.406028462 Feb 09 04:11:32 PM UTC 25 Feb 09 04:11:47 PM UTC 25 104713189 ps
T1841 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.1005766341 Feb 09 04:11:08 PM UTC 25 Feb 09 04:12:00 PM UTC 25 3227843058 ps
T1842 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.1001475669 Feb 09 04:11:41 PM UTC 25 Feb 09 04:12:00 PM UTC 25 397887258 ps
T1843 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.905698959 Feb 09 04:11:38 PM UTC 25 Feb 09 04:12:01 PM UTC 25 247005285 ps
T1844 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.3540566368 Feb 09 04:11:36 PM UTC 25 Feb 09 04:12:03 PM UTC 25 935422431 ps
T869 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.22795932 Feb 09 04:09:17 PM UTC 25 Feb 09 04:12:13 PM UTC 25 324867703 ps
T1845 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.2462402617 Feb 09 04:12:09 PM UTC 25 Feb 09 04:12:20 PM UTC 25 49647846 ps
T1846 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.60883601 Feb 09 04:11:42 PM UTC 25 Feb 09 04:12:22 PM UTC 25 825130028 ps
T1847 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.581133184 Feb 09 04:11:57 PM UTC 25 Feb 09 04:12:25 PM UTC 25 497824744 ps
T1848 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.1707904319 Feb 09 04:11:02 PM UTC 25 Feb 09 04:12:32 PM UTC 25 7558838183 ps
T1849 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.1110532601 Feb 09 03:54:21 PM UTC 25 Feb 09 04:12:35 PM UTC 25 93124834852 ps
T1850 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.1093669946 Feb 09 04:11:15 PM UTC 25 Feb 09 04:12:42 PM UTC 25 1697336788 ps
T1851 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.4055740833 Feb 09 04:12:28 PM UTC 25 Feb 09 04:12:47 PM UTC 25 125880041 ps
T1852 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.2240081036 Feb 09 04:11:52 PM UTC 25 Feb 09 04:12:47 PM UTC 25 29473158 ps
T1853 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.488460890 Feb 09 03:03:35 PM UTC 25 Feb 09 04:12:48 PM UTC 25 29326704146 ps
T542 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.979648458 Feb 09 04:09:15 PM UTC 25 Feb 09 04:12:51 PM UTC 25 2634247211 ps
T1854 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.3413761343 Feb 09 04:12:22 PM UTC 25 Feb 09 04:12:53 PM UTC 25 233607330 ps
T1855 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.3226133440 Feb 09 03:58:26 PM UTC 25 Feb 09 04:13:05 PM UTC 25 16367545235 ps
T1856 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.82368776 Feb 09 04:12:47 PM UTC 25 Feb 09 04:13:12 PM UTC 25 211894214 ps
T1857 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.2991400133 Feb 09 04:03:47 PM UTC 25 Feb 09 04:13:15 PM UTC 25 31996824655 ps
T1858 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.3856382853 Feb 09 04:01:58 PM UTC 25 Feb 09 04:13:15 PM UTC 25 46930369419 ps
T1859 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.2751005428 Feb 09 04:11:34 PM UTC 25 Feb 09 04:13:24 PM UTC 25 5656189467 ps
T1860 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.360508844 Feb 09 04:13:00 PM UTC 25 Feb 09 04:13:27 PM UTC 25 163404119 ps
T1861 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.2572550544 Feb 09 04:13:18 PM UTC 25 Feb 09 04:13:28 PM UTC 25 42433326 ps
T1862 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.3544692570 Feb 09 04:13:14 PM UTC 25 Feb 09 04:13:30 PM UTC 25 228972550 ps
T850 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.416640760 Feb 09 03:59:05 PM UTC 25 Feb 09 04:13:30 PM UTC 25 41631512053 ps
T1863 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.1797516882 Feb 09 04:00:09 PM UTC 25 Feb 09 04:13:30 PM UTC 25 74625238967 ps
T1864 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.2765190207 Feb 09 04:12:09 PM UTC 25 Feb 09 04:13:32 PM UTC 25 3738502395 ps
T1865 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3152652436 Feb 09 04:11:59 PM UTC 25 Feb 09 04:13:36 PM UTC 25 835328699 ps
T1866 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.2950471278 Feb 09 04:12:52 PM UTC 25 Feb 09 04:13:36 PM UTC 25 332783788 ps
T1867 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.4085842406 Feb 09 04:07:57 PM UTC 25 Feb 09 04:13:39 PM UTC 25 577386847 ps
T1868 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.1813997533 Feb 09 04:12:13 PM UTC 25 Feb 09 04:13:41 PM UTC 25 8144067381 ps
T1869 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.2220159702 Feb 09 04:09:19 PM UTC 25 Feb 09 04:13:42 PM UTC 25 6333552377 ps
T1870 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.2136468158 Feb 09 03:01:16 PM UTC 25 Feb 09 04:13:43 PM UTC 25 29789746000 ps
T1871 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.1185078836 Feb 09 04:13:15 PM UTC 25 Feb 09 04:13:43 PM UTC 25 146625480 ps
T1872 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.1628235168 Feb 09 04:05:40 PM UTC 25 Feb 09 04:13:57 PM UTC 25 33894009055 ps
T1873 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.3376418613 Feb 09 03:57:26 PM UTC 25 Feb 09 04:14:01 PM UTC 25 63431410839 ps
T847 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.937744608 Feb 09 03:50:53 PM UTC 25 Feb 09 04:14:03 PM UTC 25 92404834671 ps
T1874 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.1672169865 Feb 09 04:13:52 PM UTC 25 Feb 09 04:14:05 PM UTC 25 270161666 ps
T1875 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.609849882 Feb 09 04:10:31 PM UTC 25 Feb 09 04:14:08 PM UTC 25 2683720923 ps
T1876 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.287132256 Feb 09 04:14:03 PM UTC 25 Feb 09 04:14:08 PM UTC 25 5569404 ps
T1877 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.1824429013 Feb 09 04:13:54 PM UTC 25 Feb 09 04:14:11 PM UTC 25 330908905 ps
T1878 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.3447753349 Feb 09 04:13:41 PM UTC 25 Feb 09 04:14:14 PM UTC 25 874138294 ps
T1879 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.774240324 Feb 09 04:13:55 PM UTC 25 Feb 09 04:14:16 PM UTC 25 297472831 ps
T1880 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.2302766180 Feb 09 04:14:07 PM UTC 25 Feb 09 04:14:17 PM UTC 25 41347290 ps
T1881 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.4054781771 Feb 09 04:14:05 PM UTC 25 Feb 09 04:14:17 PM UTC 25 238299220 ps
T1882 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.1553401429 Feb 09 04:05:52 PM UTC 25 Feb 09 04:14:23 PM UTC 25 12980227970 ps
T1883 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.420876411 Feb 09 04:12:29 PM UTC 25 Feb 09 04:14:27 PM UTC 25 10083781213 ps
T1884 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.2187776741 Feb 09 04:13:42 PM UTC 25 Feb 09 04:14:34 PM UTC 25 435876093 ps
T1885 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.2823307148 Feb 09 04:12:50 PM UTC 25 Feb 09 04:14:35 PM UTC 25 2809444400 ps
T855 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.3971616452 Feb 09 03:30:07 PM UTC 25 Feb 09 04:14:40 PM UTC 25 147412676978 ps
T1886 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.3224141568 Feb 09 04:13:20 PM UTC 25 Feb 09 04:14:43 PM UTC 25 6929575324 ps
T1887 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.1709216670 Feb 09 04:12:38 PM UTC 25 Feb 09 04:14:48 PM UTC 25 3072749284 ps
T1888 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.2245752948 Feb 09 04:13:55 PM UTC 25 Feb 09 04:14:50 PM UTC 25 1483801872 ps
T1889 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.1604694840 Feb 09 04:13:52 PM UTC 25 Feb 09 04:14:53 PM UTC 25 596820366 ps
T1890 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.1321328764 Feb 09 04:14:41 PM UTC 25 Feb 09 04:14:59 PM UTC 25 122245871 ps
T1891 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.1960948355 Feb 09 04:14:41 PM UTC 25 Feb 09 04:14:59 PM UTC 25 190943022 ps
T1892 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.611032517 Feb 09 04:14:27 PM UTC 25 Feb 09 04:15:01 PM UTC 25 357071705 ps
T1893 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.3628877487 Feb 09 04:13:31 PM UTC 25 Feb 09 04:15:03 PM UTC 25 4405247138 ps
T1894 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.2878437429 Feb 09 04:14:51 PM UTC 25 Feb 09 04:15:13 PM UTC 25 148543819 ps
T1895 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.301692448 Feb 09 04:14:28 PM UTC 25 Feb 09 04:15:16 PM UTC 25 475965757 ps
T1896 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.2936445500 Feb 09 04:15:03 PM UTC 25 Feb 09 04:15:17 PM UTC 25 174969827 ps
T1897 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.1909448110 Feb 09 04:15:11 PM UTC 25 Feb 09 04:15:19 PM UTC 25 51429185 ps
T1898 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.2608548983 Feb 09 04:07:08 PM UTC 25 Feb 09 04:15:20 PM UTC 25 29284691208 ps
T1899 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.3396819314 Feb 09 04:14:39 PM UTC 25 Feb 09 04:15:25 PM UTC 25 997080233 ps
T1900 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.776211673 Feb 09 04:14:43 PM UTC 25 Feb 09 04:15:27 PM UTC 25 291235024 ps
T1901 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.1189175375 Feb 09 04:15:26 PM UTC 25 Feb 09 04:15:39 PM UTC 25 72302361 ps
T1902 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.1379235583 Feb 09 04:15:42 PM UTC 25 Feb 09 04:15:59 PM UTC 25 356921616 ps
T1903 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.390337416 Feb 09 04:14:20 PM UTC 25 Feb 09 04:16:03 PM UTC 25 4406152417 ps
T1904 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.2930480865 Feb 09 04:14:11 PM UTC 25 Feb 09 04:16:07 PM UTC 25 10454573867 ps
T1905 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.3312984635 Feb 09 04:15:46 PM UTC 25 Feb 09 04:16:30 PM UTC 25 294265192 ps
T822 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.2860456101 Feb 09 04:13:01 PM UTC 25 Feb 09 04:16:32 PM UTC 25 5204397676 ps
T1906 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.1401984019 Feb 09 04:15:46 PM UTC 25 Feb 09 04:16:34 PM UTC 25 849667599 ps
T1907 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.1565087363 Feb 09 04:16:32 PM UTC 25 Feb 09 04:16:40 PM UTC 25 46177140 ps
T1908 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.1477082403 Feb 09 04:16:36 PM UTC 25 Feb 09 04:16:47 PM UTC 25 57803739 ps
T1909 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.376298979 Feb 09 04:15:28 PM UTC 25 Feb 09 04:16:48 PM UTC 25 686668146 ps
T1910 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.521292837 Feb 09 04:14:00 PM UTC 25 Feb 09 04:16:53 PM UTC 25 2115900135 ps
T1911 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.3835658516 Feb 09 04:15:42 PM UTC 25 Feb 09 04:17:01 PM UTC 25 2212324438 ps
T1912 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.2211074830 Feb 09 04:14:34 PM UTC 25 Feb 09 04:17:07 PM UTC 25 2977581479 ps
T1913 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.886868593 Feb 09 04:15:20 PM UTC 25 Feb 09 04:17:07 PM UTC 25 2284202256 ps
T1914 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.872403285 Feb 09 04:11:32 PM UTC 25 Feb 09 04:17:08 PM UTC 25 16558044072 ps
T1915 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.1307953633 Feb 09 04:15:11 PM UTC 25 Feb 09 04:17:13 PM UTC 25 8455276377 ps
T1916 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.797555379 Feb 09 04:15:18 PM UTC 25 Feb 09 04:17:20 PM UTC 25 5652040011 ps
T1917 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.3188986838 Feb 09 03:54:36 PM UTC 25 Feb 09 04:17:21 PM UTC 25 92477292707 ps
T1918 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.228618536 Feb 09 04:17:00 PM UTC 25 Feb 09 04:17:30 PM UTC 25 318852948 ps
T873 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.1810530776 Feb 09 04:15:52 PM UTC 25 Feb 09 04:17:32 PM UTC 25 196881601 ps
T1919 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.3817922419 Feb 09 04:09:59 PM UTC 25 Feb 09 04:17:37 PM UTC 25 43472711959 ps
T1920 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.169927516 Feb 09 04:17:07 PM UTC 25 Feb 09 04:17:46 PM UTC 25 353722047 ps
T1921 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.1288394529 Feb 09 04:16:06 PM UTC 25 Feb 09 04:17:48 PM UTC 25 924604225 ps
T1922 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.3071060255 Feb 09 04:17:31 PM UTC 25 Feb 09 04:17:52 PM UTC 25 431262662 ps
T1923 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.4274811341 Feb 09 04:15:02 PM UTC 25 Feb 09 04:17:53 PM UTC 25 5688327026 ps
T1924 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.107485336 Feb 09 04:17:38 PM UTC 25 Feb 09 04:17:55 PM UTC 25 86619390 ps
T543 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.4018698818 Feb 09 04:11:42 PM UTC 25 Feb 09 04:17:58 PM UTC 25 11089019662 ps
T1925 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.2301830140 Feb 09 04:17:20 PM UTC 25 Feb 09 04:18:10 PM UTC 25 914507864 ps
T1926 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.2028992613 Feb 09 04:18:02 PM UTC 25 Feb 09 04:18:11 PM UTC 25 57117476 ps
T1927 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.3916163400 Feb 09 04:17:35 PM UTC 25 Feb 09 04:18:21 PM UTC 25 1299779298 ps
T1928 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.542016324 Feb 09 04:18:14 PM UTC 25 Feb 09 04:18:24 PM UTC 25 49751157 ps
T1929 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.3025336719 Feb 09 04:17:00 PM UTC 25 Feb 09 04:18:25 PM UTC 25 5352393249 ps
T1930 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.2702077048 Feb 09 04:13:13 PM UTC 25 Feb 09 04:18:35 PM UTC 25 9733870947 ps
T823 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.1768160371 Feb 09 03:49:37 PM UTC 25 Feb 09 04:18:36 PM UTC 25 101140578051 ps
T1931 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.3624177131 Feb 09 04:12:29 PM UTC 25 Feb 09 04:18:36 PM UTC 25 24271466431 ps
T1932 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.3208629878 Feb 09 04:18:18 PM UTC 25 Feb 09 04:18:37 PM UTC 25 124611586 ps
T1933 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.2703601019 Feb 09 04:03:53 PM UTC 25 Feb 09 04:18:38 PM UTC 25 53234900677 ps
T885 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.3859833803 Feb 09 04:16:27 PM UTC 25 Feb 09 04:18:39 PM UTC 25 494079476 ps
T1934 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.3391984714 Feb 09 04:13:43 PM UTC 25 Feb 09 04:18:51 PM UTC 25 23794245472 ps
T1935 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.388868103 Feb 09 04:17:36 PM UTC 25 Feb 09 04:18:58 PM UTC 25 2442144090 ps
T1936 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.2343934532 Feb 09 04:16:57 PM UTC 25 Feb 09 04:18:59 PM UTC 25 8076618531 ps
T1937 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.2396584879 Feb 09 04:18:38 PM UTC 25 Feb 09 04:19:09 PM UTC 25 214920925 ps
T1938 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.4022651094 Feb 09 04:18:22 PM UTC 25 Feb 09 04:19:10 PM UTC 25 524565693 ps
T1939 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.2428368330 Feb 09 04:19:05 PM UTC 25 Feb 09 04:19:17 PM UTC 25 67672271 ps
T1940 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.2471359035 Feb 09 04:18:52 PM UTC 25 Feb 09 04:19:18 PM UTC 25 685210243 ps
T1941 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.1232835428 Feb 09 04:05:32 PM UTC 25 Feb 09 04:19:24 PM UTC 25 82471980107 ps
T1942 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.2691381638 Feb 09 04:19:19 PM UTC 25 Feb 09 04:19:30 PM UTC 25 50418776 ps
T1943 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.1298113624 Feb 09 04:18:19 PM UTC 25 Feb 09 04:19:30 PM UTC 25 4066456594 ps
T1944 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.369309448 Feb 09 04:18:50 PM UTC 25 Feb 09 04:19:33 PM UTC 25 1010434800 ps
T1945 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.1097630710 Feb 09 04:19:04 PM UTC 25 Feb 09 04:19:33 PM UTC 25 204601567 ps
T1946 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.1613039212 Feb 09 04:19:25 PM UTC 25 Feb 09 04:19:35 PM UTC 25 35649564 ps
T870 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.641420322 Feb 09 04:10:43 PM UTC 25 Feb 09 04:19:36 PM UTC 25 5606013059 ps
T1947 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.3568249119 Feb 09 04:17:57 PM UTC 25 Feb 09 04:19:38 PM UTC 25 2357595831 ps
T1948 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.2787849686 Feb 09 03:08:33 PM UTC 25 Feb 09 04:19:41 PM UTC 25 32350566931 ps
T1949 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.2574125531 Feb 09 04:19:05 PM UTC 25 Feb 09 04:19:45 PM UTC 25 101715448 ps
T1950 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.203953760 Feb 09 04:10:00 PM UTC 25 Feb 09 04:19:47 PM UTC 25 33775635304 ps
T1951 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.1003096968 Feb 09 04:15:02 PM UTC 25 Feb 09 04:19:50 PM UTC 25 2674555500 ps
T1952 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.444493071 Feb 09 04:20:55 PM UTC 25 Feb 09 04:21:48 PM UTC 25 1859373184 ps
T1953 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.1731143453 Feb 09 04:19:03 PM UTC 25 Feb 09 04:19:52 PM UTC 25 1351634971 ps
T1954 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.3991849658 Feb 09 03:37:20 PM UTC 25 Feb 09 04:19:58 PM UTC 25 146235375519 ps
T1955 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.2606842311 Feb 09 04:17:48 PM UTC 25 Feb 09 04:19:59 PM UTC 25 3529660663 ps
T1956 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.2467936491 Feb 09 04:19:44 PM UTC 25 Feb 09 04:20:02 PM UTC 25 135910877 ps
T1957 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.4155602324 Feb 09 04:19:37 PM UTC 25 Feb 09 04:20:10 PM UTC 25 337617443 ps
T1958 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.4096703296 Feb 09 03:40:23 PM UTC 25 Feb 09 04:20:15 PM UTC 25 146244180265 ps
T1959 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.3606590831 Feb 09 04:15:53 PM UTC 25 Feb 09 04:20:19 PM UTC 25 3055634696 ps
T1960 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.1636788265 Feb 09 04:20:00 PM UTC 25 Feb 09 04:20:21 PM UTC 25 203755009 ps
T1961 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.3993550453 Feb 09 04:20:15 PM UTC 25 Feb 09 04:20:25 PM UTC 25 45933151 ps
T1962 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.72625481 Feb 09 04:20:17 PM UTC 25 Feb 09 04:20:26 PM UTC 25 41003394 ps
T1963 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.678889225 Feb 09 04:20:03 PM UTC 25 Feb 09 04:20:28 PM UTC 25 529542444 ps
T871 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3927885322 Feb 09 04:17:48 PM UTC 25 Feb 09 04:20:31 PM UTC 25 1063950801 ps
T1964 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.4283729747 Feb 09 04:20:01 PM UTC 25 Feb 09 04:20:34 PM UTC 25 538045007 ps
T1965 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.271931317 Feb 09 03:57:40 PM UTC 25 Feb 09 04:20:34 PM UTC 25 83134942248 ps
T1966 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.4098579585 Feb 09 04:18:39 PM UTC 25 Feb 09 04:20:35 PM UTC 25 6998866114 ps
T1967 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.2001752661 Feb 09 03:21:30 PM UTC 25 Feb 09 04:20:39 PM UTC 25 27704944806 ps
T1968 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.3028617892 Feb 09 04:20:01 PM UTC 25 Feb 09 04:20:45 PM UTC 25 945004750 ps
T1969 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.186887090 Feb 09 04:19:27 PM UTC 25 Feb 09 04:20:45 PM UTC 25 7250562492 ps
T1970 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.978268896 Feb 09 04:18:16 PM UTC 25 Feb 09 04:20:47 PM UTC 25 8857683661 ps
T1971 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.2492859689 Feb 09 04:20:33 PM UTC 25 Feb 09 04:20:54 PM UTC 25 184361344 ps
T1972 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.1798478991 Feb 09 04:20:06 PM UTC 25 Feb 09 04:20:56 PM UTC 25 36426569 ps
T1973 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.2470204891 Feb 09 03:16:56 PM UTC 25 Feb 09 04:20:58 PM UTC 25 28320453428 ps
T1974 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.325944917 Feb 09 04:19:56 PM UTC 25 Feb 09 04:21:00 PM UTC 25 1151522710 ps
T1975 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.3636684272 Feb 09 04:20:54 PM UTC 25 Feb 09 04:21:11 PM UTC 25 182209997 ps
T1976 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.2485737425 Feb 09 04:20:26 PM UTC 25 Feb 09 04:21:15 PM UTC 25 1110785809 ps
T1977 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1507244810 Feb 09 04:00:22 PM UTC 25 Feb 09 04:21:22 PM UTC 25 83106154193 ps
T1978 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.2404369811 Feb 09 04:19:35 PM UTC 25 Feb 09 04:21:23 PM UTC 25 6487970699 ps
T1979 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3274148513 Feb 09 04:21:13 PM UTC 25 Feb 09 04:21:23 PM UTC 25 42902320 ps
T1980 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.736551554 Feb 09 04:21:13 PM UTC 25 Feb 09 04:21:27 PM UTC 25 191274238 ps
T1981 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.2553691766 Feb 09 04:20:47 PM UTC 25 Feb 09 04:21:28 PM UTC 25 571772673 ps
T520 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.2326096617 Feb 09 04:19:59 PM UTC 25 Feb 09 04:21:30 PM UTC 25 2261517522 ps
T1982 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.258309542 Feb 09 04:20:56 PM UTC 25 Feb 09 04:21:34 PM UTC 25 805037122 ps
T1983 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.2686804010 Feb 09 04:21:26 PM UTC 25 Feb 09 04:21:35 PM UTC 25 36251374 ps
T1984 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.1190620926 Feb 09 04:21:01 PM UTC 25 Feb 09 04:21:35 PM UTC 25 224168152 ps
T1985 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.3438563519 Feb 09 04:20:26 PM UTC 25 Feb 09 04:21:37 PM UTC 25 3673149263 ps
T1986 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.3234757218 Feb 09 04:20:19 PM UTC 25 Feb 09 04:21:44 PM UTC 25 8082229936 ps
T1987 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.1069259064 Feb 09 04:21:27 PM UTC 25 Feb 09 04:21:59 PM UTC 25 327712032 ps
T1988 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.4166223174 Feb 09 04:21:53 PM UTC 25 Feb 09 04:22:12 PM UTC 25 262330639 ps
T1989 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.946073019 Feb 09 04:19:04 PM UTC 25 Feb 09 04:22:12 PM UTC 25 5136935470 ps
T1990 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.4056025942 Feb 09 04:15:25 PM UTC 25 Feb 09 04:22:14 PM UTC 25 25648743684 ps
T1991 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.574349298 Feb 09 04:22:05 PM UTC 25 Feb 09 04:22:15 PM UTC 25 41219202 ps
T1992 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.1660584136 Feb 09 04:22:00 PM UTC 25 Feb 09 04:22:16 PM UTC 25 237672098 ps
T1993 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.1241501011 Feb 09 04:21:48 PM UTC 25 Feb 09 04:22:18 PM UTC 25 314468422 ps
T1994 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.949796940 Feb 09 04:22:07 PM UTC 25 Feb 09 04:22:19 PM UTC 25 223414067 ps
T1995 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.222191042 Feb 09 04:21:52 PM UTC 25 Feb 09 04:22:21 PM UTC 25 187816472 ps
T1996 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.999107862 Feb 09 04:19:58 PM UTC 25 Feb 09 04:22:21 PM UTC 25 9432598547 ps
T1997 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.894950369 Feb 09 04:21:22 PM UTC 25 Feb 09 04:22:34 PM UTC 25 6394330821 ps
T893 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.2088554875 Feb 09 04:13:06 PM UTC 25 Feb 09 04:22:40 PM UTC 25 10387380428 ps
T1998 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.444658582 Feb 09 04:14:36 PM UTC 25 Feb 09 04:22:51 PM UTC 25 28411504227 ps
T1999 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.1808528225 Feb 09 04:21:20 PM UTC 25 Feb 09 04:22:56 PM UTC 25 5658588928 ps
T2000 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.3596597989 Feb 09 04:22:36 PM UTC 25 Feb 09 04:23:01 PM UTC 25 648719709 ps
T2001 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.2262725197 Feb 09 04:21:53 PM UTC 25 Feb 09 04:23:03 PM UTC 25 1802210282 ps
T894 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.4060482202 Feb 09 04:21:11 PM UTC 25 Feb 09 04:23:04 PM UTC 25 1612774267 ps
T892 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.563203164 Feb 09 04:19:06 PM UTC 25 Feb 09 04:23:09 PM UTC 25 3217959617 ps
T2002 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.3791137621 Feb 09 04:17:15 PM UTC 25 Feb 09 04:23:18 PM UTC 25 28774126365 ps
T2003 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.1563470913 Feb 09 04:22:40 PM UTC 25 Feb 09 04:23:18 PM UTC 25 377156243 ps
T2004 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.3527414627 Feb 09 04:22:57 PM UTC 25 Feb 09 04:23:22 PM UTC 25 174932525 ps
T2005 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.541572980 Feb 09 04:21:48 PM UTC 25 Feb 09 04:23:28 PM UTC 25 2695244357 ps
T2006 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.3394403824 Feb 09 04:20:11 PM UTC 25 Feb 09 04:23:32 PM UTC 25 645438385 ps
T2007 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.4094923219 Feb 09 04:22:45 PM UTC 25 Feb 09 04:23:34 PM UTC 25 558878008 ps
T2008 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.3758844732 Feb 09 04:22:00 PM UTC 25 Feb 09 04:23:41 PM UTC 25 128573957 ps
T2009 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.503364227 Feb 09 04:23:29 PM UTC 25 Feb 09 04:23:43 PM UTC 25 201983028 ps
T2010 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.4005497313 Feb 09 04:23:33 PM UTC 25 Feb 09 04:23:43 PM UTC 25 46420961 ps
T2011 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.691659075 Feb 09 04:23:08 PM UTC 25 Feb 09 04:23:46 PM UTC 25 301272559 ps
T2012 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.4273979361 Feb 09 04:20:43 PM UTC 25 Feb 09 04:23:49 PM UTC 25 13263820681 ps
T2013 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.1476117433 Feb 09 04:21:57 PM UTC 25 Feb 09 04:23:50 PM UTC 25 1495000748 ps
T2014 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.1193741246 Feb 09 04:22:48 PM UTC 25 Feb 09 04:23:51 PM UTC 25 1480877363 ps
T2015 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.3567150549 Feb 09 04:21:03 PM UTC 25 Feb 09 04:23:59 PM UTC 25 4957847141 ps
T2016 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.1023866241 Feb 09 04:17:15 PM UTC 25 Feb 09 04:23:59 PM UTC 25 26638415089 ps
T2017 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.903865182 Feb 09 04:22:25 PM UTC 25 Feb 09 04:24:04 PM UTC 25 9731828527 ps
T2018 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.511681545 Feb 09 04:22:44 PM UTC 25 Feb 09 04:24:11 PM UTC 25 1528903202 ps
T2019 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.1627891335 Feb 09 04:22:38 PM UTC 25 Feb 09 04:24:17 PM UTC 25 4639076224 ps
T2020 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.1928618612 Feb 09 04:23:53 PM UTC 25 Feb 09 04:24:20 PM UTC 25 191502779 ps
T2021 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.2198829085 Feb 09 04:20:11 PM UTC 25 Feb 09 04:24:32 PM UTC 25 3447216651 ps
T2022 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.2268115726 Feb 09 04:24:03 PM UTC 25 Feb 09 04:24:35 PM UTC 25 249794615 ps
T2023 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.495386807 Feb 09 04:23:50 PM UTC 25 Feb 09 04:24:41 PM UTC 25 1280551692 ps