Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.95 95.51 93.50 95.41 94.18 97.57 99.53


Total test records in report: 2918
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html
T1803 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.3361359522 Oct 15 03:41:03 PM UTC 24 Oct 15 03:41:32 PM UTC 24 321124365 ps
T1804 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.256315371 Oct 15 03:40:09 PM UTC 24 Oct 15 03:41:37 PM UTC 24 8636052301 ps
T1805 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.2555483431 Oct 15 03:40:41 PM UTC 24 Oct 15 03:41:46 PM UTC 24 1649988806 ps
T1806 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.2384382207 Oct 15 03:41:31 PM UTC 24 Oct 15 03:41:49 PM UTC 24 90045899 ps
T1807 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.3452971280 Oct 15 03:41:36 PM UTC 24 Oct 15 03:41:55 PM UTC 24 142682577 ps
T792 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.149723875 Oct 15 03:36:23 PM UTC 24 Oct 15 03:41:57 PM UTC 24 7447860676 ps
T1808 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.2645417992 Oct 15 03:41:45 PM UTC 24 Oct 15 03:42:01 PM UTC 24 30524197 ps
T1809 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.2560658177 Oct 15 03:40:57 PM UTC 24 Oct 15 03:42:03 PM UTC 24 5878062606 ps
T1810 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.2416943150 Oct 15 03:39:03 PM UTC 24 Oct 15 03:42:04 PM UTC 24 17303783483 ps
T1811 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.3875426930 Oct 15 03:41:54 PM UTC 24 Oct 15 03:42:07 PM UTC 24 147226767 ps
T1812 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.441562963 Oct 15 03:42:00 PM UTC 24 Oct 15 03:42:09 PM UTC 24 57951181 ps
T1813 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.4167619800 Oct 15 03:36:00 PM UTC 24 Oct 15 03:42:09 PM UTC 24 26344195288 ps
T1814 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.2755338161 Oct 15 03:40:56 PM UTC 24 Oct 15 03:42:11 PM UTC 24 4227688723 ps
T1815 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.3512840071 Oct 15 03:37:34 PM UTC 24 Oct 15 03:42:16 PM UTC 24 1868850794 ps
T1816 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.4189868931 Oct 15 03:41:28 PM UTC 24 Oct 15 03:42:17 PM UTC 24 1447625098 ps
T1817 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.968529657 Oct 15 03:34:35 PM UTC 24 Oct 15 03:42:21 PM UTC 24 27495802205 ps
T1818 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.1005076813 Oct 15 03:41:30 PM UTC 24 Oct 15 03:42:26 PM UTC 24 618664286 ps
T861 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.1008175871 Oct 15 03:41:49 PM UTC 24 Oct 15 03:42:27 PM UTC 24 154566759 ps
T1819 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.1714755248 Oct 15 03:38:10 PM UTC 24 Oct 15 03:42:28 PM UTC 24 16786591064 ps
T1820 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.946636098 Oct 15 03:40:47 PM UTC 24 Oct 15 03:42:34 PM UTC 24 1287138505 ps
T1821 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.765981687 Oct 15 03:40:48 PM UTC 24 Oct 15 03:42:35 PM UTC 24 1315307138 ps
T1822 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.3239416318 Oct 15 03:42:20 PM UTC 24 Oct 15 03:42:44 PM UTC 24 258245208 ps
T1823 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.2360428870 Oct 15 03:42:37 PM UTC 24 Oct 15 03:42:45 PM UTC 24 24954094 ps
T1824 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.4149899573 Oct 15 03:38:12 PM UTC 24 Oct 15 03:42:46 PM UTC 24 29193720194 ps
T1825 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.1251409241 Oct 15 03:42:16 PM UTC 24 Oct 15 03:42:49 PM UTC 24 807412213 ps
T1826 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.3587941969 Oct 15 03:42:32 PM UTC 24 Oct 15 03:42:52 PM UTC 24 241953017 ps
T1827 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.2767569446 Oct 15 03:41:27 PM UTC 24 Oct 15 03:42:57 PM UTC 24 1236047845 ps
T1828 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.2094042612 Oct 15 03:42:50 PM UTC 24 Oct 15 03:42:59 PM UTC 24 38770924 ps
T1829 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3505512299 Oct 15 03:38:34 PM UTC 24 Oct 15 03:43:00 PM UTC 24 527321260 ps
T1830 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.3388696431 Oct 15 03:32:24 PM UTC 24 Oct 15 03:43:00 PM UTC 24 40293406846 ps
T1831 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.2688929976 Oct 15 03:42:53 PM UTC 24 Oct 15 03:43:01 PM UTC 24 38907544 ps
T836 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.2515492685 Oct 15 03:37:30 PM UTC 24 Oct 15 03:43:02 PM UTC 24 10421371671 ps
T1832 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.3371473885 Oct 15 03:42:42 PM UTC 24 Oct 15 03:43:06 PM UTC 24 133417490 ps
T874 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1416242314 Oct 15 03:40:05 PM UTC 24 Oct 15 03:43:10 PM UTC 24 872590113 ps
T1833 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.2150964257 Oct 15 03:42:48 PM UTC 24 Oct 15 03:43:13 PM UTC 24 344683537 ps
T1834 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1248471082 Oct 15 03:42:12 PM UTC 24 Oct 15 03:43:17 PM UTC 24 4506498558 ps
T1835 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.3227504020 Oct 15 03:42:04 PM UTC 24 Oct 15 03:43:31 PM UTC 24 9321243238 ps
T1836 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.4004884222 Oct 15 03:43:19 PM UTC 24 Oct 15 03:43:31 PM UTC 24 136568286 ps
T1837 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.415255845 Oct 15 03:43:21 PM UTC 24 Oct 15 03:43:34 PM UTC 24 59334790 ps
T1838 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.1340340300 Oct 15 03:42:37 PM UTC 24 Oct 15 03:43:37 PM UTC 24 1262794114 ps
T1839 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.3693954614 Oct 15 03:43:09 PM UTC 24 Oct 15 03:43:42 PM UTC 24 350956755 ps
T1840 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.760051946 Oct 15 03:43:23 PM UTC 24 Oct 15 03:43:42 PM UTC 24 117256743 ps
T1841 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.3808123954 Oct 15 03:43:15 PM UTC 24 Oct 15 03:43:47 PM UTC 24 321949735 ps
T1842 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.2002034001 Oct 15 03:43:39 PM UTC 24 Oct 15 03:43:50 PM UTC 24 246207709 ps
T1843 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.1124454598 Oct 15 03:42:33 PM UTC 24 Oct 15 03:43:53 PM UTC 24 2378789404 ps
T1844 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.205175431 Oct 15 03:32:41 PM UTC 24 Oct 15 03:44:01 PM UTC 24 18435420742 ps
T1845 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.2290711108 Oct 15 03:43:29 PM UTC 24 Oct 15 03:44:01 PM UTC 24 71741232 ps
T1846 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1535167971 Oct 15 03:38:27 PM UTC 24 Oct 15 03:44:03 PM UTC 24 2460229986 ps
T1847 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.2299516837 Oct 15 03:43:56 PM UTC 24 Oct 15 03:44:06 PM UTC 24 43834821 ps
T1848 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.20348665 Oct 15 03:43:01 PM UTC 24 Oct 15 03:44:11 PM UTC 24 6337019191 ps
T1849 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.3744542784 Oct 15 03:43:28 PM UTC 24 Oct 15 03:44:14 PM UTC 24 703164347 ps
T529 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.364947806 Oct 15 03:26:51 PM UTC 24 Oct 15 03:44:23 PM UTC 24 68072860029 ps
T1850 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.2443349838 Oct 15 03:43:06 PM UTC 24 Oct 15 03:44:23 PM UTC 24 1863082405 ps
T1851 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.3633999161 Oct 15 03:35:17 PM UTC 24 Oct 15 03:44:33 PM UTC 24 6249467295 ps
T1852 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.2649342776 Oct 15 03:44:06 PM UTC 24 Oct 15 03:44:35 PM UTC 24 303938534 ps
T801 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.1884179661 Oct 15 03:42:26 PM UTC 24 Oct 15 03:44:35 PM UTC 24 3180362285 ps
T1853 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.2975718118 Oct 15 03:43:00 PM UTC 24 Oct 15 03:44:37 PM UTC 24 5736732491 ps
T1854 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.3633580871 Oct 15 03:44:34 PM UTC 24 Oct 15 03:44:42 PM UTC 24 22854056 ps
T1855 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.54551863 Oct 15 03:44:04 PM UTC 24 Oct 15 03:44:51 PM UTC 24 557409101 ps
T1856 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.1333108830 Oct 15 03:44:15 PM UTC 24 Oct 15 03:44:52 PM UTC 24 1941980295 ps
T1857 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.1789992579 Oct 15 03:43:59 PM UTC 24 Oct 15 03:44:52 PM UTC 24 4038264290 ps
T1858 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.3230014448 Oct 15 03:44:27 PM UTC 24 Oct 15 03:44:54 PM UTC 24 653601513 ps
T1859 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.1691858588 Oct 15 03:44:37 PM UTC 24 Oct 15 03:44:55 PM UTC 24 377773010 ps
T1860 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.2535156047 Oct 15 03:44:29 PM UTC 24 Oct 15 03:45:06 PM UTC 24 265707680 ps
T828 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.254931710 Oct 15 03:34:48 PM UTC 24 Oct 15 03:45:11 PM UTC 24 43170081949 ps
T1861 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.1861429983 Oct 15 03:44:59 PM UTC 24 Oct 15 03:45:12 PM UTC 24 179683939 ps
T1862 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3301361949 Oct 15 03:44:41 PM UTC 24 Oct 15 03:45:13 PM UTC 24 119709709 ps
T1863 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.1942907053 Oct 15 03:45:02 PM UTC 24 Oct 15 03:45:13 PM UTC 24 60568482 ps
T1864 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.3550898829 Oct 15 03:39:39 PM UTC 24 Oct 15 03:45:14 PM UTC 24 10839020208 ps
T1865 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.3285239460 Oct 15 03:42:29 PM UTC 24 Oct 15 03:45:15 PM UTC 24 11842982785 ps
T1866 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.284246181 Oct 15 03:39:18 PM UTC 24 Oct 15 03:45:17 PM UTC 24 21193490719 ps
T1867 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.3974023397 Oct 15 03:37:09 PM UTC 24 Oct 15 03:45:18 PM UTC 24 41766139312 ps
T1868 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.2350383688 Oct 15 03:33:45 PM UTC 24 Oct 15 03:45:25 PM UTC 24 42089439764 ps
T1869 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.3377722798 Oct 15 03:14:31 PM UTC 24 Oct 15 03:45:25 PM UTC 24 16663112620 ps
T1870 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.1392510896 Oct 15 03:45:06 PM UTC 24 Oct 15 03:45:31 PM UTC 24 484662658 ps
T1871 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.3822330099 Oct 15 03:45:20 PM UTC 24 Oct 15 03:45:35 PM UTC 24 108524178 ps
T1872 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.2207307759 Oct 15 03:43:56 PM UTC 24 Oct 15 03:45:41 PM UTC 24 9439751618 ps
T1873 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.909635809 Oct 15 03:41:41 PM UTC 24 Oct 15 03:45:48 PM UTC 24 2230429160 ps
T839 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.3970794140 Oct 15 03:44:17 PM UTC 24 Oct 15 03:45:48 PM UTC 24 2053464497 ps
T1874 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.4037310212 Oct 15 03:45:41 PM UTC 24 Oct 15 03:45:54 PM UTC 24 168180851 ps
T1875 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.3229272676 Oct 15 03:45:50 PM UTC 24 Oct 15 03:45:59 PM UTC 24 46047469 ps
T1876 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.2680674884 Oct 15 03:45:02 PM UTC 24 Oct 15 03:46:01 PM UTC 24 3803975739 ps
T1877 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.1167430365 Oct 15 03:40:46 PM UTC 24 Oct 15 03:46:03 PM UTC 24 530381149 ps
T1878 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.1444592787 Oct 15 03:44:27 PM UTC 24 Oct 15 03:46:07 PM UTC 24 2527612189 ps
T1879 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.3570320663 Oct 15 03:45:18 PM UTC 24 Oct 15 03:46:12 PM UTC 24 555018179 ps
T1880 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.731818995 Oct 15 03:45:33 PM UTC 24 Oct 15 03:46:15 PM UTC 24 1477986886 ps
T1881 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.4294764102 Oct 15 03:45:40 PM UTC 24 Oct 15 03:46:21 PM UTC 24 840813660 ps
T1882 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.118304894 Oct 15 03:41:26 PM UTC 24 Oct 15 03:46:23 PM UTC 24 20830935687 ps
T1883 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.1713954416 Oct 15 03:45:36 PM UTC 24 Oct 15 03:46:34 PM UTC 24 604374001 ps
T1884 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.837642033 Oct 15 03:46:26 PM UTC 24 Oct 15 03:46:36 PM UTC 24 39064401 ps
T1885 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.2022289147 Oct 15 03:45:36 PM UTC 24 Oct 15 03:46:38 PM UTC 24 1074723671 ps
T1886 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.213670602 Oct 15 03:46:30 PM UTC 24 Oct 15 03:46:40 PM UTC 24 86656668 ps
T1887 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.3435831469 Oct 15 03:46:05 PM UTC 24 Oct 15 03:46:42 PM UTC 24 311846356 ps
T470 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.217044399 Oct 15 03:39:40 PM UTC 24 Oct 15 03:46:56 PM UTC 24 5931338767 ps
T1888 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.870510393 Oct 15 03:43:38 PM UTC 24 Oct 15 03:46:56 PM UTC 24 450411282 ps
T1889 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.842137853 Oct 15 03:45:00 PM UTC 24 Oct 15 03:47:00 PM UTC 24 8364723977 ps
T1890 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.269185006 Oct 15 03:39:06 PM UTC 24 Oct 15 03:47:02 PM UTC 24 31890163022 ps
T1891 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.4121296699 Oct 15 03:45:17 PM UTC 24 Oct 15 03:47:03 PM UTC 24 10652917523 ps
T1892 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.4046249540 Oct 15 03:46:39 PM UTC 24 Oct 15 03:47:08 PM UTC 24 274560129 ps
T1893 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.2928696094 Oct 15 03:45:58 PM UTC 24 Oct 15 03:47:13 PM UTC 24 5044309277 ps
T1894 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.4054231501 Oct 15 03:47:04 PM UTC 24 Oct 15 03:47:14 PM UTC 24 48806191 ps
T1895 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.1429586207 Oct 15 03:47:05 PM UTC 24 Oct 15 03:47:15 PM UTC 24 48887558 ps
T1896 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.141726780 Oct 15 03:40:39 PM UTC 24 Oct 15 03:47:22 PM UTC 24 23975306453 ps
T1897 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.1656021069 Oct 15 03:46:24 PM UTC 24 Oct 15 03:47:25 PM UTC 24 1746193216 ps
T887 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.1523882006 Oct 15 03:40:50 PM UTC 24 Oct 15 03:47:27 PM UTC 24 6628759327 ps
T1898 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.1854953722 Oct 15 03:45:59 PM UTC 24 Oct 15 03:47:32 PM UTC 24 2116728388 ps
T1899 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.3171302036 Oct 15 03:43:26 PM UTC 24 Oct 15 03:47:33 PM UTC 24 7537949185 ps
T1900 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.606555814 Oct 15 03:44:47 PM UTC 24 Oct 15 03:47:37 PM UTC 24 470541925 ps
T1901 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.3009899563 Oct 15 03:45:49 PM UTC 24 Oct 15 03:47:40 PM UTC 24 7711663457 ps
T1902 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.4164385918 Oct 15 03:45:37 PM UTC 24 Oct 15 03:47:40 PM UTC 24 3606617365 ps
T471 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.1090515397 Oct 15 03:42:42 PM UTC 24 Oct 15 03:47:41 PM UTC 24 9901670194 ps
T1903 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.1379238216 Oct 15 03:47:22 PM UTC 24 Oct 15 03:47:50 PM UTC 24 274441337 ps
T825 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.2049130751 Oct 15 03:31:19 PM UTC 24 Oct 15 03:47:51 PM UTC 24 71559487788 ps
T1904 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.935415953 Oct 15 03:47:25 PM UTC 24 Oct 15 03:47:55 PM UTC 24 278145787 ps
T1905 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.3721975140 Oct 15 03:47:25 PM UTC 24 Oct 15 03:47:57 PM UTC 24 305675886 ps
T1906 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.1227157222 Oct 15 03:42:24 PM UTC 24 Oct 15 03:48:07 PM UTC 24 31432403376 ps
T1907 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.1996773957 Oct 15 03:48:00 PM UTC 24 Oct 15 03:48:07 PM UTC 24 44907479 ps
T1908 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.3586889016 Oct 15 03:47:46 PM UTC 24 Oct 15 03:48:12 PM UTC 24 212161737 ps
T1909 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.2455487486 Oct 15 03:48:03 PM UTC 24 Oct 15 03:48:13 PM UTC 24 42442453 ps
T1910 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.2059801314 Oct 15 03:47:26 PM UTC 24 Oct 15 03:48:15 PM UTC 24 2410112159 ps
T1911 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.2196741507 Oct 15 03:47:41 PM UTC 24 Oct 15 03:48:16 PM UTC 24 260913055 ps
T1912 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.1904042308 Oct 15 03:46:20 PM UTC 24 Oct 15 03:48:18 PM UTC 24 3131713490 ps
T1913 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.848269647 Oct 15 03:47:08 PM UTC 24 Oct 15 03:48:18 PM UTC 24 4009713029 ps
T1914 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.1846668514 Oct 15 03:41:29 PM UTC 24 Oct 15 03:48:25 PM UTC 24 44058382255 ps
T1915 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.710730224 Oct 15 03:48:15 PM UTC 24 Oct 15 03:48:28 PM UTC 24 62455563 ps
T1916 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.398982888 Oct 15 03:44:51 PM UTC 24 Oct 15 03:48:37 PM UTC 24 5874276497 ps
T1917 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.3316295350 Oct 15 03:47:42 PM UTC 24 Oct 15 03:48:42 PM UTC 24 2012191581 ps
T1918 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.3917978775 Oct 15 03:45:37 PM UTC 24 Oct 15 03:48:43 PM UTC 24 2426393066 ps
T1919 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.1409086964 Oct 15 03:47:38 PM UTC 24 Oct 15 03:48:44 PM UTC 24 1856593517 ps
T1920 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.139042364 Oct 15 03:48:33 PM UTC 24 Oct 15 03:48:46 PM UTC 24 169295384 ps
T1921 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.2708531712 Oct 15 03:48:04 PM UTC 24 Oct 15 03:48:52 PM UTC 24 2954549333 ps
T603 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.2810520147 Oct 15 03:41:46 PM UTC 24 Oct 15 03:48:54 PM UTC 24 11562578896 ps
T1922 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.1532646854 Oct 15 03:47:05 PM UTC 24 Oct 15 03:48:55 PM UTC 24 7087354364 ps
T1923 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.4229861557 Oct 15 03:48:39 PM UTC 24 Oct 15 03:48:58 PM UTC 24 249692302 ps
T1924 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.3206890448 Oct 15 03:46:48 PM UTC 24 Oct 15 03:48:58 PM UTC 24 103379406 ps
T1925 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.3926149595 Oct 15 03:46:08 PM UTC 24 Oct 15 03:49:03 PM UTC 24 10540454773 ps
T1926 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.3432292059 Oct 15 03:48:38 PM UTC 24 Oct 15 03:49:05 PM UTC 24 354972946 ps
T517 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.4083093267 Oct 15 03:48:17 PM UTC 24 Oct 15 03:49:06 PM UTC 24 455006489 ps
T646 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.2663529854 Oct 15 03:36:35 PM UTC 24 Oct 15 03:49:13 PM UTC 24 22808954414 ps
T1927 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.1416851156 Oct 15 03:49:02 PM UTC 24 Oct 15 03:49:13 PM UTC 24 141769910 ps
T1928 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.3952691319 Oct 15 03:43:11 PM UTC 24 Oct 15 03:49:17 PM UTC 24 23203770082 ps
T1929 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.548871102 Oct 15 03:49:10 PM UTC 24 Oct 15 03:49:20 PM UTC 24 37196730 ps
T1930 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.1269107361 Oct 15 03:48:08 PM UTC 24 Oct 15 03:49:21 PM UTC 24 7355116246 ps
T871 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.2650466583 Oct 15 03:47:59 PM UTC 24 Oct 15 03:49:23 PM UTC 24 155932712 ps
T1931 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.3143237493 Oct 15 03:48:42 PM UTC 24 Oct 15 03:49:28 PM UTC 24 329292991 ps
T1932 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.2399718373 Oct 15 03:48:40 PM UTC 24 Oct 15 03:49:31 PM UTC 24 1209842252 ps
T1933 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.4010668795 Oct 15 03:42:26 PM UTC 24 Oct 15 03:49:43 PM UTC 24 29984047985 ps
T1934 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.3621210661 Oct 15 03:49:30 PM UTC 24 Oct 15 03:49:43 PM UTC 24 66902551 ps
T1935 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.1014797316 Oct 15 03:49:17 PM UTC 24 Oct 15 03:49:46 PM UTC 24 202342849 ps
T1936 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.2375750309 Oct 15 03:49:29 PM UTC 24 Oct 15 03:49:48 PM UTC 24 173558544 ps
T495 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.2222930624 Oct 15 03:38:20 PM UTC 24 Oct 15 03:49:49 PM UTC 24 18153977014 ps
T1937 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.3464178200 Oct 15 03:49:51 PM UTC 24 Oct 15 03:50:00 PM UTC 24 37846869 ps
T1938 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.1297857919 Oct 15 03:49:50 PM UTC 24 Oct 15 03:50:06 PM UTC 24 260616801 ps
T1939 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.971228783 Oct 15 03:49:32 PM UTC 24 Oct 15 03:50:09 PM UTC 24 221739860 ps
T1940 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.1824498855 Oct 15 03:49:14 PM UTC 24 Oct 15 03:50:10 PM UTC 24 598534479 ps
T806 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.311346156 Oct 15 03:43:32 PM UTC 24 Oct 15 03:50:17 PM UTC 24 10852774480 ps
T1941 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.3714717606 Oct 15 03:49:33 PM UTC 24 Oct 15 03:50:24 PM UTC 24 1250383409 ps
T1942 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.543012724 Oct 15 03:49:11 PM UTC 24 Oct 15 03:50:25 PM UTC 24 4458721334 ps
T847 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.1237083927 Oct 15 03:40:41 PM UTC 24 Oct 15 03:50:32 PM UTC 24 40329944749 ps
T1943 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.4116141168 Oct 15 03:48:45 PM UTC 24 Oct 15 03:50:39 PM UTC 24 1160322732 ps
T1944 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.3123808006 Oct 15 03:50:09 PM UTC 24 Oct 15 03:50:40 PM UTC 24 236857238 ps
T1945 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.668674451 Oct 15 03:48:22 PM UTC 24 Oct 15 03:50:43 PM UTC 24 12852792833 ps
T1946 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.1240653341 Oct 15 03:47:21 PM UTC 24 Oct 15 03:50:44 PM UTC 24 20979590407 ps
T1947 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.913790602 Oct 15 03:50:29 PM UTC 24 Oct 15 03:50:45 PM UTC 24 464068914 ps
T1948 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.3433781982 Oct 15 03:50:39 PM UTC 24 Oct 15 03:50:53 PM UTC 24 173198410 ps
T1949 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.4069226410 Oct 15 03:49:11 PM UTC 24 Oct 15 03:50:58 PM UTC 24 7027999152 ps
T1950 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.1605338737 Oct 15 03:50:09 PM UTC 24 Oct 15 03:51:04 PM UTC 24 1544497852 ps
T1951 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.1908002325 Oct 15 03:45:39 PM UTC 24 Oct 15 03:51:05 PM UTC 24 3166608660 ps
T1952 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.3051893981 Oct 15 03:40:28 PM UTC 24 Oct 15 03:51:09 PM UTC 24 53945375108 ps
T1953 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.3096454966 Oct 15 03:50:50 PM UTC 24 Oct 15 03:51:14 PM UTC 24 202744321 ps
T1954 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.324540053 Oct 15 03:49:55 PM UTC 24 Oct 15 03:51:17 PM UTC 24 8734502677 ps
T1955 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.3959619488 Oct 15 03:48:54 PM UTC 24 Oct 15 03:51:19 PM UTC 24 3645438553 ps
T1956 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.1314896062 Oct 15 03:50:32 PM UTC 24 Oct 15 03:51:21 PM UTC 24 1751345570 ps
T1957 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.163806365 Oct 15 03:51:11 PM UTC 24 Oct 15 03:51:21 PM UTC 24 52474022 ps
T1958 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.2332716232 Oct 15 03:51:07 PM UTC 24 Oct 15 03:51:21 PM UTC 24 209078419 ps
T886 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.3229597025 Oct 15 03:47:54 PM UTC 24 Oct 15 03:51:25 PM UTC 24 1930685645 ps
T1959 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.2397489058 Oct 15 03:47:51 PM UTC 24 Oct 15 03:51:31 PM UTC 24 2684625117 ps
T1960 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.3085511735 Oct 15 03:50:07 PM UTC 24 Oct 15 03:51:31 PM UTC 24 5379851181 ps
T1961 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.812791271 Oct 15 03:50:28 PM UTC 24 Oct 15 03:51:41 PM UTC 24 830391584 ps
T1962 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.3350881673 Oct 15 03:47:47 PM UTC 24 Oct 15 03:51:43 PM UTC 24 2303785570 ps
T1963 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.3640244351 Oct 15 03:49:45 PM UTC 24 Oct 15 03:51:46 PM UTC 24 1167887470 ps
T1964 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.1438950367 Oct 15 03:49:43 PM UTC 24 Oct 15 03:51:47 PM UTC 24 300481273 ps
T1965 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.3723827839 Oct 15 03:51:43 PM UTC 24 Oct 15 03:51:59 PM UTC 24 195695005 ps
T819 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.2721576770 Oct 15 03:49:22 PM UTC 24 Oct 15 03:52:00 PM UTC 24 3320718313 ps
T1966 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.2890536183 Oct 15 03:51:47 PM UTC 24 Oct 15 03:52:00 PM UTC 24 213583177 ps
T1967 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.2315038409 Oct 15 03:51:45 PM UTC 24 Oct 15 03:52:07 PM UTC 24 135062730 ps
T1968 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.1274400436 Oct 15 03:51:40 PM UTC 24 Oct 15 03:52:13 PM UTC 24 716326259 ps
T1969 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.3817447658 Oct 15 03:51:04 PM UTC 24 Oct 15 03:52:15 PM UTC 24 255734480 ps
T1970 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.4159716639 Oct 15 03:51:18 PM UTC 24 Oct 15 03:52:15 PM UTC 24 4562338209 ps
T1971 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.1653167389 Oct 15 03:52:09 PM UTC 24 Oct 15 03:52:19 PM UTC 24 198656915 ps
T1972 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.1689397093 Oct 15 03:51:25 PM UTC 24 Oct 15 03:52:20 PM UTC 24 1366213493 ps
T1973 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3863399295 Oct 15 03:52:11 PM UTC 24 Oct 15 03:52:21 PM UTC 24 48909608 ps
T1974 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2874860152 Oct 15 03:45:40 PM UTC 24 Oct 15 03:52:23 PM UTC 24 6935899207 ps
T1975 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.4101704025 Oct 15 03:51:52 PM UTC 24 Oct 15 03:52:26 PM UTC 24 78579915 ps
T1976 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.956103041 Oct 15 03:46:13 PM UTC 24 Oct 15 03:52:28 PM UTC 24 34728557289 ps
T1977 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.3265557071 Oct 15 03:51:29 PM UTC 24 Oct 15 03:52:28 PM UTC 24 572512132 ps
T1978 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.3866446243 Oct 15 03:49:40 PM UTC 24 Oct 15 03:52:39 PM UTC 24 2068760635 ps
T1979 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.2184035568 Oct 15 03:46:42 PM UTC 24 Oct 15 03:52:42 PM UTC 24 10128259173 ps
T1980 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.264136263 Oct 15 03:56:04 PM UTC 24 Oct 15 03:57:20 PM UTC 24 1082105730 ps
T1981 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.4033946100 Oct 15 03:56:20 PM UTC 24 Oct 15 03:57:18 PM UTC 24 3981555832 ps
T1982 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.3114629044 Oct 15 03:52:25 PM UTC 24 Oct 15 03:52:52 PM UTC 24 560155534 ps
T1983 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.3157274922 Oct 15 03:44:09 PM UTC 24 Oct 15 03:52:59 PM UTC 24 40718741781 ps
T1984 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.364044645 Oct 15 03:51:10 PM UTC 24 Oct 15 03:53:04 PM UTC 24 9756350656 ps
T1985 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.1496834118 Oct 15 03:45:18 PM UTC 24 Oct 15 03:53:05 PM UTC 24 29748795674 ps
T1986 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.376399108 Oct 15 03:52:28 PM UTC 24 Oct 15 03:53:15 PM UTC 24 499965456 ps
T1987 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.1832678207 Oct 15 03:51:44 PM UTC 24 Oct 15 03:53:20 PM UTC 24 2558857708 ps
T1988 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.3438279471 Oct 15 03:52:43 PM UTC 24 Oct 15 03:53:22 PM UTC 24 1263723774 ps
T1989 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.3948361322 Oct 15 03:53:08 PM UTC 24 Oct 15 03:53:23 PM UTC 24 230817888 ps
T1990 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.876312609 Oct 15 03:52:53 PM UTC 24 Oct 15 03:53:24 PM UTC 24 46906608 ps
T1991 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.1697865785 Oct 15 03:46:48 PM UTC 24 Oct 15 03:53:24 PM UTC 24 11585797127 ps
T1992 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.497140910 Oct 15 03:53:17 PM UTC 24 Oct 15 03:53:25 PM UTC 24 42163402 ps
T1993 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.621179901 Oct 15 03:52:47 PM UTC 24 Oct 15 03:53:31 PM UTC 24 788169704 ps
T1994 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.3225463427 Oct 15 03:52:48 PM UTC 24 Oct 15 03:53:37 PM UTC 24 1112065228 ps
T1995 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.3243721488 Oct 15 03:52:26 PM UTC 24 Oct 15 03:53:40 PM UTC 24 4018515878 ps
T1996 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.94154745 Oct 15 03:52:09 PM UTC 24 Oct 15 03:53:41 PM UTC 24 9100542116 ps
T1997 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.3005167581 Oct 15 03:49:45 PM UTC 24 Oct 15 03:53:44 PM UTC 24 1247439592 ps
T1998 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.2830285542 Oct 15 03:53:33 PM UTC 24 Oct 15 03:53:45 PM UTC 24 128020902 ps
T1999 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.3379164048 Oct 15 03:52:43 PM UTC 24 Oct 15 03:53:49 PM UTC 24 1444740662 ps
T2000 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.467219648 Oct 15 03:52:43 PM UTC 24 Oct 15 03:53:53 PM UTC 24 1312269245 ps
T2001 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.755987501 Oct 15 03:53:40 PM UTC 24 Oct 15 03:53:54 PM UTC 24 69573335 ps
T2002 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.4089800375 Oct 15 03:48:48 PM UTC 24 Oct 15 03:53:58 PM UTC 24 9149372387 ps
T2003 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.3300937728 Oct 15 03:50:10 PM UTC 24 Oct 15 03:54:00 PM UTC 24 10772540225 ps
T2004 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.1292033381 Oct 15 03:52:50 PM UTC 24 Oct 15 03:54:10 PM UTC 24 1748022015 ps
T2005 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.605402911 Oct 15 03:38:12 PM UTC 24 Oct 15 03:54:12 PM UTC 24 61471224187 ps
T2006 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.3409121721 Oct 15 03:53:49 PM UTC 24 Oct 15 03:54:13 PM UTC 24 193621234 ps
T2007 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.2967632734 Oct 15 03:49:20 PM UTC 24 Oct 15 03:54:13 PM UTC 24 28556976481 ps
T2008 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.2693664766 Oct 15 03:53:59 PM UTC 24 Oct 15 03:54:15 PM UTC 24 78457072 ps
T2009 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3798616567 Oct 15 03:43:20 PM UTC 24 Oct 15 03:54:22 PM UTC 24 45579012918 ps
T2010 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.2001477090 Oct 15 03:54:17 PM UTC 24 Oct 15 03:54:25 PM UTC 24 43345078 ps
T2011 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.2854029505 Oct 15 03:48:24 PM UTC 24 Oct 15 03:54:27 PM UTC 24 25962913838 ps
T2012 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.204163270 Oct 15 03:52:54 PM UTC 24 Oct 15 03:54:30 PM UTC 24 2813239551 ps
T2013 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.2380127788 Oct 15 03:54:19 PM UTC 24 Oct 15 03:54:30 PM UTC 24 59975582 ps
T2014 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.3129281154 Oct 15 03:53:26 PM UTC 24 Oct 15 03:54:31 PM UTC 24 5704894759 ps
T2015 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.3472823643 Oct 15 03:53:46 PM UTC 24 Oct 15 03:54:42 PM UTC 24 4931117756 ps
T2016 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.626393761 Oct 15 03:53:06 PM UTC 24 Oct 15 03:54:44 PM UTC 24 1796191002 ps
T2017 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.2674914705 Oct 15 03:53:28 PM UTC 24 Oct 15 03:54:45 PM UTC 24 4935411938 ps
T2018 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.2479599431 Oct 15 03:43:10 PM UTC 24 Oct 15 03:54:51 PM UTC 24 52441559786 ps
T2019 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.562213505 Oct 15 03:54:04 PM UTC 24 Oct 15 03:54:55 PM UTC 24 945339341 ps
T2020 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.1520471243 Oct 15 03:54:52 PM UTC 24 Oct 15 03:55:01 PM UTC 24 49520437 ps
T484 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.2153122111 Oct 15 03:50:49 PM UTC 24 Oct 15 03:55:06 PM UTC 24 6279311210 ps
T2021 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.3816826154 Oct 15 03:54:31 PM UTC 24 Oct 15 03:55:12 PM UTC 24 308505303 ps
T2022 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.1415272221 Oct 15 03:54:45 PM UTC 24 Oct 15 03:55:16 PM UTC 24 830331775 ps
T2023 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.2285350677 Oct 15 03:54:45 PM UTC 24 Oct 15 03:55:18 PM UTC 24 760229887 ps
T2024 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.2300906337 Oct 15 03:55:12 PM UTC 24 Oct 15 03:55:22 PM UTC 24 201975555 ps
T2025 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.2711526148 Oct 15 03:53:51 PM UTC 24 Oct 15 03:55:24 PM UTC 24 6669132963 ps
T2026 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.4148649990 Oct 15 03:54:24 PM UTC 24 Oct 15 03:55:26 PM UTC 24 4130358925 ps
T2027 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.2919661164 Oct 15 03:55:18 PM UTC 24 Oct 15 03:55:26 PM UTC 24 55050122 ps
T2028 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.655241962 Oct 15 03:54:51 PM UTC 24 Oct 15 03:55:27 PM UTC 24 237596516 ps
T2029 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.1077849866 Oct 15 03:54:23 PM UTC 24 Oct 15 03:55:35 PM UTC 24 1933527870 ps
T2030 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.772716694 Oct 15 03:54:22 PM UTC 24 Oct 15 03:55:40 PM UTC 24 8286283783 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%