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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.96 95.39 93.47 95.36 94.22 97.71 99.60


Total test records in report: 2930
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T2268 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.1856646021 Feb 09 04:40:26 PM UTC 25 Feb 09 04:42:25 PM UTC 25 2693882384 ps
T2269 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.3700124927 Feb 09 04:41:20 PM UTC 25 Feb 09 04:42:28 PM UTC 25 3598122590 ps
T2270 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.3134624367 Feb 09 04:41:58 PM UTC 25 Feb 09 04:42:33 PM UTC 25 328169803 ps
T2271 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.1421058946 Feb 09 04:42:01 PM UTC 25 Feb 09 04:42:34 PM UTC 25 718125676 ps
T2272 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.2049611898 Feb 09 04:41:05 PM UTC 25 Feb 09 04:42:47 PM UTC 25 156389062 ps
T2273 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.253085731 Feb 09 04:42:40 PM UTC 25 Feb 09 04:42:51 PM UTC 25 42393402 ps
T2274 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.1713990838 Feb 09 04:42:41 PM UTC 25 Feb 09 04:42:52 PM UTC 25 53306681 ps
T2275 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.553402617 Feb 09 04:31:25 PM UTC 25 Feb 09 04:42:53 PM UTC 25 48224391511 ps
T2276 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.2275999369 Feb 09 04:42:01 PM UTC 25 Feb 09 04:42:55 PM UTC 25 916236650 ps
T2277 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.1212447866 Feb 09 04:38:44 PM UTC 25 Feb 09 04:42:56 PM UTC 25 482401133 ps
T2278 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.2292955609 Feb 09 04:41:20 PM UTC 25 Feb 09 04:43:03 PM UTC 25 8616444980 ps
T2279 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.3591499986 Feb 09 04:40:41 PM UTC 25 Feb 09 04:43:23 PM UTC 25 524737495 ps
T2280 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.1351029767 Feb 09 04:33:23 PM UTC 25 Feb 09 04:43:27 PM UTC 25 18586614167 ps
T2281 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.704421051 Feb 09 04:42:53 PM UTC 25 Feb 09 04:43:28 PM UTC 25 451972869 ps
T2282 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.4013893138 Feb 09 04:43:20 PM UTC 25 Feb 09 04:43:39 PM UTC 25 250309936 ps
T2283 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.2558007516 Feb 09 04:35:58 PM UTC 25 Feb 09 04:43:48 PM UTC 25 4070625115 ps
T2284 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.3573070363 Feb 09 04:43:22 PM UTC 25 Feb 09 04:43:51 PM UTC 25 465347935 ps
T2285 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.3973728133 Feb 09 04:43:14 PM UTC 25 Feb 09 04:43:59 PM UTC 25 544211275 ps
T2286 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.227584108 Feb 09 04:42:54 PM UTC 25 Feb 09 04:44:00 PM UTC 25 1339705371 ps
T2287 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.1117239706 Feb 09 04:43:23 PM UTC 25 Feb 09 04:44:00 PM UTC 25 595633327 ps
T2288 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.976609464 Feb 09 04:43:18 PM UTC 25 Feb 09 04:44:02 PM UTC 25 597157281 ps
T2289 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.93987329 Feb 09 04:34:41 PM UTC 25 Feb 09 04:44:10 PM UTC 25 3496068170 ps
T2290 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.122872073 Feb 09 04:40:22 PM UTC 25 Feb 09 04:44:10 PM UTC 25 13063450522 ps
T2291 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.3002267247 Feb 09 04:42:52 PM UTC 25 Feb 09 04:44:16 PM UTC 25 6054181858 ps
T2292 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.4160878583 Feb 09 04:44:03 PM UTC 25 Feb 09 04:44:17 PM UTC 25 207917692 ps
T2293 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.615623879 Feb 09 04:41:57 PM UTC 25 Feb 09 04:44:25 PM UTC 25 2659312599 ps
T2294 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.3399314493 Feb 09 04:44:17 PM UTC 25 Feb 09 04:44:26 PM UTC 25 43459824 ps
T2295 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.3740141539 Feb 09 04:42:46 PM UTC 25 Feb 09 04:44:29 PM UTC 25 6039972761 ps
T2296 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1964566398 Feb 09 04:34:55 PM UTC 25 Feb 09 04:44:37 PM UTC 25 5864787332 ps
T2297 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.1670418365 Feb 09 04:44:51 PM UTC 25 Feb 09 04:45:02 PM UTC 25 80958361 ps
T2298 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.3799576148 Feb 09 04:32:43 PM UTC 25 Feb 09 04:45:04 PM UTC 25 43743504198 ps
T2299 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.2616956523 Feb 09 04:44:58 PM UTC 25 Feb 09 04:45:09 PM UTC 25 40615395 ps
T2300 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.3229127994 Feb 09 04:44:53 PM UTC 25 Feb 09 04:45:10 PM UTC 25 312998505 ps
T2301 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.3933380178 Feb 09 04:41:43 PM UTC 25 Feb 09 04:45:16 PM UTC 25 18128778549 ps
T2302 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.2107061622 Feb 09 04:33:24 PM UTC 25 Feb 09 04:45:24 PM UTC 25 6639817123 ps
T2303 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.1470406940 Feb 09 04:44:29 PM UTC 25 Feb 09 04:45:31 PM UTC 25 518002807 ps
T2304 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.3553837844 Feb 09 04:44:45 PM UTC 25 Feb 09 04:45:35 PM UTC 25 471520310 ps
T2305 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.1533358219 Feb 09 04:38:17 PM UTC 25 Feb 09 04:45:44 PM UTC 25 25733082586 ps
T2306 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.2191625084 Feb 09 04:35:22 PM UTC 25 Feb 09 04:45:49 PM UTC 25 51045252357 ps
T2307 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.3349951512 Feb 09 04:44:29 PM UTC 25 Feb 09 04:45:52 PM UTC 25 1870132305 ps
T2308 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.3026905513 Feb 09 04:45:44 PM UTC 25 Feb 09 04:45:54 PM UTC 25 36962143 ps
T2309 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.175045340 Feb 09 04:45:39 PM UTC 25 Feb 09 04:45:54 PM UTC 25 240050733 ps
T2310 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.1176751773 Feb 09 04:43:56 PM UTC 25 Feb 09 04:46:06 PM UTC 25 229903349 ps
T2311 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.309093652 Feb 09 04:40:15 PM UTC 25 Feb 09 04:46:07 PM UTC 25 32590714443 ps
T2312 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.4045740256 Feb 09 04:42:07 PM UTC 25 Feb 09 04:46:08 PM UTC 25 2454260485 ps
T2313 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.2941411427 Feb 09 04:15:41 PM UTC 25 Feb 09 04:46:09 PM UTC 25 117246363786 ps
T2314 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.3799399480 Feb 09 04:36:03 PM UTC 25 Feb 09 04:46:21 PM UTC 25 16162703801 ps
T2315 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.727793793 Feb 09 04:46:03 PM UTC 25 Feb 09 04:46:21 PM UTC 25 163045575 ps
T2316 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.2973294673 Feb 09 04:44:28 PM UTC 25 Feb 09 04:46:22 PM UTC 25 5627017133 ps
T2317 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.2759949053 Feb 09 04:44:39 PM UTC 25 Feb 09 04:46:23 PM UTC 25 1406779689 ps
T2318 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.3476965520 Feb 09 04:44:17 PM UTC 25 Feb 09 04:46:31 PM UTC 25 9180009233 ps
T2319 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.3896863759 Feb 09 04:46:13 PM UTC 25 Feb 09 04:46:34 PM UTC 25 192092445 ps
T2320 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.1389123539 Feb 09 04:46:23 PM UTC 25 Feb 09 04:46:36 PM UTC 25 92317793 ps
T2321 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.1858727626 Feb 09 04:39:50 PM UTC 25 Feb 09 04:46:37 PM UTC 25 12556362390 ps
T2322 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.744539773 Feb 09 04:41:58 PM UTC 25 Feb 09 04:46:44 PM UTC 25 19150856676 ps
T2323 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.3549132322 Feb 09 04:46:36 PM UTC 25 Feb 09 04:46:46 PM UTC 25 78168439 ps
T2324 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.2456012205 Feb 09 04:13:53 PM UTC 25 Feb 09 04:46:50 PM UTC 25 138830789639 ps
T2325 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.1659407613 Feb 09 04:46:35 PM UTC 25 Feb 09 04:47:05 PM UTC 25 706836357 ps
T2326 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.2578070977 Feb 09 04:46:35 PM UTC 25 Feb 09 04:47:05 PM UTC 25 308967082 ps
T2327 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.723725770 Feb 09 04:46:58 PM UTC 25 Feb 09 04:47:08 PM UTC 25 36063458 ps
T2328 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.3629038199 Feb 09 04:47:02 PM UTC 25 Feb 09 04:47:13 PM UTC 25 46827162 ps
T2329 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.1662461115 Feb 09 04:24:08 PM UTC 25 Feb 09 04:47:13 PM UTC 25 87783858532 ps
T2330 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.1279778800 Feb 09 04:46:35 PM UTC 25 Feb 09 04:47:25 PM UTC 25 805204274 ps
T2331 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.1996201630 Feb 09 04:45:53 PM UTC 25 Feb 09 04:47:40 PM UTC 25 8589365031 ps
T2332 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.739452578 Feb 09 04:39:44 PM UTC 25 Feb 09 04:47:43 PM UTC 25 3870706466 ps
T2333 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.2915891041 Feb 09 04:45:58 PM UTC 25 Feb 09 04:47:48 PM UTC 25 5430458793 ps
T2334 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.1243627501 Feb 09 04:46:21 PM UTC 25 Feb 09 04:47:58 PM UTC 25 5736832833 ps
T2335 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.1780426062 Feb 09 04:42:03 PM UTC 25 Feb 09 04:48:00 PM UTC 25 9180947518 ps
T2336 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.2386108859 Feb 09 04:47:14 PM UTC 25 Feb 09 04:48:04 PM UTC 25 475591327 ps
T2337 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.3695098758 Feb 09 04:46:45 PM UTC 25 Feb 09 04:48:09 PM UTC 25 1015240708 ps
T2338 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.355483156 Feb 09 04:47:40 PM UTC 25 Feb 09 04:48:10 PM UTC 25 420666056 ps
T2339 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.2980076531 Feb 09 04:31:29 PM UTC 25 Feb 09 04:48:15 PM UTC 25 104475451673 ps
T2340 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.992533727 Feb 09 04:47:14 PM UTC 25 Feb 09 04:48:19 PM UTC 25 585964359 ps
T2341 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.3697187642 Feb 09 04:43:56 PM UTC 25 Feb 09 04:48:26 PM UTC 25 7878214437 ps
T2342 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.1164259260 Feb 09 04:46:51 PM UTC 25 Feb 09 04:48:39 PM UTC 25 3468297273 ps
T2343 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.2330597361 Feb 09 04:47:03 PM UTC 25 Feb 09 04:48:42 PM UTC 25 4733453991 ps
T2344 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.887096334 Feb 09 04:48:09 PM UTC 25 Feb 09 04:48:44 PM UTC 25 595247722 ps
T2345 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.1819435909 Feb 09 04:48:37 PM UTC 25 Feb 09 04:48:45 PM UTC 25 42758949 ps
T2346 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.3698344162 Feb 09 04:48:32 PM UTC 25 Feb 09 04:48:47 PM UTC 25 204810120 ps
T2347 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.4103745956 Feb 09 04:47:03 PM UTC 25 Feb 09 04:48:47 PM UTC 25 8703576805 ps
T2348 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.1510528414 Feb 09 04:27:57 PM UTC 25 Feb 09 04:48:49 PM UTC 25 81311255155 ps
T2349 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.610467840 Feb 09 04:47:43 PM UTC 25 Feb 09 04:48:54 PM UTC 25 1954362012 ps
T2350 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.3347041627 Feb 09 04:34:05 PM UTC 25 Feb 09 04:48:54 PM UTC 25 47424691947 ps
T2351 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.635156669 Feb 09 04:40:43 PM UTC 25 Feb 09 04:48:59 PM UTC 25 14782162834 ps
T2352 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.4067250390 Feb 09 04:45:06 PM UTC 25 Feb 09 04:49:04 PM UTC 25 4902310921 ps
T2353 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.2226727040 Feb 09 04:48:46 PM UTC 25 Feb 09 04:49:04 PM UTC 25 153504208 ps
T2354 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.3101015568 Feb 09 04:47:53 PM UTC 25 Feb 09 04:49:18 PM UTC 25 1430112573 ps
T506 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.1676704447 Feb 09 04:47:34 PM UTC 25 Feb 09 04:49:19 PM UTC 25 2176801345 ps
T2355 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.3095599115 Feb 09 04:49:06 PM UTC 25 Feb 09 04:49:33 PM UTC 25 337123243 ps
T2356 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.373213335 Feb 09 04:41:54 PM UTC 25 Feb 09 04:49:37 PM UTC 25 23965514940 ps
T2357 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.1310540424 Feb 09 04:48:53 PM UTC 25 Feb 09 04:49:41 PM UTC 25 439792544 ps
T2358 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.2113702282 Feb 09 04:49:10 PM UTC 25 Feb 09 04:49:48 PM UTC 25 744862330 ps
T2359 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.155286993 Feb 09 04:49:14 PM UTC 25 Feb 09 04:49:49 PM UTC 25 496244100 ps
T2360 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.3567562767 Feb 09 04:45:32 PM UTC 25 Feb 09 04:49:55 PM UTC 25 6877405147 ps
T2361 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.2742300572 Feb 09 04:49:14 PM UTC 25 Feb 09 04:49:55 PM UTC 25 600041648 ps
T2362 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.2575064734 Feb 09 04:49:46 PM UTC 25 Feb 09 04:49:56 PM UTC 25 38390287 ps
T2363 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.2504629151 Feb 09 04:39:52 PM UTC 25 Feb 09 04:49:56 PM UTC 25 12418422807 ps
T2364 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.944696443 Feb 09 04:49:47 PM UTC 25 Feb 09 04:49:58 PM UTC 25 49370747 ps
T2365 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.2269614995 Feb 09 04:49:19 PM UTC 25 Feb 09 04:50:05 PM UTC 25 825179590 ps
T2366 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.3049092309 Feb 09 04:32:39 PM UTC 25 Feb 09 04:50:25 PM UTC 25 105321324543 ps
T2367 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.3249626866 Feb 09 04:48:39 PM UTC 25 Feb 09 04:50:28 PM UTC 25 11796353808 ps
T2368 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.3610110742 Feb 09 04:49:05 PM UTC 25 Feb 09 04:50:29 PM UTC 25 3734658399 ps
T2369 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.3056130834 Feb 09 04:43:51 PM UTC 25 Feb 09 04:50:36 PM UTC 25 5371977637 ps
T2370 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.2894535344 Feb 09 04:50:15 PM UTC 25 Feb 09 04:50:38 PM UTC 25 216742551 ps
T2371 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.315710394 Feb 09 04:50:20 PM UTC 25 Feb 09 04:50:47 PM UTC 25 542344167 ps
T2372 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.2094788927 Feb 09 04:45:37 PM UTC 25 Feb 09 04:50:47 PM UTC 25 7796163098 ps
T2373 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.2383083125 Feb 09 04:40:42 PM UTC 25 Feb 09 04:50:47 PM UTC 25 16285201618 ps
T2374 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.3234802854 Feb 09 04:50:04 PM UTC 25 Feb 09 04:50:52 PM UTC 25 548505528 ps
T2375 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.3256078355 Feb 09 04:50:33 PM UTC 25 Feb 09 04:50:55 PM UTC 25 496338410 ps
T2376 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.3518005701 Feb 09 04:43:30 PM UTC 25 Feb 09 04:51:00 PM UTC 25 4739355796 ps
T2377 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.3765832903 Feb 09 04:48:40 PM UTC 25 Feb 09 04:51:00 PM UTC 25 5688937144 ps
T2378 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.3651435702 Feb 09 04:50:54 PM UTC 25 Feb 09 04:51:03 PM UTC 25 138918174 ps
T2379 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.1375426142 Feb 09 04:42:37 PM UTC 25 Feb 09 04:51:04 PM UTC 25 3695867024 ps
T2380 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.2337325584 Feb 09 04:50:22 PM UTC 25 Feb 09 04:51:07 PM UTC 25 1347005894 ps
T2381 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.623054533 Feb 09 04:48:24 PM UTC 25 Feb 09 04:51:07 PM UTC 25 2159441272 ps
T2382 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.3723039286 Feb 09 04:51:07 PM UTC 25 Feb 09 04:51:20 PM UTC 25 168363387 ps
T2383 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.1271888842 Feb 09 04:51:10 PM UTC 25 Feb 09 04:51:21 PM UTC 25 54298009 ps
T2384 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.989732204 Feb 09 04:50:16 PM UTC 25 Feb 09 04:51:26 PM UTC 25 5399873030 ps
T2385 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.1497007021 Feb 09 04:50:05 PM UTC 25 Feb 09 04:51:27 PM UTC 25 5861994200 ps
T2386 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.431532625 Feb 09 04:50:57 PM UTC 25 Feb 09 04:51:31 PM UTC 25 150660485 ps
T2387 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.75221791 Feb 09 04:38:05 PM UTC 25 Feb 09 04:51:35 PM UTC 25 40791986111 ps
T2388 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.3913698591 Feb 09 04:42:39 PM UTC 25 Feb 09 04:51:43 PM UTC 25 14897878706 ps
T2389 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.3788399800 Feb 09 04:50:02 PM UTC 25 Feb 09 04:51:46 PM UTC 25 8351290431 ps
T2390 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.2879490472 Feb 09 04:51:22 PM UTC 25 Feb 09 04:51:47 PM UTC 25 282952052 ps
T2391 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.576035652 Feb 09 04:51:24 PM UTC 25 Feb 09 04:52:04 PM UTC 25 434267525 ps
T2392 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.2595745002 Feb 09 04:48:09 PM UTC 25 Feb 09 04:52:05 PM UTC 25 2635652488 ps
T2393 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.3315135031 Feb 09 04:49:20 PM UTC 25 Feb 09 04:52:06 PM UTC 25 4028999392 ps
T2394 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.4003193148 Feb 09 04:49:32 PM UTC 25 Feb 09 04:52:13 PM UTC 25 4755460855 ps
T2395 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.2799611366 Feb 09 04:51:48 PM UTC 25 Feb 09 04:52:20 PM UTC 25 265776598 ps
T2396 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.596344588 Feb 09 04:52:15 PM UTC 25 Feb 09 04:52:23 PM UTC 25 42658678 ps
T2397 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.190344662 Feb 09 04:52:13 PM UTC 25 Feb 09 04:52:24 PM UTC 25 45403521 ps
T2398 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.3750893976 Feb 09 04:50:25 PM UTC 25 Feb 09 04:52:24 PM UTC 25 2624804634 ps
T2399 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.2320078046 Feb 09 04:51:32 PM UTC 25 Feb 09 04:52:26 PM UTC 25 1486277556 ps
T2400 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.4082289563 Feb 09 04:51:51 PM UTC 25 Feb 09 04:52:30 PM UTC 25 948282782 ps
T2401 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.1252893024 Feb 09 04:51:44 PM UTC 25 Feb 09 04:52:30 PM UTC 25 1004268018 ps
T2402 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.1113790406 Feb 09 04:51:16 PM UTC 25 Feb 09 04:52:32 PM UTC 25 4543842280 ps
T2403 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3839066647 Feb 09 04:46:50 PM UTC 25 Feb 09 04:52:35 PM UTC 25 2247311626 ps
T2404 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.1124153289 Feb 09 04:51:59 PM UTC 25 Feb 09 04:52:42 PM UTC 25 69993258 ps
T2405 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.3097171672 Feb 09 04:39:12 PM UTC 25 Feb 09 04:52:43 PM UTC 25 81477418709 ps
T2406 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.2876903200 Feb 09 04:51:30 PM UTC 25 Feb 09 04:52:52 PM UTC 25 1039687566 ps
T2407 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.4103545032 Feb 09 04:52:33 PM UTC 25 Feb 09 04:52:54 PM UTC 25 336008402 ps
T2408 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.2856523932 Feb 09 04:48:17 PM UTC 25 Feb 09 04:52:59 PM UTC 25 4937385190 ps
T2409 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.1844675696 Feb 09 04:52:48 PM UTC 25 Feb 09 04:53:02 PM UTC 25 93662062 ps
T2410 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.960519691 Feb 09 04:49:32 PM UTC 25 Feb 09 04:53:03 PM UTC 25 584096702 ps
T2411 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.227408922 Feb 09 04:47:16 PM UTC 25 Feb 09 04:53:04 PM UTC 25 22250221530 ps
T2412 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.707022036 Feb 09 04:53:09 PM UTC 25 Feb 09 04:53:16 PM UTC 25 5826134 ps
T2413 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.383794990 Feb 09 04:44:39 PM UTC 25 Feb 09 04:53:20 PM UTC 25 29594163962 ps
T2414 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.3527984469 Feb 09 04:52:56 PM UTC 25 Feb 09 04:53:23 PM UTC 25 219437230 ps
T2415 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.490238720 Feb 09 04:51:16 PM UTC 25 Feb 09 04:53:24 PM UTC 25 7795265719 ps
T2416 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.2433022338 Feb 09 04:52:31 PM UTC 25 Feb 09 04:53:27 PM UTC 25 3962356937 ps
T2417 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.3456863423 Feb 09 04:52:50 PM UTC 25 Feb 09 04:53:28 PM UTC 25 1335234755 ps
T2418 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.536256400 Feb 09 04:52:55 PM UTC 25 Feb 09 04:53:29 PM UTC 25 180293256 ps
T2419 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.1445190303 Feb 09 04:53:18 PM UTC 25 Feb 09 04:53:33 PM UTC 25 253534622 ps
T2420 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.622440528 Feb 09 04:53:27 PM UTC 25 Feb 09 04:53:37 PM UTC 25 41707412 ps
T2421 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.587789673 Feb 09 04:51:02 PM UTC 25 Feb 09 04:53:40 PM UTC 25 1993673850 ps
T2422 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.353134611 Feb 09 04:52:53 PM UTC 25 Feb 09 04:53:41 PM UTC 25 1212039503 ps
T2423 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.2700969894 Feb 09 04:52:40 PM UTC 25 Feb 09 04:53:41 PM UTC 25 612527827 ps
T2424 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.3403467719 Feb 09 04:53:33 PM UTC 25 Feb 09 04:53:43 PM UTC 25 43356506 ps
T2425 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.2394283923 Feb 09 04:49:28 PM UTC 25 Feb 09 04:53:44 PM UTC 25 1230113495 ps
T2426 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.1392691025 Feb 09 04:52:31 PM UTC 25 Feb 09 04:53:48 PM UTC 25 7605451994 ps
T2427 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.1207356681 Feb 09 04:39:17 PM UTC 25 Feb 09 04:53:49 PM UTC 25 58187468036 ps
T2428 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.2875851804 Feb 09 04:53:53 PM UTC 25 Feb 09 04:54:06 PM UTC 25 140025762 ps
T2429 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.2286565617 Feb 09 04:53:18 PM UTC 25 Feb 09 04:54:06 PM UTC 25 178610105 ps
T2430 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.1058081214 Feb 09 04:44:31 PM UTC 25 Feb 09 04:54:07 PM UTC 25 52515200997 ps
T2431 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.1591361074 Feb 09 04:50:54 PM UTC 25 Feb 09 04:54:12 PM UTC 25 1877738945 ps
T2432 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.979921550 Feb 09 04:53:44 PM UTC 25 Feb 09 04:54:19 PM UTC 25 392388114 ps
T2433 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.3169055436 Feb 09 04:53:53 PM UTC 25 Feb 09 04:54:24 PM UTC 25 1107237556 ps
T2434 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.3181268791 Feb 09 04:54:10 PM UTC 25 Feb 09 04:54:24 PM UTC 25 211059855 ps
T2435 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.1226420137 Feb 09 04:54:13 PM UTC 25 Feb 09 04:54:25 PM UTC 25 49561370 ps
T2436 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.1490628560 Feb 09 04:53:59 PM UTC 25 Feb 09 04:54:28 PM UTC 25 257028239 ps
T2437 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.703223073 Feb 09 04:50:21 PM UTC 25 Feb 09 04:54:28 PM UTC 25 15268204071 ps
T2438 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.229565023 Feb 09 04:54:02 PM UTC 25 Feb 09 04:54:42 PM UTC 25 300312106 ps
T2439 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.4156785164 Feb 09 04:53:50 PM UTC 25 Feb 09 04:54:42 PM UTC 25 474589221 ps
T2440 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.4183259864 Feb 09 04:39:24 PM UTC 25 Feb 09 04:54:47 PM UTC 25 48027501846 ps
T2441 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.1069518766 Feb 09 04:51:05 PM UTC 25 Feb 09 04:54:55 PM UTC 25 740732041 ps
T2442 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.835723044 Feb 09 04:20:51 PM UTC 25 Feb 09 04:55:03 PM UTC 25 134644857599 ps
T2443 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.2924005848 Feb 09 04:53:31 PM UTC 25 Feb 09 04:55:05 PM UTC 25 7823736109 ps
T2444 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.3562993317 Feb 09 04:53:10 PM UTC 25 Feb 09 04:55:16 PM UTC 25 221199042 ps
T2445 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.1390770760 Feb 09 04:43:01 PM UTC 25 Feb 09 04:55:22 PM UTC 25 48367514610 ps
T2446 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.1935049569 Feb 09 04:54:51 PM UTC 25 Feb 09 04:55:24 PM UTC 25 483202592 ps
T2447 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.2247405499 Feb 09 04:33:01 PM UTC 25 Feb 09 04:55:25 PM UTC 25 72870615268 ps
T2448 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.2363899379 Feb 09 04:54:49 PM UTC 25 Feb 09 04:55:28 PM UTC 25 340646110 ps
T2449 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.2771665491 Feb 09 04:54:37 PM UTC 25 Feb 09 04:55:32 PM UTC 25 474902970 ps
T2450 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.3871535847 Feb 09 04:52:11 PM UTC 25 Feb 09 04:55:32 PM UTC 25 620768976 ps
T2451 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.3600020139 Feb 09 04:48:27 PM UTC 25 Feb 09 04:55:34 PM UTC 25 3620892424 ps
T2452 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.2756648315 Feb 09 04:54:33 PM UTC 25 Feb 09 04:55:36 PM UTC 25 1802594658 ps
T2453 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.89048679 Feb 09 04:46:50 PM UTC 25 Feb 09 04:55:38 PM UTC 25 5017003339 ps
T2454 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.2441289031 Feb 09 04:52:44 PM UTC 25 Feb 09 04:55:42 PM UTC 25 17971953176 ps
T2455 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.857712238 Feb 09 04:55:34 PM UTC 25 Feb 09 04:55:44 PM UTC 25 37082601 ps
T2456 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.67683365 Feb 09 04:53:33 PM UTC 25 Feb 09 04:55:49 PM UTC 25 7002272650 ps
T2457 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.3481665977 Feb 09 04:55:42 PM UTC 25 Feb 09 04:55:51 PM UTC 25 36449328 ps
T2458 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.3695032111 Feb 09 04:54:32 PM UTC 25 Feb 09 04:55:56 PM UTC 25 5028773748 ps
T2459 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.3218624719 Feb 09 04:54:49 PM UTC 25 Feb 09 04:56:00 PM UTC 25 2124008656 ps
T2460 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.1751463163 Feb 09 04:36:40 PM UTC 25 Feb 09 04:56:04 PM UTC 25 87748931639 ps
T2461 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.2168573924 Feb 09 04:36:50 PM UTC 25 Feb 09 04:56:05 PM UTC 25 65650435374 ps
T2462 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.2192521460 Feb 09 04:55:07 PM UTC 25 Feb 09 04:56:06 PM UTC 25 1241825563 ps
T2463 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.3678524988 Feb 09 04:54:48 PM UTC 25 Feb 09 04:56:21 PM UTC 25 2203326315 ps
T2464 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3126261842 Feb 09 04:54:09 PM UTC 25 Feb 09 04:56:22 PM UTC 25 390597094 ps
T2465 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.1301135361 Feb 09 04:56:08 PM UTC 25 Feb 09 04:56:26 PM UTC 25 274997551 ps
T2466 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.3850214720 Feb 09 04:54:13 PM UTC 25 Feb 09 04:56:29 PM UTC 25 9271945617 ps
T2467 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.472280439 Feb 09 04:55:52 PM UTC 25 Feb 09 04:56:30 PM UTC 25 1016959242 ps
T2468 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.2022532619 Feb 09 04:56:09 PM UTC 25 Feb 09 04:56:33 PM UTC 25 452352616 ps
T2469 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.662553530 Feb 09 04:53:03 PM UTC 25 Feb 09 04:56:33 PM UTC 25 5805942802 ps
T2470 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.2957082815 Feb 09 04:56:00 PM UTC 25 Feb 09 04:56:38 PM UTC 25 621444431 ps
T2471 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.7282627 Feb 09 04:55:58 PM UTC 25 Feb 09 04:56:39 PM UTC 25 475935575 ps
T2472 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.4174644440 Feb 09 04:56:33 PM UTC 25 Feb 09 04:56:43 PM UTC 25 48743190 ps
T2473 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.1082387583 Feb 09 04:56:32 PM UTC 25 Feb 09 04:56:43 PM UTC 25 242431690 ps
T2474 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.4208538773 Feb 09 04:54:48 PM UTC 25 Feb 09 04:56:53 PM UTC 25 6469919242 ps
T2475 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.2183504293 Feb 09 04:55:50 PM UTC 25 Feb 09 04:56:55 PM UTC 25 6341619654 ps
T2476 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.548739548 Feb 09 04:56:53 PM UTC 25 Feb 09 04:57:09 PM UTC 25 125904006 ps
T2477 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2656566229 Feb 09 04:56:18 PM UTC 25 Feb 09 04:57:10 PM UTC 25 1395177925 ps
T2478 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.3463870664 Feb 09 04:56:02 PM UTC 25 Feb 09 04:57:14 PM UTC 25 2175666646 ps
T2479 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.4124820523 Feb 09 04:22:46 PM UTC 25 Feb 09 04:57:17 PM UTC 25 147544852518 ps
T2480 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.87910399 Feb 09 04:57:08 PM UTC 25 Feb 09 04:57:18 PM UTC 25 51449716 ps
T2481 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.3309239967 Feb 09 04:55:51 PM UTC 25 Feb 09 04:57:25 PM UTC 25 6073078359 ps
T2482 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.883906983 Feb 09 04:54:04 PM UTC 25 Feb 09 04:57:26 PM UTC 25 2122883586 ps
T2483 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.2041606183 Feb 09 04:56:52 PM UTC 25 Feb 09 04:57:27 PM UTC 25 342430770 ps
T2484 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.141677871 Feb 09 04:21:49 PM UTC 25 Feb 09 04:57:30 PM UTC 25 123645490004 ps
T2485 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.1921496609 Feb 09 04:45:31 PM UTC 25 Feb 09 04:57:33 PM UTC 25 5712146447 ps
T2486 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.2464005979 Feb 09 04:54:41 PM UTC 25 Feb 09 04:57:33 PM UTC 25 11419025152 ps
T2487 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.3369066928 Feb 09 04:55:59 PM UTC 25 Feb 09 04:57:36 PM UTC 25 9360560666 ps
T2488 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.3289041332 Feb 09 04:54:05 PM UTC 25 Feb 09 04:57:38 PM UTC 25 535663703 ps
T2489 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.1597670830 Feb 09 04:57:19 PM UTC 25 Feb 09 04:57:40 PM UTC 25 315940097 ps
T2490 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.3414385656 Feb 09 04:49:03 PM UTC 25 Feb 09 04:57:48 PM UTC 25 46430178798 ps
T2491 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.3517464579 Feb 09 04:57:41 PM UTC 25 Feb 09 04:57:53 PM UTC 25 190522646 ps
T2492 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.20089795 Feb 09 04:57:33 PM UTC 25 Feb 09 04:57:54 PM UTC 25 71037831 ps
T2493 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.356532131 Feb 09 04:57:46 PM UTC 25 Feb 09 04:57:55 PM UTC 25 42278286 ps
T2494 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.2774422626 Feb 09 04:57:10 PM UTC 25 Feb 09 04:57:57 PM UTC 25 1060382272 ps
T2495 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.3336060185 Feb 09 04:56:21 PM UTC 25 Feb 09 04:58:05 PM UTC 25 2708198966 ps
T634 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.2231563341 Feb 09 04:55:32 PM UTC 25 Feb 09 04:58:23 PM UTC 25 3974860680 ps
T2496 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.631635505 Feb 09 04:57:06 PM UTC 25 Feb 09 04:58:24 PM UTC 25 2670109037 ps
T2497 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.116267124 Feb 09 04:56:50 PM UTC 25 Feb 09 04:58:25 PM UTC 25 4935141260 ps
T2498 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.2008821327 Feb 09 04:57:53 PM UTC 25 Feb 09 04:58:26 PM UTC 25 361635693 ps
T2499 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.19603382 Feb 09 04:52:03 PM UTC 25 Feb 09 04:58:30 PM UTC 25 13477852732 ps
T2500 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.2314354751 Feb 09 04:51:25 PM UTC 25 Feb 09 04:58:31 PM UTC 25 45336595358 ps
T2501 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.607751529 Feb 09 04:57:42 PM UTC 25 Feb 09 04:58:32 PM UTC 25 210460321 ps
T2502 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.323033391 Feb 09 04:51:54 PM UTC 25 Feb 09 04:58:34 PM UTC 25 11775828317 ps
T2503 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.517307421 Feb 09 04:58:16 PM UTC 25 Feb 09 04:58:38 PM UTC 25 193994132 ps
T2504 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.2714221744 Feb 09 04:57:55 PM UTC 25 Feb 09 04:58:42 PM UTC 25 539106242 ps
T2505 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.3616051788 Feb 09 04:56:48 PM UTC 25 Feb 09 04:58:47 PM UTC 25 9852459876 ps
T2506 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.3902468972 Feb 09 04:43:01 PM UTC 25 Feb 09 04:58:51 PM UTC 25 86347073981 ps
T2507 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.693492933 Feb 09 04:58:03 PM UTC 25 Feb 09 04:58:54 PM UTC 25 559932874 ps
T2508 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.3915805312 Feb 09 04:58:48 PM UTC 25 Feb 09 04:59:00 PM UTC 25 196719962 ps
T2509 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.1357979176 Feb 09 04:58:53 PM UTC 25 Feb 09 04:59:02 PM UTC 25 57444405 ps
T2510 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.1474419670 Feb 09 04:58:21 PM UTC 25 Feb 09 04:59:05 PM UTC 25 1035593922 ps
T2511 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.3431051965 Feb 09 04:57:47 PM UTC 25 Feb 09 04:59:08 PM UTC 25 8037024465 ps
T2512 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.3561099616 Feb 09 04:58:19 PM UTC 25 Feb 09 04:59:09 PM UTC 25 1241849071 ps
T2513 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.1601490656 Feb 09 04:54:06 PM UTC 25 Feb 09 04:59:18 PM UTC 25 8814620215 ps
T2514 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.2512979835 Feb 09 04:59:01 PM UTC 25 Feb 09 04:59:19 PM UTC 25 125960273 ps
T2515 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.3170470047 Feb 09 04:56:52 PM UTC 25 Feb 09 04:59:22 PM UTC 25 15000291486 ps
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