| T2266 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.1319103613 |
|
|
Oct 15 04:07:08 PM UTC 24 |
Oct 15 04:09:45 PM UTC 24 |
602359578 ps |
| T2267 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.2555843006 |
|
|
Oct 15 04:08:23 PM UTC 24 |
Oct 15 04:09:47 PM UTC 24 |
9245009199 ps |
| T2268 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.3030943157 |
|
|
Oct 15 04:08:49 PM UTC 24 |
Oct 15 04:09:48 PM UTC 24 |
1415735727 ps |
| T2269 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3181388984 |
|
|
Oct 15 04:07:10 PM UTC 24 |
Oct 15 04:09:48 PM UTC 24 |
410740875 ps |
| T2270 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.3081620132 |
|
|
Oct 15 04:08:54 PM UTC 24 |
Oct 15 04:09:49 PM UTC 24 |
1803464056 ps |
| T2271 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.1510425882 |
|
|
Oct 15 04:09:32 PM UTC 24 |
Oct 15 04:09:51 PM UTC 24 |
176360835 ps |
| T2272 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.364957528 |
|
|
Oct 15 04:08:56 PM UTC 24 |
Oct 15 04:09:58 PM UTC 24 |
1377857610 ps |
| T2273 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.762917512 |
|
|
Oct 15 04:08:27 PM UTC 24 |
Oct 15 04:10:02 PM UTC 24 |
5686887021 ps |
| T2274 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.2579065877 |
|
|
Oct 15 03:01:17 PM UTC 24 |
Oct 15 04:10:02 PM UTC 24 |
27188077878 ps |
| T2275 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.3152057234 |
|
|
Oct 15 04:07:35 PM UTC 24 |
Oct 15 04:10:07 PM UTC 24 |
3880724115 ps |
| T2276 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.3110717874 |
|
|
Oct 15 04:01:31 PM UTC 24 |
Oct 15 04:10:17 PM UTC 24 |
55950824874 ps |
| T2277 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.3610831409 |
|
|
Oct 15 04:09:39 PM UTC 24 |
Oct 15 04:10:19 PM UTC 24 |
454557101 ps |
| T2278 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.4249628026 |
|
|
Oct 15 04:10:02 PM UTC 24 |
Oct 15 04:10:20 PM UTC 24 |
275224278 ps |
| T2279 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.3514505345 |
|
|
Oct 15 04:10:11 PM UTC 24 |
Oct 15 04:10:21 PM UTC 24 |
36606413 ps |
| T2280 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.2169123524 |
|
|
Oct 15 04:10:11 PM UTC 24 |
Oct 15 04:10:21 PM UTC 24 |
42671725 ps |
| T2281 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.75597916 |
|
|
Oct 15 04:06:41 PM UTC 24 |
Oct 15 04:10:21 PM UTC 24 |
23847762989 ps |
| T2282 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.206720891 |
|
|
Oct 15 04:08:10 PM UTC 24 |
Oct 15 04:10:23 PM UTC 24 |
3797093751 ps |
| T2283 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.397109768 |
|
|
Oct 15 04:09:58 PM UTC 24 |
Oct 15 04:10:25 PM UTC 24 |
290058746 ps |
| T2284 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.1271710523 |
|
|
Oct 15 04:09:55 PM UTC 24 |
Oct 15 04:10:31 PM UTC 24 |
510200924 ps |
| T2285 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.2089673892 |
|
|
Oct 15 04:01:59 PM UTC 24 |
Oct 15 04:10:39 PM UTC 24 |
7191346498 ps |
| T2286 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.2357792984 |
|
|
Oct 15 04:05:36 PM UTC 24 |
Oct 15 04:10:47 PM UTC 24 |
30513293017 ps |
| T2287 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.3456602181 |
|
|
Oct 15 04:01:36 PM UTC 24 |
Oct 15 04:10:47 PM UTC 24 |
37377125906 ps |
| T2288 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.2457380043 |
|
|
Oct 15 04:10:00 PM UTC 24 |
Oct 15 04:10:48 PM UTC 24 |
1232798540 ps |
| T2289 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.2059089859 |
|
|
Oct 15 04:09:46 PM UTC 24 |
Oct 15 04:10:48 PM UTC 24 |
5902142746 ps |
| T2290 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.2255886365 |
|
|
Oct 15 04:03:03 PM UTC 24 |
Oct 15 04:10:49 PM UTC 24 |
8234889151 ps |
| T2291 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.279479124 |
|
|
Oct 15 04:09:25 PM UTC 24 |
Oct 15 04:10:53 PM UTC 24 |
5837633176 ps |
| T2292 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.1734337485 |
|
|
Oct 15 04:09:50 PM UTC 24 |
Oct 15 04:11:00 PM UTC 24 |
659042057 ps |
| T2293 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.966693584 |
|
|
Oct 15 04:09:16 PM UTC 24 |
Oct 15 04:11:02 PM UTC 24 |
9877018103 ps |
| T2294 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.2751375717 |
|
|
Oct 15 04:09:12 PM UTC 24 |
Oct 15 04:11:10 PM UTC 24 |
361331865 ps |
| T2295 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.1831065409 |
|
|
Oct 15 04:03:47 PM UTC 24 |
Oct 15 04:11:14 PM UTC 24 |
42918350037 ps |
| T2296 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.238500841 |
|
|
Oct 15 04:10:48 PM UTC 24 |
Oct 15 04:11:14 PM UTC 24 |
210812043 ps |
| T2297 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.3308792975 |
|
|
Oct 15 04:10:28 PM UTC 24 |
Oct 15 04:11:16 PM UTC 24 |
1349469714 ps |
| T2298 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.4064741627 |
|
|
Oct 15 04:03:44 PM UTC 24 |
Oct 15 04:11:18 PM UTC 24 |
31715639886 ps |
| T2299 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.1699921508 |
|
|
Oct 15 04:11:09 PM UTC 24 |
Oct 15 04:11:18 PM UTC 24 |
46857106 ps |
| T2300 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.1535835420 |
|
|
Oct 15 04:11:11 PM UTC 24 |
Oct 15 04:11:18 PM UTC 24 |
43063942 ps |
| T2301 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.3628045941 |
|
|
Oct 15 04:10:26 PM UTC 24 |
Oct 15 04:11:24 PM UTC 24 |
637433171 ps |
| T2302 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.2573640733 |
|
|
Oct 15 04:10:48 PM UTC 24 |
Oct 15 04:11:26 PM UTC 24 |
1282055571 ps |
| T2303 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.3775886811 |
|
|
Oct 15 04:10:24 PM UTC 24 |
Oct 15 04:11:27 PM UTC 24 |
4005843126 ps |
| T2304 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.1724693090 |
|
|
Oct 15 04:04:36 PM UTC 24 |
Oct 15 04:11:36 PM UTC 24 |
37937130280 ps |
| T2305 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.1303407190 |
|
|
Oct 15 04:10:11 PM UTC 24 |
Oct 15 04:11:39 PM UTC 24 |
9157914829 ps |
| T2306 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.2516572423 |
|
|
Oct 15 04:10:51 PM UTC 24 |
Oct 15 04:11:39 PM UTC 24 |
1124340536 ps |
| T2307 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.3569915489 |
|
|
Oct 15 04:10:47 PM UTC 24 |
Oct 15 04:11:46 PM UTC 24 |
1254376899 ps |
| T2308 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.4265895650 |
|
|
Oct 15 04:11:43 PM UTC 24 |
Oct 15 04:11:53 PM UTC 24 |
66911865 ps |
| T2309 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.3642439662 |
|
|
Oct 15 04:11:44 PM UTC 24 |
Oct 15 04:11:56 PM UTC 24 |
112137752 ps |
| T2310 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.739169399 |
|
|
Oct 15 04:11:41 PM UTC 24 |
Oct 15 04:11:57 PM UTC 24 |
100476091 ps |
| T2311 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.1273088050 |
|
|
Oct 15 04:11:21 PM UTC 24 |
Oct 15 04:12:00 PM UTC 24 |
429816089 ps |
| T2312 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.65544947 |
|
|
Oct 15 04:11:45 PM UTC 24 |
Oct 15 04:12:00 PM UTC 24 |
186302730 ps |
| T2313 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.3572175124 |
|
|
Oct 15 04:12:03 PM UTC 24 |
Oct 15 04:12:12 PM UTC 24 |
40784014 ps |
| T2314 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.594532547 |
|
|
Oct 15 04:09:47 PM UTC 24 |
Oct 15 04:12:12 PM UTC 24 |
10220427820 ps |
| T2315 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.2152834926 |
|
|
Oct 15 04:02:31 PM UTC 24 |
Oct 15 04:12:12 PM UTC 24 |
35613534452 ps |
| T2316 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.3695676218 |
|
|
Oct 15 04:12:04 PM UTC 24 |
Oct 15 04:12:12 PM UTC 24 |
36784076 ps |
| T2317 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.2778553366 |
|
|
Oct 15 04:04:46 PM UTC 24 |
Oct 15 04:12:22 PM UTC 24 |
23755151982 ps |
| T2318 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.2488898733 |
|
|
Oct 15 04:12:23 PM UTC 24 |
Oct 15 04:12:33 PM UTC 24 |
28913876 ps |
| T2319 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.666630183 |
|
|
Oct 15 04:12:20 PM UTC 24 |
Oct 15 04:12:37 PM UTC 24 |
307590560 ps |
| T2320 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.1479744551 |
|
|
Oct 15 04:06:09 PM UTC 24 |
Oct 15 04:12:41 PM UTC 24 |
11144013706 ps |
| T2321 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.4145345305 |
|
|
Oct 15 04:11:17 PM UTC 24 |
Oct 15 04:12:43 PM UTC 24 |
2147264722 ps |
| T2322 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.414598093 |
|
|
Oct 15 04:07:34 PM UTC 24 |
Oct 15 04:12:45 PM UTC 24 |
19501702728 ps |
| T2323 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.2606758944 |
|
|
Oct 15 04:11:41 PM UTC 24 |
Oct 15 04:12:48 PM UTC 24 |
809599424 ps |
| T2324 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.633953721 |
|
|
Oct 15 04:11:15 PM UTC 24 |
Oct 15 04:12:53 PM UTC 24 |
4896039164 ps |
| T2325 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.1712743685 |
|
|
Oct 15 04:10:45 PM UTC 24 |
Oct 15 04:12:57 PM UTC 24 |
3422294336 ps |
| T2326 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.4100840522 |
|
|
Oct 15 04:12:48 PM UTC 24 |
Oct 15 04:12:57 PM UTC 24 |
45523084 ps |
| T2327 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.780441008 |
|
|
Oct 15 04:11:13 PM UTC 24 |
Oct 15 04:13:02 PM UTC 24 |
6654091667 ps |
| T2328 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.1466141117 |
|
|
Oct 15 04:12:38 PM UTC 24 |
Oct 15 04:13:11 PM UTC 24 |
424964205 ps |
| T2329 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.1393048534 |
|
|
Oct 15 04:13:15 PM UTC 24 |
Oct 15 04:13:24 PM UTC 24 |
36865040 ps |
| T2330 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.501439337 |
|
|
Oct 15 04:13:19 PM UTC 24 |
Oct 15 04:13:29 PM UTC 24 |
51920039 ps |
| T2331 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.1143688193 |
|
|
Oct 15 04:12:16 PM UTC 24 |
Oct 15 04:13:30 PM UTC 24 |
4760453725 ps |
| T2332 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.594863041 |
|
|
Oct 15 04:12:01 PM UTC 24 |
Oct 15 04:13:30 PM UTC 24 |
73063743 ps |
| T2333 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.4198937282 |
|
|
Oct 15 04:12:10 PM UTC 24 |
Oct 15 04:13:42 PM UTC 24 |
7933204906 ps |
| T2334 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.2980004820 |
|
|
Oct 15 04:09:08 PM UTC 24 |
Oct 15 04:13:47 PM UTC 24 |
7893350212 ps |
| T2335 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.3840338051 |
|
|
Oct 15 04:10:09 PM UTC 24 |
Oct 15 04:13:47 PM UTC 24 |
3019263145 ps |
| T2336 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.4183532708 |
|
|
Oct 15 04:12:57 PM UTC 24 |
Oct 15 04:13:50 PM UTC 24 |
1320671843 ps |
| T2337 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.3908090571 |
|
|
Oct 15 04:07:28 PM UTC 24 |
Oct 15 04:13:50 PM UTC 24 |
38886017447 ps |
| T2338 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.2201425422 |
|
|
Oct 15 04:12:40 PM UTC 24 |
Oct 15 04:13:54 PM UTC 24 |
1648525926 ps |
| T2339 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.1602921267 |
|
|
Oct 15 04:13:38 PM UTC 24 |
Oct 15 04:13:55 PM UTC 24 |
93768033 ps |
| T2340 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.934873965 |
|
|
Oct 15 04:12:37 PM UTC 24 |
Oct 15 04:13:59 PM UTC 24 |
1108652541 ps |
| T2341 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1959865320 |
|
|
Oct 15 04:03:05 PM UTC 24 |
Oct 15 04:14:13 PM UTC 24 |
12853429463 ps |
| T2342 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.1893860856 |
|
|
Oct 15 04:14:13 PM UTC 24 |
Oct 15 04:14:25 PM UTC 24 |
125340159 ps |
| T2343 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.2184273395 |
|
|
Oct 15 04:14:06 PM UTC 24 |
Oct 15 04:14:25 PM UTC 24 |
140303726 ps |
| T2344 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.931491657 |
|
|
Oct 15 03:59:45 PM UTC 24 |
Oct 15 04:14:31 PM UTC 24 |
51173263403 ps |
| T2345 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.2569539495 |
|
|
Oct 15 04:13:22 PM UTC 24 |
Oct 15 04:14:36 PM UTC 24 |
4930827965 ps |
| T2346 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.2873630527 |
|
|
Oct 15 04:10:45 PM UTC 24 |
Oct 15 04:14:37 PM UTC 24 |
15786424795 ps |
| T2347 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.706137365 |
|
|
Oct 15 04:10:50 PM UTC 24 |
Oct 15 04:14:44 PM UTC 24 |
5729743658 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.4069654572 |
|
|
Oct 15 03:10:42 PM UTC 24 |
Oct 15 04:14:44 PM UTC 24 |
27748001421 ps |
| T2348 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.584815363 |
|
|
Oct 15 04:14:12 PM UTC 24 |
Oct 15 04:14:45 PM UTC 24 |
231684188 ps |
| T2349 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.1850940003 |
|
|
Oct 15 04:14:13 PM UTC 24 |
Oct 15 04:14:48 PM UTC 24 |
221483264 ps |
| T2350 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.2284990909 |
|
|
Oct 15 04:14:41 PM UTC 24 |
Oct 15 04:14:54 PM UTC 24 |
184583015 ps |
| T2351 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_aliasing.4280350965 |
|
|
Oct 15 02:38:12 PM UTC 24 |
Oct 15 04:14:55 PM UTC 24 |
34912443576 ps |
| T2352 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.4128419469 |
|
|
Oct 15 04:13:23 PM UTC 24 |
Oct 15 04:14:57 PM UTC 24 |
8406831151 ps |
| T2353 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.395292291 |
|
|
Oct 15 04:14:51 PM UTC 24 |
Oct 15 04:14:59 PM UTC 24 |
46831045 ps |
| T2354 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.2738563181 |
|
|
Oct 15 04:13:27 PM UTC 24 |
Oct 15 04:15:01 PM UTC 24 |
2566892060 ps |
| T2355 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.38200942 |
|
|
Oct 15 04:14:20 PM UTC 24 |
Oct 15 04:15:02 PM UTC 24 |
167803702 ps |
| T2356 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.1163639859 |
|
|
Oct 15 04:11:51 PM UTC 24 |
Oct 15 04:15:16 PM UTC 24 |
2132975089 ps |
| T2357 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.1520440349 |
|
|
Oct 15 04:05:54 PM UTC 24 |
Oct 15 04:15:19 PM UTC 24 |
37277030131 ps |
| T2358 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.1712545345 |
|
|
Oct 15 04:10:07 PM UTC 24 |
Oct 15 04:15:24 PM UTC 24 |
9592689545 ps |
| T2359 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.1088813063 |
|
|
Oct 15 04:15:05 PM UTC 24 |
Oct 15 04:15:28 PM UTC 24 |
245381216 ps |
| T2360 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.4012693106 |
|
|
Oct 15 04:13:04 PM UTC 24 |
Oct 15 04:15:31 PM UTC 24 |
1601478696 ps |
| T2361 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.4136963132 |
|
|
Oct 15 04:10:56 PM UTC 24 |
Oct 15 04:15:31 PM UTC 24 |
6320504915 ps |
| T2362 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.4172886822 |
|
|
Oct 15 04:13:54 PM UTC 24 |
Oct 15 04:15:32 PM UTC 24 |
1862387851 ps |
| T2363 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.496477443 |
|
|
Oct 15 04:11:03 PM UTC 24 |
Oct 15 04:15:35 PM UTC 24 |
3415366750 ps |
| T2364 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.1092506266 |
|
|
Oct 15 04:15:22 PM UTC 24 |
Oct 15 04:15:36 PM UTC 24 |
57444565 ps |
| T2365 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.712923738 |
|
|
Oct 15 04:15:23 PM UTC 24 |
Oct 15 04:15:37 PM UTC 24 |
220338439 ps |
| T2366 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.1592853800 |
|
|
Oct 15 04:15:20 PM UTC 24 |
Oct 15 04:15:41 PM UTC 24 |
229271432 ps |
| T2367 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.1562885864 |
|
|
Oct 15 04:15:13 PM UTC 24 |
Oct 15 04:15:43 PM UTC 24 |
305436076 ps |
| T2368 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.988830882 |
|
|
Oct 15 04:13:07 PM UTC 24 |
Oct 15 04:15:43 PM UTC 24 |
5021117424 ps |
| T2369 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.2584979444 |
|
|
Oct 15 04:11:08 PM UTC 24 |
Oct 15 04:15:45 PM UTC 24 |
722252096 ps |
| T2370 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.2093360608 |
|
|
Oct 15 04:15:20 PM UTC 24 |
Oct 15 04:15:48 PM UTC 24 |
267659746 ps |
| T2371 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.3013180871 |
|
|
Oct 15 04:12:26 PM UTC 24 |
Oct 15 04:15:51 PM UTC 24 |
11157404131 ps |
| T2372 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.3201418657 |
|
|
Oct 15 04:11:51 PM UTC 24 |
Oct 15 04:15:56 PM UTC 24 |
6476141203 ps |
| T2373 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.2127333865 |
|
|
Oct 15 04:15:49 PM UTC 24 |
Oct 15 04:15:59 PM UTC 24 |
38161787 ps |
| T2374 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.1712798349 |
|
|
Oct 15 04:15:52 PM UTC 24 |
Oct 15 04:16:02 PM UTC 24 |
55972255 ps |
| T2375 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.4259483492 |
|
|
Oct 15 04:15:02 PM UTC 24 |
Oct 15 04:16:03 PM UTC 24 |
1741777584 ps |
| T2376 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.804639186 |
|
|
Oct 15 04:12:40 PM UTC 24 |
Oct 15 04:16:13 PM UTC 24 |
12802387224 ps |
| T2377 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.2210155707 |
|
|
Oct 15 04:14:58 PM UTC 24 |
Oct 15 04:16:19 PM UTC 24 |
5620922983 ps |
| T2378 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.638341490 |
|
|
Oct 15 04:10:47 PM UTC 24 |
Oct 15 04:16:23 PM UTC 24 |
17529719097 ps |
| T2379 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.2573521758 |
|
|
Oct 15 04:14:52 PM UTC 24 |
Oct 15 04:16:24 PM UTC 24 |
9691992698 ps |
| T2380 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.2749455522 |
|
|
Oct 15 04:16:05 PM UTC 24 |
Oct 15 04:16:28 PM UTC 24 |
535771146 ps |
| T2381 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.3726950367 |
|
|
Oct 15 04:15:59 PM UTC 24 |
Oct 15 04:16:29 PM UTC 24 |
608803964 ps |
| T2382 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.3392484965 |
|
|
Oct 15 04:16:17 PM UTC 24 |
Oct 15 04:16:32 PM UTC 24 |
214588116 ps |
| T2383 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.3788234752 |
|
|
Oct 15 04:16:10 PM UTC 24 |
Oct 15 04:16:36 PM UTC 24 |
149753132 ps |
| T2384 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.2043481794 |
|
|
Oct 15 04:09:03 PM UTC 24 |
Oct 15 04:16:36 PM UTC 24 |
11836579263 ps |
| T2385 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.2714577357 |
|
|
Oct 15 03:16:19 PM UTC 24 |
Oct 15 04:16:37 PM UTC 24 |
31825138652 ps |
| T2386 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.2098853899 |
|
|
Oct 15 04:15:59 PM UTC 24 |
Oct 15 04:16:47 PM UTC 24 |
616751691 ps |
| T2387 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.718390955 |
|
|
Oct 15 04:16:39 PM UTC 24 |
Oct 15 04:16:49 PM UTC 24 |
43372098 ps |
| T2388 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.1255978224 |
|
|
Oct 15 04:16:08 PM UTC 24 |
Oct 15 04:16:51 PM UTC 24 |
1165888392 ps |
| T2389 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.1056075247 |
|
|
Oct 15 04:16:44 PM UTC 24 |
Oct 15 04:16:53 PM UTC 24 |
37360661 ps |
| T2390 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.3614819840 |
|
|
Oct 15 04:07:38 PM UTC 24 |
Oct 15 04:17:05 PM UTC 24 |
36446124473 ps |
| T2391 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.683694122 |
|
|
Oct 15 04:14:27 PM UTC 24 |
Oct 15 04:17:09 PM UTC 24 |
4123874269 ps |
| T2392 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.3620507965 |
|
|
Oct 15 04:10:33 PM UTC 24 |
Oct 15 04:17:12 PM UTC 24 |
42944680670 ps |
| T2393 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.305379334 |
|
|
Oct 15 04:16:26 PM UTC 24 |
Oct 15 04:17:25 PM UTC 24 |
142738996 ps |
| T2394 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.2174234242 |
|
|
Oct 15 04:17:20 PM UTC 24 |
Oct 15 04:17:35 PM UTC 24 |
168079817 ps |
| T2395 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.642440820 |
|
|
Oct 15 04:17:17 PM UTC 24 |
Oct 15 04:17:36 PM UTC 24 |
97114517 ps |
| T2396 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.2003748817 |
|
|
Oct 15 04:15:58 PM UTC 24 |
Oct 15 04:17:37 PM UTC 24 |
6078044013 ps |
| T2397 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.3800100217 |
|
|
Oct 15 04:16:54 PM UTC 24 |
Oct 15 04:17:37 PM UTC 24 |
469211989 ps |
| T2398 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.2074063317 |
|
|
Oct 15 04:14:15 PM UTC 24 |
Oct 15 04:17:44 PM UTC 24 |
2771785045 ps |
| T2399 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.2952156933 |
|
|
Oct 15 04:16:55 PM UTC 24 |
Oct 15 04:17:54 PM UTC 24 |
573657022 ps |
| T2400 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.2059305602 |
|
|
Oct 15 04:17:11 PM UTC 24 |
Oct 15 04:17:54 PM UTC 24 |
524766234 ps |
| T2401 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.1749228557 |
|
|
Oct 15 04:15:54 PM UTC 24 |
Oct 15 04:17:55 PM UTC 24 |
8638603309 ps |
| T2402 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.859832599 |
|
|
Oct 15 04:16:50 PM UTC 24 |
Oct 15 04:18:05 PM UTC 24 |
3192234822 ps |
| T2403 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.2803824145 |
|
|
Oct 15 04:17:13 PM UTC 24 |
Oct 15 04:18:07 PM UTC 24 |
542367040 ps |
| T2404 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.3064903500 |
|
|
Oct 15 04:16:08 PM UTC 24 |
Oct 15 04:18:10 PM UTC 24 |
2836253515 ps |
| T2405 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.1487819893 |
|
|
Oct 15 04:18:02 PM UTC 24 |
Oct 15 04:18:10 PM UTC 24 |
37008996 ps |
| T2406 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.3683682146 |
|
|
Oct 15 04:18:01 PM UTC 24 |
Oct 15 04:18:12 PM UTC 24 |
119623816 ps |
| T2407 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.1368878632 |
|
|
Oct 15 04:16:46 PM UTC 24 |
Oct 15 04:18:16 PM UTC 24 |
7386548797 ps |
| T2408 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.115111137 |
|
|
Oct 15 04:13:56 PM UTC 24 |
Oct 15 04:18:19 PM UTC 24 |
17801332681 ps |
| T2409 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.3230988378 |
|
|
Oct 15 04:10:10 PM UTC 24 |
Oct 15 04:18:20 PM UTC 24 |
3964985604 ps |
| T2410 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.267979572 |
|
|
Oct 15 04:15:42 PM UTC 24 |
Oct 15 04:18:20 PM UTC 24 |
2090097147 ps |
| T2411 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.570968946 |
|
|
Oct 15 04:07:10 PM UTC 24 |
Oct 15 04:18:29 PM UTC 24 |
21476567899 ps |
| T2412 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1262122324 |
|
|
Oct 15 04:06:46 PM UTC 24 |
Oct 15 04:18:31 PM UTC 24 |
49245445826 ps |
| T2413 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.2572823052 |
|
|
Oct 15 04:16:30 PM UTC 24 |
Oct 15 04:18:35 PM UTC 24 |
3468015204 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.3979908108 |
|
|
Oct 15 04:10:10 PM UTC 24 |
Oct 15 04:18:39 PM UTC 24 |
9539257584 ps |
| T2414 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.1536899415 |
|
|
Oct 15 04:17:01 PM UTC 24 |
Oct 15 04:18:43 PM UTC 24 |
1096465802 ps |
| T2415 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.1807438251 |
|
|
Oct 15 04:07:59 PM UTC 24 |
Oct 15 04:18:46 PM UTC 24 |
16633773773 ps |
| T2416 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.1878816964 |
|
|
Oct 15 04:11:51 PM UTC 24 |
Oct 15 04:18:48 PM UTC 24 |
4878428932 ps |
| T2417 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.3324757988 |
|
|
Oct 15 04:13:02 PM UTC 24 |
Oct 15 04:18:57 PM UTC 24 |
710682044 ps |
| T2418 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.2808049277 |
|
|
Oct 15 04:18:37 PM UTC 24 |
Oct 15 04:18:59 PM UTC 24 |
481357733 ps |
| T2419 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.269664942 |
|
|
Oct 15 04:13:07 PM UTC 24 |
Oct 15 04:19:06 PM UTC 24 |
4845484855 ps |
| T2420 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.1308690989 |
|
|
Oct 15 04:18:56 PM UTC 24 |
Oct 15 04:19:08 PM UTC 24 |
189281304 ps |
| T2421 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.2692363817 |
|
|
Oct 15 04:17:36 PM UTC 24 |
Oct 15 04:19:08 PM UTC 24 |
249662293 ps |
| T2422 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.333961061 |
|
|
Oct 15 04:19:03 PM UTC 24 |
Oct 15 04:19:13 PM UTC 24 |
49234188 ps |
| T2423 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.3173850788 |
|
|
Oct 15 04:18:20 PM UTC 24 |
Oct 15 04:19:14 PM UTC 24 |
611389545 ps |
| T2424 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.2745332630 |
|
|
Oct 15 04:11:37 PM UTC 24 |
Oct 15 04:19:16 PM UTC 24 |
27631985842 ps |
| T2425 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.2359185451 |
|
|
Oct 15 04:18:09 PM UTC 24 |
Oct 15 04:19:18 PM UTC 24 |
1567764011 ps |
| T2426 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.2243859129 |
|
|
Oct 15 04:18:43 PM UTC 24 |
Oct 15 04:19:20 PM UTC 24 |
98486249 ps |
| T2427 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3085642703 |
|
|
Oct 15 04:18:55 PM UTC 24 |
Oct 15 04:19:30 PM UTC 24 |
42743300 ps |
| T2428 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.1073816878 |
|
|
Oct 15 04:15:09 PM UTC 24 |
Oct 15 04:19:31 PM UTC 24 |
18088455714 ps |
| T2429 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.4188963512 |
|
|
Oct 15 04:18:33 PM UTC 24 |
Oct 15 04:19:31 PM UTC 24 |
591658879 ps |
| T2430 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.93454456 |
|
|
Oct 15 04:19:16 PM UTC 24 |
Oct 15 04:19:34 PM UTC 24 |
145032813 ps |
| T2431 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.2671315811 |
|
|
Oct 15 04:18:42 PM UTC 24 |
Oct 15 04:19:36 PM UTC 24 |
1192764962 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.671281422 |
|
|
Oct 15 04:09:49 PM UTC 24 |
Oct 15 04:19:40 PM UTC 24 |
32976687131 ps |
| T2432 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.141881913 |
|
|
Oct 15 04:08:34 PM UTC 24 |
Oct 15 04:19:40 PM UTC 24 |
33549674200 ps |
| T2433 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.722963442 |
|
|
Oct 15 04:18:35 PM UTC 24 |
Oct 15 04:19:41 PM UTC 24 |
2099272417 ps |
| T2434 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.936780456 |
|
|
Oct 15 04:18:36 PM UTC 24 |
Oct 15 04:19:46 PM UTC 24 |
2073609647 ps |
| T2435 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.1751102594 |
|
|
Oct 15 04:15:27 PM UTC 24 |
Oct 15 04:19:47 PM UTC 24 |
3197966255 ps |
| T2436 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.3361069406 |
|
|
Oct 15 04:18:02 PM UTC 24 |
Oct 15 04:19:48 PM UTC 24 |
7053089240 ps |
| T2437 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.3970845235 |
|
|
Oct 15 04:14:22 PM UTC 24 |
Oct 15 04:19:49 PM UTC 24 |
4656293704 ps |
| T2438 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.4206199802 |
|
|
Oct 15 04:08:33 PM UTC 24 |
Oct 15 04:19:55 PM UTC 24 |
54925948316 ps |
| T2439 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.914445119 |
|
|
Oct 15 04:19:44 PM UTC 24 |
Oct 15 04:20:01 PM UTC 24 |
7847596 ps |
| T2440 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.1023887363 |
|
|
Oct 15 04:15:10 PM UTC 24 |
Oct 15 04:20:02 PM UTC 24 |
21670042089 ps |
| T2441 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.2497711523 |
|
|
Oct 15 04:19:54 PM UTC 24 |
Oct 15 04:20:08 PM UTC 24 |
240173793 ps |
| T2442 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.3461794210 |
|
|
Oct 15 04:20:01 PM UTC 24 |
Oct 15 04:20:09 PM UTC 24 |
51491017 ps |
| T2443 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.2580114145 |
|
|
Oct 15 04:18:03 PM UTC 24 |
Oct 15 04:20:09 PM UTC 24 |
9592763310 ps |
| T2444 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.2375711676 |
|
|
Oct 15 04:17:31 PM UTC 24 |
Oct 15 04:20:22 PM UTC 24 |
4934455303 ps |
| T2445 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.996886352 |
|
|
Oct 15 03:58:46 PM UTC 24 |
Oct 15 04:20:24 PM UTC 24 |
89132484146 ps |
| T2446 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.3491680011 |
|
|
Oct 15 04:19:42 PM UTC 24 |
Oct 15 04:20:24 PM UTC 24 |
318704476 ps |
| T2447 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.2210306381 |
|
|
Oct 15 04:16:22 PM UTC 24 |
Oct 15 04:20:27 PM UTC 24 |
6710168525 ps |
| T2448 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.531896703 |
|
|
Oct 15 04:20:17 PM UTC 24 |
Oct 15 04:20:28 PM UTC 24 |
95337659 ps |
| T2449 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.2942378331 |
|
|
Oct 15 04:19:07 PM UTC 24 |
Oct 15 04:20:30 PM UTC 24 |
6026593085 ps |
| T2450 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.2233368962 |
|
|
Oct 15 04:19:06 PM UTC 24 |
Oct 15 04:20:30 PM UTC 24 |
7173827306 ps |
| T2451 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.2798792167 |
|
|
Oct 15 04:19:41 PM UTC 24 |
Oct 15 04:20:31 PM UTC 24 |
1202714597 ps |
| T2452 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.3278554191 |
|
|
Oct 15 04:06:07 PM UTC 24 |
Oct 15 04:20:33 PM UTC 24 |
5876942257 ps |
| T2453 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.203527676 |
|
|
Oct 15 04:19:39 PM UTC 24 |
Oct 15 04:20:34 PM UTC 24 |
1305049917 ps |
| T2454 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.244341276 |
|
|
Oct 15 04:20:05 PM UTC 24 |
Oct 15 04:20:37 PM UTC 24 |
323188384 ps |
| T2455 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.299580203 |
|
|
Oct 15 04:17:52 PM UTC 24 |
Oct 15 04:20:39 PM UTC 24 |
2702000809 ps |
| T2456 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.4010707119 |
|
|
Oct 15 04:20:25 PM UTC 24 |
Oct 15 04:20:41 PM UTC 24 |
118686932 ps |
| T2457 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.2967058652 |
|
|
Oct 15 04:19:54 PM UTC 24 |
Oct 15 04:20:44 PM UTC 24 |
364719792 ps |
| T2458 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.1125998443 |
|
|
Oct 15 04:08:44 PM UTC 24 |
Oct 15 04:20:51 PM UTC 24 |
47114303968 ps |
| T2459 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.778476571 |
|
|
Oct 15 04:20:08 PM UTC 24 |
Oct 15 04:20:57 PM UTC 24 |
423753556 ps |
| T2460 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.518120693 |
|
|
Oct 15 04:20:19 PM UTC 24 |
Oct 15 04:20:57 PM UTC 24 |
385789450 ps |
| T2461 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.3629032760 |
|
|
Oct 15 04:19:14 PM UTC 24 |
Oct 15 04:20:57 PM UTC 24 |
2554596668 ps |
| T2462 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.381304336 |
|
|
Oct 15 04:19:43 PM UTC 24 |
Oct 15 04:20:59 PM UTC 24 |
842412395 ps |
| T2463 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.4202767619 |
|
|
Oct 15 04:19:35 PM UTC 24 |
Oct 15 04:20:59 PM UTC 24 |
2404086015 ps |
| T2464 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.1520687406 |
|
|
Oct 15 04:20:52 PM UTC 24 |
Oct 15 04:21:00 PM UTC 24 |
48461974 ps |
| T2465 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.3222563939 |
|
|
Oct 15 04:20:49 PM UTC 24 |
Oct 15 04:21:03 PM UTC 24 |
208828648 ps |
| T2466 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.3793633969 |
|
|
Oct 15 04:20:27 PM UTC 24 |
Oct 15 04:21:04 PM UTC 24 |
780421353 ps |
| T2467 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2474260022 |
|
|
Oct 15 04:20:33 PM UTC 24 |
Oct 15 04:21:09 PM UTC 24 |
239015277 ps |
| T2468 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.1698682415 |
|
|
Oct 15 04:20:53 PM UTC 24 |
Oct 15 04:21:16 PM UTC 24 |
220208219 ps |
| T2469 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.3920501410 |
|
|
Oct 15 04:19:32 PM UTC 24 |
Oct 15 04:21:17 PM UTC 24 |
2397875725 ps |
| T2470 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.748973876 |
|
|
Oct 15 04:19:59 PM UTC 24 |
Oct 15 04:21:19 PM UTC 24 |
6293433412 ps |
| T2471 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.3485489365 |
|
|
Oct 15 04:20:07 PM UTC 24 |
Oct 15 04:21:20 PM UTC 24 |
5481698826 ps |
| T2472 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.264968141 |
|
|
Oct 15 04:03:55 PM UTC 24 |
Oct 15 04:21:23 PM UTC 24 |
65283866385 ps |
| T2473 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.2180061143 |
|
|
Oct 15 04:09:08 PM UTC 24 |
Oct 15 04:21:23 PM UTC 24 |
5922964184 ps |
| T2474 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.2315174742 |
|
|
Oct 15 04:11:28 PM UTC 24 |
Oct 15 04:21:24 PM UTC 24 |
63425161141 ps |
| T2475 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.3826336272 |
|
|
Oct 15 04:15:43 PM UTC 24 |
Oct 15 04:21:29 PM UTC 24 |
1780309811 ps |
| T2476 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.3185583110 |
|
|
Oct 15 04:21:23 PM UTC 24 |
Oct 15 04:21:33 PM UTC 24 |
44603465 ps |
| T2477 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.1342392633 |
|
|
Oct 15 04:21:26 PM UTC 24 |
Oct 15 04:21:35 PM UTC 24 |
56467045 ps |
| T2478 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.811731675 |
|
|
Oct 15 04:21:13 PM UTC 24 |
Oct 15 04:21:39 PM UTC 24 |
199849601 ps |
| T2479 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.561764136 |
|
|
Oct 15 04:20:51 PM UTC 24 |
Oct 15 04:21:40 PM UTC 24 |
1471356679 ps |
| T2480 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.2004800250 |
|
|
Oct 15 04:12:26 PM UTC 24 |
Oct 15 04:21:41 PM UTC 24 |
57761884772 ps |
| T2481 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.3686193223 |
|
|
Oct 15 04:15:27 PM UTC 24 |
Oct 15 04:21:43 PM UTC 24 |
1218989717 ps |
| T2482 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.2477761708 |
|
|
Oct 15 04:20:57 PM UTC 24 |
Oct 15 04:21:51 PM UTC 24 |
3615061878 ps |
| T2483 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.720439552 |
|
|
Oct 15 04:21:04 PM UTC 24 |
Oct 15 04:22:05 PM UTC 24 |
1960648955 ps |
| T2484 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.3600530100 |
|
|
Oct 15 04:21:22 PM UTC 24 |
Oct 15 04:22:05 PM UTC 24 |
819171283 ps |
| T2485 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.2689255179 |
|
|
Oct 15 04:21:39 PM UTC 24 |
Oct 15 04:22:06 PM UTC 24 |
265072236 ps |
| T2486 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.2821484586 |
|
|
Oct 15 04:21:10 PM UTC 24 |
Oct 15 04:22:07 PM UTC 24 |
1439036492 ps |
| T2487 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.2216459165 |
|
|
Oct 15 04:17:00 PM UTC 24 |
Oct 15 04:22:24 PM UTC 24 |
21078731397 ps |
| T2488 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.1409738876 |
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|
Oct 15 04:20:49 PM UTC 24 |
Oct 15 04:22:30 PM UTC 24 |
8906259061 ps |
| T2489 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.2505002729 |
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|
Oct 15 04:22:18 PM UTC 24 |
Oct 15 04:22:32 PM UTC 24 |
204457676 ps |
| T2490 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.701055435 |
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|
Oct 15 04:21:41 PM UTC 24 |
Oct 15 04:22:32 PM UTC 24 |
1043604206 ps |
| T2491 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.2894813649 |
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|
Oct 15 04:21:47 PM UTC 24 |
Oct 15 04:22:35 PM UTC 24 |
479517795 ps |
| T2492 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.3843225307 |
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|
Oct 15 04:20:47 PM UTC 24 |
Oct 15 04:22:36 PM UTC 24 |
3925607498 ps |
| T2493 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.890007035 |
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|
Oct 15 04:02:38 PM UTC 24 |
Oct 15 04:22:37 PM UTC 24 |
66357413315 ps |
| T2494 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.1751979377 |
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|
Oct 15 04:21:00 PM UTC 24 |
Oct 15 04:22:40 PM UTC 24 |
2334198067 ps |
| T2495 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.4188859093 |
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|
Oct 15 04:22:33 PM UTC 24 |
Oct 15 04:22:41 PM UTC 24 |
42539986 ps |
| T2496 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.309648410 |
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|
Oct 15 04:18:20 PM UTC 24 |
Oct 15 04:22:52 PM UTC 24 |
28662037835 ps |
| T2497 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.4134250844 |
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|
Oct 15 04:21:33 PM UTC 24 |
Oct 15 04:22:53 PM UTC 24 |
3393028764 ps |
| T2498 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.1555004077 |
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|
Oct 15 04:21:58 PM UTC 24 |
Oct 15 04:22:56 PM UTC 24 |
1455491522 ps |
| T2499 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.2741226082 |
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|
Oct 15 04:21:57 PM UTC 24 |
Oct 15 04:22:56 PM UTC 24 |
1114108142 ps |
| T2500 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.4067615475 |
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|
Oct 15 04:21:46 PM UTC 24 |
Oct 15 04:23:00 PM UTC 24 |
974865090 ps |
| T2501 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.1057217509 |
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|
Oct 15 04:18:45 PM UTC 24 |
Oct 15 04:23:03 PM UTC 24 |
3041938185 ps |
| T2502 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.1976672553 |
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|
Oct 15 04:21:28 PM UTC 24 |
Oct 15 04:23:05 PM UTC 24 |
9512179509 ps |
| T2503 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.3265617237 |
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|
Oct 15 04:16:59 PM UTC 24 |
Oct 15 04:23:07 PM UTC 24 |
36593387529 ps |
| T2504 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.3571197394 |
|
|
Oct 15 04:22:59 PM UTC 24 |
Oct 15 04:23:14 PM UTC 24 |
109782769 ps |
| T2505 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.245086077 |
|
|
Oct 15 04:23:04 PM UTC 24 |
Oct 15 04:23:20 PM UTC 24 |
245024764 ps |
| T2506 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.3551522504 |
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|
Oct 15 04:05:01 PM UTC 24 |
Oct 15 04:23:20 PM UTC 24 |
19552878726 ps |
| T2507 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.496584045 |
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|
Oct 15 04:21:53 PM UTC 24 |
Oct 15 04:23:22 PM UTC 24 |
2511327378 ps |
| T2508 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.3472354834 |
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|
Oct 15 04:23:03 PM UTC 24 |
Oct 15 04:23:23 PM UTC 24 |
150036936 ps |
| T2509 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.3397573283 |
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|
Oct 15 04:13:52 PM UTC 24 |
Oct 15 04:23:24 PM UTC 24 |
53236554205 ps |
| T2510 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.819532042 |
|
|
Oct 15 04:15:59 PM UTC 24 |
Oct 15 04:23:27 PM UTC 24 |
45992934285 ps |
| T2511 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.817383887 |
|
|
Oct 15 04:21:27 PM UTC 24 |
Oct 15 04:23:34 PM UTC 24 |
2766720318 ps |
| T2512 |
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.592752 |
|
|
Oct 15 04:20:59 PM UTC 24 |
Oct 15 04:23:36 PM UTC 24 |
16601646263 ps |