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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.95 95.51 93.50 95.41 94.18 97.57 99.53


Total test records in report: 2918
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T2031 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.2927998485 Oct 15 03:54:40 PM UTC 24 Oct 15 03:55:41 PM UTC 24 801765759 ps
T643 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.2166621472 Oct 15 03:42:50 PM UTC 24 Oct 15 03:55:47 PM UTC 24 7488334160 ps
T2032 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.2130342626 Oct 15 03:55:11 PM UTC 24 Oct 15 03:55:49 PM UTC 24 74921368 ps
T2033 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.1880309221 Oct 15 03:49:21 PM UTC 24 Oct 15 03:55:49 PM UTC 24 23276729319 ps
T2034 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.2395261420 Oct 15 03:53:53 PM UTC 24 Oct 15 03:55:50 PM UTC 24 2443897570 ps
T2035 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.3757364792 Oct 15 03:54:59 PM UTC 24 Oct 15 03:55:56 PM UTC 24 107173422 ps
T2036 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.1740963134 Oct 15 03:52:39 PM UTC 24 Oct 15 03:55:56 PM UTC 24 13452538708 ps
T2037 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.308152066 Oct 15 03:51:31 PM UTC 24 Oct 15 03:55:56 PM UTC 24 22960065266 ps
T807 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.3157912917 Oct 15 03:51:05 PM UTC 24 Oct 15 03:55:57 PM UTC 24 8983949185 ps
T2038 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.1581111373 Oct 15 03:54:09 PM UTC 24 Oct 15 03:55:59 PM UTC 24 3403524372 ps
T2039 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.1742979805 Oct 15 02:51:10 PM UTC 24 Oct 15 03:56:02 PM UTC 24 28547300389 ps
T2040 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.691263039 Oct 15 03:55:50 PM UTC 24 Oct 15 03:56:03 PM UTC 24 56241208 ps
T2041 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.3606359997 Oct 15 03:55:53 PM UTC 24 Oct 15 03:56:05 PM UTC 24 222501651 ps
T2042 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.1213179103 Oct 15 03:55:51 PM UTC 24 Oct 15 03:56:11 PM UTC 24 475919565 ps
T2043 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.569061590 Oct 15 03:55:37 PM UTC 24 Oct 15 03:56:15 PM UTC 24 374356724 ps
T2044 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.2733890907 Oct 15 03:56:14 PM UTC 24 Oct 15 03:56:25 PM UTC 24 173396340 ps
T2045 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.1036225580 Oct 15 03:56:16 PM UTC 24 Oct 15 03:56:27 PM UTC 24 44860050 ps
T2046 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.322178084 Oct 15 03:55:32 PM UTC 24 Oct 15 03:56:30 PM UTC 24 536775058 ps
T2047 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.3070725600 Oct 15 03:53:50 PM UTC 24 Oct 15 03:56:33 PM UTC 24 3713567725 ps
T2048 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.1056415505 Oct 15 03:56:00 PM UTC 24 Oct 15 03:56:34 PM UTC 24 603708832 ps
T2049 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.3262103491 Oct 15 03:56:29 PM UTC 24 Oct 15 03:56:39 PM UTC 24 28648604 ps
T2050 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.2264759927 Oct 15 03:54:07 PM UTC 24 Oct 15 03:56:40 PM UTC 24 4620595263 ps
T2051 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.2773576943 Oct 15 03:55:26 PM UTC 24 Oct 15 03:56:43 PM UTC 24 5251978041 ps
T2052 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.1333195336 Oct 15 03:56:38 PM UTC 24 Oct 15 03:56:54 PM UTC 24 393558794 ps
T2053 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.2116634413 Oct 15 03:51:57 PM UTC 24 Oct 15 03:57:01 PM UTC 24 7642118667 ps
T2054 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.997466132 Oct 15 03:56:23 PM UTC 24 Oct 15 03:57:07 PM UTC 24 442486379 ps
T2055 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.3510306279 Oct 15 03:56:22 PM UTC 24 Oct 15 03:57:18 PM UTC 24 524300410 ps
T2056 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.3035650024 Oct 15 03:57:07 PM UTC 24 Oct 15 03:57:19 PM UTC 24 56076474 ps
T2057 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.213553933 Oct 15 03:56:50 PM UTC 24 Oct 15 03:57:21 PM UTC 24 424138838 ps
T2058 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.51129877 Oct 15 03:57:11 PM UTC 24 Oct 15 03:57:21 PM UTC 24 53689314 ps
T2059 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.3576512302 Oct 15 03:51:32 PM UTC 24 Oct 15 03:57:27 PM UTC 24 24442931838 ps
T2060 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.4170995682 Oct 15 03:55:22 PM UTC 24 Oct 15 03:57:30 PM UTC 24 8353536239 ps
T2061 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.3004182223 Oct 15 03:55:46 PM UTC 24 Oct 15 03:57:31 PM UTC 24 2523247280 ps
T881 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.3544768127 Oct 15 03:54:04 PM UTC 24 Oct 15 03:57:33 PM UTC 24 1386237384 ps
T2062 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.2559514075 Oct 15 03:47:01 PM UTC 24 Oct 15 03:57:47 PM UTC 24 5970817795 ps
T2063 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.783593266 Oct 15 03:50:14 PM UTC 24 Oct 15 03:57:49 PM UTC 24 42429381447 ps
T2064 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.2174412657 Oct 15 03:56:53 PM UTC 24 Oct 15 03:57:50 PM UTC 24 1090224865 ps
T882 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.3835636720 Oct 15 03:54:10 PM UTC 24 Oct 15 03:57:50 PM UTC 24 2486378266 ps
T2065 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.2009991929 Oct 15 03:56:04 PM UTC 24 Oct 15 03:57:53 PM UTC 24 281786259 ps
T2066 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.291905696 Oct 15 03:56:43 PM UTC 24 Oct 15 03:57:55 PM UTC 24 2114052023 ps
T2067 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.3974832101 Oct 15 03:50:56 PM UTC 24 Oct 15 03:57:57 PM UTC 24 2933514870 ps
T2068 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.3774461500 Oct 15 03:56:21 PM UTC 24 Oct 15 03:58:08 PM UTC 24 10133286113 ps
T2069 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.3327928002 Oct 15 03:57:43 PM UTC 24 Oct 15 03:58:10 PM UTC 24 319459809 ps
T2070 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.1352727315 Oct 15 03:57:46 PM UTC 24 Oct 15 03:58:12 PM UTC 24 806747144 ps
T2071 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.1668880483 Oct 15 03:48:33 PM UTC 24 Oct 15 03:58:14 PM UTC 24 36919864305 ps
T2072 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.2158137598 Oct 15 03:56:17 PM UTC 24 Oct 15 03:58:22 PM UTC 24 343054717 ps
T2073 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.2663035336 Oct 15 03:58:16 PM UTC 24 Oct 15 03:58:23 PM UTC 24 40452053 ps
T2074 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.2852263455 Oct 15 03:57:34 PM UTC 24 Oct 15 03:58:25 PM UTC 24 528967960 ps
T2075 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.3491261354 Oct 15 03:58:13 PM UTC 24 Oct 15 03:58:27 PM UTC 24 192815937 ps
T2076 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2233153859 Oct 15 03:54:40 PM UTC 24 Oct 15 03:58:27 PM UTC 24 13806154745 ps
T2077 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.3549765102 Oct 15 03:56:32 PM UTC 24 Oct 15 03:58:31 PM UTC 24 5922257713 ps
T2078 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.536638388 Oct 15 03:57:55 PM UTC 24 Oct 15 03:58:32 PM UTC 24 200799723 ps
T862 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.1602881268 Oct 15 03:57:01 PM UTC 24 Oct 15 03:58:33 PM UTC 24 32870258 ps
T2079 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.203157231 Oct 15 03:57:53 PM UTC 24 Oct 15 03:58:34 PM UTC 24 1044637072 ps
T788 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.4248394558 Oct 15 03:57:46 PM UTC 24 Oct 15 03:58:41 PM UTC 24 1213176370 ps
T2080 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.2295748259 Oct 15 03:57:50 PM UTC 24 Oct 15 03:58:43 PM UTC 24 1594995165 ps
T2081 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.2639823643 Oct 15 03:52:33 PM UTC 24 Oct 15 03:58:45 PM UTC 24 38569976566 ps
T2082 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2374863763 Oct 15 03:44:21 PM UTC 24 Oct 15 03:58:45 PM UTC 24 60894706980 ps
T876 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3067980872 Oct 15 03:48:42 PM UTC 24 Oct 15 03:58:51 PM UTC 24 11360763711 ps
T2083 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.1065937427 Oct 15 03:57:44 PM UTC 24 Oct 15 03:59:07 PM UTC 24 6356537986 ps
T2084 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.1361782611 Oct 15 03:55:10 PM UTC 24 Oct 15 03:59:07 PM UTC 24 3299360010 ps
T2085 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.1072358418 Oct 15 02:48:25 PM UTC 24 Oct 15 03:59:08 PM UTC 24 28761022116 ps
T2086 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.2233719714 Oct 15 03:58:53 PM UTC 24 Oct 15 03:59:13 PM UTC 24 353074730 ps
T2087 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.1728432357 Oct 15 03:58:35 PM UTC 24 Oct 15 03:59:16 PM UTC 24 511081874 ps
T2088 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.2145214845 Oct 15 03:52:06 PM UTC 24 Oct 15 03:59:20 PM UTC 24 7174604173 ps
T2089 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.1537781323 Oct 15 03:58:44 PM UTC 24 Oct 15 03:59:20 PM UTC 24 290285052 ps
T2090 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.3213356911 Oct 15 03:59:08 PM UTC 24 Oct 15 03:59:21 PM UTC 24 186712872 ps
T2091 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.2897531019 Oct 15 03:59:12 PM UTC 24 Oct 15 03:59:23 PM UTC 24 49851182 ps
T2092 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.1894446075 Oct 15 03:58:24 PM UTC 24 Oct 15 03:59:25 PM UTC 24 3910585815 ps
T2093 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.3900180657 Oct 15 03:58:21 PM UTC 24 Oct 15 03:59:25 PM UTC 24 6213536088 ps
T2094 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.1063452093 Oct 15 03:56:57 PM UTC 24 Oct 15 03:59:26 PM UTC 24 3230912892 ps
T2095 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.2631914598 Oct 15 03:57:22 PM UTC 24 Oct 15 03:59:27 PM UTC 24 8964962923 ps
T2096 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.602514545 Oct 15 03:58:51 PM UTC 24 Oct 15 03:59:29 PM UTC 24 319991199 ps
T2097 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.2064585767 Oct 15 03:58:54 PM UTC 24 Oct 15 03:59:31 PM UTC 24 918201316 ps
T2098 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.3478631033 Oct 15 03:58:53 PM UTC 24 Oct 15 03:59:31 PM UTC 24 482691326 ps
T2099 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.3584961795 Oct 15 03:58:57 PM UTC 24 Oct 15 03:59:32 PM UTC 24 7284350 ps
T2100 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.1380639532 Oct 15 03:57:28 PM UTC 24 Oct 15 03:59:37 PM UTC 24 5849159934 ps
T2101 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.2722929576 Oct 15 03:58:53 PM UTC 24 Oct 15 03:59:41 PM UTC 24 485877991 ps
T2102 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.2224661989 Oct 15 03:58:29 PM UTC 24 Oct 15 03:59:48 PM UTC 24 1995173383 ps
T2103 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.1474267139 Oct 15 03:58:14 PM UTC 24 Oct 15 03:59:54 PM UTC 24 433833677 ps
T2104 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.3711479863 Oct 15 03:59:34 PM UTC 24 Oct 15 04:00:05 PM UTC 24 317721229 ps
T2105 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.780406207 Oct 15 03:59:56 PM UTC 24 Oct 15 04:00:06 PM UTC 24 55188486 ps
T2106 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.142135874 Oct 15 03:59:58 PM UTC 24 Oct 15 04:00:08 PM UTC 24 163631765 ps
T2107 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.2940692756 Oct 15 03:59:33 PM UTC 24 Oct 15 04:00:14 PM UTC 24 976984248 ps
T2108 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.175133730 Oct 15 03:59:50 PM UTC 24 Oct 15 04:00:17 PM UTC 24 143771009 ps
T2109 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.3416264423 Oct 15 03:59:08 PM UTC 24 Oct 15 04:00:18 PM UTC 24 6569615427 ps
T2110 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.110046754 Oct 15 03:59:42 PM UTC 24 Oct 15 04:00:20 PM UTC 24 687362850 ps
T2111 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.1856662201 Oct 15 03:59:44 PM UTC 24 Oct 15 04:00:25 PM UTC 24 468920984 ps
T2112 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.2712842158 Oct 15 03:59:53 PM UTC 24 Oct 15 04:00:27 PM UTC 24 92388505 ps
T2113 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.2368590039 Oct 15 03:59:49 PM UTC 24 Oct 15 04:00:30 PM UTC 24 643565417 ps
T2114 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.425493873 Oct 15 04:00:00 PM UTC 24 Oct 15 04:00:37 PM UTC 24 244375220 ps
T2115 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.315928382 Oct 15 03:59:49 PM UTC 24 Oct 15 04:00:42 PM UTC 24 1191867320 ps
T2116 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.3215130895 Oct 15 04:00:43 PM UTC 24 Oct 15 04:00:54 PM UTC 24 32909452 ps
T2117 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.1444514211 Oct 15 03:59:19 PM UTC 24 Oct 15 04:00:56 PM UTC 24 5159836102 ps
T2118 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.2759404117 Oct 15 03:58:37 PM UTC 24 Oct 15 04:00:56 PM UTC 24 9564888888 ps
T2119 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.1890715608 Oct 15 04:00:39 PM UTC 24 Oct 15 04:00:57 PM UTC 24 132277554 ps
T2120 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.124611927 Oct 15 04:00:14 PM UTC 24 Oct 15 04:01:00 PM UTC 24 489223999 ps
T2121 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.1905987109 Oct 15 03:41:28 PM UTC 24 Oct 15 04:01:03 PM UTC 24 72430774778 ps
T2122 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.1159439894 Oct 15 04:00:42 PM UTC 24 Oct 15 04:01:13 PM UTC 24 692572358 ps
T2123 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.3554125870 Oct 15 03:57:44 PM UTC 24 Oct 15 04:01:14 PM UTC 24 14189880836 ps
T2124 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1108819018 Oct 15 03:47:33 PM UTC 24 Oct 15 04:01:16 PM UTC 24 52381827716 ps
T2125 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.3588136839 Oct 15 03:59:44 PM UTC 24 Oct 15 04:01:16 PM UTC 24 2518410716 ps
T2126 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.2176875270 Oct 15 03:56:15 PM UTC 24 Oct 15 04:01:19 PM UTC 24 8786628854 ps
T2127 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.1722843908 Oct 15 04:01:08 PM UTC 24 Oct 15 04:01:20 PM UTC 24 136076516 ps
T2128 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.2564657997 Oct 15 03:59:06 PM UTC 24 Oct 15 04:01:21 PM UTC 24 406351848 ps
T2129 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.577264984 Oct 15 04:00:55 PM UTC 24 Oct 15 04:01:22 PM UTC 24 7415223 ps
T2130 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.153676838 Oct 15 04:00:44 PM UTC 24 Oct 15 04:01:24 PM UTC 24 1033583539 ps
T2131 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.1145097788 Oct 15 03:59:57 PM UTC 24 Oct 15 04:01:27 PM UTC 24 8613802034 ps
T2132 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.167261299 Oct 15 03:58:58 PM UTC 24 Oct 15 04:01:32 PM UTC 24 1724614957 ps
T2133 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.3630489528 Oct 15 04:01:22 PM UTC 24 Oct 15 04:01:32 PM UTC 24 57434558 ps
T2134 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.2576136003 Oct 15 04:00:01 PM UTC 24 Oct 15 04:01:45 PM UTC 24 5230361415 ps
T2135 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.1580241137 Oct 15 03:56:26 PM UTC 24 Oct 15 04:01:48 PM UTC 24 22189578625 ps
T2136 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.2950243585 Oct 15 04:01:45 PM UTC 24 Oct 15 04:01:57 PM UTC 24 37838490 ps
T2137 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.2287229980 Oct 15 04:01:37 PM UTC 24 Oct 15 04:01:59 PM UTC 24 327283264 ps
T2138 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.1893496875 Oct 15 04:01:23 PM UTC 24 Oct 15 04:02:00 PM UTC 24 647697596 ps
T2139 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.170753600 Oct 15 04:00:30 PM UTC 24 Oct 15 04:01:59 PM UTC 24 1154306685 ps
T2140 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.3276006255 Oct 15 02:55:34 PM UTC 24 Oct 15 04:02:06 PM UTC 24 28545340330 ps
T2141 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.1891396377 Oct 15 04:01:47 PM UTC 24 Oct 15 04:02:08 PM UTC 24 151169522 ps
T2142 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.611148499 Oct 15 04:01:27 PM UTC 24 Oct 15 04:02:10 PM UTC 24 462607469 ps
T2143 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.1436546015 Oct 15 04:01:43 PM UTC 24 Oct 15 04:02:11 PM UTC 24 569301511 ps
T2144 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.650309464 Oct 15 04:01:58 PM UTC 24 Oct 15 04:02:13 PM UTC 24 240653691 ps
T2145 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.1138704755 Oct 15 03:55:44 PM UTC 24 Oct 15 04:02:15 PM UTC 24 28267963394 ps
T2146 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.86015499 Oct 15 04:02:11 PM UTC 24 Oct 15 04:02:21 PM UTC 24 50817141 ps
T2147 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.4251064923 Oct 15 04:01:45 PM UTC 24 Oct 15 04:02:25 PM UTC 24 914997537 ps
T2148 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.2593775556 Oct 15 03:58:13 PM UTC 24 Oct 15 04:02:36 PM UTC 24 3520850679 ps
T2149 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.3473340447 Oct 15 04:01:21 PM UTC 24 Oct 15 04:02:36 PM UTC 24 5641186523 ps
T2150 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.160907950 Oct 15 04:01:49 PM UTC 24 Oct 15 04:02:40 PM UTC 24 66674176 ps
T2151 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.3381314761 Oct 15 03:57:58 PM UTC 24 Oct 15 04:02:45 PM UTC 24 7984250955 ps
T2152 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.3190623779 Oct 15 04:02:26 PM UTC 24 Oct 15 04:02:53 PM UTC 24 191602358 ps
T2153 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.3011250565 Oct 15 04:02:40 PM UTC 24 Oct 15 04:02:55 PM UTC 24 114047585 ps
T2154 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.2763222245 Oct 15 03:54:54 PM UTC 24 Oct 15 04:03:05 PM UTC 24 14849665245 ps
T2155 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.44654629 Oct 15 04:02:22 PM UTC 24 Oct 15 04:03:12 PM UTC 24 3590186075 ps
T2156 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.2412040629 Oct 15 03:54:37 PM UTC 24 Oct 15 04:03:13 PM UTC 24 37606527194 ps
T2157 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.3284121878 Oct 15 04:02:36 PM UTC 24 Oct 15 04:03:22 PM UTC 24 509906866 ps
T2158 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.4156402566 Oct 15 04:03:10 PM UTC 24 Oct 15 04:03:22 PM UTC 24 148923953 ps
T2159 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3526571590 Oct 15 04:02:47 PM UTC 24 Oct 15 04:03:28 PM UTC 24 774176840 ps
T2160 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.1065394949 Oct 15 04:02:40 PM UTC 24 Oct 15 04:03:29 PM UTC 24 1113774455 ps
T2161 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.1491512584 Oct 15 04:02:26 PM UTC 24 Oct 15 04:03:31 PM UTC 24 1347780885 ps
T2162 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.1907901231 Oct 15 04:03:22 PM UTC 24 Oct 15 04:03:32 PM UTC 24 42691402 ps
T613 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.610477052 Oct 15 04:01:55 PM UTC 24 Oct 15 04:03:35 PM UTC 24 2588677483 ps
T2163 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.987119446 Oct 15 03:55:49 PM UTC 24 Oct 15 04:03:35 PM UTC 24 30417301406 ps
T2164 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.3467472749 Oct 15 04:02:36 PM UTC 24 Oct 15 04:03:47 PM UTC 24 2537875479 ps
T2165 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.1620053976 Oct 15 03:45:23 PM UTC 24 Oct 15 04:03:49 PM UTC 24 71915811046 ps
T2166 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.1070677292 Oct 15 04:01:22 PM UTC 24 Oct 15 04:03:50 PM UTC 24 9191938767 ps
T2167 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.1841728522 Oct 15 03:55:43 PM UTC 24 Oct 15 04:03:53 PM UTC 24 48065614521 ps
T2168 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.4257211033 Oct 15 04:00:30 PM UTC 24 Oct 15 04:03:53 PM UTC 24 14390223920 ps
T2169 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.878349511 Oct 15 04:02:15 PM UTC 24 Oct 15 04:03:55 PM UTC 24 8426506181 ps
T2170 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.1560165530 Oct 15 03:54:35 PM UTC 24 Oct 15 04:03:59 PM UTC 24 51097571984 ps
T2171 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.354370477 Oct 15 03:50:29 PM UTC 24 Oct 15 04:04:00 PM UTC 24 55753797652 ps
T2172 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.3906767576 Oct 15 04:03:54 PM UTC 24 Oct 15 04:04:04 PM UTC 24 71592007 ps
T850 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.104344557 Oct 15 03:49:25 PM UTC 24 Oct 15 04:04:05 PM UTC 24 57859656685 ps
T2173 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.2634264528 Oct 15 04:03:38 PM UTC 24 Oct 15 04:04:11 PM UTC 24 235492288 ps
T489 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1334091840 Oct 15 03:46:22 PM UTC 24 Oct 15 04:04:17 PM UTC 24 74526198379 ps
T2174 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.258619549 Oct 15 04:00:56 PM UTC 24 Oct 15 04:04:19 PM UTC 24 5828472684 ps
T2175 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2529772210 Oct 15 03:57:07 PM UTC 24 Oct 15 04:04:19 PM UTC 24 3141045287 ps
T2176 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.2707979867 Oct 15 04:04:16 PM UTC 24 Oct 15 04:04:24 PM UTC 24 50546573 ps
T2177 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.3166972580 Oct 15 04:03:54 PM UTC 24 Oct 15 04:04:25 PM UTC 24 946793595 ps
T2178 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.1587397536 Oct 15 04:04:16 PM UTC 24 Oct 15 04:04:26 PM UTC 24 45808420 ps
T2179 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.1712302443 Oct 15 04:03:58 PM UTC 24 Oct 15 04:04:29 PM UTC 24 198928577 ps
T2180 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.4221043169 Oct 15 04:03:58 PM UTC 24 Oct 15 04:04:32 PM UTC 24 260159126 ps
T2181 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.3642086240 Oct 15 03:59:48 PM UTC 24 Oct 15 04:04:35 PM UTC 24 2265774199 ps
T2182 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.472057301 Oct 15 04:03:39 PM UTC 24 Oct 15 04:04:37 PM UTC 24 505967852 ps
T2183 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.757765543 Oct 15 04:04:28 PM UTC 24 Oct 15 04:04:38 PM UTC 24 38476064 ps
T490 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.2944837116 Oct 15 03:51:51 PM UTC 24 Oct 15 04:04:44 PM UTC 24 20722303750 ps
T2184 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.2876602061 Oct 15 04:03:21 PM UTC 24 Oct 15 04:04:50 PM UTC 24 7920096032 ps
T2185 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.3435577736 Oct 15 03:51:41 PM UTC 24 Oct 15 04:04:54 PM UTC 24 50031930783 ps
T611 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.2427263513 Oct 15 03:57:02 PM UTC 24 Oct 15 04:05:03 PM UTC 24 13131884673 ps
T2186 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.1779560222 Oct 15 04:04:51 PM UTC 24 Oct 15 04:05:05 PM UTC 24 56446585 ps
T2187 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.3212502604 Oct 15 04:03:32 PM UTC 24 Oct 15 04:05:08 PM UTC 24 6760155916 ps
T2188 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.3961890375 Oct 15 04:03:50 PM UTC 24 Oct 15 04:05:10 PM UTC 24 773164922 ps
T2189 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.2462902614 Oct 15 04:05:06 PM UTC 24 Oct 15 04:05:16 PM UTC 24 159962046 ps
T2190 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.2460139139 Oct 15 04:01:50 PM UTC 24 Oct 15 04:05:20 PM UTC 24 5660237305 ps
T2191 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.3316806163 Oct 15 04:05:18 PM UTC 24 Oct 15 04:05:28 PM UTC 24 54115376 ps
T2192 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.2472695230 Oct 15 03:57:46 PM UTC 24 Oct 15 04:05:30 PM UTC 24 32124896516 ps
T2193 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.4121177342 Oct 15 04:02:49 PM UTC 24 Oct 15 04:05:32 PM UTC 24 3605774293 ps
T2194 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.4097818708 Oct 15 04:04:50 PM UTC 24 Oct 15 04:05:37 PM UTC 24 899631602 ps
T2195 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.1589000900 Oct 15 03:59:37 PM UTC 24 Oct 15 04:05:40 PM UTC 24 22947688554 ps
T2196 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.1234806262 Oct 15 04:04:56 PM UTC 24 Oct 15 04:05:40 PM UTC 24 1076066412 ps
T2197 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.3901026026 Oct 15 04:04:51 PM UTC 24 Oct 15 04:05:40 PM UTC 24 1502118786 ps
T2198 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.3578926578 Oct 15 04:04:27 PM UTC 24 Oct 15 04:05:44 PM UTC 24 2023381583 ps
T851 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.1646381059 Oct 15 03:52:40 PM UTC 24 Oct 15 04:05:49 PM UTC 24 53910862365 ps
T2199 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.3142113754 Oct 15 04:04:26 PM UTC 24 Oct 15 04:05:50 PM UTC 24 5826941006 ps
T2200 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.1185945887 Oct 15 04:04:43 PM UTC 24 Oct 15 04:05:56 PM UTC 24 1912884492 ps
T2201 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.710843742 Oct 15 03:56:29 PM UTC 24 Oct 15 04:06:06 PM UTC 24 32451678632 ps
T2202 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.175354206 Oct 15 04:00:21 PM UTC 24 Oct 15 04:06:09 PM UTC 24 37521469292 ps
T2203 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.3905898564 Oct 15 04:04:24 PM UTC 24 Oct 15 04:06:11 PM UTC 24 8398473569 ps
T2204 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.3882534582 Oct 15 04:01:03 PM UTC 24 Oct 15 04:06:13 PM UTC 24 6498734908 ps
T2205 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.2759701427 Oct 15 04:05:36 PM UTC 24 Oct 15 04:06:14 PM UTC 24 409276430 ps
T2206 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.386596023 Oct 15 03:58:38 PM UTC 24 Oct 15 04:06:14 PM UTC 24 45267398077 ps
T2207 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.2644458673 Oct 15 04:05:04 PM UTC 24 Oct 15 04:06:17 PM UTC 24 200769016 ps
T2208 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3262761917 Oct 15 04:01:43 PM UTC 24 Oct 15 04:06:21 PM UTC 24 17341212164 ps
T2209 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.518485698 Oct 15 04:04:42 PM UTC 24 Oct 15 04:06:22 PM UTC 24 6325965099 ps
T2210 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.2649262457 Oct 15 04:06:14 PM UTC 24 Oct 15 04:06:23 PM UTC 24 52330957 ps
T2211 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.127997879 Oct 15 04:06:23 PM UTC 24 Oct 15 04:06:33 PM UTC 24 47931771 ps
T2212 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.2828817676 Oct 15 04:05:55 PM UTC 24 Oct 15 04:06:34 PM UTC 24 909445459 ps
T2213 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.373621456 Oct 15 04:03:04 PM UTC 24 Oct 15 04:06:37 PM UTC 24 5473710397 ps
T2214 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.3326583875 Oct 15 04:05:30 PM UTC 24 Oct 15 04:06:41 PM UTC 24 4693921351 ps
T2215 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.794927129 Oct 15 04:04:15 PM UTC 24 Oct 15 04:06:45 PM UTC 24 4873721364 ps
T2216 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.3103497705 Oct 15 04:05:59 PM UTC 24 Oct 15 04:06:45 PM UTC 24 451251206 ps
T2217 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.1529069037 Oct 15 04:05:32 PM UTC 24 Oct 15 04:06:46 PM UTC 24 1789984310 ps
T2218 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.304154042 Oct 15 04:06:00 PM UTC 24 Oct 15 04:06:51 PM UTC 24 1043281544 ps
T2219 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.2628156090 Oct 15 04:06:01 PM UTC 24 Oct 15 04:06:54 PM UTC 24 1117437764 ps
T2220 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.4055769514 Oct 15 04:04:12 PM UTC 24 Oct 15 04:06:55 PM UTC 24 4169115810 ps
T2221 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.2547690589 Oct 15 03:58:13 PM UTC 24 Oct 15 04:07:02 PM UTC 24 9304292060 ps
T2222 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.3427754244 Oct 15 04:06:36 PM UTC 24 Oct 15 04:07:04 PM UTC 24 280522900 ps
T2223 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.1858430081 Oct 15 04:05:21 PM UTC 24 Oct 15 04:07:04 PM UTC 24 9102692880 ps
T2224 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.474617427 Oct 15 04:05:46 PM UTC 24 Oct 15 04:07:08 PM UTC 24 1762175500 ps
T2225 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.1462781111 Oct 15 04:06:39 PM UTC 24 Oct 15 04:07:08 PM UTC 24 318335670 ps
T2226 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.1095441790 Oct 15 04:07:01 PM UTC 24 Oct 15 04:07:13 PM UTC 24 175372543 ps
T2227 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.2452523068 Oct 15 03:59:34 PM UTC 24 Oct 15 04:07:15 PM UTC 24 47474734362 ps
T2228 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.64111298 Oct 15 04:00:52 PM UTC 24 Oct 15 04:07:16 PM UTC 24 10763118628 ps
T2229 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.1155288287 Oct 15 04:07:11 PM UTC 24 Oct 15 04:07:21 PM UTC 24 42929066 ps
T2230 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.207321273 Oct 15 04:07:16 PM UTC 24 Oct 15 04:07:24 PM UTC 24 47672181 ps
T2231 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.3363495751 Oct 15 04:07:00 PM UTC 24 Oct 15 04:07:35 PM UTC 24 272705642 ps
T2232 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.2315239480 Oct 15 04:04:56 PM UTC 24 Oct 15 04:07:42 PM UTC 24 4015835453 ps
T2233 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.450567638 Oct 15 04:06:49 PM UTC 24 Oct 15 04:07:43 PM UTC 24 1668644989 ps
T820 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.3995723492 Oct 15 03:53:51 PM UTC 24 Oct 15 04:07:53 PM UTC 24 40497012354 ps
T2234 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.3014969071 Oct 15 04:04:17 PM UTC 24 Oct 15 04:07:54 PM UTC 24 2109256881 ps
T2235 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.4234857365 Oct 15 04:06:16 PM UTC 24 Oct 15 04:07:55 PM UTC 24 837058064 ps
T2236 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.3444249262 Oct 15 04:06:30 PM UTC 24 Oct 15 04:07:56 PM UTC 24 7517898040 ps
T2237 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.865273466 Oct 15 04:06:31 PM UTC 24 Oct 15 04:08:01 PM UTC 24 4853800626 ps
T2238 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.957760653 Oct 15 04:07:51 PM UTC 24 Oct 15 04:08:02 PM UTC 24 150294245 ps
T2239 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.3475778755 Oct 15 04:07:41 PM UTC 24 Oct 15 04:08:03 PM UTC 24 500520657 ps
T2240 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.1835038135 Oct 15 04:06:50 PM UTC 24 Oct 15 04:08:07 PM UTC 24 2432535812 ps
T2241 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.1588322795 Oct 15 04:00:34 PM UTC 24 Oct 15 04:08:10 PM UTC 24 33591949857 ps
T2242 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.671961757 Oct 15 04:07:43 PM UTC 24 Oct 15 04:08:12 PM UTC 24 569676615 ps
T2243 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.2246742879 Oct 15 04:07:47 PM UTC 24 Oct 15 04:08:19 PM UTC 24 502259507 ps
T2244 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.3588949368 Oct 15 04:07:26 PM UTC 24 Oct 15 04:08:23 PM UTC 24 543558547 ps
T2245 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.1203504145 Oct 15 04:04:13 PM UTC 24 Oct 15 04:08:27 PM UTC 24 2285124579 ps
T2246 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.2315336906 Oct 15 04:08:18 PM UTC 24 Oct 15 04:08:27 PM UTC 24 205622324 ps
T2247 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.1708159009 Oct 15 04:08:21 PM UTC 24 Oct 15 04:08:29 PM UTC 24 43089208 ps
T2248 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.338488458 Oct 15 04:02:26 PM UTC 24 Oct 15 04:08:36 PM UTC 24 31741928446 ps
T2249 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.1299311766 Oct 15 04:08:29 PM UTC 24 Oct 15 04:08:40 PM UTC 24 46251257 ps
T2250 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.3035745463 Oct 15 04:05:04 PM UTC 24 Oct 15 04:08:44 PM UTC 24 3050895426 ps
T2251 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.1321052464 Oct 15 04:06:44 PM UTC 24 Oct 15 04:08:49 PM UTC 24 2434156586 ps
T2252 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.1207226964 Oct 15 04:07:20 PM UTC 24 Oct 15 04:08:50 PM UTC 24 4257481189 ps
T2253 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.1471701963 Oct 15 04:06:07 PM UTC 24 Oct 15 04:08:50 PM UTC 24 4754402026 ps
T863 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.2476582374 Oct 15 04:08:16 PM UTC 24 Oct 15 04:08:53 PM UTC 24 195733707 ps
T2254 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.91698613 Oct 15 04:07:19 PM UTC 24 Oct 15 04:08:58 PM UTC 24 9023842434 ps
T2255 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.3818949783 Oct 15 04:07:27 PM UTC 24 Oct 15 04:09:06 PM UTC 24 2589669636 ps
T2256 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.2095984121 Oct 15 04:08:26 PM UTC 24 Oct 15 04:09:13 PM UTC 24 1309473762 ps
T2257 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.3566293393 Oct 15 04:08:09 PM UTC 24 Oct 15 04:09:19 PM UTC 24 128331063 ps
T2258 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.730417428 Oct 15 04:08:50 PM UTC 24 Oct 15 04:09:21 PM UTC 24 975456609 ps
T2259 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.376395680 Oct 15 04:09:15 PM UTC 24 Oct 15 04:09:24 PM UTC 24 49115569 ps
T2260 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.1393027725 Oct 15 04:09:15 PM UTC 24 Oct 15 04:09:25 PM UTC 24 51214076 ps
T2261 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.320490724 Oct 15 04:08:39 PM UTC 24 Oct 15 04:09:31 PM UTC 24 737494749 ps
T2262 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.3576706874 Oct 15 04:05:44 PM UTC 24 Oct 15 04:09:34 PM UTC 24 14279784993 ps
T2263 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.3452112393 Oct 15 03:59:51 PM UTC 24 Oct 15 04:09:35 PM UTC 24 15172999003 ps
T2264 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.1376742895 Oct 15 04:06:42 PM UTC 24 Oct 15 04:09:37 PM UTC 24 9342442835 ps
T2265 /workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.2968909728 Oct 15 04:07:03 PM UTC 24 Oct 15 04:09:42 PM UTC 24 4415403574 ps
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