| T2024 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.3955944695 |
|
|
Feb 09 04:24:10 PM UTC 25 |
Feb 09 04:24:44 PM UTC 25 |
290691991 ps |
| T2025 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.2603737807 |
|
|
Feb 09 04:23:45 PM UTC 25 |
Feb 09 04:24:47 PM UTC 25 |
4007797004 ps |
| T2026 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.742234915 |
|
|
Feb 09 04:24:38 PM UTC 25 |
Feb 09 04:24:48 PM UTC 25 |
212165807 ps |
| T2027 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.677020391 |
|
|
Feb 09 04:18:00 PM UTC 25 |
Feb 09 04:24:48 PM UTC 25 |
1008816836 ps |
| T2028 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.1977977161 |
|
|
Feb 09 04:24:15 PM UTC 25 |
Feb 09 04:24:54 PM UTC 25 |
272307264 ps |
| T2029 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.1860967608 |
|
|
Feb 09 04:24:45 PM UTC 25 |
Feb 09 04:24:57 PM UTC 25 |
58449592 ps |
| T2030 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.1661767493 |
|
|
Feb 09 04:24:16 PM UTC 25 |
Feb 09 04:24:59 PM UTC 25 |
1077334630 ps |
| T2031 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.3386128678 |
|
|
Feb 09 04:23:44 PM UTC 25 |
Feb 09 04:25:00 PM UTC 25 |
6732423829 ps |
| T2032 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.784620471 |
|
|
Feb 09 04:14:52 PM UTC 25 |
Feb 09 04:25:08 PM UTC 25 |
3824150980 ps |
| T2033 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.4094161774 |
|
|
Feb 09 04:24:07 PM UTC 25 |
Feb 09 04:25:17 PM UTC 25 |
1531096336 ps |
| T2034 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.2898270956 |
|
|
Feb 09 04:07:01 PM UTC 25 |
Feb 09 04:25:45 PM UTC 25 |
106474046710 ps |
| T2035 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.98231224 |
|
|
Feb 09 04:25:10 PM UTC 25 |
Feb 09 04:25:46 PM UTC 25 |
481951189 ps |
| T2036 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.3537751305 |
|
|
Feb 09 04:14:02 PM UTC 25 |
Feb 09 04:25:49 PM UTC 25 |
4822539979 ps |
| T2037 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.1347804231 |
|
|
Feb 09 04:24:57 PM UTC 25 |
Feb 09 04:25:53 PM UTC 25 |
472925006 ps |
| T2038 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.3450880000 |
|
|
Feb 09 04:25:05 PM UTC 25 |
Feb 09 04:25:53 PM UTC 25 |
521866006 ps |
| T2039 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.919011679 |
|
|
Feb 09 04:25:20 PM UTC 25 |
Feb 09 04:26:02 PM UTC 25 |
291668670 ps |
| T2040 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.2773271775 |
|
|
Feb 09 04:25:26 PM UTC 25 |
Feb 09 04:26:08 PM UTC 25 |
318303417 ps |
| T2041 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.2505376883 |
|
|
Feb 09 04:24:25 PM UTC 25 |
Feb 09 04:26:09 PM UTC 25 |
2709109466 ps |
| T2042 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.2012580060 |
|
|
Feb 09 04:25:25 PM UTC 25 |
Feb 09 04:26:09 PM UTC 25 |
1073284585 ps |
| T2043 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.377753684 |
|
|
Feb 09 04:25:18 PM UTC 25 |
Feb 09 04:26:14 PM UTC 25 |
497317509 ps |
| T2044 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.2654708081 |
|
|
Feb 09 04:25:46 PM UTC 25 |
Feb 09 04:26:14 PM UTC 25 |
105351711 ps |
| T2045 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.804598885 |
|
|
Feb 09 04:26:14 PM UTC 25 |
Feb 09 04:26:24 PM UTC 25 |
210700023 ps |
| T2046 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.4254906431 |
|
|
Feb 09 04:24:59 PM UTC 25 |
Feb 09 04:26:25 PM UTC 25 |
5302574101 ps |
| T2047 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.4164320281 |
|
|
Feb 09 04:26:19 PM UTC 25 |
Feb 09 04:26:26 PM UTC 25 |
53312200 ps |
| T2048 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.1344210195 |
|
|
Feb 09 04:24:48 PM UTC 25 |
Feb 09 04:26:37 PM UTC 25 |
8156714632 ps |
| T2049 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.2639341663 |
|
|
Feb 09 04:25:37 PM UTC 25 |
Feb 09 04:26:52 PM UTC 25 |
928520077 ps |
| T2050 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.4246557304 |
|
|
Feb 09 04:14:32 PM UTC 25 |
Feb 09 04:26:54 PM UTC 25 |
69355144175 ps |
| T2051 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2335061720 |
|
|
Feb 09 04:21:58 PM UTC 25 |
Feb 09 04:26:55 PM UTC 25 |
1659738755 ps |
| T2052 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.3336163014 |
|
|
Feb 09 04:23:27 PM UTC 25 |
Feb 09 04:26:59 PM UTC 25 |
2913981070 ps |
| T2053 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.968876135 |
|
|
Feb 09 04:14:03 PM UTC 25 |
Feb 09 04:26:59 PM UTC 25 |
6885787745 ps |
| T2054 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.259730417 |
|
|
Feb 09 04:23:18 PM UTC 25 |
Feb 09 04:27:04 PM UTC 25 |
4749089393 ps |
| T2055 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.847008679 |
|
|
Feb 09 04:21:05 PM UTC 25 |
Feb 09 04:27:06 PM UTC 25 |
12042442699 ps |
| T2056 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.814674084 |
|
|
Feb 09 04:26:54 PM UTC 25 |
Feb 09 04:27:07 PM UTC 25 |
185516181 ps |
| T2057 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.2776428221 |
|
|
Feb 09 04:08:51 PM UTC 25 |
Feb 09 04:27:08 PM UTC 25 |
66708962239 ps |
| T2058 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.922657106 |
|
|
Feb 09 04:26:35 PM UTC 25 |
Feb 09 04:27:13 PM UTC 25 |
290418640 ps |
| T2059 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.3663482641 |
|
|
Feb 09 04:26:32 PM UTC 25 |
Feb 09 04:27:14 PM UTC 25 |
402988722 ps |
| T2060 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.1068998797 |
|
|
Feb 09 04:18:47 PM UTC 25 |
Feb 09 04:27:17 PM UTC 25 |
31142967450 ps |
| T2061 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.2057109764 |
|
|
Feb 09 04:26:53 PM UTC 25 |
Feb 09 04:27:18 PM UTC 25 |
326858518 ps |
| T2062 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.3290572014 |
|
|
Feb 09 04:11:30 PM UTC 25 |
Feb 09 04:27:26 PM UTC 25 |
85967905546 ps |
| T2063 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.2606545829 |
|
|
Feb 09 04:25:10 PM UTC 25 |
Feb 09 04:27:30 PM UTC 25 |
7910755834 ps |
| T2064 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.3795589266 |
|
|
Feb 09 04:27:21 PM UTC 25 |
Feb 09 04:27:30 PM UTC 25 |
22221103 ps |
| T2065 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.1920173916 |
|
|
Feb 09 04:26:13 PM UTC 25 |
Feb 09 04:27:38 PM UTC 25 |
208368641 ps |
| T2066 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.3941211676 |
|
|
Feb 09 04:27:30 PM UTC 25 |
Feb 09 04:27:43 PM UTC 25 |
156502474 ps |
| T2067 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.3555204345 |
|
|
Feb 09 04:27:32 PM UTC 25 |
Feb 09 04:27:43 PM UTC 25 |
49685228 ps |
| T2068 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1920578195 |
|
|
Feb 09 04:26:27 PM UTC 25 |
Feb 09 04:27:49 PM UTC 25 |
3419411519 ps |
| T2069 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.2519852609 |
|
|
Feb 09 04:02:09 PM UTC 25 |
Feb 09 04:27:58 PM UTC 25 |
106984777911 ps |
| T2070 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.3263275688 |
|
|
Feb 09 04:26:36 PM UTC 25 |
Feb 09 04:28:04 PM UTC 25 |
9112574600 ps |
| T2071 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.1189580486 |
|
|
Feb 09 04:26:18 PM UTC 25 |
Feb 09 04:28:04 PM UTC 25 |
8651952842 ps |
| T2072 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.2607526855 |
|
|
Feb 09 04:27:38 PM UTC 25 |
Feb 09 04:28:09 PM UTC 25 |
240661874 ps |
| T2073 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.3297297129 |
|
|
Feb 09 04:27:06 PM UTC 25 |
Feb 09 04:28:14 PM UTC 25 |
1174122511 ps |
| T2074 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.2012899768 |
|
|
Feb 09 04:28:04 PM UTC 25 |
Feb 09 04:28:16 PM UTC 25 |
135624176 ps |
| T2075 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.3752854096 |
|
|
Feb 09 04:26:40 PM UTC 25 |
Feb 09 04:28:16 PM UTC 25 |
2519003883 ps |
| T2076 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.4046838152 |
|
|
Feb 09 04:27:54 PM UTC 25 |
Feb 09 04:28:16 PM UTC 25 |
772314675 ps |
| T2077 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.1446955986 |
|
|
Feb 09 04:21:34 PM UTC 25 |
Feb 09 04:28:18 PM UTC 25 |
34446369064 ps |
| T2078 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.3375569873 |
|
|
Feb 09 04:26:12 PM UTC 25 |
Feb 09 04:28:20 PM UTC 25 |
1444883852 ps |
| T2079 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.4131687103 |
|
|
Feb 09 04:27:23 PM UTC 25 |
Feb 09 04:28:25 PM UTC 25 |
737248049 ps |
| T2080 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.2744167551 |
|
|
Feb 09 04:21:02 PM UTC 25 |
Feb 09 04:28:28 PM UTC 25 |
3978166480 ps |
| T2081 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.3132406441 |
|
|
Feb 09 04:27:35 PM UTC 25 |
Feb 09 04:28:37 PM UTC 25 |
4023823277 ps |
| T2082 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.265273353 |
|
|
Feb 09 04:28:12 PM UTC 25 |
Feb 09 04:28:38 PM UTC 25 |
433426725 ps |
| T2083 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.1485461099 |
|
|
Feb 09 04:13:48 PM UTC 25 |
Feb 09 04:28:38 PM UTC 25 |
55800436868 ps |
| T2084 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.3770601576 |
|
|
Feb 09 04:27:34 PM UTC 25 |
Feb 09 04:28:47 PM UTC 25 |
7314171838 ps |
| T2085 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.2518447861 |
|
|
Feb 09 04:27:51 PM UTC 25 |
Feb 09 04:28:48 PM UTC 25 |
1044609185 ps |
| T2086 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.895223853 |
|
|
Feb 09 04:28:40 PM UTC 25 |
Feb 09 04:28:51 PM UTC 25 |
38491865 ps |
| T2087 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.981249301 |
|
|
Feb 09 04:28:38 PM UTC 25 |
Feb 09 04:28:54 PM UTC 25 |
242129508 ps |
| T2088 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.2062659543 |
|
|
Feb 09 04:18:27 PM UTC 25 |
Feb 09 04:29:02 PM UTC 25 |
54554426583 ps |
| T2089 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.4083461856 |
|
|
Feb 09 04:27:36 PM UTC 25 |
Feb 09 04:29:10 PM UTC 25 |
2212629828 ps |
| T2090 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.2037744353 |
|
|
Feb 09 04:24:16 PM UTC 25 |
Feb 09 04:29:11 PM UTC 25 |
7381240783 ps |
| T2091 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.4252884297 |
|
|
Feb 09 04:08:48 PM UTC 25 |
Feb 09 04:29:12 PM UTC 25 |
100538783023 ps |
| T2092 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.3354536504 |
|
|
Feb 09 04:29:06 PM UTC 25 |
Feb 09 04:29:17 PM UTC 25 |
41188426 ps |
| T2093 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.363475860 |
|
|
Feb 09 04:28:10 PM UTC 25 |
Feb 09 04:29:20 PM UTC 25 |
1252734043 ps |
| T2094 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.1746415403 |
|
|
Feb 09 04:28:43 PM UTC 25 |
Feb 09 04:29:25 PM UTC 25 |
460786394 ps |
| T2095 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.653466962 |
|
|
Feb 09 04:28:44 PM UTC 25 |
Feb 09 04:29:35 PM UTC 25 |
1283000046 ps |
| T2096 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.982191713 |
|
|
Feb 09 04:29:05 PM UTC 25 |
Feb 09 04:29:39 PM UTC 25 |
351904896 ps |
| T2097 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.1103169565 |
|
|
Feb 09 04:29:37 PM UTC 25 |
Feb 09 04:29:46 PM UTC 25 |
45608601 ps |
| T2098 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.1191141672 |
|
|
Feb 09 04:29:14 PM UTC 25 |
Feb 09 04:29:48 PM UTC 25 |
914831254 ps |
| T2099 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.4255469816 |
|
|
Feb 09 04:29:39 PM UTC 25 |
Feb 09 04:29:50 PM UTC 25 |
51708506 ps |
| T2100 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.3792157941 |
|
|
Feb 09 04:10:07 PM UTC 25 |
Feb 09 04:29:59 PM UTC 25 |
82270453350 ps |
| T2101 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.1990786262 |
|
|
Feb 09 04:19:52 PM UTC 25 |
Feb 09 04:30:05 PM UTC 25 |
39497056525 ps |
| T2102 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.4137527552 |
|
|
Feb 09 04:29:13 PM UTC 25 |
Feb 09 04:30:09 PM UTC 25 |
1120590640 ps |
| T2103 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.4155849814 |
|
|
Feb 09 04:28:40 PM UTC 25 |
Feb 09 04:30:12 PM UTC 25 |
7207251210 ps |
| T2104 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.1467178324 |
|
|
Feb 09 04:30:03 PM UTC 25 |
Feb 09 04:30:13 PM UTC 25 |
29381321 ps |
| T2105 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.3247565593 |
|
|
Feb 09 04:24:01 PM UTC 25 |
Feb 09 04:30:21 PM UTC 25 |
25373116404 ps |
| T2106 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.170595839 |
|
|
Feb 09 04:29:54 PM UTC 25 |
Feb 09 04:30:24 PM UTC 25 |
762097387 ps |
| T2107 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.1816626867 |
|
|
Feb 09 04:28:55 PM UTC 25 |
Feb 09 04:30:27 PM UTC 25 |
1765724809 ps |
| T2108 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.1266475197 |
|
|
Feb 09 04:28:41 PM UTC 25 |
Feb 09 04:30:30 PM UTC 25 |
5278425707 ps |
| T2109 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.3805115026 |
|
|
Feb 09 02:50:52 PM UTC 25 |
Feb 09 04:30:38 PM UTC 25 |
59186305904 ps |
| T2110 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.2430507555 |
|
|
Feb 09 04:30:31 PM UTC 25 |
Feb 09 04:30:47 PM UTC 25 |
246973215 ps |
| T2111 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.358860 |
|
|
Feb 09 04:28:32 PM UTC 25 |
Feb 09 04:30:53 PM UTC 25 |
1542745033 ps |
| T2112 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.662428389 |
|
|
Feb 09 04:30:14 PM UTC 25 |
Feb 09 04:30:54 PM UTC 25 |
295295582 ps |
| T2113 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.1300852872 |
|
|
Feb 09 04:30:40 PM UTC 25 |
Feb 09 04:30:55 PM UTC 25 |
76907101 ps |
| T2114 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.1920510875 |
|
|
Feb 09 04:29:45 PM UTC 25 |
Feb 09 04:31:00 PM UTC 25 |
3137746433 ps |
| T2115 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.1927367956 |
|
|
Feb 09 04:28:24 PM UTC 25 |
Feb 09 04:31:00 PM UTC 25 |
326948101 ps |
| T2116 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.1975890397 |
|
|
Feb 09 04:30:56 PM UTC 25 |
Feb 09 04:31:06 PM UTC 25 |
40940848 ps |
| T2117 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.3941236859 |
|
|
Feb 09 04:27:26 PM UTC 25 |
Feb 09 04:31:14 PM UTC 25 |
3401111627 ps |
| T2118 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.1283836755 |
|
|
Feb 09 04:20:38 PM UTC 25 |
Feb 09 04:31:14 PM UTC 25 |
57414716185 ps |
| T2119 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.953694546 |
|
|
Feb 09 04:31:06 PM UTC 25 |
Feb 09 04:31:16 PM UTC 25 |
41797688 ps |
| T2120 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.827008897 |
|
|
Feb 09 04:28:17 PM UTC 25 |
Feb 09 04:31:31 PM UTC 25 |
2666501783 ps |
| T2121 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.286848558 |
|
|
Feb 09 04:29:16 PM UTC 25 |
Feb 09 04:31:35 PM UTC 25 |
1741493582 ps |
| T2122 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.89441247 |
|
|
Feb 09 04:29:42 PM UTC 25 |
Feb 09 04:31:36 PM UTC 25 |
8336421027 ps |
| T2123 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.795267225 |
|
|
Feb 09 04:31:22 PM UTC 25 |
Feb 09 04:31:37 PM UTC 25 |
90084159 ps |
| T2124 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.3888391580 |
|
|
Feb 09 04:30:34 PM UTC 25 |
Feb 09 04:31:41 PM UTC 25 |
1618397160 ps |
| T2125 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.3859740499 |
|
|
Feb 09 04:30:45 PM UTC 25 |
Feb 09 04:31:48 PM UTC 25 |
128414660 ps |
| T2126 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.2341884444 |
|
|
Feb 09 04:28:26 PM UTC 25 |
Feb 09 04:31:52 PM UTC 25 |
1783246610 ps |
| T2127 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.267440384 |
|
|
Feb 09 04:29:28 PM UTC 25 |
Feb 09 04:31:57 PM UTC 25 |
1797835852 ps |
| T2128 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.2422605757 |
|
|
Feb 09 04:30:55 PM UTC 25 |
Feb 09 04:32:04 PM UTC 25 |
300301791 ps |
| T2129 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.603934248 |
|
|
Feb 09 04:27:41 PM UTC 25 |
Feb 09 04:32:05 PM UTC 25 |
15022948602 ps |
| T2130 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.620779164 |
|
|
Feb 09 04:31:34 PM UTC 25 |
Feb 09 04:32:07 PM UTC 25 |
405127131 ps |
| T2131 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.2330898550 |
|
|
Feb 09 04:30:25 PM UTC 25 |
Feb 09 04:32:11 PM UTC 25 |
2648415254 ps |
| T2132 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.573152901 |
|
|
Feb 09 04:31:19 PM UTC 25 |
Feb 09 04:32:12 PM UTC 25 |
474619462 ps |
| T2133 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.3307416234 |
|
|
Feb 09 04:31:45 PM UTC 25 |
Feb 09 04:32:15 PM UTC 25 |
349488833 ps |
| T2134 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.2780207824 |
|
|
Feb 09 04:31:57 PM UTC 25 |
Feb 09 04:32:16 PM UTC 25 |
96113113 ps |
| T2135 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.781330112 |
|
|
Feb 09 04:31:14 PM UTC 25 |
Feb 09 04:32:32 PM UTC 25 |
7497692594 ps |
| T2136 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.2831232622 |
|
|
Feb 09 04:32:24 PM UTC 25 |
Feb 09 04:32:35 PM UTC 25 |
53506146 ps |
| T2137 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.927867150 |
|
|
Feb 09 04:32:20 PM UTC 25 |
Feb 09 04:32:35 PM UTC 25 |
222971615 ps |
| T2138 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.2644230919 |
|
|
Feb 09 04:31:41 PM UTC 25 |
Feb 09 04:32:35 PM UTC 25 |
548111485 ps |
| T2139 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.2530853372 |
|
|
Feb 09 04:24:30 PM UTC 25 |
Feb 09 04:32:38 PM UTC 25 |
8238875400 ps |
| T2140 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.1208532265 |
|
|
Feb 09 04:32:04 PM UTC 25 |
Feb 09 04:32:45 PM UTC 25 |
693575720 ps |
| T886 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.2098180809 |
|
|
Feb 09 04:29:36 PM UTC 25 |
Feb 09 04:32:52 PM UTC 25 |
609610866 ps |
| T2141 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.2088578268 |
|
|
Feb 09 03:33:42 PM UTC 25 |
Feb 09 04:32:56 PM UTC 25 |
32701733702 ps |
| T2142 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.1504238599 |
|
|
Feb 09 04:23:25 PM UTC 25 |
Feb 09 04:32:56 PM UTC 25 |
10584194323 ps |
| T2143 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.1333043621 |
|
|
Feb 09 04:31:16 PM UTC 25 |
Feb 09 04:32:57 PM UTC 25 |
5912762302 ps |
| T898 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.3311919910 |
|
|
Feb 09 04:23:29 PM UTC 25 |
Feb 09 04:32:58 PM UTC 25 |
8477585933 ps |
| T2144 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.2946659362 |
|
|
Feb 09 04:21:43 PM UTC 25 |
Feb 09 04:33:04 PM UTC 25 |
43912709786 ps |
| T2145 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.3243389033 |
|
|
Feb 09 04:15:26 PM UTC 25 |
Feb 09 04:33:15 PM UTC 25 |
95379750147 ps |
| T2146 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.3026177979 |
|
|
Feb 09 04:32:17 PM UTC 25 |
Feb 09 04:33:33 PM UTC 25 |
273171736 ps |
| T2147 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.2910244779 |
|
|
Feb 09 04:33:04 PM UTC 25 |
Feb 09 04:33:33 PM UTC 25 |
274119929 ps |
| T2148 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.4246005178 |
|
|
Feb 09 04:33:25 PM UTC 25 |
Feb 09 04:33:34 PM UTC 25 |
51735726 ps |
| T2149 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.443239598 |
|
|
Feb 09 04:33:24 PM UTC 25 |
Feb 09 04:33:37 PM UTC 25 |
178390783 ps |
| T2150 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.785954855 |
|
|
Feb 09 04:32:39 PM UTC 25 |
Feb 09 04:33:38 PM UTC 25 |
535878795 ps |
| T2151 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.3907461673 |
|
|
Feb 09 04:32:34 PM UTC 25 |
Feb 09 04:33:39 PM UTC 25 |
1326417991 ps |
| T2152 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.1545678769 |
|
|
Feb 09 04:32:32 PM UTC 25 |
Feb 09 04:33:41 PM UTC 25 |
4236107407 ps |
| T2153 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.3280004852 |
|
|
Feb 09 04:30:11 PM UTC 25 |
Feb 09 04:33:41 PM UTC 25 |
12609112933 ps |
| T2154 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.2897896075 |
|
|
Feb 09 04:32:42 PM UTC 25 |
Feb 09 04:33:54 PM UTC 25 |
828242934 ps |
| T2155 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.4005135601 |
|
|
Feb 09 04:33:07 PM UTC 25 |
Feb 09 04:34:00 PM UTC 25 |
1007573539 ps |
| T2156 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.2924061553 |
|
|
Feb 09 04:33:03 PM UTC 25 |
Feb 09 04:34:07 PM UTC 25 |
2213792173 ps |
| T2157 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.1521065350 |
|
|
Feb 09 04:32:32 PM UTC 25 |
Feb 09 04:34:12 PM UTC 25 |
8062805875 ps |
| T2158 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.1056346537 |
|
|
Feb 09 04:34:08 PM UTC 25 |
Feb 09 04:34:17 PM UTC 25 |
36480106 ps |
| T2159 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.4204035964 |
|
|
Feb 09 04:33:04 PM UTC 25 |
Feb 09 04:34:28 PM UTC 25 |
1757801367 ps |
| T2160 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.2887102046 |
|
|
Feb 09 04:19:47 PM UTC 25 |
Feb 09 04:34:32 PM UTC 25 |
79039256397 ps |
| T2161 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.1160352752 |
|
|
Feb 09 04:34:08 PM UTC 25 |
Feb 09 04:34:32 PM UTC 25 |
451926575 ps |
| T2162 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.288599412 |
|
|
Feb 09 04:33:10 PM UTC 25 |
Feb 09 04:34:40 PM UTC 25 |
1113373996 ps |
| T2163 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.2698594610 |
|
|
Feb 09 04:30:51 PM UTC 25 |
Feb 09 04:34:40 PM UTC 25 |
2815532005 ps |
| T2164 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.2236755865 |
|
|
Feb 09 04:34:02 PM UTC 25 |
Feb 09 04:34:47 PM UTC 25 |
477055484 ps |
| T899 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.2729905655 |
|
|
Feb 09 04:29:19 PM UTC 25 |
Feb 09 04:34:48 PM UTC 25 |
838217094 ps |
| T2165 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3126792472 |
|
|
Feb 09 04:34:28 PM UTC 25 |
Feb 09 04:34:57 PM UTC 25 |
714992034 ps |
| T2166 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.887353981 |
|
|
Feb 09 04:24:25 PM UTC 25 |
Feb 09 04:34:58 PM UTC 25 |
9549474827 ps |
| T2167 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.1847248217 |
|
|
Feb 09 04:33:25 PM UTC 25 |
Feb 09 04:34:59 PM UTC 25 |
9022117075 ps |
| T2168 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.3911646736 |
|
|
Feb 09 03:31:28 PM UTC 25 |
Feb 09 04:35:06 PM UTC 25 |
30321957752 ps |
| T2169 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.1226477270 |
|
|
Feb 09 04:35:01 PM UTC 25 |
Feb 09 04:35:10 PM UTC 25 |
58867712 ps |
| T2170 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.4098848043 |
|
|
Feb 09 04:35:01 PM UTC 25 |
Feb 09 04:35:12 PM UTC 25 |
211460614 ps |
| T2171 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.2431488726 |
|
|
Feb 09 04:34:06 PM UTC 25 |
Feb 09 04:35:14 PM UTC 25 |
1518715736 ps |
| T2172 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.1243520274 |
|
|
Feb 09 04:27:28 PM UTC 25 |
Feb 09 04:35:26 PM UTC 25 |
2549298195 ps |
| T2173 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.2786803874 |
|
|
Feb 09 04:34:00 PM UTC 25 |
Feb 09 04:35:29 PM UTC 25 |
1966597924 ps |
| T2174 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.1537845283 |
|
|
Feb 09 04:33:43 PM UTC 25 |
Feb 09 04:35:30 PM UTC 25 |
4427114282 ps |
| T2175 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.466167548 |
|
|
Feb 09 04:34:22 PM UTC 25 |
Feb 09 04:35:33 PM UTC 25 |
1312531499 ps |
| T2176 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.752578270 |
|
|
Feb 09 04:32:06 PM UTC 25 |
Feb 09 04:35:34 PM UTC 25 |
3224468427 ps |
| T2177 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.682965753 |
|
|
Feb 09 04:35:17 PM UTC 25 |
Feb 09 04:35:48 PM UTC 25 |
352343133 ps |
| T2178 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.3153588105 |
|
|
Feb 09 04:35:36 PM UTC 25 |
Feb 09 04:35:51 PM UTC 25 |
195379999 ps |
| T2179 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.51891487 |
|
|
Feb 09 04:14:31 PM UTC 25 |
Feb 09 04:36:04 PM UTC 25 |
61114716253 ps |
| T2180 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.1096182739 |
|
|
Feb 09 04:35:41 PM UTC 25 |
Feb 09 04:36:06 PM UTC 25 |
179226552 ps |
| T2181 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.2156846042 |
|
|
Feb 09 04:17:27 PM UTC 25 |
Feb 09 04:36:10 PM UTC 25 |
71142305299 ps |
| T2182 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.569691756 |
|
|
Feb 09 04:35:27 PM UTC 25 |
Feb 09 04:36:11 PM UTC 25 |
498325438 ps |
| T2183 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.1140121807 |
|
|
Feb 09 04:35:40 PM UTC 25 |
Feb 09 04:36:13 PM UTC 25 |
465072413 ps |
| T2184 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1992741548 |
|
|
Feb 09 04:35:52 PM UTC 25 |
Feb 09 04:36:22 PM UTC 25 |
501652190 ps |
| T2185 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.3564467110 |
|
|
Feb 09 04:35:05 PM UTC 25 |
Feb 09 04:36:25 PM UTC 25 |
7843606315 ps |
| T2186 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.3728017684 |
|
|
Feb 09 04:36:18 PM UTC 25 |
Feb 09 04:36:29 PM UTC 25 |
47625304 ps |
| T2187 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.2542740523 |
|
|
Feb 09 04:36:16 PM UTC 25 |
Feb 09 04:36:30 PM UTC 25 |
244597167 ps |
| T2188 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.4269537110 |
|
|
Feb 09 04:35:08 PM UTC 25 |
Feb 09 04:36:30 PM UTC 25 |
5375119286 ps |
| T2189 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.3638336515 |
|
|
Feb 09 04:22:43 PM UTC 25 |
Feb 09 04:36:36 PM UTC 25 |
69669137455 ps |
| T505 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.2337085440 |
|
|
Feb 09 04:34:37 PM UTC 25 |
Feb 09 04:36:40 PM UTC 25 |
1462681449 ps |
| T2190 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.60903646 |
|
|
Feb 09 04:35:16 PM UTC 25 |
Feb 09 04:36:46 PM UTC 25 |
1808474744 ps |
| T2191 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.3121816685 |
|
|
Feb 09 04:36:39 PM UTC 25 |
Feb 09 04:36:53 PM UTC 25 |
60142265 ps |
| T2192 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.2476137636 |
|
|
Feb 09 04:36:35 PM UTC 25 |
Feb 09 04:37:04 PM UTC 25 |
291670726 ps |
| T2193 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.1532918519 |
|
|
Feb 09 04:36:55 PM UTC 25 |
Feb 09 04:37:12 PM UTC 25 |
131877457 ps |
| T2194 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.295590645 |
|
|
Feb 09 04:32:09 PM UTC 25 |
Feb 09 04:37:13 PM UTC 25 |
10450900737 ps |
| T2195 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.3904102645 |
|
|
Feb 09 04:37:09 PM UTC 25 |
Feb 09 04:37:20 PM UTC 25 |
81827909 ps |
| T2196 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.447869105 |
|
|
Feb 09 04:26:38 PM UTC 25 |
Feb 09 04:37:24 PM UTC 25 |
40550314253 ps |
| T2197 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.1074478454 |
|
|
Feb 09 04:23:57 PM UTC 25 |
Feb 09 04:37:25 PM UTC 25 |
71243240269 ps |
| T2198 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.180330518 |
|
|
Feb 09 04:25:09 PM UTC 25 |
Feb 09 04:37:29 PM UTC 25 |
67702421058 ps |
| T612 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.3825179932 |
|
|
Feb 09 04:34:46 PM UTC 25 |
Feb 09 04:37:37 PM UTC 25 |
5127270813 ps |
| T2199 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.4202441592 |
|
|
Feb 09 04:36:55 PM UTC 25 |
Feb 09 04:37:38 PM UTC 25 |
423943373 ps |
| T2200 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.2773890791 |
|
|
Feb 09 04:32:06 PM UTC 25 |
Feb 09 04:37:41 PM UTC 25 |
4152717218 ps |
| T2201 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.1304375498 |
|
|
Feb 09 04:37:04 PM UTC 25 |
Feb 09 04:37:41 PM UTC 25 |
203370737 ps |
| T2202 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.451372358 |
|
|
Feb 09 04:27:21 PM UTC 25 |
Feb 09 04:37:48 PM UTC 25 |
6680405394 ps |
| T2203 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.4028661723 |
|
|
Feb 09 04:37:40 PM UTC 25 |
Feb 09 04:37:55 PM UTC 25 |
260601167 ps |
| T2204 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.460210964 |
|
|
Feb 09 04:37:47 PM UTC 25 |
Feb 09 04:37:57 PM UTC 25 |
41674353 ps |
| T2205 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.3602513042 |
|
|
Feb 09 04:36:34 PM UTC 25 |
Feb 09 04:37:58 PM UTC 25 |
4961542640 ps |
| T2206 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.754053427 |
|
|
Feb 09 04:37:32 PM UTC 25 |
Feb 09 04:38:02 PM UTC 25 |
339414158 ps |
| T2207 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.2945925735 |
|
|
Feb 09 04:28:43 PM UTC 25 |
Feb 09 04:38:05 PM UTC 25 |
53650578712 ps |
| T521 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.3467467836 |
|
|
Feb 09 04:33:20 PM UTC 25 |
Feb 09 04:38:16 PM UTC 25 |
2903369840 ps |
| T2208 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.3477100143 |
|
|
Feb 09 04:26:53 PM UTC 25 |
Feb 09 04:38:18 PM UTC 25 |
48385326772 ps |
| T2209 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.4167833430 |
|
|
Feb 09 04:38:06 PM UTC 25 |
Feb 09 04:38:20 PM UTC 25 |
160625732 ps |
| T2210 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.2774619947 |
|
|
Feb 09 04:37:54 PM UTC 25 |
Feb 09 04:38:24 PM UTC 25 |
646302127 ps |
| T2211 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.605160979 |
|
|
Feb 09 04:30:39 PM UTC 25 |
Feb 09 04:38:26 PM UTC 25 |
11917899673 ps |
| T2212 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.989480630 |
|
|
Feb 09 04:36:51 PM UTC 25 |
Feb 09 04:38:31 PM UTC 25 |
972286562 ps |
| T2213 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.4046318330 |
|
|
Feb 09 04:30:07 PM UTC 25 |
Feb 09 04:38:32 PM UTC 25 |
47666050501 ps |
| T2214 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.484131223 |
|
|
Feb 09 04:36:01 PM UTC 25 |
Feb 09 04:38:35 PM UTC 25 |
3397121217 ps |
| T2215 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.3380888490 |
|
|
Feb 09 04:38:04 PM UTC 25 |
Feb 09 04:38:37 PM UTC 25 |
407314117 ps |
| T2216 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.2685484937 |
|
|
Feb 09 04:38:24 PM UTC 25 |
Feb 09 04:38:44 PM UTC 25 |
449001121 ps |
| T2217 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.626367818 |
|
|
Feb 09 04:36:32 PM UTC 25 |
Feb 09 04:38:52 PM UTC 25 |
9588127954 ps |
| T2218 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.2619190706 |
|
|
Feb 09 04:38:25 PM UTC 25 |
Feb 09 04:38:52 PM UTC 25 |
521251606 ps |
| T2219 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.2980037109 |
|
|
Feb 09 04:37:52 PM UTC 25 |
Feb 09 04:38:57 PM UTC 25 |
4456083082 ps |
| T2220 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.2293875097 |
|
|
Feb 09 04:38:51 PM UTC 25 |
Feb 09 04:39:02 PM UTC 25 |
49553221 ps |
| T2221 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.15279256 |
|
|
Feb 09 04:38:24 PM UTC 25 |
Feb 09 04:39:03 PM UTC 25 |
248421360 ps |
| T2222 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.2394102395 |
|
|
Feb 09 04:33:57 PM UTC 25 |
Feb 09 04:39:08 PM UTC 25 |
31588034947 ps |
| T2223 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.3309287645 |
|
|
Feb 09 04:38:52 PM UTC 25 |
Feb 09 04:39:09 PM UTC 25 |
239809751 ps |
| T2224 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.4251255361 |
|
|
Feb 09 04:22:40 PM UTC 25 |
Feb 09 04:39:12 PM UTC 25 |
62446300103 ps |
| T2225 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.353957203 |
|
|
Feb 09 04:25:18 PM UTC 25 |
Feb 09 04:39:19 PM UTC 25 |
51555779052 ps |
| T2226 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.2287889962 |
|
|
Feb 09 04:38:30 PM UTC 25 |
Feb 09 04:39:22 PM UTC 25 |
1339871739 ps |
| T2227 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.3497285898 |
|
|
Feb 09 04:38:34 PM UTC 25 |
Feb 09 04:39:25 PM UTC 25 |
716410030 ps |
| T2228 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.1493628750 |
|
|
Feb 09 04:37:52 PM UTC 25 |
Feb 09 04:39:25 PM UTC 25 |
6405248603 ps |
| T2229 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.3492003351 |
|
|
Feb 09 04:28:49 PM UTC 25 |
Feb 09 04:39:28 PM UTC 25 |
41517271455 ps |
| T2230 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.3222825520 |
|
|
Feb 09 04:39:02 PM UTC 25 |
Feb 09 04:39:35 PM UTC 25 |
274240691 ps |
| T2231 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.3185899901 |
|
|
Feb 09 04:12:40 PM UTC 25 |
Feb 09 04:39:41 PM UTC 25 |
122592941786 ps |
| T2232 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.1224341794 |
|
|
Feb 09 04:39:33 PM UTC 25 |
Feb 09 04:39:42 PM UTC 25 |
16803028 ps |
| T2233 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.1005086395 |
|
|
Feb 09 04:39:03 PM UTC 25 |
Feb 09 04:39:47 PM UTC 25 |
438436905 ps |
| T2234 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.2756467582 |
|
|
Feb 09 04:39:00 PM UTC 25 |
Feb 09 04:39:51 PM UTC 25 |
5312835096 ps |
| T2235 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.853785813 |
|
|
Feb 09 04:39:35 PM UTC 25 |
Feb 09 04:39:57 PM UTC 25 |
302536342 ps |
| T2236 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.1757516332 |
|
|
Feb 09 04:39:28 PM UTC 25 |
Feb 09 04:39:58 PM UTC 25 |
374497713 ps |
| T2237 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.3718429453 |
|
|
Feb 09 04:39:20 PM UTC 25 |
Feb 09 04:40:03 PM UTC 25 |
1097781837 ps |
| T2238 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.3345303111 |
|
|
Feb 09 04:39:55 PM UTC 25 |
Feb 09 04:40:05 PM UTC 25 |
38630732 ps |
| T2239 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.591273765 |
|
|
Feb 09 04:39:54 PM UTC 25 |
Feb 09 04:40:08 PM UTC 25 |
208759677 ps |
| T2240 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.1132811813 |
|
|
Feb 09 04:38:48 PM UTC 25 |
Feb 09 04:40:12 PM UTC 25 |
373127009 ps |
| T2241 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.364906061 |
|
|
Feb 09 04:38:47 PM UTC 25 |
Feb 09 04:40:14 PM UTC 25 |
1255805988 ps |
| T2242 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.2077776133 |
|
|
Feb 09 04:39:23 PM UTC 25 |
Feb 09 04:40:16 PM UTC 25 |
548378625 ps |
| T2243 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.3292993660 |
|
|
Feb 09 04:08:57 PM UTC 25 |
Feb 09 04:40:17 PM UTC 25 |
109584090922 ps |
| T2244 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.1946454768 |
|
|
Feb 09 04:35:26 PM UTC 25 |
Feb 09 04:40:21 PM UTC 25 |
18377318697 ps |
| T2245 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.3300282721 |
|
|
Feb 09 04:39:00 PM UTC 25 |
Feb 09 04:40:37 PM UTC 25 |
6360660153 ps |
| T2246 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.2038969106 |
|
|
Feb 09 04:40:37 PM UTC 25 |
Feb 09 04:40:50 PM UTC 25 |
256881324 ps |
| T2247 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.817089657 |
|
|
Feb 09 04:40:09 PM UTC 25 |
Feb 09 04:40:50 PM UTC 25 |
326956683 ps |
| T2248 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.3284497401 |
|
|
Feb 09 04:40:30 PM UTC 25 |
Feb 09 04:40:51 PM UTC 25 |
166187659 ps |
| T2249 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.480834803 |
|
|
Feb 09 04:40:14 PM UTC 25 |
Feb 09 04:40:53 PM UTC 25 |
410852306 ps |
| T2250 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.2978279265 |
|
|
Feb 09 04:35:58 PM UTC 25 |
Feb 09 04:40:55 PM UTC 25 |
3452436800 ps |
| T2251 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.4286516510 |
|
|
Feb 09 04:40:40 PM UTC 25 |
Feb 09 04:41:04 PM UTC 25 |
174246593 ps |
| T2252 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.2163746500 |
|
|
Feb 09 04:40:32 PM UTC 25 |
Feb 09 04:41:18 PM UTC 25 |
530832274 ps |
| T2253 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.2962686972 |
|
|
Feb 09 04:39:31 PM UTC 25 |
Feb 09 04:41:26 PM UTC 25 |
1271769340 ps |
| T2254 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.1111330146 |
|
|
Feb 09 04:41:18 PM UTC 25 |
Feb 09 04:41:27 PM UTC 25 |
47405611 ps |
| T2255 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.4172671361 |
|
|
Feb 09 03:52:55 PM UTC 25 |
Feb 09 04:41:29 PM UTC 25 |
175069118762 ps |
| T2256 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.2845200797 |
|
|
Feb 09 04:41:18 PM UTC 25 |
Feb 09 04:41:31 PM UTC 25 |
187355843 ps |
| T2257 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.3079038871 |
|
|
Feb 09 04:41:23 PM UTC 25 |
Feb 09 04:41:32 PM UTC 25 |
121846967 ps |
| T2258 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.4144520179 |
|
|
Feb 09 04:37:22 PM UTC 25 |
Feb 09 04:41:34 PM UTC 25 |
493528723 ps |
| T2259 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.861567099 |
|
|
Feb 09 04:40:05 PM UTC 25 |
Feb 09 04:41:34 PM UTC 25 |
6394189155 ps |
| T2260 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.1835692921 |
|
|
Feb 09 04:41:33 PM UTC 25 |
Feb 09 04:41:40 PM UTC 25 |
29004944 ps |
| T2261 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.3795219964 |
|
|
Feb 09 04:37:37 PM UTC 25 |
Feb 09 04:41:42 PM UTC 25 |
4756524067 ps |
| T2262 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.1280800891 |
|
|
Feb 09 04:40:04 PM UTC 25 |
Feb 09 04:42:11 PM UTC 25 |
7529999973 ps |
| T2263 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.3253866884 |
|
|
Feb 09 04:27:42 PM UTC 25 |
Feb 09 04:42:12 PM UTC 25 |
86385751173 ps |
| T2264 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.831456014 |
|
|
Feb 09 04:37:13 PM UTC 25 |
Feb 09 04:42:14 PM UTC 25 |
8665079757 ps |
| T2265 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.3158080322 |
|
|
Feb 09 04:36:55 PM UTC 25 |
Feb 09 04:42:16 PM UTC 25 |
15926242295 ps |
| T2266 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.1944327883 |
|
|
Feb 09 04:41:58 PM UTC 25 |
Feb 09 04:42:18 PM UTC 25 |
230084602 ps |
| T2267 |
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.2104940838 |
|
|
Feb 09 04:38:03 PM UTC 25 |
Feb 09 04:42:24 PM UTC 25 |
24684136100 ps |